ispmbox.h revision 157943
1/* $FreeBSD: head/sys/dev/isp/ispmbox.h 157943 2006-04-21 18:30:01Z mjacob $ */ 2/*- 3 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters. 4 * 5 * Copyright (c) 1997-2006 by Matthew Jacob 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice immediately at the beginning of the file, without modification, 13 * this list of conditions, and the following disclaimer. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30#ifndef _ISPMBOX_H 31#define _ISPMBOX_H 32 33/* 34 * Mailbox Command Opcodes 35 */ 36#define MBOX_NO_OP 0x0000 37#define MBOX_LOAD_RAM 0x0001 38#define MBOX_EXEC_FIRMWARE 0x0002 39#define MBOX_DUMP_RAM 0x0003 40#define MBOX_WRITE_RAM_WORD 0x0004 41#define MBOX_READ_RAM_WORD 0x0005 42#define MBOX_MAILBOX_REG_TEST 0x0006 43#define MBOX_VERIFY_CHECKSUM 0x0007 44#define MBOX_ABOUT_FIRMWARE 0x0008 45 /* 9 */ 46 /* a */ 47 /* b */ 48 /* c */ 49 /* d */ 50#define MBOX_CHECK_FIRMWARE 0x000e 51#define MBOX_READ_RAM_WORD_EXTENDED 0x000f 52#define MBOX_INIT_REQ_QUEUE 0x0010 53#define MBOX_INIT_RES_QUEUE 0x0011 54#define MBOX_EXECUTE_IOCB 0x0012 55#define MBOX_WAKE_UP 0x0013 56#define MBOX_STOP_FIRMWARE 0x0014 57#define MBOX_ABORT 0x0015 58#define MBOX_ABORT_DEVICE 0x0016 59#define MBOX_ABORT_TARGET 0x0017 60#define MBOX_BUS_RESET 0x0018 61#define MBOX_STOP_QUEUE 0x0019 62#define MBOX_START_QUEUE 0x001a 63#define MBOX_SINGLE_STEP_QUEUE 0x001b 64#define MBOX_ABORT_QUEUE 0x001c 65#define MBOX_GET_DEV_QUEUE_STATUS 0x001d 66 /* 1e */ 67#define MBOX_GET_FIRMWARE_STATUS 0x001f 68#define MBOX_GET_INIT_SCSI_ID 0x0020 69#define MBOX_GET_SELECT_TIMEOUT 0x0021 70#define MBOX_GET_RETRY_COUNT 0x0022 71#define MBOX_GET_TAG_AGE_LIMIT 0x0023 72#define MBOX_GET_CLOCK_RATE 0x0024 73#define MBOX_GET_ACT_NEG_STATE 0x0025 74#define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026 75#define MBOX_GET_SBUS_PARAMS 0x0027 76#define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS 77#define MBOX_GET_TARGET_PARAMS 0x0028 78#define MBOX_GET_DEV_QUEUE_PARAMS 0x0029 79#define MBOX_GET_RESET_DELAY_PARAMS 0x002a 80 /* 2b */ 81 /* 2c */ 82 /* 2d */ 83 /* 2e */ 84 /* 2f */ 85#define MBOX_SET_INIT_SCSI_ID 0x0030 86#define MBOX_SET_SELECT_TIMEOUT 0x0031 87#define MBOX_SET_RETRY_COUNT 0x0032 88#define MBOX_SET_TAG_AGE_LIMIT 0x0033 89#define MBOX_SET_CLOCK_RATE 0x0034 90#define MBOX_SET_ACT_NEG_STATE 0x0035 91#define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036 92#define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037 93#define MBOX_SET_PCI_PARAMETERS 0x0037 94#define MBOX_SET_TARGET_PARAMS 0x0038 95#define MBOX_SET_DEV_QUEUE_PARAMS 0x0039 96#define MBOX_SET_RESET_DELAY_PARAMS 0x003a 97 /* 3b */ 98 /* 3c */ 99 /* 3d */ 100 /* 3e */ 101 /* 3f */ 102#define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040 103#define MBOX_WRITE_FOUR_RAM_WORDS 0x0041 104#define MBOX_EXEC_BIOS_IOCB 0x0042 105#define MBOX_SET_FW_FEATURES 0x004a 106#define MBOX_GET_FW_FEATURES 0x004b 107#define FW_FEATURE_FAST_POST 0x1 108#define FW_FEATURE_LVD_NOTIFY 0x2 109#define FW_FEATURE_RIO_32BIT 0x4 110#define FW_FEATURE_RIO_16BIT 0x8 111 112#define MBOX_INIT_REQ_QUEUE_A64 0x0052 113#define MBOX_INIT_RES_QUEUE_A64 0x0053 114 115#define MBOX_ENABLE_TARGET_MODE 0x0055 116#define ENABLE_TARGET_FLAG 0x8000 117#define ENABLE_TQING_FLAG 0x0004 118#define ENABLE_MANDATORY_DISC 0x0002 119#define MBOX_GET_TARGET_STATUS 0x0056 120 121/* These are for the ISP2X00 FC cards */ 122#define MBOX_GET_LOOP_ID 0x0020 123#define MBOX_GET_FIRMWARE_OPTIONS 0x0028 124#define MBOX_SET_FIRMWARE_OPTIONS 0x0038 125#define MBOX_GET_RESOURCE_COUNT 0x0042 126#define MBOX_ENHANCED_GET_PDB 0x0047 127#define MBOX_EXEC_COMMAND_IOCB_A64 0x0054 128#define MBOX_INIT_FIRMWARE 0x0060 129#define MBOX_GET_INIT_CONTROL_BLOCK 0x0061 130#define MBOX_INIT_LIP 0x0062 131#define MBOX_GET_FC_AL_POSITION_MAP 0x0063 132#define MBOX_GET_PORT_DB 0x0064 133#define MBOX_CLEAR_ACA 0x0065 134#define MBOX_TARGET_RESET 0x0066 135#define MBOX_CLEAR_TASK_SET 0x0067 136#define MBOX_ABORT_TASK_SET 0x0068 137#define MBOX_GET_FW_STATE 0x0069 138#define MBOX_GET_PORT_NAME 0x006A 139#define MBOX_GET_LINK_STATUS 0x006B 140#define MBOX_INIT_LIP_RESET 0x006C 141#define MBOX_SEND_SNS 0x006E 142#define MBOX_FABRIC_LOGIN 0x006F 143#define MBOX_SEND_CHANGE_REQUEST 0x0070 144#define MBOX_FABRIC_LOGOUT 0x0071 145#define MBOX_INIT_LIP_LOGIN 0x0072 146#define MBOX_LUN_RESET 0x007E 147 148#define MBOX_DRIVER_HEARTBEAT 0x005B 149#define MBOX_FW_HEARTBEAT 0x005C 150 151#define MBOX_GET_SET_DATA_RATE 0x005D /* 23XX only */ 152#define MBGSD_GET_RATE 0 153#define MBGSD_SET_RATE 1 154#define MBGSD_ONEGB 0 155#define MBGSD_TWOGB 1 156#define MBGSD_AUTO 2 157 158 159#define ISP2100_SET_PCI_PARAM 0x00ff 160 161#define MBOX_BUSY 0x04 162 163/* 164 * Mailbox Command Complete Status Codes 165 */ 166#define MBOX_COMMAND_COMPLETE 0x4000 167#define MBOX_INVALID_COMMAND 0x4001 168#define MBOX_HOST_INTERFACE_ERROR 0x4002 169#define MBOX_TEST_FAILED 0x4003 170#define MBOX_COMMAND_ERROR 0x4005 171#define MBOX_COMMAND_PARAM_ERROR 0x4006 172#define MBOX_PORT_ID_USED 0x4007 173#define MBOX_LOOP_ID_USED 0x4008 174#define MBOX_ALL_IDS_USED 0x4009 175#define MBOX_NOT_LOGGED_IN 0x400A 176#define MBLOGALL 0x000f 177#define MBLOGNONE 0x0000 178#define MBLOGMASK(x) ((x) & 0xf) 179 180/* 181 * Asynchronous event status codes 182 */ 183#define ASYNC_BUS_RESET 0x8001 184#define ASYNC_SYSTEM_ERROR 0x8002 185#define ASYNC_RQS_XFER_ERR 0x8003 186#define ASYNC_RSP_XFER_ERR 0x8004 187#define ASYNC_QWAKEUP 0x8005 188#define ASYNC_TIMEOUT_RESET 0x8006 189#define ASYNC_DEVICE_RESET 0x8007 190#define ASYNC_EXTMSG_UNDERRUN 0x800A 191#define ASYNC_SCAM_INT 0x800B 192#define ASYNC_HUNG_SCSI 0x800C 193#define ASYNC_KILLED_BUS 0x800D 194#define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */ 195#define ASYNC_LIP_OCCURRED 0x8010 196#define ASYNC_LOOP_UP 0x8011 197#define ASYNC_LOOP_DOWN 0x8012 198#define ASYNC_LOOP_RESET 0x8013 199#define ASYNC_PDB_CHANGED 0x8014 200#define ASYNC_CHANGE_NOTIFY 0x8015 201#define ASYNC_LIP_F8 0x8016 202#define ASYNC_CMD_CMPLT 0x8020 203#define ASYNC_CTIO_DONE 0x8021 204#define ASYNC_IP_XMIT_DONE 0x8022 205#define ASYNC_IP_RECV_DONE 0x8023 206#define ASYNC_IP_BROADCAST 0x8024 207#define ASYNC_IP_RCVQ_LOW 0x8025 208#define ASYNC_IP_RCVQ_EMPTY 0x8026 209#define ASYNC_IP_RECV_DONE_ALIGNED 0x8027 210#define ASYNC_PTPMODE 0x8030 211#define ASYNC_RIO1 0x8031 212#define ASYNC_RIO2 0x8032 213#define ASYNC_RIO3 0x8033 214#define ASYNC_RIO4 0x8034 215#define ASYNC_RIO5 0x8035 216#define ASYNC_CONNMODE 0x8036 217#define ISP_CONN_LOOP 1 218#define ISP_CONN_PTP 2 219#define ISP_CONN_BADLIP 3 220#define ISP_CONN_FATAL 4 221#define ISP_CONN_LOOPBACK 5 222#define ASYNC_RIO_RESP 0x8040 223#define ASYNC_RIO_COMP 0x8042 224/* 225 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options 226 * mailbox command to enable this. 227 */ 228#define ASYNC_QFULL_SENT 0x8049 229 230/* 231 * Mailbox Usages 232 */ 233 234#define WRITE_REQUEST_QUEUE_IN_POINTER(isp, value) \ 235 ISP_WRITE(isp, isp->isp_rqstinrp, value) 236 237#define READ_REQUEST_QUEUE_OUT_POINTER(isp) \ 238 ISP_READ(isp, isp->isp_rqstoutrp) 239 240#define READ_RESPONSE_QUEUE_IN_POINTER(isp) \ 241 ISP_READ(isp, isp->isp_respinrp) 242 243#define WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, value) \ 244 ISP_WRITE(isp, isp->isp_respoutrp, value) 245 246/* 247 * Command Structure Definitions 248 */ 249 250typedef struct { 251 uint32_t ds_base; 252 uint32_t ds_count; 253} ispds_t; 254 255typedef struct { 256 uint32_t ds_base; 257 uint32_t ds_basehi; 258 uint32_t ds_count; 259} ispds64_t; 260 261#define DSTYPE_32BIT 0 262#define DSTYPE_64BIT 1 263typedef struct { 264 uint16_t ds_type; /* 0-> ispds_t, 1-> ispds64_t */ 265 uint32_t ds_segment; /* unused */ 266 uint32_t ds_base; /* 32 bit address of DSD list */ 267} ispdslist_t; 268 269 270/* 271 * These elements get swizzled around for SBus instances. 272 */ 273#define ISP_SWAP8(a, b) { \ 274 uint8_t tmp; \ 275 tmp = a; \ 276 a = b; \ 277 b = tmp; \ 278} 279typedef struct { 280 uint8_t rqs_entry_type; 281 uint8_t rqs_entry_count; 282 uint8_t rqs_seqno; 283 uint8_t rqs_flags; 284} isphdr_t; 285 286/* RQS Flag definitions */ 287#define RQSFLAG_CONTINUATION 0x01 288#define RQSFLAG_FULL 0x02 289#define RQSFLAG_BADHEADER 0x04 290#define RQSFLAG_BADPACKET 0x08 291 292/* RQS entry_type definitions */ 293#define RQSTYPE_REQUEST 0x01 294#define RQSTYPE_DATASEG 0x02 295#define RQSTYPE_RESPONSE 0x03 296#define RQSTYPE_MARKER 0x04 297#define RQSTYPE_CMDONLY 0x05 298#define RQSTYPE_ATIO 0x06 /* Target Mode */ 299#define RQSTYPE_CTIO 0x07 /* Target Mode */ 300#define RQSTYPE_SCAM 0x08 301#define RQSTYPE_A64 0x09 302#define RQSTYPE_A64_CONT 0x0a 303#define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */ 304#define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */ 305#define RQSTYPE_NOTIFY 0x0d /* Target Mode */ 306#define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */ 307#define RQSTYPE_CTIO1 0x0f /* Target Mode */ 308#define RQSTYPE_STATUS_CONT 0x10 309#define RQSTYPE_T2RQS 0x11 310#define RQSTYPE_IP_XMIT 0x13 311#define RQSTYPE_T4RQS 0x15 312#define RQSTYPE_ATIO2 0x16 /* Target Mode */ 313#define RQSTYPE_CTIO2 0x17 /* Target Mode */ 314#define RQSTYPE_CSET0 0x18 315#define RQSTYPE_T3RQS 0x19 316#define RQSTYPE_IP_XMIT_64 0x1b 317#define RQSTYPE_CTIO4 0x1e /* Target Mode */ 318#define RQSTYPE_CTIO3 0x1f /* Target Mode */ 319#define RQSTYPE_RIO1 0x21 320#define RQSTYPE_RIO2 0x22 321#define RQSTYPE_IP_RECV 0x23 322#define RQSTYPE_IP_RECV_CONT 0x24 323 324 325#define ISP_RQDSEG 4 326typedef struct { 327 isphdr_t req_header; 328 uint32_t req_handle; 329 uint8_t req_lun_trn; 330 uint8_t req_target; 331 uint16_t req_cdblen; 332#define req_modifier req_cdblen /* marker packet */ 333 uint16_t req_flags; 334 uint16_t req_reserved; 335 uint16_t req_time; 336 uint16_t req_seg_count; 337 uint8_t req_cdb[12]; 338 ispds_t req_dataseg[ISP_RQDSEG]; 339} ispreq_t; 340 341#define ispreq64_t ispreqt3_t /* same as.... */ 342#define ISP_RQDSEG_A64 2 343 344/* 345 * A request packet can also be a marker packet. 346 */ 347#define SYNC_DEVICE 0 348#define SYNC_TARGET 1 349#define SYNC_ALL 2 350#define SYNC_LIP 3 351 352#define ISP_RQDSEG_T2 3 353typedef struct { 354 isphdr_t req_header; 355 uint32_t req_handle; 356 uint8_t req_lun_trn; 357 uint8_t req_target; 358 uint16_t req_scclun; 359 uint16_t req_flags; 360 uint16_t _res2; 361 uint16_t req_time; 362 uint16_t req_seg_count; 363 uint8_t req_cdb[16]; 364 uint32_t req_totalcnt; 365 ispds_t req_dataseg[ISP_RQDSEG_T2]; 366} ispreqt2_t; 367 368typedef struct { 369 isphdr_t req_header; 370 uint32_t req_handle; 371 uint16_t req_target; 372 uint16_t req_scclun; 373 uint16_t req_flags; 374 uint16_t _res2; 375 uint16_t req_time; 376 uint16_t req_seg_count; 377 uint8_t req_cdb[16]; 378 uint32_t req_totalcnt; 379 ispds_t req_dataseg[ISP_RQDSEG_T2]; 380} ispreqt2e_t; 381 382#define ISP_RQDSEG_T3 2 383typedef struct { 384 isphdr_t req_header; 385 uint32_t req_handle; 386 uint8_t req_lun_trn; 387 uint8_t req_target; 388 uint16_t req_scclun; 389 uint16_t req_flags; 390 uint16_t _res2; 391 uint16_t req_time; 392 uint16_t req_seg_count; 393 uint8_t req_cdb[16]; 394 uint32_t req_totalcnt; 395 ispds64_t req_dataseg[ISP_RQDSEG_T3]; 396} ispreqt3_t; 397 398typedef struct { 399 isphdr_t req_header; 400 uint32_t req_handle; 401 uint16_t req_target; 402 uint16_t req_scclun; 403 uint16_t req_flags; 404 uint16_t _res2; 405 uint16_t req_time; 406 uint16_t req_seg_count; 407 uint8_t req_cdb[16]; 408 uint32_t req_totalcnt; 409 ispds64_t req_dataseg[ISP_RQDSEG_T3]; 410} ispreqt3e_t; 411 412/* req_flag values */ 413#define REQFLAG_NODISCON 0x0001 414#define REQFLAG_HTAG 0x0002 415#define REQFLAG_OTAG 0x0004 416#define REQFLAG_STAG 0x0008 417#define REQFLAG_TARGET_RTN 0x0010 418 419#define REQFLAG_NODATA 0x0000 420#define REQFLAG_DATA_IN 0x0020 421#define REQFLAG_DATA_OUT 0x0040 422#define REQFLAG_DATA_UNKNOWN 0x0060 423 424#define REQFLAG_DISARQ 0x0100 425#define REQFLAG_FRC_ASYNC 0x0200 426#define REQFLAG_FRC_SYNC 0x0400 427#define REQFLAG_FRC_WIDE 0x0800 428#define REQFLAG_NOPARITY 0x1000 429#define REQFLAG_STOPQ 0x2000 430#define REQFLAG_XTRASNS 0x4000 431#define REQFLAG_PRIORITY 0x8000 432 433typedef struct { 434 isphdr_t req_header; 435 uint32_t req_handle; 436 uint8_t req_lun_trn; 437 uint8_t req_target; 438 uint16_t req_cdblen; 439 uint16_t req_flags; 440 uint16_t _res1; 441 uint16_t req_time; 442 uint16_t req_seg_count; 443 uint8_t req_cdb[44]; 444} ispextreq_t; 445 446#define ISP_CDSEG 7 447typedef struct { 448 isphdr_t req_header; 449 uint32_t _res1; 450 ispds_t req_dataseg[ISP_CDSEG]; 451} ispcontreq_t; 452 453#define ISP_CDSEG64 5 454typedef struct { 455 isphdr_t req_header; 456 ispds64_t req_dataseg[ISP_CDSEG64]; 457} ispcontreq64_t; 458 459typedef struct { 460 isphdr_t req_header; 461 uint32_t req_handle; 462 uint16_t req_scsi_status; 463 uint16_t req_completion_status; 464 uint16_t req_state_flags; 465 uint16_t req_status_flags; 466 uint16_t req_time; 467#define req_response_len req_time /* FC only */ 468 uint16_t req_sense_len; 469 uint32_t req_resid; 470 uint8_t req_response[8]; /* FC only */ 471 uint8_t req_sense_data[32]; 472} ispstatusreq_t; 473 474typedef struct { 475 isphdr_t req_header; 476 uint8_t req_sense_data[60]; 477} ispstatus_cont_t; 478 479/* 480 * For Qlogic 2X00, the high order byte of SCSI status has 481 * additional meaning. 482 */ 483#define RQCS_RU 0x800 /* Residual Under */ 484#define RQCS_RO 0x400 /* Residual Over */ 485#define RQCS_RESID (RQCS_RU|RQCS_RO) 486#define RQCS_SV 0x200 /* Sense Length Valid */ 487#define RQCS_RV 0x100 /* FCP Response Length Valid */ 488 489/* 490 * Completion Status Codes. 491 */ 492#define RQCS_COMPLETE 0x0000 493#define RQCS_DMA_ERROR 0x0002 494#define RQCS_RESET_OCCURRED 0x0004 495#define RQCS_ABORTED 0x0005 496#define RQCS_TIMEOUT 0x0006 497#define RQCS_DATA_OVERRUN 0x0007 498#define RQCS_DATA_UNDERRUN 0x0015 499#define RQCS_QUEUE_FULL 0x001C 500 501/* 1X00 Only Completion Codes */ 502#define RQCS_INCOMPLETE 0x0001 503#define RQCS_TRANSPORT_ERROR 0x0003 504#define RQCS_COMMAND_OVERRUN 0x0008 505#define RQCS_STATUS_OVERRUN 0x0009 506#define RQCS_BAD_MESSAGE 0x000a 507#define RQCS_NO_MESSAGE_OUT 0x000b 508#define RQCS_EXT_ID_FAILED 0x000c 509#define RQCS_IDE_MSG_FAILED 0x000d 510#define RQCS_ABORT_MSG_FAILED 0x000e 511#define RQCS_REJECT_MSG_FAILED 0x000f 512#define RQCS_NOP_MSG_FAILED 0x0010 513#define RQCS_PARITY_ERROR_MSG_FAILED 0x0011 514#define RQCS_DEVICE_RESET_MSG_FAILED 0x0012 515#define RQCS_ID_MSG_FAILED 0x0013 516#define RQCS_UNEXP_BUS_FREE 0x0014 517#define RQCS_XACT_ERR1 0x0018 518#define RQCS_XACT_ERR2 0x0019 519#define RQCS_XACT_ERR3 0x001A 520#define RQCS_BAD_ENTRY 0x001B 521#define RQCS_PHASE_SKIPPED 0x001D 522#define RQCS_ARQS_FAILED 0x001E 523#define RQCS_WIDE_FAILED 0x001F 524#define RQCS_SYNCXFER_FAILED 0x0020 525#define RQCS_LVD_BUSERR 0x0021 526 527/* 2X00 Only Completion Codes */ 528#define RQCS_PORT_UNAVAILABLE 0x0028 529#define RQCS_PORT_LOGGED_OUT 0x0029 530#define RQCS_PORT_CHANGED 0x002A 531#define RQCS_PORT_BUSY 0x002B 532 533/* 534 * 1X00 specific State Flags 535 */ 536#define RQSF_GOT_BUS 0x0100 537#define RQSF_GOT_TARGET 0x0200 538#define RQSF_SENT_CDB 0x0400 539#define RQSF_XFRD_DATA 0x0800 540#define RQSF_GOT_STATUS 0x1000 541#define RQSF_GOT_SENSE 0x2000 542#define RQSF_XFER_COMPLETE 0x4000 543 544/* 545 * 2X00 specific State Flags 546 * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available) 547 */ 548#define RQSF_DATA_IN 0x0020 549#define RQSF_DATA_OUT 0x0040 550#define RQSF_STAG 0x0008 551#define RQSF_OTAG 0x0004 552#define RQSF_HTAG 0x0002 553/* 554 * 1X00 Status Flags 555 */ 556#define RQSTF_DISCONNECT 0x0001 557#define RQSTF_SYNCHRONOUS 0x0002 558#define RQSTF_PARITY_ERROR 0x0004 559#define RQSTF_BUS_RESET 0x0008 560#define RQSTF_DEVICE_RESET 0x0010 561#define RQSTF_ABORTED 0x0020 562#define RQSTF_TIMEOUT 0x0040 563#define RQSTF_NEGOTIATION 0x0080 564 565/* 566 * 2X00 specific state flags 567 */ 568/* RQSF_SENT_CDB */ 569/* RQSF_XFRD_DATA */ 570/* RQSF_GOT_STATUS */ 571/* RQSF_XFER_COMPLETE */ 572 573/* 574 * 2X00 specific status flags 575 */ 576/* RQSTF_ABORTED */ 577/* RQSTF_TIMEOUT */ 578#define RQSTF_DMA_ERROR 0x0080 579#define RQSTF_LOGOUT 0x2000 580 581/* 582 * Miscellaneous 583 */ 584#ifndef ISP_EXEC_THROTTLE 585#define ISP_EXEC_THROTTLE 16 586#endif 587 588/* 589 * About Firmware returns an 'attribute' word in mailbox 6. 590 */ 591#define ISP_FW_ATTR_TMODE 0x01 592#define ISP_FW_ATTR_SCCLUN 0x02 593#define ISP_FW_ATTR_FABRIC 0x04 594#define ISP_FW_ATTR_CLASS2 0x08 595#define ISP_FW_ATTR_FCTAPE 0x10 596#define ISP_FW_ATTR_IP 0x20 597#define ISP_FW_ATTR_VI 0x40 598#define ISP_FW_ATTR_VI_SOLARIS 0x80 599#define ISP_FW_ATTR_2KLOGINS 0x100 /* XXX: just a guess */ 600 601#define IS_2KLOGIN(isp) \ 602 (IS_FC(isp) && (FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_2KLOGINS)) 603 604/* 605 * Reduced Interrupt Operation Response Queue Entreis 606 */ 607 608typedef struct { 609 isphdr_t req_header; 610 uint32_t req_handles[15]; 611} isp_rio1_t; 612 613typedef struct { 614 isphdr_t req_header; 615 uint16_t req_handles[30]; 616} isp_rio2_t; 617 618/* 619 * FC (ISP2100) specific data structures 620 */ 621 622/* 623 * Initialization Control Block 624 * 625 * Version One (prime) format. 626 */ 627typedef struct isp_icb { 628 uint8_t icb_version; 629 uint8_t _reserved0; 630 uint16_t icb_fwoptions; 631 uint16_t icb_maxfrmlen; 632 uint16_t icb_maxalloc; 633 uint16_t icb_execthrottle; 634 uint8_t icb_retry_count; 635 uint8_t icb_retry_delay; 636 uint8_t icb_portname[8]; 637 uint16_t icb_hardaddr; 638 uint8_t icb_iqdevtype; 639 uint8_t icb_logintime; 640 uint8_t icb_nodename[8]; 641 uint16_t icb_rqstout; 642 uint16_t icb_rspnsin; 643 uint16_t icb_rqstqlen; 644 uint16_t icb_rsltqlen; 645 uint16_t icb_rqstaddr[4]; 646 uint16_t icb_respaddr[4]; 647 uint16_t icb_lunenables; 648 uint8_t icb_ccnt; 649 uint8_t icb_icnt; 650 uint16_t icb_lunetimeout; 651 uint16_t _reserved1; 652 uint16_t icb_xfwoptions; 653 uint8_t icb_racctimer; 654 uint8_t icb_idelaytimer; 655 uint16_t icb_zfwoptions; 656 uint16_t _reserved2[13]; 657} isp_icb_t; 658#define ICB_VERSION1 1 659 660#define ICBOPT_HARD_ADDRESS 0x0001 661#define ICBOPT_FAIRNESS 0x0002 662#define ICBOPT_FULL_DUPLEX 0x0004 663#define ICBOPT_FAST_POST 0x0008 664#define ICBOPT_TGT_ENABLE 0x0010 665#define ICBOPT_INI_DISABLE 0x0020 666#define ICBOPT_INI_ADISC 0x0040 667#define ICBOPT_INI_TGTTYPE 0x0080 668#define ICBOPT_PDBCHANGE_AE 0x0100 669#define ICBOPT_NOLIP 0x0200 670#define ICBOPT_SRCHDOWN 0x0400 671#define ICBOPT_PREVLOOP 0x0800 672#define ICBOPT_STOP_ON_QFULL 0x1000 673#define ICBOPT_FULL_LOGIN 0x2000 674#define ICBOPT_BOTH_WWNS 0x4000 675#define ICBOPT_EXTENDED 0x8000 676 677#define ICBXOPT_CLASS2_ACK0 0x0200 678#define ICBXOPT_CLASS2 0x0100 679#define ICBXOPT_LOOP_ONLY (0 << 4) 680#define ICBXOPT_PTP_ONLY (1 << 4) 681#define ICBXOPT_LOOP_2_PTP (2 << 4) 682#define ICBXOPT_PTP_2_LOOP (3 << 4) 683 684/* 685 * The lower 4 bits of the xfwoptions field are the OPERATION MODE bits. 686 * RIO is not defined for the 23XX cards 687 */ 688#define ICBXOPT_RIO_OFF 0 689#define ICBXOPT_RIO_16BIT 1 690#define ICBXOPT_RIO_32BIT 2 691#define ICBXOPT_RIO_16BIT_IOCB 3 692#define ICBXOPT_RIO_32BIT_IOCB 4 693#define ICBXOPT_ZIO 5 694 695#define ICBZOPT_ENA_RDXFR_RDY 0x01 696#define ICBZOPT_ENA_OOF (1 << 6) /* out of order frame handling */ 697/* These 3 only apply to the 2300 */ 698#define ICBZOPT_RATE_ONEGB (MBGSD_ONEGB << 14) 699#define ICBZOPT_RATE_TWOGB (MBGSD_TWOGB << 14) 700#define ICBZOPT_RATE_AUTO (MBGSD_AUTO << 14) 701 702 703#define ICB_MIN_FRMLEN 256 704#define ICB_MAX_FRMLEN 2112 705#define ICB_DFLT_FRMLEN 1024 706#define ICB_DFLT_ALLOC 256 707#define ICB_DFLT_THROTTLE 16 708#define ICB_DFLT_RDELAY 5 709#define ICB_DFLT_RCOUNT 3 710 711#define ICB_LOGIN_TOV 30 712#define ICB_LUN_ENABLE_TOV 180 713 714 715 716#define RQRSP_ADDR0015 0 717#define RQRSP_ADDR1631 1 718#define RQRSP_ADDR3247 2 719#define RQRSP_ADDR4863 3 720 721 722#define ICB_NNM0 7 723#define ICB_NNM1 6 724#define ICB_NNM2 5 725#define ICB_NNM3 4 726#define ICB_NNM4 3 727#define ICB_NNM5 2 728#define ICB_NNM6 1 729#define ICB_NNM7 0 730 731#define MAKE_NODE_NAME_FROM_WWN(array, wwn) \ 732 array[ICB_NNM0] = (uint8_t) ((wwn >> 0) & 0xff), \ 733 array[ICB_NNM1] = (uint8_t) ((wwn >> 8) & 0xff), \ 734 array[ICB_NNM2] = (uint8_t) ((wwn >> 16) & 0xff), \ 735 array[ICB_NNM3] = (uint8_t) ((wwn >> 24) & 0xff), \ 736 array[ICB_NNM4] = (uint8_t) ((wwn >> 32) & 0xff), \ 737 array[ICB_NNM5] = (uint8_t) ((wwn >> 40) & 0xff), \ 738 array[ICB_NNM6] = (uint8_t) ((wwn >> 48) & 0xff), \ 739 array[ICB_NNM7] = (uint8_t) ((wwn >> 56) & 0xff) 740 741#define MAKE_WWN_FROM_NODE_NAME(wwn, array) \ 742 wwn = ((uint64_t) array[ICB_NNM0]) | \ 743 ((uint64_t) array[ICB_NNM1] << 8) | \ 744 ((uint64_t) array[ICB_NNM2] << 16) | \ 745 ((uint64_t) array[ICB_NNM3] << 24) | \ 746 ((uint64_t) array[ICB_NNM4] << 32) | \ 747 ((uint64_t) array[ICB_NNM5] << 40) | \ 748 ((uint64_t) array[ICB_NNM6] << 48) | \ 749 ((uint64_t) array[ICB_NNM7] << 56) 750 751/* 752 * FC-AL Position Map 753 * 754 * This is an at most 128 byte map that returns either 755 * the LILP or Firmware generated list of ports. 756 * 757 * We deviate a bit from the returned qlogic format to 758 * use an extra bit to say whether this was a LILP or 759 * f/w generated map. 760 */ 761typedef struct { 762 uint8_t fwmap : 1, 763 count : 7; 764 uint8_t map[127]; 765} fcpos_map_t; 766 767/* 768 * Port Data Base Element 769 */ 770 771typedef struct { 772 uint16_t pdb_options; 773 uint8_t pdb_mstate; 774 uint8_t pdb_sstate; 775#define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2]) 776 uint8_t pdb_hardaddr_bits[4]; 777 uint8_t pdb_portid_bits[4]; 778 uint8_t pdb_nodename[8]; 779 uint8_t pdb_portname[8]; 780 uint16_t pdb_execthrottle; 781 uint16_t pdb_exec_count; 782 uint8_t pdb_retry_count; 783 uint8_t pdb_retry_delay; 784 uint16_t pdb_resalloc; 785 uint16_t pdb_curalloc; 786 uint16_t pdb_qhead; 787 uint16_t pdb_qtail; 788 uint16_t pdb_tl_next; 789 uint16_t pdb_tl_last; 790 uint16_t pdb_features; /* PLOGI, Common Service */ 791 uint16_t pdb_pconcurrnt; /* PLOGI, Common Service */ 792 uint16_t pdb_roi; /* PLOGI, Common Service */ 793 uint8_t pdb_target; 794 uint8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */ 795 uint16_t pdb_rdsiz; /* PLOGI, Class 3 */ 796 uint16_t pdb_ncseq; /* PLOGI, Class 3 */ 797 uint16_t pdb_noseq; /* PLOGI, Class 3 */ 798 uint16_t pdb_labrtflg; 799 uint16_t pdb_lstopflg; 800 uint16_t pdb_sqhead; 801 uint16_t pdb_sqtail; 802 uint16_t pdb_ptimer; 803 uint16_t pdb_nxt_seqid; 804 uint16_t pdb_fcount; 805 uint16_t pdb_prli_len; 806 uint16_t pdb_prli_svc0; 807 uint16_t pdb_prli_svc3; 808 uint16_t pdb_loopid; 809 uint16_t pdb_il_ptr; 810 uint16_t pdb_sl_ptr; 811} isp_pdb_t; 812 813#define PDB_OPTIONS_XMITTING (1<<11) 814#define PDB_OPTIONS_LNKXMIT (1<<10) 815#define PDB_OPTIONS_ABORTED (1<<9) 816#define PDB_OPTIONS_ADISC (1<<1) 817 818#define PDB_STATE_DISCOVERY 0 819#define PDB_STATE_WDISC_ACK 1 820#define PDB_STATE_PLOGI 2 821#define PDB_STATE_PLOGI_ACK 3 822#define PDB_STATE_PRLI 4 823#define PDB_STATE_PRLI_ACK 5 824#define PDB_STATE_LOGGED_IN 6 825#define PDB_STATE_PORT_UNAVAIL 7 826#define PDB_STATE_PRLO 8 827#define PDB_STATE_PRLO_ACK 9 828#define PDB_STATE_PLOGO 10 829#define PDB_STATE_PLOG_ACK 11 830 831#define SVC3_TGT_ROLE 0x10 832#define SVC3_INI_ROLE 0x20 833#define SVC3_ROLE_MASK 0x30 834#define SVC3_ROLE_SHIFT 4 835 836/* 837 * CT definition 838 * 839 * This is as the QLogic f/w documentations defines it- which is just opposite, 840 * bit wise, from what the specification defines it as. Additionally, the 841 * ct_response and ct_resid (really from FC-GS-2) need to be byte swapped. 842 */ 843 844typedef struct { 845 uint8_t ct_revision; 846 uint8_t ct_portid[3]; 847 uint8_t ct_fcs_type; 848 uint8_t ct_fcs_subtype; 849 uint8_t ct_options; 850 uint8_t ct_res0; 851 uint16_t ct_response; 852 uint16_t ct_resid; 853 uint8_t ct_res1; 854 uint8_t ct_reason; 855 uint8_t ct_explanation; 856 uint8_t ct_vunique; 857} ct_hdr_t; 858#define FS_ACC 0x8002 859#define FS_RJT 0x8001 860 861#define FC4_IP 5 /* ISO/EEC 8802-2 LLC/SNAP "Out of Order Delivery" */ 862#define FC4_SCSI 8 /* SCSI-3 via Fivre Channel Protocol (FCP) */ 863#define FC4_FC_SVC 0x20 /* Fibre Channel Services */ 864 865#define SNS_GA_NXT 0x100 866#define SNS_GPN_ID 0x112 867#define SNS_GNN_ID 0x113 868#define SNS_GFF_ID 0x11F 869#define SNS_GID_FT 0x171 870#define SNS_RFT_ID 0x217 871typedef struct { 872 uint16_t snscb_rblen; /* response buffer length (words) */ 873 uint16_t snscb_res0; 874 uint16_t snscb_addr[4]; /* response buffer address */ 875 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 876 uint16_t snscb_res1; 877 uint16_t snscb_data[1]; /* variable data */ 878} sns_screq_t; /* Subcommand Request Structure */ 879 880typedef struct { 881 uint16_t snscb_rblen; /* response buffer length (words) */ 882 uint16_t snscb_res0; 883 uint16_t snscb_addr[4]; /* response buffer address */ 884 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 885 uint16_t snscb_res1; 886 uint16_t snscb_cmd; 887 uint16_t snscb_res2; 888 uint32_t snscb_res3; 889 uint32_t snscb_port; 890} sns_ga_nxt_req_t; 891#define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t)) 892 893typedef struct { 894 uint16_t snscb_rblen; /* response buffer length (words) */ 895 uint16_t snscb_res0; 896 uint16_t snscb_addr[4]; /* response buffer address */ 897 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 898 uint16_t snscb_res1; 899 uint16_t snscb_cmd; 900 uint16_t snscb_res2; 901 uint32_t snscb_res3; 902 uint32_t snscb_portid; 903} sns_gxn_id_req_t; 904#define SNS_GXN_ID_REQ_SIZE (sizeof (sns_gxn_id_req_t)) 905 906typedef struct { 907 uint16_t snscb_rblen; /* response buffer length (words) */ 908 uint16_t snscb_res0; 909 uint16_t snscb_addr[4]; /* response buffer address */ 910 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 911 uint16_t snscb_res1; 912 uint16_t snscb_cmd; 913 uint16_t snscb_mword_div_2; 914 uint32_t snscb_res3; 915 uint32_t snscb_fc4_type; 916} sns_gid_ft_req_t; 917#define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t)) 918 919typedef struct { 920 uint16_t snscb_rblen; /* response buffer length (words) */ 921 uint16_t snscb_res0; 922 uint16_t snscb_addr[4]; /* response buffer address */ 923 uint16_t snscb_sblen; /* subcommand buffer length (words) */ 924 uint16_t snscb_res1; 925 uint16_t snscb_cmd; 926 uint16_t snscb_res2; 927 uint32_t snscb_res3; 928 uint32_t snscb_port; 929 uint32_t snscb_fc4_types[8]; 930} sns_rft_id_req_t; 931#define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t)) 932 933typedef struct { 934 ct_hdr_t snscb_cthdr; 935 uint8_t snscb_port_type; 936 uint8_t snscb_port_id[3]; 937 uint8_t snscb_portname[8]; 938 uint16_t snscb_data[1]; /* variable data */ 939} sns_scrsp_t; /* Subcommand Response Structure */ 940 941typedef struct { 942 ct_hdr_t snscb_cthdr; 943 uint8_t snscb_port_type; 944 uint8_t snscb_port_id[3]; 945 uint8_t snscb_portname[8]; 946 uint8_t snscb_pnlen; /* symbolic port name length */ 947 uint8_t snscb_pname[255]; /* symbolic port name */ 948 uint8_t snscb_nodename[8]; 949 uint8_t snscb_nnlen; /* symbolic node name length */ 950 uint8_t snscb_nname[255]; /* symbolic node name */ 951 uint8_t snscb_ipassoc[8]; 952 uint8_t snscb_ipaddr[16]; 953 uint8_t snscb_svc_class[4]; 954 uint8_t snscb_fc4_types[32]; 955 uint8_t snscb_fpname[8]; 956 uint8_t snscb_reserved; 957 uint8_t snscb_hardaddr[3]; 958} sns_ga_nxt_rsp_t; /* Subcommand Response Structure */ 959#define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t)) 960 961typedef struct { 962 ct_hdr_t snscb_cthdr; 963 uint8_t snscb_wwn[8]; 964} sns_gxn_id_rsp_t; 965#define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t)) 966 967typedef struct { 968 ct_hdr_t snscb_cthdr; 969 uint32_t snscb_fc4_features[32]; 970} sns_gff_id_rsp_t; 971#define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t)) 972 973typedef struct { 974 ct_hdr_t snscb_cthdr; 975 struct { 976 uint8_t control; 977 uint8_t portid[3]; 978 } snscb_ports[1]; 979} sns_gid_ft_rsp_t; 980#define SNS_GID_FT_RESP_SIZE(x) ((sizeof (sns_gid_ft_rsp_t)) + ((x - 1) << 2)) 981 982#define SNS_RFT_ID_RESP_SIZE (sizeof (ct_hdr_t)) 983 984#endif /* _ISPMBOX_H */ 985