ioat.c revision 300661
1/*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/10/sys/dev/ioat/ioat.c 300661 2016-05-25 07:09:54Z mav $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <sys/ioccom.h> 35#include <sys/kernel.h> 36#include <sys/lock.h> 37#include <sys/malloc.h> 38#include <sys/module.h> 39#include <sys/mutex.h> 40#include <sys/rman.h> 41#include <sys/sbuf.h> 42#include <sys/sysctl.h> 43#include <sys/taskqueue.h> 44#include <sys/time.h> 45#include <dev/pci/pcireg.h> 46#include <dev/pci/pcivar.h> 47#include <machine/bus.h> 48#include <machine/resource.h> 49#include <machine/stdarg.h> 50 51#include "ioat.h" 52#include "ioat_hw.h" 53#include "ioat_internal.h" 54 55#ifndef BUS_SPACE_MAXADDR_40BIT 56#define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL 57#endif 58#define IOAT_INTR_TIMO (hz / 10) 59#define IOAT_REFLK (&ioat->submit_lock) 60 61static int ioat_probe(device_t device); 62static int ioat_attach(device_t device); 63static int ioat_detach(device_t device); 64static int ioat_setup_intr(struct ioat_softc *ioat); 65static int ioat_teardown_intr(struct ioat_softc *ioat); 66static int ioat3_attach(device_t device); 67static int ioat_start_channel(struct ioat_softc *ioat); 68static int ioat_map_pci_bar(struct ioat_softc *ioat); 69static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, 70 int error); 71static void ioat_interrupt_handler(void *arg); 72static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat); 73static int chanerr_to_errno(uint32_t); 74static void ioat_process_events(struct ioat_softc *ioat); 75static inline uint32_t ioat_get_active(struct ioat_softc *ioat); 76static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat); 77static void ioat_free_ring(struct ioat_softc *, uint32_t size, 78 struct ioat_descriptor **); 79static void ioat_free_ring_entry(struct ioat_softc *ioat, 80 struct ioat_descriptor *desc); 81static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *, 82 int mflags); 83static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags); 84static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat, 85 uint32_t index); 86static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *, 87 uint32_t size, boolean_t need_dscr, int mflags); 88static int ring_grow(struct ioat_softc *, uint32_t oldorder, 89 struct ioat_descriptor **); 90static int ring_shrink(struct ioat_softc *, uint32_t oldorder, 91 struct ioat_descriptor **); 92static void ioat_halted_debug(struct ioat_softc *, uint32_t); 93static void ioat_timer_callback(void *arg); 94static void dump_descriptor(void *hw_desc); 95static void ioat_submit_single(struct ioat_softc *ioat); 96static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, 97 int error); 98static int ioat_reset_hw(struct ioat_softc *ioat); 99static void ioat_reset_hw_task(void *, int); 100static void ioat_setup_sysctl(device_t device); 101static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS); 102static inline struct ioat_softc *ioat_get(struct ioat_softc *, 103 enum ioat_ref_kind); 104static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind); 105static inline void _ioat_putn(struct ioat_softc *, uint32_t, 106 enum ioat_ref_kind, boolean_t); 107static inline void ioat_putn(struct ioat_softc *, uint32_t, 108 enum ioat_ref_kind); 109static inline void ioat_putn_locked(struct ioat_softc *, uint32_t, 110 enum ioat_ref_kind); 111static void ioat_drain_locked(struct ioat_softc *); 112 113#define ioat_log_message(v, ...) do { \ 114 if ((v) <= g_ioat_debug_level) { \ 115 device_printf(ioat->device, __VA_ARGS__); \ 116 } \ 117} while (0) 118 119MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations"); 120SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node"); 121 122static int g_force_legacy_interrupts; 123SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN, 124 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled"); 125 126int g_ioat_debug_level = 0; 127SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level, 128 0, "Set log level (0-3) for ioat(4). Higher is more verbose."); 129 130/* 131 * OS <-> Driver interface structures 132 */ 133static device_method_t ioat_pci_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, ioat_probe), 136 DEVMETHOD(device_attach, ioat_attach), 137 DEVMETHOD(device_detach, ioat_detach), 138 DEVMETHOD_END 139}; 140 141static driver_t ioat_pci_driver = { 142 "ioat", 143 ioat_pci_methods, 144 sizeof(struct ioat_softc), 145}; 146 147static devclass_t ioat_devclass; 148DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0); 149MODULE_VERSION(ioat, 1); 150 151/* 152 * Private data structures 153 */ 154static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS]; 155static int ioat_channel_index = 0; 156SYSCTL_INT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0, 157 "Number of IOAT channels attached"); 158 159static struct _pcsid 160{ 161 u_int32_t type; 162 const char *desc; 163} pci_ids[] = { 164 { 0x34308086, "TBG IOAT Ch0" }, 165 { 0x34318086, "TBG IOAT Ch1" }, 166 { 0x34328086, "TBG IOAT Ch2" }, 167 { 0x34338086, "TBG IOAT Ch3" }, 168 { 0x34298086, "TBG IOAT Ch4" }, 169 { 0x342a8086, "TBG IOAT Ch5" }, 170 { 0x342b8086, "TBG IOAT Ch6" }, 171 { 0x342c8086, "TBG IOAT Ch7" }, 172 173 { 0x37108086, "JSF IOAT Ch0" }, 174 { 0x37118086, "JSF IOAT Ch1" }, 175 { 0x37128086, "JSF IOAT Ch2" }, 176 { 0x37138086, "JSF IOAT Ch3" }, 177 { 0x37148086, "JSF IOAT Ch4" }, 178 { 0x37158086, "JSF IOAT Ch5" }, 179 { 0x37168086, "JSF IOAT Ch6" }, 180 { 0x37178086, "JSF IOAT Ch7" }, 181 { 0x37188086, "JSF IOAT Ch0 (RAID)" }, 182 { 0x37198086, "JSF IOAT Ch1 (RAID)" }, 183 184 { 0x3c208086, "SNB IOAT Ch0" }, 185 { 0x3c218086, "SNB IOAT Ch1" }, 186 { 0x3c228086, "SNB IOAT Ch2" }, 187 { 0x3c238086, "SNB IOAT Ch3" }, 188 { 0x3c248086, "SNB IOAT Ch4" }, 189 { 0x3c258086, "SNB IOAT Ch5" }, 190 { 0x3c268086, "SNB IOAT Ch6" }, 191 { 0x3c278086, "SNB IOAT Ch7" }, 192 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" }, 193 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" }, 194 195 { 0x0e208086, "IVB IOAT Ch0" }, 196 { 0x0e218086, "IVB IOAT Ch1" }, 197 { 0x0e228086, "IVB IOAT Ch2" }, 198 { 0x0e238086, "IVB IOAT Ch3" }, 199 { 0x0e248086, "IVB IOAT Ch4" }, 200 { 0x0e258086, "IVB IOAT Ch5" }, 201 { 0x0e268086, "IVB IOAT Ch6" }, 202 { 0x0e278086, "IVB IOAT Ch7" }, 203 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" }, 204 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" }, 205 206 { 0x2f208086, "HSW IOAT Ch0" }, 207 { 0x2f218086, "HSW IOAT Ch1" }, 208 { 0x2f228086, "HSW IOAT Ch2" }, 209 { 0x2f238086, "HSW IOAT Ch3" }, 210 { 0x2f248086, "HSW IOAT Ch4" }, 211 { 0x2f258086, "HSW IOAT Ch5" }, 212 { 0x2f268086, "HSW IOAT Ch6" }, 213 { 0x2f278086, "HSW IOAT Ch7" }, 214 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" }, 215 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" }, 216 217 { 0x0c508086, "BWD IOAT Ch0" }, 218 { 0x0c518086, "BWD IOAT Ch1" }, 219 { 0x0c528086, "BWD IOAT Ch2" }, 220 { 0x0c538086, "BWD IOAT Ch3" }, 221 222 { 0x6f508086, "BDXDE IOAT Ch0" }, 223 { 0x6f518086, "BDXDE IOAT Ch1" }, 224 { 0x6f528086, "BDXDE IOAT Ch2" }, 225 { 0x6f538086, "BDXDE IOAT Ch3" }, 226 227 { 0x6f208086, "BDX IOAT Ch0" }, 228 { 0x6f218086, "BDX IOAT Ch1" }, 229 { 0x6f228086, "BDX IOAT Ch2" }, 230 { 0x6f238086, "BDX IOAT Ch3" }, 231 { 0x6f248086, "BDX IOAT Ch4" }, 232 { 0x6f258086, "BDX IOAT Ch5" }, 233 { 0x6f268086, "BDX IOAT Ch6" }, 234 { 0x6f278086, "BDX IOAT Ch7" }, 235 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" }, 236 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" }, 237 238 { 0x00000000, NULL } 239}; 240 241/* 242 * OS <-> Driver linkage functions 243 */ 244static int 245ioat_probe(device_t device) 246{ 247 struct _pcsid *ep; 248 u_int32_t type; 249 250 type = pci_get_devid(device); 251 for (ep = pci_ids; ep->type; ep++) { 252 if (ep->type == type) { 253 device_set_desc(device, ep->desc); 254 return (0); 255 } 256 } 257 return (ENXIO); 258} 259 260static int 261ioat_attach(device_t device) 262{ 263 struct ioat_softc *ioat; 264 int error; 265 266 ioat = DEVICE2SOFTC(device); 267 ioat->device = device; 268 269 error = ioat_map_pci_bar(ioat); 270 if (error != 0) 271 goto err; 272 273 ioat->version = ioat_read_cbver(ioat); 274 if (ioat->version < IOAT_VER_3_0) { 275 error = ENODEV; 276 goto err; 277 } 278 279 error = ioat3_attach(device); 280 if (error != 0) 281 goto err; 282 283 error = pci_enable_busmaster(device); 284 if (error != 0) 285 goto err; 286 287 error = ioat_setup_intr(ioat); 288 if (error != 0) 289 goto err; 290 291 error = ioat_reset_hw(ioat); 292 if (error != 0) 293 goto err; 294 295 ioat_process_events(ioat); 296 ioat_setup_sysctl(device); 297 298 ioat->chan_idx = ioat_channel_index; 299 ioat_channel[ioat_channel_index++] = ioat; 300 ioat_test_attach(); 301 302err: 303 if (error != 0) 304 ioat_detach(device); 305 return (error); 306} 307 308static int 309ioat_detach(device_t device) 310{ 311 struct ioat_softc *ioat; 312 313 ioat = DEVICE2SOFTC(device); 314 315 ioat_test_detach(); 316 taskqueue_drain(taskqueue_thread, &ioat->reset_task); 317 318 mtx_lock(IOAT_REFLK); 319 ioat->quiescing = TRUE; 320 ioat->destroying = TRUE; 321 wakeup(&ioat->quiescing); 322 323 ioat_channel[ioat->chan_idx] = NULL; 324 325 ioat_drain_locked(ioat); 326 mtx_unlock(IOAT_REFLK); 327 328 ioat_teardown_intr(ioat); 329 callout_drain(&ioat->timer); 330 331 pci_disable_busmaster(device); 332 333 if (ioat->pci_resource != NULL) 334 bus_release_resource(device, SYS_RES_MEMORY, 335 ioat->pci_resource_id, ioat->pci_resource); 336 337 if (ioat->ring != NULL) 338 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring); 339 340 if (ioat->comp_update != NULL) { 341 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map); 342 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update, 343 ioat->comp_update_map); 344 bus_dma_tag_destroy(ioat->comp_update_tag); 345 } 346 347 bus_dma_tag_destroy(ioat->hw_desc_tag); 348 349 return (0); 350} 351 352static int 353ioat_teardown_intr(struct ioat_softc *ioat) 354{ 355 356 if (ioat->tag != NULL) 357 bus_teardown_intr(ioat->device, ioat->res, ioat->tag); 358 359 if (ioat->res != NULL) 360 bus_release_resource(ioat->device, SYS_RES_IRQ, 361 rman_get_rid(ioat->res), ioat->res); 362 363 pci_release_msi(ioat->device); 364 return (0); 365} 366 367static int 368ioat_start_channel(struct ioat_softc *ioat) 369{ 370 uint64_t status; 371 uint32_t chanerr; 372 int i; 373 374 ioat_acquire(&ioat->dmaengine); 375 ioat_null(&ioat->dmaengine, NULL, NULL, 0); 376 ioat_release(&ioat->dmaengine); 377 378 for (i = 0; i < 100; i++) { 379 DELAY(1); 380 status = ioat_get_chansts(ioat); 381 if (is_ioat_idle(status)) 382 return (0); 383 } 384 385 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 386 ioat_log_message(0, "could not start channel: " 387 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr, 388 IOAT_CHANERR_STR); 389 return (ENXIO); 390} 391 392/* 393 * Initialize Hardware 394 */ 395static int 396ioat3_attach(device_t device) 397{ 398 struct ioat_softc *ioat; 399 struct ioat_descriptor **ring; 400 struct ioat_descriptor *next; 401 struct ioat_dma_hw_descriptor *dma_hw_desc; 402 int i, num_descriptors; 403 int error; 404 uint8_t xfercap; 405 406 error = 0; 407 ioat = DEVICE2SOFTC(device); 408 ioat->capabilities = ioat_read_dmacapability(ioat); 409 410 ioat_log_message(1, "Capabilities: %b\n", (int)ioat->capabilities, 411 IOAT_DMACAP_STR); 412 413 xfercap = ioat_read_xfercap(ioat); 414 ioat->max_xfer_size = 1 << xfercap; 415 416 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & 417 IOAT_INTRDELAY_SUPPORTED) != 0; 418 if (ioat->intrdelay_supported) 419 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK; 420 421 /* TODO: need to check DCA here if we ever do XOR/PQ */ 422 423 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF); 424 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF); 425 callout_init(&ioat->timer, 1); 426 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat); 427 428 /* Establish lock order for Witness */ 429 mtx_lock(&ioat->submit_lock); 430 mtx_lock(&ioat->cleanup_lock); 431 mtx_unlock(&ioat->cleanup_lock); 432 mtx_unlock(&ioat->submit_lock); 433 434 ioat->is_resize_pending = FALSE; 435 ioat->is_completion_pending = FALSE; 436 ioat->is_reset_pending = FALSE; 437 ioat->is_channel_running = FALSE; 438 439 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0, 440 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 441 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL, 442 &ioat->comp_update_tag); 443 444 error = bus_dmamem_alloc(ioat->comp_update_tag, 445 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map); 446 if (ioat->comp_update == NULL) 447 return (ENOMEM); 448 449 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map, 450 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat, 451 0); 452 if (error != 0) 453 return (error); 454 455 ioat->ring_size_order = IOAT_MIN_ORDER; 456 457 num_descriptors = 1 << ioat->ring_size_order; 458 459 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0, 460 BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL, 461 sizeof(struct ioat_dma_hw_descriptor), 1, 462 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL, 463 &ioat->hw_desc_tag); 464 465 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT, 466 M_ZERO | M_WAITOK); 467 468 ring = ioat->ring; 469 for (i = 0; i < num_descriptors; i++) { 470 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK); 471 if (ring[i] == NULL) 472 return (ENOMEM); 473 474 ring[i]->id = i; 475 } 476 477 for (i = 0; i < num_descriptors - 1; i++) { 478 next = ring[i + 1]; 479 dma_hw_desc = ring[i]->u.dma; 480 481 dma_hw_desc->next = next->hw_desc_bus_addr; 482 } 483 484 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr; 485 486 ioat->head = ioat->hw_head = 0; 487 ioat->tail = 0; 488 ioat->last_seen = 0; 489 return (0); 490} 491 492static int 493ioat_map_pci_bar(struct ioat_softc *ioat) 494{ 495 496 ioat->pci_resource_id = PCIR_BAR(0); 497 ioat->pci_resource = bus_alloc_resource_any(ioat->device, 498 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE); 499 500 if (ioat->pci_resource == NULL) { 501 ioat_log_message(0, "unable to allocate pci resource\n"); 502 return (ENODEV); 503 } 504 505 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource); 506 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource); 507 return (0); 508} 509 510static void 511ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 512{ 513 struct ioat_softc *ioat = arg; 514 515 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 516 ioat->comp_update_bus_addr = seg[0].ds_addr; 517} 518 519static void 520ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 521{ 522 bus_addr_t *baddr; 523 524 KASSERT(error == 0, ("%s: error:%d", __func__, error)); 525 baddr = arg; 526 *baddr = segs->ds_addr; 527} 528 529/* 530 * Interrupt setup and handlers 531 */ 532static int 533ioat_setup_intr(struct ioat_softc *ioat) 534{ 535 uint32_t num_vectors; 536 int error; 537 boolean_t use_msix; 538 boolean_t force_legacy_interrupts; 539 540 use_msix = FALSE; 541 force_legacy_interrupts = FALSE; 542 543 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) { 544 num_vectors = 1; 545 pci_alloc_msix(ioat->device, &num_vectors); 546 if (num_vectors == 1) 547 use_msix = TRUE; 548 } 549 550 if (use_msix) { 551 ioat->rid = 1; 552 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 553 &ioat->rid, RF_ACTIVE); 554 } else { 555 ioat->rid = 0; 556 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ, 557 &ioat->rid, RF_SHAREABLE | RF_ACTIVE); 558 } 559 if (ioat->res == NULL) { 560 ioat_log_message(0, "bus_alloc_resource failed\n"); 561 return (ENOMEM); 562 } 563 564 ioat->tag = NULL; 565 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE | 566 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag); 567 if (error != 0) { 568 ioat_log_message(0, "bus_setup_intr failed\n"); 569 return (error); 570 } 571 572 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN); 573 return (0); 574} 575 576static boolean_t 577ioat_model_resets_msix(struct ioat_softc *ioat) 578{ 579 u_int32_t pciid; 580 581 pciid = pci_get_devid(ioat->device); 582 switch (pciid) { 583 /* BWD: */ 584 case 0x0c508086: 585 case 0x0c518086: 586 case 0x0c528086: 587 case 0x0c538086: 588 /* BDXDE: */ 589 case 0x6f508086: 590 case 0x6f518086: 591 case 0x6f528086: 592 case 0x6f538086: 593 return (TRUE); 594 } 595 596 return (FALSE); 597} 598 599static void 600ioat_interrupt_handler(void *arg) 601{ 602 struct ioat_softc *ioat = arg; 603 604 ioat->stats.interrupts++; 605 ioat_process_events(ioat); 606} 607 608static int 609chanerr_to_errno(uint32_t chanerr) 610{ 611 612 if (chanerr == 0) 613 return (0); 614 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0) 615 return (EFAULT); 616 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0) 617 return (EIO); 618 /* This one is probably our fault: */ 619 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0) 620 return (EIO); 621 return (EIO); 622} 623 624static void 625ioat_process_events(struct ioat_softc *ioat) 626{ 627 struct ioat_descriptor *desc; 628 struct bus_dmadesc *dmadesc; 629 uint64_t comp_update, status; 630 uint32_t completed, chanerr; 631 int error; 632 633 mtx_lock(&ioat->cleanup_lock); 634 635 completed = 0; 636 comp_update = *ioat->comp_update; 637 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK; 638 639 CTR0(KTR_IOAT, __func__); 640 641 if (status == ioat->last_seen) { 642 /* 643 * If we landed in process_events and nothing has been 644 * completed, check for a timeout due to channel halt. 645 */ 646 comp_update = ioat_get_chansts(ioat); 647 goto out; 648 } 649 650 while (1) { 651 desc = ioat_get_ring_entry(ioat, ioat->tail); 652 dmadesc = &desc->bus_dmadesc; 653 CTR1(KTR_IOAT, "completing desc %d", ioat->tail); 654 655 if (dmadesc->callback_fn != NULL) 656 dmadesc->callback_fn(dmadesc->callback_arg, 0); 657 658 completed++; 659 ioat->tail++; 660 if (desc->hw_desc_bus_addr == status) 661 break; 662 } 663 664 ioat->last_seen = desc->hw_desc_bus_addr; 665 666 if (ioat->head == ioat->tail) { 667 ioat->is_completion_pending = FALSE; 668 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 669 ioat_timer_callback, ioat); 670 } 671 672 ioat->stats.descriptors_processed += completed; 673 674out: 675 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 676 mtx_unlock(&ioat->cleanup_lock); 677 678 if (completed != 0) { 679 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF); 680 wakeup(&ioat->tail); 681 } 682 683 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update)) 684 return; 685 686 ioat->stats.channel_halts++; 687 688 /* 689 * Fatal programming error on this DMA channel. Flush any outstanding 690 * work with error status and restart the engine. 691 */ 692 ioat_log_message(0, "Channel halted due to fatal programming error\n"); 693 mtx_lock(&ioat->submit_lock); 694 mtx_lock(&ioat->cleanup_lock); 695 ioat->quiescing = TRUE; 696 697 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 698 ioat_halted_debug(ioat, chanerr); 699 ioat->stats.last_halt_chanerr = chanerr; 700 701 while (ioat_get_active(ioat) > 0) { 702 desc = ioat_get_ring_entry(ioat, ioat->tail); 703 dmadesc = &desc->bus_dmadesc; 704 CTR1(KTR_IOAT, "completing err desc %d", ioat->tail); 705 706 if (dmadesc->callback_fn != NULL) 707 dmadesc->callback_fn(dmadesc->callback_arg, 708 chanerr_to_errno(chanerr)); 709 710 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF); 711 ioat->tail++; 712 ioat->stats.descriptors_processed++; 713 ioat->stats.descriptors_error++; 714 } 715 716 /* Clear error status */ 717 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 718 719 mtx_unlock(&ioat->cleanup_lock); 720 mtx_unlock(&ioat->submit_lock); 721 722 ioat_log_message(0, "Resetting channel to recover from error\n"); 723 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task); 724 KASSERT(error == 0, 725 ("%s: taskqueue_enqueue failed: %d", __func__, error)); 726} 727 728static void 729ioat_reset_hw_task(void *ctx, int pending __unused) 730{ 731 struct ioat_softc *ioat; 732 int error; 733 734 ioat = ctx; 735 ioat_log_message(1, "%s: Resetting channel\n", __func__); 736 737 error = ioat_reset_hw(ioat); 738 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error)); 739 (void)error; 740} 741 742/* 743 * User API functions 744 */ 745bus_dmaengine_t 746ioat_get_dmaengine(uint32_t index, int flags) 747{ 748 struct ioat_softc *ioat; 749 750 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0, 751 ("invalid flags: 0x%08x", flags)); 752 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK), 753 ("invalid wait | nowait")); 754 755 if (index >= ioat_channel_index) 756 return (NULL); 757 758 ioat = ioat_channel[index]; 759 if (ioat == NULL || ioat->destroying) 760 return (NULL); 761 762 if (ioat->quiescing) { 763 if ((flags & M_NOWAIT) != 0) 764 return (NULL); 765 766 mtx_lock(IOAT_REFLK); 767 while (ioat->quiescing && !ioat->destroying) 768 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0); 769 mtx_unlock(IOAT_REFLK); 770 771 if (ioat->destroying) 772 return (NULL); 773 } 774 775 /* 776 * There's a race here between the quiescing check and HW reset or 777 * module destroy. 778 */ 779 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine); 780} 781 782void 783ioat_put_dmaengine(bus_dmaengine_t dmaengine) 784{ 785 struct ioat_softc *ioat; 786 787 ioat = to_ioat_softc(dmaengine); 788 ioat_put(ioat, IOAT_DMAENGINE_REF); 789} 790 791int 792ioat_get_hwversion(bus_dmaengine_t dmaengine) 793{ 794 struct ioat_softc *ioat; 795 796 ioat = to_ioat_softc(dmaengine); 797 return (ioat->version); 798} 799 800size_t 801ioat_get_max_io_size(bus_dmaengine_t dmaengine) 802{ 803 struct ioat_softc *ioat; 804 805 ioat = to_ioat_softc(dmaengine); 806 return (ioat->max_xfer_size); 807} 808 809int 810ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay) 811{ 812 struct ioat_softc *ioat; 813 814 ioat = to_ioat_softc(dmaengine); 815 if (!ioat->intrdelay_supported) 816 return (ENODEV); 817 if (delay > ioat->intrdelay_max) 818 return (ERANGE); 819 820 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay); 821 ioat->cached_intrdelay = 822 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK; 823 return (0); 824} 825 826uint16_t 827ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine) 828{ 829 struct ioat_softc *ioat; 830 831 ioat = to_ioat_softc(dmaengine); 832 return (ioat->intrdelay_max); 833} 834 835void 836ioat_acquire(bus_dmaengine_t dmaengine) 837{ 838 struct ioat_softc *ioat; 839 840 ioat = to_ioat_softc(dmaengine); 841 mtx_lock(&ioat->submit_lock); 842 CTR0(KTR_IOAT, __func__); 843} 844 845int 846ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags) 847{ 848 struct ioat_softc *ioat; 849 int error; 850 851 ioat = to_ioat_softc(dmaengine); 852 ioat_acquire(dmaengine); 853 854 error = ioat_reserve_space(ioat, n, mflags); 855 if (error != 0) 856 ioat_release(dmaengine); 857 return (error); 858} 859 860void 861ioat_release(bus_dmaengine_t dmaengine) 862{ 863 struct ioat_softc *ioat; 864 865 ioat = to_ioat_softc(dmaengine); 866 CTR0(KTR_IOAT, __func__); 867 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head); 868 mtx_unlock(&ioat->submit_lock); 869} 870 871static struct ioat_descriptor * 872ioat_op_generic(struct ioat_softc *ioat, uint8_t op, 873 uint32_t size, uint64_t src, uint64_t dst, 874 bus_dmaengine_callback_t callback_fn, void *callback_arg, 875 uint32_t flags) 876{ 877 struct ioat_generic_hw_descriptor *hw_desc; 878 struct ioat_descriptor *desc; 879 int mflags; 880 881 mtx_assert(&ioat->submit_lock, MA_OWNED); 882 883 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0, 884 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS)); 885 if ((flags & DMA_NO_WAIT) != 0) 886 mflags = M_NOWAIT; 887 else 888 mflags = M_WAITOK; 889 890 if (size > ioat->max_xfer_size) { 891 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n", 892 __func__, ioat->max_xfer_size, (unsigned)size); 893 return (NULL); 894 } 895 896 if (ioat_reserve_space(ioat, 1, mflags) != 0) 897 return (NULL); 898 899 desc = ioat_get_ring_entry(ioat, ioat->head); 900 hw_desc = desc->u.generic; 901 902 hw_desc->u.control_raw = 0; 903 hw_desc->u.control_generic.op = op; 904 hw_desc->u.control_generic.completion_update = 1; 905 906 if ((flags & DMA_INT_EN) != 0) 907 hw_desc->u.control_generic.int_enable = 1; 908 if ((flags & DMA_FENCE) != 0) 909 hw_desc->u.control_generic.fence = 1; 910 911 hw_desc->size = size; 912 hw_desc->src_addr = src; 913 hw_desc->dest_addr = dst; 914 915 desc->bus_dmadesc.callback_fn = callback_fn; 916 desc->bus_dmadesc.callback_arg = callback_arg; 917 return (desc); 918} 919 920struct bus_dmadesc * 921ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn, 922 void *callback_arg, uint32_t flags) 923{ 924 struct ioat_dma_hw_descriptor *hw_desc; 925 struct ioat_descriptor *desc; 926 struct ioat_softc *ioat; 927 928 CTR0(KTR_IOAT, __func__); 929 ioat = to_ioat_softc(dmaengine); 930 931 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn, 932 callback_arg, flags); 933 if (desc == NULL) 934 return (NULL); 935 936 hw_desc = desc->u.dma; 937 hw_desc->u.control.null = 1; 938 ioat_submit_single(ioat); 939 return (&desc->bus_dmadesc); 940} 941 942struct bus_dmadesc * 943ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst, 944 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn, 945 void *callback_arg, uint32_t flags) 946{ 947 struct ioat_dma_hw_descriptor *hw_desc; 948 struct ioat_descriptor *desc; 949 struct ioat_softc *ioat; 950 951 CTR0(KTR_IOAT, __func__); 952 ioat = to_ioat_softc(dmaengine); 953 954 if (((src | dst) & (0xffffull << 48)) != 0) { 955 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 956 __func__); 957 return (NULL); 958 } 959 960 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn, 961 callback_arg, flags); 962 if (desc == NULL) 963 return (NULL); 964 965 hw_desc = desc->u.dma; 966 if (g_ioat_debug_level >= 3) 967 dump_descriptor(hw_desc); 968 969 ioat_submit_single(ioat); 970 return (&desc->bus_dmadesc); 971} 972 973struct bus_dmadesc * 974ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1, 975 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2, 976 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 977{ 978 struct ioat_dma_hw_descriptor *hw_desc; 979 struct ioat_descriptor *desc; 980 struct ioat_softc *ioat; 981 982 CTR0(KTR_IOAT, __func__); 983 ioat = to_ioat_softc(dmaengine); 984 985 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) { 986 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n", 987 __func__); 988 return (NULL); 989 } 990 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) { 991 ioat_log_message(0, "%s: Addresses must be page-aligned\n", 992 __func__); 993 return (NULL); 994 } 995 996 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1, 997 callback_fn, callback_arg, flags); 998 if (desc == NULL) 999 return (NULL); 1000 1001 hw_desc = desc->u.dma; 1002 if (src2 != src1 + PAGE_SIZE) { 1003 hw_desc->u.control.src_page_break = 1; 1004 hw_desc->next_src_addr = src2; 1005 } 1006 if (dst2 != dst1 + PAGE_SIZE) { 1007 hw_desc->u.control.dest_page_break = 1; 1008 hw_desc->next_dest_addr = dst2; 1009 } 1010 1011 if (g_ioat_debug_level >= 3) 1012 dump_descriptor(hw_desc); 1013 1014 ioat_submit_single(ioat); 1015 return (&desc->bus_dmadesc); 1016} 1017 1018struct bus_dmadesc * 1019ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src, 1020 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr, 1021 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1022{ 1023 struct ioat_crc32_hw_descriptor *hw_desc; 1024 struct ioat_descriptor *desc; 1025 struct ioat_softc *ioat; 1026 uint32_t teststore; 1027 uint8_t op; 1028 1029 CTR0(KTR_IOAT, __func__); 1030 ioat = to_ioat_softc(dmaengine); 1031 1032 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) { 1033 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n", 1034 __func__); 1035 return (NULL); 1036 } 1037 if (((src | dst) & (0xffffffull << 40)) != 0) { 1038 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n", 1039 __func__); 1040 return (NULL); 1041 } 1042 teststore = (flags & _DMA_CRC_TESTSTORE); 1043 if (teststore == _DMA_CRC_TESTSTORE) { 1044 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1045 return (NULL); 1046 } 1047 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1048 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1049 __func__); 1050 return (NULL); 1051 } 1052 1053 switch (teststore) { 1054 case DMA_CRC_STORE: 1055 op = IOAT_OP_MOVECRC_STORE; 1056 break; 1057 case DMA_CRC_TEST: 1058 op = IOAT_OP_MOVECRC_TEST; 1059 break; 1060 default: 1061 KASSERT(teststore == 0, ("bogus")); 1062 op = IOAT_OP_MOVECRC; 1063 break; 1064 } 1065 1066 if ((flags & DMA_CRC_INLINE) == 0 && 1067 (crcptr & (0xffffffull << 40)) != 0) { 1068 ioat_log_message(0, 1069 "%s: High 24 bits of crcptr invalid\n", __func__); 1070 return (NULL); 1071 } 1072 1073 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn, 1074 callback_arg, flags & ~_DMA_CRC_FLAGS); 1075 if (desc == NULL) 1076 return (NULL); 1077 1078 hw_desc = desc->u.crc32; 1079 1080 if ((flags & DMA_CRC_INLINE) == 0) 1081 hw_desc->crc_address = crcptr; 1082 else 1083 hw_desc->u.control.crc_location = 1; 1084 1085 if (initialseed != NULL) { 1086 hw_desc->u.control.use_seed = 1; 1087 hw_desc->seed = *initialseed; 1088 } 1089 1090 if (g_ioat_debug_level >= 3) 1091 dump_descriptor(hw_desc); 1092 1093 ioat_submit_single(ioat); 1094 return (&desc->bus_dmadesc); 1095} 1096 1097struct bus_dmadesc * 1098ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len, 1099 uint32_t *initialseed, bus_addr_t crcptr, 1100 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags) 1101{ 1102 struct ioat_crc32_hw_descriptor *hw_desc; 1103 struct ioat_descriptor *desc; 1104 struct ioat_softc *ioat; 1105 uint32_t teststore; 1106 uint8_t op; 1107 1108 CTR0(KTR_IOAT, __func__); 1109 ioat = to_ioat_softc(dmaengine); 1110 1111 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) { 1112 ioat_log_message(0, "%s: Device lacks CRC capability\n", 1113 __func__); 1114 return (NULL); 1115 } 1116 if ((src & (0xffffffull << 40)) != 0) { 1117 ioat_log_message(0, "%s: High 24 bits of src invalid\n", 1118 __func__); 1119 return (NULL); 1120 } 1121 teststore = (flags & _DMA_CRC_TESTSTORE); 1122 if (teststore == _DMA_CRC_TESTSTORE) { 1123 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__); 1124 return (NULL); 1125 } 1126 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) { 1127 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n", 1128 __func__); 1129 return (NULL); 1130 } 1131 1132 switch (teststore) { 1133 case DMA_CRC_STORE: 1134 op = IOAT_OP_CRC_STORE; 1135 break; 1136 case DMA_CRC_TEST: 1137 op = IOAT_OP_CRC_TEST; 1138 break; 1139 default: 1140 KASSERT(teststore == 0, ("bogus")); 1141 op = IOAT_OP_CRC; 1142 break; 1143 } 1144 1145 if ((flags & DMA_CRC_INLINE) == 0 && 1146 (crcptr & (0xffffffull << 40)) != 0) { 1147 ioat_log_message(0, 1148 "%s: High 24 bits of crcptr invalid\n", __func__); 1149 return (NULL); 1150 } 1151 1152 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn, 1153 callback_arg, flags & ~_DMA_CRC_FLAGS); 1154 if (desc == NULL) 1155 return (NULL); 1156 1157 hw_desc = desc->u.crc32; 1158 1159 if ((flags & DMA_CRC_INLINE) == 0) 1160 hw_desc->crc_address = crcptr; 1161 else 1162 hw_desc->u.control.crc_location = 1; 1163 1164 if (initialseed != NULL) { 1165 hw_desc->u.control.use_seed = 1; 1166 hw_desc->seed = *initialseed; 1167 } 1168 1169 if (g_ioat_debug_level >= 3) 1170 dump_descriptor(hw_desc); 1171 1172 ioat_submit_single(ioat); 1173 return (&desc->bus_dmadesc); 1174} 1175 1176struct bus_dmadesc * 1177ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern, 1178 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg, 1179 uint32_t flags) 1180{ 1181 struct ioat_fill_hw_descriptor *hw_desc; 1182 struct ioat_descriptor *desc; 1183 struct ioat_softc *ioat; 1184 1185 CTR0(KTR_IOAT, __func__); 1186 ioat = to_ioat_softc(dmaengine); 1187 1188 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) { 1189 ioat_log_message(0, "%s: Device lacks BFILL capability\n", 1190 __func__); 1191 return (NULL); 1192 } 1193 1194 if ((dst & (0xffffull << 48)) != 0) { 1195 ioat_log_message(0, "%s: High 16 bits of dst invalid\n", 1196 __func__); 1197 return (NULL); 1198 } 1199 1200 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst, 1201 callback_fn, callback_arg, flags); 1202 if (desc == NULL) 1203 return (NULL); 1204 1205 hw_desc = desc->u.fill; 1206 if (g_ioat_debug_level >= 3) 1207 dump_descriptor(hw_desc); 1208 1209 ioat_submit_single(ioat); 1210 return (&desc->bus_dmadesc); 1211} 1212 1213/* 1214 * Ring Management 1215 */ 1216static inline uint32_t 1217ioat_get_active(struct ioat_softc *ioat) 1218{ 1219 1220 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1)); 1221} 1222 1223static inline uint32_t 1224ioat_get_ring_space(struct ioat_softc *ioat) 1225{ 1226 1227 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1); 1228} 1229 1230static struct ioat_descriptor * 1231ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags) 1232{ 1233 struct ioat_generic_hw_descriptor *hw_desc; 1234 struct ioat_descriptor *desc; 1235 int error, busdmaflag; 1236 1237 error = ENOMEM; 1238 hw_desc = NULL; 1239 1240 if ((mflags & M_WAITOK) != 0) 1241 busdmaflag = BUS_DMA_WAITOK; 1242 else 1243 busdmaflag = BUS_DMA_NOWAIT; 1244 1245 desc = malloc(sizeof(*desc), M_IOAT, mflags); 1246 if (desc == NULL) 1247 goto out; 1248 1249 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, 1250 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map); 1251 if (hw_desc == NULL) 1252 goto out; 1253 1254 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc)); 1255 desc->u.generic = hw_desc; 1256 1257 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc, 1258 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 1259 busdmaflag); 1260 if (error) 1261 goto out; 1262 1263out: 1264 if (error) { 1265 ioat_free_ring_entry(ioat, desc); 1266 return (NULL); 1267 } 1268 return (desc); 1269} 1270 1271static void 1272ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc) 1273{ 1274 1275 if (desc == NULL) 1276 return; 1277 1278 if (desc->u.generic) 1279 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic, 1280 ioat->hw_desc_map); 1281 free(desc, M_IOAT); 1282} 1283 1284/* 1285 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain 1286 * for 'num_descs'. 1287 * 1288 * If mflags contains M_WAITOK, blocks until enough space is available. 1289 * 1290 * Returns zero on success, or an errno on error. If num_descs is beyond the 1291 * maximum ring size, returns EINVAl; if allocation would block and mflags 1292 * contains M_NOWAIT, returns EAGAIN. 1293 * 1294 * Must be called with the submit_lock held; returns with the lock held. The 1295 * lock may be dropped to allocate the ring. 1296 * 1297 * (The submit_lock is needed to add any entries to the ring, so callers are 1298 * assured enough room is available.) 1299 */ 1300static int 1301ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags) 1302{ 1303 struct ioat_descriptor **new_ring; 1304 uint32_t order; 1305 int error; 1306 1307 mtx_assert(&ioat->submit_lock, MA_OWNED); 1308 error = 0; 1309 1310 if (num_descs < 1 || num_descs > (1 << IOAT_MAX_ORDER)) { 1311 error = EINVAL; 1312 goto out; 1313 } 1314 if (ioat->quiescing) { 1315 error = ENXIO; 1316 goto out; 1317 } 1318 1319 for (;;) { 1320 if (ioat_get_ring_space(ioat) >= num_descs) 1321 goto out; 1322 1323 order = ioat->ring_size_order; 1324 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) { 1325 if ((mflags & M_WAITOK) != 0) { 1326 msleep(&ioat->tail, &ioat->submit_lock, 0, 1327 "ioat_rsz", 0); 1328 continue; 1329 } 1330 1331 error = EAGAIN; 1332 break; 1333 } 1334 1335 ioat->is_resize_pending = TRUE; 1336 for (;;) { 1337 mtx_unlock(&ioat->submit_lock); 1338 1339 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1), 1340 TRUE, mflags); 1341 1342 mtx_lock(&ioat->submit_lock); 1343 KASSERT(ioat->ring_size_order == order, 1344 ("is_resize_pending should protect order")); 1345 1346 if (new_ring == NULL) { 1347 KASSERT((mflags & M_WAITOK) == 0, 1348 ("allocation failed")); 1349 error = EAGAIN; 1350 break; 1351 } 1352 1353 error = ring_grow(ioat, order, new_ring); 1354 if (error == 0) 1355 break; 1356 } 1357 ioat->is_resize_pending = FALSE; 1358 wakeup(&ioat->tail); 1359 if (error) 1360 break; 1361 } 1362 1363out: 1364 mtx_assert(&ioat->submit_lock, MA_OWNED); 1365 return (error); 1366} 1367 1368static struct ioat_descriptor ** 1369ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr, 1370 int mflags) 1371{ 1372 struct ioat_descriptor **ring; 1373 uint32_t i; 1374 int error; 1375 1376 KASSERT(size > 0 && powerof2(size), ("bogus size")); 1377 1378 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags); 1379 if (ring == NULL) 1380 return (NULL); 1381 1382 if (need_dscr) { 1383 error = ENOMEM; 1384 for (i = size / 2; i < size; i++) { 1385 ring[i] = ioat_alloc_ring_entry(ioat, mflags); 1386 if (ring[i] == NULL) 1387 goto out; 1388 ring[i]->id = i; 1389 } 1390 } 1391 error = 0; 1392 1393out: 1394 if (error != 0 && ring != NULL) { 1395 ioat_free_ring(ioat, size, ring); 1396 ring = NULL; 1397 } 1398 return (ring); 1399} 1400 1401static void 1402ioat_free_ring(struct ioat_softc *ioat, uint32_t size, 1403 struct ioat_descriptor **ring) 1404{ 1405 uint32_t i; 1406 1407 for (i = 0; i < size; i++) { 1408 if (ring[i] != NULL) 1409 ioat_free_ring_entry(ioat, ring[i]); 1410 } 1411 free(ring, M_IOAT); 1412} 1413 1414static struct ioat_descriptor * 1415ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index) 1416{ 1417 1418 return (ioat->ring[index % (1 << ioat->ring_size_order)]); 1419} 1420 1421static int 1422ring_grow(struct ioat_softc *ioat, uint32_t oldorder, 1423 struct ioat_descriptor **newring) 1424{ 1425 struct ioat_descriptor *tmp, *next; 1426 struct ioat_dma_hw_descriptor *hw; 1427 uint32_t oldsize, newsize, head, tail, i, end; 1428 int error; 1429 1430 CTR0(KTR_IOAT, __func__); 1431 1432 mtx_assert(&ioat->submit_lock, MA_OWNED); 1433 1434 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) { 1435 error = EINVAL; 1436 goto out; 1437 } 1438 1439 oldsize = (1 << oldorder); 1440 newsize = (1 << (oldorder + 1)); 1441 1442 mtx_lock(&ioat->cleanup_lock); 1443 1444 head = ioat->head & (oldsize - 1); 1445 tail = ioat->tail & (oldsize - 1); 1446 1447 /* Copy old descriptors to new ring */ 1448 for (i = 0; i < oldsize; i++) 1449 newring[i] = ioat->ring[i]; 1450 1451 /* 1452 * If head has wrapped but tail hasn't, we must swap some descriptors 1453 * around so that tail can increment directly to head. 1454 */ 1455 if (head < tail) { 1456 for (i = 0; i <= head; i++) { 1457 tmp = newring[oldsize + i]; 1458 1459 newring[oldsize + i] = newring[i]; 1460 newring[oldsize + i]->id = oldsize + i; 1461 1462 newring[i] = tmp; 1463 newring[i]->id = i; 1464 } 1465 head += oldsize; 1466 } 1467 1468 KASSERT(head >= tail, ("invariants")); 1469 1470 /* Head didn't wrap; we only need to link in oldsize..newsize */ 1471 if (head < oldsize) { 1472 i = oldsize - 1; 1473 end = newsize; 1474 } else { 1475 /* Head did wrap; link newhead..newsize and 0..oldhead */ 1476 i = head; 1477 end = newsize + (head - oldsize) + 1; 1478 } 1479 1480 /* 1481 * Fix up hardware ring, being careful not to trample the active 1482 * section (tail -> head). 1483 */ 1484 for (; i < end; i++) { 1485 KASSERT((i & (newsize - 1)) < tail || 1486 (i & (newsize - 1)) >= head, ("trampling snake")); 1487 1488 next = newring[(i + 1) & (newsize - 1)]; 1489 hw = newring[i & (newsize - 1)]->u.dma; 1490 hw->next = next->hw_desc_bus_addr; 1491 } 1492 1493 free(ioat->ring, M_IOAT); 1494 ioat->ring = newring; 1495 ioat->ring_size_order = oldorder + 1; 1496 ioat->tail = tail; 1497 ioat->head = head; 1498 error = 0; 1499 1500 mtx_unlock(&ioat->cleanup_lock); 1501out: 1502 if (error) 1503 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring); 1504 return (error); 1505} 1506 1507static int 1508ring_shrink(struct ioat_softc *ioat, uint32_t oldorder, 1509 struct ioat_descriptor **newring) 1510{ 1511 struct ioat_dma_hw_descriptor *hw; 1512 struct ioat_descriptor *ent, *next; 1513 uint32_t oldsize, newsize, current_idx, new_idx, i; 1514 int error; 1515 1516 CTR0(KTR_IOAT, __func__); 1517 1518 mtx_assert(&ioat->submit_lock, MA_OWNED); 1519 1520 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) { 1521 error = EINVAL; 1522 goto out_unlocked; 1523 } 1524 1525 oldsize = (1 << oldorder); 1526 newsize = (1 << (oldorder - 1)); 1527 1528 mtx_lock(&ioat->cleanup_lock); 1529 1530 /* Can't shrink below current active set! */ 1531 if (ioat_get_active(ioat) >= newsize) { 1532 error = ENOMEM; 1533 goto out; 1534 } 1535 1536 /* 1537 * Copy current descriptors to the new ring, dropping the removed 1538 * descriptors. 1539 */ 1540 for (i = 0; i < newsize; i++) { 1541 current_idx = (ioat->tail + i) & (oldsize - 1); 1542 new_idx = (ioat->tail + i) & (newsize - 1); 1543 1544 newring[new_idx] = ioat->ring[current_idx]; 1545 newring[new_idx]->id = new_idx; 1546 } 1547 1548 /* Free deleted descriptors */ 1549 for (i = newsize; i < oldsize; i++) { 1550 ent = ioat_get_ring_entry(ioat, ioat->tail + i); 1551 ioat_free_ring_entry(ioat, ent); 1552 } 1553 1554 /* Fix up hardware ring. */ 1555 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma; 1556 next = newring[(ioat->tail + newsize) & (newsize - 1)]; 1557 hw->next = next->hw_desc_bus_addr; 1558 1559 free(ioat->ring, M_IOAT); 1560 ioat->ring = newring; 1561 ioat->ring_size_order = oldorder - 1; 1562 error = 0; 1563 1564out: 1565 mtx_unlock(&ioat->cleanup_lock); 1566out_unlocked: 1567 if (error) 1568 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring); 1569 return (error); 1570} 1571 1572static void 1573ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr) 1574{ 1575 struct ioat_descriptor *desc; 1576 1577 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr, 1578 IOAT_CHANERR_STR); 1579 if (chanerr == 0) 1580 return; 1581 1582 mtx_assert(&ioat->cleanup_lock, MA_OWNED); 1583 1584 desc = ioat_get_ring_entry(ioat, ioat->tail + 0); 1585 dump_descriptor(desc->u.raw); 1586 1587 desc = ioat_get_ring_entry(ioat, ioat->tail + 1); 1588 dump_descriptor(desc->u.raw); 1589} 1590 1591static void 1592ioat_timer_callback(void *arg) 1593{ 1594 struct ioat_descriptor **newring; 1595 struct ioat_softc *ioat; 1596 uint32_t order; 1597 1598 ioat = arg; 1599 ioat_log_message(1, "%s\n", __func__); 1600 1601 if (ioat->is_completion_pending) { 1602 ioat_process_events(ioat); 1603 return; 1604 } 1605 1606 /* Slowly scale the ring down if idle. */ 1607 mtx_lock(&ioat->submit_lock); 1608 order = ioat->ring_size_order; 1609 if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) { 1610 mtx_unlock(&ioat->submit_lock); 1611 goto out; 1612 } 1613 ioat->is_resize_pending = TRUE; 1614 mtx_unlock(&ioat->submit_lock); 1615 1616 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE, 1617 M_NOWAIT); 1618 1619 mtx_lock(&ioat->submit_lock); 1620 KASSERT(ioat->ring_size_order == order, 1621 ("resize_pending protects order")); 1622 1623 if (newring != NULL) 1624 ring_shrink(ioat, order, newring); 1625 1626 ioat->is_resize_pending = FALSE; 1627 mtx_unlock(&ioat->submit_lock); 1628 1629out: 1630 if (ioat->ring_size_order > IOAT_MIN_ORDER) 1631 callout_reset(&ioat->timer, 10 * hz, 1632 ioat_timer_callback, ioat); 1633} 1634 1635/* 1636 * Support Functions 1637 */ 1638static void 1639ioat_submit_single(struct ioat_softc *ioat) 1640{ 1641 1642 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF); 1643 atomic_add_rel_int(&ioat->head, 1); 1644 atomic_add_rel_int(&ioat->hw_head, 1); 1645 1646 if (!ioat->is_completion_pending) { 1647 ioat->is_completion_pending = TRUE; 1648 callout_reset(&ioat->timer, IOAT_INTR_TIMO, 1649 ioat_timer_callback, ioat); 1650 } 1651 1652 ioat->stats.descriptors_submitted++; 1653} 1654 1655static int 1656ioat_reset_hw(struct ioat_softc *ioat) 1657{ 1658 uint64_t status; 1659 uint32_t chanerr; 1660 unsigned timeout; 1661 int error; 1662 1663 mtx_lock(IOAT_REFLK); 1664 ioat->quiescing = TRUE; 1665 ioat_drain_locked(ioat); 1666 mtx_unlock(IOAT_REFLK); 1667 1668 status = ioat_get_chansts(ioat); 1669 if (is_ioat_active(status) || is_ioat_idle(status)) 1670 ioat_suspend(ioat); 1671 1672 /* Wait at most 20 ms */ 1673 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) && 1674 timeout < 20; timeout++) { 1675 DELAY(1000); 1676 status = ioat_get_chansts(ioat); 1677 } 1678 if (timeout == 20) { 1679 error = ETIMEDOUT; 1680 goto out; 1681 } 1682 1683 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce")); 1684 1685 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1686 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr); 1687 1688 /* 1689 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors 1690 * that can cause stability issues for IOAT v3. 1691 */ 1692 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07, 1693 4); 1694 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4); 1695 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4); 1696 1697 /* 1698 * BDXDE and BWD models reset MSI-X registers on device reset. 1699 * Save/restore their contents manually. 1700 */ 1701 if (ioat_model_resets_msix(ioat)) { 1702 ioat_log_message(1, "device resets MSI-X registers; saving\n"); 1703 pci_save_state(ioat->device); 1704 } 1705 1706 ioat_reset(ioat); 1707 1708 /* Wait at most 20 ms */ 1709 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++) 1710 DELAY(1000); 1711 if (timeout == 20) { 1712 error = ETIMEDOUT; 1713 goto out; 1714 } 1715 1716 if (ioat_model_resets_msix(ioat)) { 1717 ioat_log_message(1, "device resets registers; restored\n"); 1718 pci_restore_state(ioat->device); 1719 } 1720 1721 /* Reset attempts to return the hardware to "halted." */ 1722 status = ioat_get_chansts(ioat); 1723 if (is_ioat_active(status) || is_ioat_idle(status)) { 1724 /* So this really shouldn't happen... */ 1725 ioat_log_message(0, "Device is active after a reset?\n"); 1726 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1727 error = 0; 1728 goto out; 1729 } 1730 1731 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET); 1732 if (chanerr != 0) { 1733 mtx_lock(&ioat->cleanup_lock); 1734 ioat_halted_debug(ioat, chanerr); 1735 mtx_unlock(&ioat->cleanup_lock); 1736 error = EIO; 1737 goto out; 1738 } 1739 1740 /* 1741 * Bring device back online after reset. Writing CHAINADDR brings the 1742 * device back to active. 1743 * 1744 * The internal ring counter resets to zero, so we have to start over 1745 * at zero as well. 1746 */ 1747 ioat->tail = ioat->head = ioat->hw_head = 0; 1748 ioat->last_seen = 0; 1749 1750 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN); 1751 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr); 1752 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr); 1753 error = 0; 1754 1755out: 1756 mtx_lock(IOAT_REFLK); 1757 ioat->quiescing = FALSE; 1758 wakeup(&ioat->quiescing); 1759 mtx_unlock(IOAT_REFLK); 1760 1761 if (error == 0) 1762 error = ioat_start_channel(ioat); 1763 1764 return (error); 1765} 1766 1767static int 1768sysctl_handle_chansts(SYSCTL_HANDLER_ARGS) 1769{ 1770 struct ioat_softc *ioat; 1771 struct sbuf sb; 1772 uint64_t status; 1773 int error; 1774 1775 ioat = arg1; 1776 1777 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS; 1778 1779 sbuf_new_for_sysctl(&sb, NULL, 256, req); 1780 switch (status) { 1781 case IOAT_CHANSTS_ACTIVE: 1782 sbuf_printf(&sb, "ACTIVE"); 1783 break; 1784 case IOAT_CHANSTS_IDLE: 1785 sbuf_printf(&sb, "IDLE"); 1786 break; 1787 case IOAT_CHANSTS_SUSPENDED: 1788 sbuf_printf(&sb, "SUSPENDED"); 1789 break; 1790 case IOAT_CHANSTS_HALTED: 1791 sbuf_printf(&sb, "HALTED"); 1792 break; 1793 case IOAT_CHANSTS_ARMED: 1794 sbuf_printf(&sb, "ARMED"); 1795 break; 1796 default: 1797 sbuf_printf(&sb, "UNKNOWN"); 1798 break; 1799 } 1800 error = sbuf_finish(&sb); 1801 sbuf_delete(&sb); 1802 1803 if (error != 0 || req->newptr == NULL) 1804 return (error); 1805 return (EINVAL); 1806} 1807 1808static int 1809sysctl_handle_dpi(SYSCTL_HANDLER_ARGS) 1810{ 1811 struct ioat_softc *ioat; 1812 struct sbuf sb; 1813#define PRECISION "1" 1814 const uintmax_t factor = 10; 1815 uintmax_t rate; 1816 int error; 1817 1818 ioat = arg1; 1819 sbuf_new_for_sysctl(&sb, NULL, 16, req); 1820 1821 if (ioat->stats.interrupts == 0) { 1822 sbuf_printf(&sb, "NaN"); 1823 goto out; 1824 } 1825 rate = ioat->stats.descriptors_processed * factor / 1826 ioat->stats.interrupts; 1827 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor, 1828 rate % factor); 1829#undef PRECISION 1830out: 1831 error = sbuf_finish(&sb); 1832 sbuf_delete(&sb); 1833 if (error != 0 || req->newptr == NULL) 1834 return (error); 1835 return (EINVAL); 1836} 1837 1838static int 1839sysctl_handle_error(SYSCTL_HANDLER_ARGS) 1840{ 1841 struct ioat_descriptor *desc; 1842 struct ioat_softc *ioat; 1843 int error, arg; 1844 1845 ioat = arg1; 1846 1847 arg = 0; 1848 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1849 if (error != 0 || req->newptr == NULL) 1850 return (error); 1851 1852 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1853 if (error != 0) 1854 return (error); 1855 1856 if (arg != 0) { 1857 ioat_acquire(&ioat->dmaengine); 1858 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 1, 1859 0xffff000000000000ull, 0xffff000000000000ull, NULL, NULL, 1860 0); 1861 if (desc == NULL) 1862 error = ENOMEM; 1863 else 1864 ioat_submit_single(ioat); 1865 ioat_release(&ioat->dmaengine); 1866 } 1867 return (error); 1868} 1869 1870static int 1871sysctl_handle_reset(SYSCTL_HANDLER_ARGS) 1872{ 1873 struct ioat_softc *ioat; 1874 int error, arg; 1875 1876 ioat = arg1; 1877 1878 arg = 0; 1879 error = SYSCTL_OUT(req, &arg, sizeof(arg)); 1880 if (error != 0 || req->newptr == NULL) 1881 return (error); 1882 1883 error = SYSCTL_IN(req, &arg, sizeof(arg)); 1884 if (error != 0) 1885 return (error); 1886 1887 if (arg != 0) 1888 error = ioat_reset_hw(ioat); 1889 1890 return (error); 1891} 1892 1893static void 1894dump_descriptor(void *hw_desc) 1895{ 1896 int i, j; 1897 1898 for (i = 0; i < 2; i++) { 1899 for (j = 0; j < 8; j++) 1900 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]); 1901 printf("\n"); 1902 } 1903} 1904 1905static void 1906ioat_setup_sysctl(device_t device) 1907{ 1908 struct sysctl_oid_list *par, *statpar, *state, *hammer; 1909 struct sysctl_ctx_list *ctx; 1910 struct sysctl_oid *tree, *tmp; 1911 struct ioat_softc *ioat; 1912 1913 ioat = DEVICE2SOFTC(device); 1914 ctx = device_get_sysctl_ctx(device); 1915 tree = device_get_sysctl_tree(device); 1916 par = SYSCTL_CHILDREN(tree); 1917 1918 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD, 1919 &ioat->version, 0, "HW version (0xMM form)"); 1920 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD, 1921 &ioat->max_xfer_size, 0, "HW maximum transfer size"); 1922 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD, 1923 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported"); 1924#ifdef notyet 1925 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD, 1926 &ioat->intrdelay_max, 0, 1927 "Maximum configurable INTRDELAY on this channel (microseconds)"); 1928#endif 1929 1930 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL, 1931 "IOAT channel internal state"); 1932 state = SYSCTL_CHILDREN(tmp); 1933 1934 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD, 1935 &ioat->ring_size_order, 0, "SW descriptor ring size order"); 1936 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head, 1937 0, "SW descriptor head pointer index"); 1938 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail, 1939 0, "SW descriptor tail pointer index"); 1940 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD, 1941 &ioat->hw_head, 0, "HW DMACOUNT"); 1942 1943 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD, 1944 ioat->comp_update, "HW addr of last completion"); 1945 1946 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD, 1947 &ioat->is_resize_pending, 0, "resize pending"); 1948 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending", 1949 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending"); 1950 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD, 1951 &ioat->is_reset_pending, 0, "reset pending"); 1952 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD, 1953 &ioat->is_channel_running, 0, "channel running"); 1954 1955 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts", 1956 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A", 1957 "String of the channel status"); 1958 1959#ifdef notyet 1960 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD, 1961 &ioat->cached_intrdelay, 0, 1962 "Current INTRDELAY on this channel (cached, microseconds)"); 1963#endif 1964 1965 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL, 1966 "Big hammers (mostly for testing)"); 1967 hammer = SYSCTL_CHILDREN(tmp); 1968 1969 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset", 1970 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I", 1971 "Set to non-zero to reset the hardware"); 1972 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_error", 1973 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_error, "I", 1974 "Set to non-zero to inject a recoverable hardware error"); 1975 1976 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL, 1977 "IOAT channel statistics"); 1978 statpar = SYSCTL_CHILDREN(tmp); 1979 1980 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW, 1981 &ioat->stats.interrupts, 1982 "Number of interrupts processed on this channel"); 1983 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW, 1984 &ioat->stats.descriptors_processed, 1985 "Number of descriptors processed on this channel"); 1986 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW, 1987 &ioat->stats.descriptors_submitted, 1988 "Number of descriptors submitted to this channel"); 1989 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW, 1990 &ioat->stats.descriptors_error, 1991 "Number of descriptors failed by channel errors"); 1992#ifdef notyet 1993 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW, 1994 &ioat->stats.channel_halts, 0, 1995 "Number of times the channel has halted"); 1996 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW, 1997 &ioat->stats.last_halt_chanerr, 0, 1998 "The raw CHANERR when the channel was last halted"); 1999#endif 2000 2001 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt", 2002 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A", 2003 "Descriptors per interrupt"); 2004} 2005 2006static inline struct ioat_softc * 2007ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2008{ 2009 uint32_t old; 2010 2011 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2012 2013 old = atomic_fetchadd_32(&ioat->refcnt, 1); 2014 KASSERT(old < UINT32_MAX, ("refcnt overflow")); 2015 2016#ifdef INVARIANTS 2017 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1); 2018 KASSERT(old < UINT32_MAX, ("refcnt kind overflow")); 2019#endif 2020 2021 return (ioat); 2022} 2023 2024static inline void 2025ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2026{ 2027 2028 _ioat_putn(ioat, n, kind, FALSE); 2029} 2030 2031static inline void 2032ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind) 2033{ 2034 2035 _ioat_putn(ioat, n, kind, TRUE); 2036} 2037 2038static inline void 2039_ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind, 2040 boolean_t locked) 2041{ 2042 uint32_t old; 2043 2044 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus")); 2045 2046 if (n == 0) 2047 return; 2048 2049#ifdef INVARIANTS 2050 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n); 2051 KASSERT(old >= n, ("refcnt kind underflow")); 2052#endif 2053 2054 /* Skip acquiring the lock if resulting refcnt > 0. */ 2055 for (;;) { 2056 old = ioat->refcnt; 2057 if (old <= n) 2058 break; 2059 if (atomic_cmpset_32(&ioat->refcnt, old, old - n)) 2060 return; 2061 } 2062 2063 if (locked) 2064 mtx_assert(IOAT_REFLK, MA_OWNED); 2065 else 2066 mtx_lock(IOAT_REFLK); 2067 2068 old = atomic_fetchadd_32(&ioat->refcnt, -n); 2069 KASSERT(old >= n, ("refcnt error")); 2070 2071 if (old == n) 2072 wakeup(IOAT_REFLK); 2073 if (!locked) 2074 mtx_unlock(IOAT_REFLK); 2075} 2076 2077static inline void 2078ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind) 2079{ 2080 2081 ioat_putn(ioat, 1, kind); 2082} 2083 2084static void 2085ioat_drain_locked(struct ioat_softc *ioat) 2086{ 2087 2088 mtx_assert(IOAT_REFLK, MA_OWNED); 2089 while (ioat->refcnt > 0) 2090 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0); 2091} 2092