iir_pci.c revision 166901
1119418Sobrien/*- 2120477Sscottl * Copyright (c) 2000-03 ICP vortex GmbH 3120477Sscottl * Copyright (c) 2002-03 Intel Corporation 4120477Sscottl * Copyright (c) 2003 Adaptec Inc. 589580Smsmith * All Rights Reserved 689580Smsmith * 789580Smsmith * Redistribution and use in source and binary forms, with or without 889580Smsmith * modification, are permitted provided that the following conditions 989580Smsmith * are met: 1089580Smsmith * 1. Redistributions of source code must retain the above copyright 1189580Smsmith * notice, this list of conditions, and the following disclaimer, 1289580Smsmith * without modification, immediately at the beginning of the file. 1389580Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1489580Smsmith * notice, this list of conditions and the following disclaimer in the 1589580Smsmith * documentation and/or other materials provided with the distribution. 1689580Smsmith * 3. The name of the author may not be used to endorse or promote products 1789580Smsmith * derived from this software without specific prior written permission. 1889580Smsmith * 1989580Smsmith * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2089580Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2189580Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2289580Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2389580Smsmith * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2489580Smsmith * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2589580Smsmith * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2689580Smsmith * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2789580Smsmith * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2889580Smsmith * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2989580Smsmith * SUCH DAMAGE. 3089580Smsmith */ 3189580Smsmith 32120477Sscottl#ident "$Id: iir_pci.c 1.2 2003/08/26 12:29:55 achim Exp $" 33119418Sobrien#include <sys/cdefs.h> 34119418Sobrien__FBSDID("$FreeBSD: head/sys/dev/iir/iir_pci.c 166901 2007-02-23 12:19:07Z piso $"); 35119418Sobrien 3689580Smsmith/* 3789580Smsmith * iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver 3889580Smsmith * 3989580Smsmith * Written by: Achim Leubner <achim.leubner@intel.com> 40120477Sscottl * Written by: Achim Leubner <achim_leubner@adaptec.com> 4189580Smsmith * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> 4289580Smsmith * 4389580Smsmith * TODO: 4489580Smsmith */ 4589580Smsmith 4689580Smsmith/* #include "opt_iir.h" */ 4789580Smsmith 4889580Smsmith#include <sys/param.h> 4989580Smsmith#include <sys/systm.h> 5095533Smike#include <sys/endian.h> 5189580Smsmith#include <sys/kernel.h> 52117126Sscottl#include <sys/lock.h> 53117126Sscottl#include <sys/mutex.h> 5489580Smsmith#include <sys/module.h> 5589580Smsmith#include <sys/bus.h> 5689580Smsmith 5789580Smsmith#include <machine/bus.h> 5889580Smsmith#include <machine/resource.h> 5989580Smsmith#include <sys/rman.h> 6089580Smsmith 61119280Simp#include <dev/pci/pcireg.h> 62119280Simp#include <dev/pci/pcivar.h> 6389580Smsmith 6489580Smsmith#include <cam/scsi/scsi_all.h> 6589580Smsmith 6689580Smsmith#include <dev/iir/iir.h> 6789580Smsmith 6889580Smsmith/* Mapping registers for various areas */ 69119690Sjhb#define PCI_DPMEM PCIR_BAR(0) 7089580Smsmith 7189580Smsmith/* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 7289580Smsmith#define GDT_PCI_PRODUCT_FC 0x200 7389580Smsmith 7489580Smsmith/* PCI SRAM structure */ 7589580Smsmith#define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 7689580Smsmith#define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 7789580Smsmith#define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */ 7889580Smsmith#define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 7989580Smsmith#define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 8089580Smsmith#define GDT_SRAM_SZ 0x40 8189580Smsmith 8289580Smsmith/* DPRAM PCI controllers */ 8389580Smsmith#define GDT_DPR_IF 0x00 /* interface area */ 8489580Smsmith#define GDT_6SR (0xff0 - GDT_SRAM_SZ) 8589580Smsmith#define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 8689580Smsmith#define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 8789580Smsmith#define GDT_EVENT 0xff8 /* u_int8_t, release event */ 8889580Smsmith#define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 8989580Smsmith#define GDT_DPRAM_SZ 0x1000 9089580Smsmith 9189580Smsmith/* PLX register structure (new PCI controllers) */ 9289580Smsmith#define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 9389580Smsmith#define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 9489580Smsmith#define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 9589580Smsmith#define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 9689580Smsmith#define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */ 9789580Smsmith#define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 9889580Smsmith#define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 9989580Smsmith#define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 10089580Smsmith#define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 10189580Smsmith#define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 10289580Smsmith#define GDT_PLX_SZ 0x80 10389580Smsmith 10489580Smsmith/* DPRAM new PCI controllers */ 10589580Smsmith#define GDT_IC 0x00 /* interface */ 10689580Smsmith#define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ) 10789580Smsmith /* SRAM structure */ 10889580Smsmith#define GDT_PCINEW_SZ 0x4000 10989580Smsmith 11089580Smsmith/* i960 register structure (PCI MPR controllers) */ 11189580Smsmith#define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 11289580Smsmith#define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 11389580Smsmith#define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 11489580Smsmith#define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */ 11589580Smsmith#define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 11689580Smsmith#define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 11789580Smsmith#define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 11889580Smsmith#define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 11989580Smsmith#define GDT_SEVERITY 0xefc /* u_int8_t, event severity */ 12089580Smsmith#define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */ 12189580Smsmith#define GDT_I960_SZ 0x1000 12289580Smsmith 12389580Smsmith/* DPRAM PCI MPR controllers */ 12489580Smsmith#define GDT_I960R 0x00 /* 4KB i960 registers */ 12589580Smsmith#define GDT_MPR_IC GDT_I960_SZ 12689580Smsmith /* i960 register area */ 12789580Smsmith#define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ) 12889580Smsmith /* DPRAM struct. */ 12989580Smsmith#define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ) 13089580Smsmith 13192739Salfredstatic int iir_pci_probe(device_t dev); 13292739Salfredstatic int iir_pci_attach(device_t dev); 13389580Smsmith 13492739Salfredvoid gdt_pci_enable_intr(struct gdt_softc *); 13589580Smsmith 13692739Salfredvoid gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 13792739Salfredu_int8_t gdt_mpr_get_status(struct gdt_softc *); 13892739Salfredvoid gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *); 13992739Salfredvoid gdt_mpr_release_event(struct gdt_softc *); 14092739Salfredvoid gdt_mpr_set_sema0(struct gdt_softc *); 14192739Salfredint gdt_mpr_test_busy(struct gdt_softc *); 14289580Smsmith 14389580Smsmithstatic device_method_t iir_pci_methods[] = { 14489580Smsmith /* Device interface */ 14589580Smsmith DEVMETHOD(device_probe, iir_pci_probe), 14689580Smsmith DEVMETHOD(device_attach, iir_pci_attach), 14789580Smsmith { 0, 0} 14889580Smsmith}; 14989580Smsmith 15089580Smsmith 15189580Smsmithstatic driver_t iir_pci_driver = 15289580Smsmith{ 15389580Smsmith "iir", 15489580Smsmith iir_pci_methods, 15589580Smsmith sizeof(struct gdt_softc) 15689580Smsmith}; 15789580Smsmith 15889580Smsmithstatic devclass_t iir_devclass; 15989580Smsmith 16089580SmsmithDRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0); 161165102SmjacobMODULE_DEPEND(iir, pci, 1, 1, 1); 162165102SmjacobMODULE_DEPEND(iir, cam, 1, 1, 1); 16389580Smsmith 16489580Smsmithstatic int 16589580Smsmithiir_pci_probe(device_t dev) 16689580Smsmith{ 16789580Smsmith if (pci_get_vendor(dev) == INTEL_VENDOR_ID && 16889580Smsmith pci_get_device(dev) == INTEL_DEVICE_ID_IIR) { 16989580Smsmith device_set_desc(dev, "Intel Integrated RAID Controller"); 170143160Simp return (BUS_PROBE_DEFAULT); 17189580Smsmith } 17289580Smsmith if (pci_get_vendor(dev) == GDT_VENDOR_ID && 17389580Smsmith ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN && 17489580Smsmith pci_get_device(dev) <= GDT_DEVICE_ID_MAX) || 17589580Smsmith pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) { 17689580Smsmith device_set_desc(dev, "ICP Disk Array Controller"); 177143160Simp return (BUS_PROBE_DEFAULT); 17889580Smsmith } 17989580Smsmith return (ENXIO); 18089580Smsmith} 18189580Smsmith 18289580Smsmith 18389580Smsmithstatic int 18489580Smsmithiir_pci_attach(device_t dev) 18589580Smsmith{ 18689580Smsmith struct gdt_softc *gdt; 18789580Smsmith struct resource *io = NULL, *irq = NULL; 18889580Smsmith int retries, rid, error = 0; 18989580Smsmith void *ih; 19089580Smsmith u_int8_t protocol; 19189580Smsmith 19289580Smsmith /* map DPMEM */ 19389580Smsmith rid = PCI_DPMEM; 194127135Snjl io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 19589580Smsmith if (io == NULL) { 19689580Smsmith device_printf(dev, "can't allocate register resources\n"); 19789580Smsmith error = ENOMEM; 19889580Smsmith goto err; 19989580Smsmith } 20089580Smsmith 20189580Smsmith /* get IRQ */ 20289580Smsmith rid = 0; 203127135Snjl irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 204127135Snjl RF_ACTIVE | RF_SHAREABLE); 20589580Smsmith if (io == NULL) { 20689580Smsmith device_printf(dev, "can't find IRQ value\n"); 20789580Smsmith error = ENOMEM; 20889580Smsmith goto err; 20989580Smsmith } 21089580Smsmith 21189580Smsmith gdt = device_get_softc(dev); 21289580Smsmith bzero(gdt, sizeof(struct gdt_softc)); 21389580Smsmith gdt->sc_init_level = 0; 21489580Smsmith gdt->sc_dpmemt = rman_get_bustag(io); 21589580Smsmith gdt->sc_dpmemh = rman_get_bushandle(io); 21689580Smsmith gdt->sc_dpmembase = rman_get_start(io); 21789580Smsmith gdt->sc_hanum = device_get_unit(dev); 21889580Smsmith gdt->sc_bus = pci_get_bus(dev); 21989580Smsmith gdt->sc_slot = pci_get_slot(dev); 220114001Sscottl gdt->sc_vendor = pci_get_vendor(dev); 22189580Smsmith gdt->sc_device = pci_get_device(dev); 22289580Smsmith gdt->sc_subdevice = pci_get_subdevice(dev); 22389580Smsmith gdt->sc_class = GDT_MPR; 22489580Smsmith/* no FC ctr. 22589580Smsmith if (gdt->sc_device >= GDT_PCI_PRODUCT_FC) 22689580Smsmith gdt->sc_class |= GDT_FC; 22789580Smsmith*/ 22889580Smsmith 22989580Smsmith /* initialize RP controller */ 23089580Smsmith /* check and reset interface area */ 23189580Smsmith bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC, 23289580Smsmith htole32(GDT_MPR_MAGIC)); 23389580Smsmith if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) != 23489580Smsmith htole32(GDT_MPR_MAGIC)) { 235106591Sjhb printf("cannot access DPMEM at 0x%jx (shadowed?)\n", 236106591Sjhb (uintmax_t)gdt->sc_dpmembase); 23789580Smsmith error = ENXIO; 23889580Smsmith goto err; 23989580Smsmith } 24089580Smsmith bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0), 24189580Smsmith GDT_MPR_SZ >> 2); 24289580Smsmith 24389580Smsmith /* Disable everything */ 24489580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 24589580Smsmith bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 24689580Smsmith GDT_EDOOR_EN) | 4); 24789580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 24889580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 24989580Smsmith 0); 25089580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX, 25189580Smsmith 0); 25289580Smsmith 25389580Smsmith bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 25489580Smsmith htole32(gdt->sc_dpmembase)); 25589580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 25689580Smsmith 0xff); 25789580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 25889580Smsmith 25989580Smsmith DELAY(20); 26089580Smsmith retries = GDT_RETRIES; 26189580Smsmith while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 26289580Smsmith GDT_MPR_IC + GDT_S_STATUS) != 0xff) { 26389580Smsmith if (--retries == 0) { 26489580Smsmith printf("DEINIT failed\n"); 26589580Smsmith error = ENXIO; 26689580Smsmith goto err; 26789580Smsmith } 26889580Smsmith DELAY(1); 26989580Smsmith } 27089580Smsmith 271114001Sscottl protocol = (uint8_t)le32toh(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 27289580Smsmith GDT_MPR_IC + GDT_S_INFO)); 27389580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 27489580Smsmith 0); 27589580Smsmith if (protocol != GDT_PROTOCOL_VERSION) { 27689580Smsmith printf("unsupported protocol %d\n", protocol); 27789580Smsmith error = ENXIO; 27889580Smsmith goto err; 27989580Smsmith } 28089580Smsmith 28189580Smsmith /* special commnd to controller BIOS */ 28289580Smsmith bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 28389580Smsmith htole32(0)); 28489580Smsmith bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 28589580Smsmith GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0)); 28689580Smsmith bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 28789580Smsmith GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 28889580Smsmith htole32(1)); 28989580Smsmith bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 29089580Smsmith GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 29189580Smsmith htole32(0)); 29289580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 29389580Smsmith 0xfe); 29489580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 29589580Smsmith 29689580Smsmith DELAY(20); 29789580Smsmith retries = GDT_RETRIES; 29889580Smsmith while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 29989580Smsmith GDT_MPR_IC + GDT_S_STATUS) != 0xfe) { 30089580Smsmith if (--retries == 0) { 30189580Smsmith printf("initialization error\n"); 30289580Smsmith error = ENXIO; 30389580Smsmith goto err; 30489580Smsmith } 30589580Smsmith DELAY(1); 30689580Smsmith } 30789580Smsmith 30889580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 30989580Smsmith 0); 31089580Smsmith 31189580Smsmith gdt->sc_ic_all_size = GDT_MPR_SZ; 31289580Smsmith 31389580Smsmith gdt->sc_copy_cmd = gdt_mpr_copy_cmd; 31489580Smsmith gdt->sc_get_status = gdt_mpr_get_status; 31589580Smsmith gdt->sc_intr = gdt_mpr_intr; 31689580Smsmith gdt->sc_release_event = gdt_mpr_release_event; 31789580Smsmith gdt->sc_set_sema0 = gdt_mpr_set_sema0; 31889580Smsmith gdt->sc_test_busy = gdt_mpr_test_busy; 31989580Smsmith 32089580Smsmith /* Allocate a dmatag representing the capabilities of this attachment */ 32189580Smsmith /* XXX Should be a child of the PCI bus dma tag */ 32289580Smsmith if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0, 32389580Smsmith /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 32489580Smsmith /*highaddr*/BUS_SPACE_MAXADDR, 32589580Smsmith /*filter*/NULL, /*filterarg*/NULL, 32689580Smsmith /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 32789580Smsmith /*nsegments*/GDT_MAXSG, 32889580Smsmith /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 329117126Sscottl /*flags*/0, /*lockfunc*/busdma_lock_mutex, 330117126Sscottl /*lockarg*/&Giant, &gdt->sc_parent_dmat) != 0) { 33189580Smsmith error = ENXIO; 33289580Smsmith goto err; 33389580Smsmith } 33489580Smsmith gdt->sc_init_level++; 33589580Smsmith 33689580Smsmith if (iir_init(gdt) != 0) { 33789580Smsmith iir_free(gdt); 33889580Smsmith error = ENXIO; 33989580Smsmith goto err; 34089580Smsmith } 34189580Smsmith 34289580Smsmith /* Register with the XPT */ 34389580Smsmith iir_attach(gdt); 34489580Smsmith 34589580Smsmith /* associate interrupt handler */ 34689580Smsmith if (bus_setup_intr( dev, irq, INTR_TYPE_CAM, 347166901Spiso NULL, iir_intr, gdt, &ih )) { 34889580Smsmith device_printf(dev, "Unable to register interrupt handler\n"); 34989580Smsmith error = ENXIO; 35089580Smsmith goto err; 35189580Smsmith } 35289580Smsmith 35389580Smsmith gdt_pci_enable_intr(gdt); 35489580Smsmith return (0); 35589580Smsmith 35689580Smsmitherr: 35789580Smsmith if (irq) 35889580Smsmith bus_release_resource( dev, SYS_RES_IRQ, 0, irq ); 35989580Smsmith/* 36089580Smsmith if (io) 36189580Smsmith bus_release_resource( dev, SYS_RES_MEMORY, rid, io ); 36289580Smsmith*/ 36389580Smsmith return (error); 36489580Smsmith} 36589580Smsmith 36689580Smsmith 36789580Smsmith/* Enable interrupts */ 36889580Smsmithvoid 36989580Smsmithgdt_pci_enable_intr(struct gdt_softc *gdt) 37089580Smsmith{ 37189580Smsmith GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt)); 37289580Smsmith 37389580Smsmith switch(GDT_CLASS(gdt)) { 37489580Smsmith case GDT_MPR: 37589580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 37689580Smsmith GDT_MPR_EDOOR, 0xff); 37789580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 37889580Smsmith bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 37989580Smsmith GDT_EDOOR_EN) & ~4); 38089580Smsmith break; 38189580Smsmith } 38289580Smsmith} 38389580Smsmith 38489580Smsmith 38589580Smsmith/* 38689580Smsmith * MPR PCI controller-specific functions 38789580Smsmith */ 38889580Smsmith 38989580Smsmithvoid 390156139Sscottlgdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *gccb) 39189580Smsmith{ 392156139Sscottl u_int16_t cp_count = roundup(gccb->gc_cmd_len, sizeof (u_int32_t)); 39389580Smsmith u_int16_t dp_offset = gdt->sc_cmd_off; 39489580Smsmith u_int16_t cmd_no = gdt->sc_cmd_cnt++; 39589580Smsmith 39689580Smsmith GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt)); 39789580Smsmith 39889580Smsmith gdt->sc_cmd_off += cp_count; 39989580Smsmith 400156139Sscottl bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 401156139Sscottl GDT_MPR_IC + GDT_DPR_CMD + dp_offset, 402156139Sscottl (u_int32_t *)gccb->gc_cmd, cp_count >> 2); 40389580Smsmith bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 40489580Smsmith GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET, 40589580Smsmith htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset)); 40689580Smsmith bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 40789580Smsmith GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID, 408156139Sscottl htole16(gccb->gc_service)); 40989580Smsmith} 41089580Smsmith 41189580Smsmithu_int8_t 41289580Smsmithgdt_mpr_get_status(struct gdt_softc *gdt) 41389580Smsmith{ 41489580Smsmith GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt)); 41589580Smsmith 41689580Smsmith return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR); 41789580Smsmith} 41889580Smsmith 41989580Smsmithvoid 42089580Smsmithgdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx) 42189580Smsmith{ 42289580Smsmith int i; 42389580Smsmith 42489580Smsmith GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt)); 42589580Smsmith 426156139Sscottl bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 427156139Sscottl 42889580Smsmith if (ctx->istatus & 0x80) { /* error flag */ 42989580Smsmith ctx->istatus &= ~0x80; 43089580Smsmith ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt, 43189580Smsmith gdt->sc_dpmemh, GDT_MPR_STATUS); 43289580Smsmith } else /* no error */ 43389580Smsmith ctx->cmd_status = GDT_S_OK; 43489580Smsmith 43589580Smsmith ctx->info = 43689580Smsmith bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO); 43789580Smsmith ctx->service = 43889580Smsmith bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE); 43989580Smsmith ctx->info2 = 44089580Smsmith bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 44189580Smsmith GDT_MPR_INFO + sizeof (u_int32_t)); 44289580Smsmith 44389580Smsmith /* event string */ 44489580Smsmith if (ctx->istatus == GDT_ASYNCINDEX) { 44589580Smsmith if (ctx->service != GDT_SCREENSERVICE && 44689580Smsmith (gdt->sc_fw_vers & 0xff) >= 0x1a) { 44789580Smsmith gdt->sc_dvr.severity = 44889580Smsmith bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY); 44989580Smsmith for (i = 0; i < 256; ++i) { 45089580Smsmith gdt->sc_dvr.event_string[i] = 45189580Smsmith bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 45289580Smsmith GDT_EVT_BUF + i); 45389580Smsmith if (gdt->sc_dvr.event_string[i] == 0) 45489580Smsmith break; 45589580Smsmith } 45689580Smsmith } 45789580Smsmith } 45889580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0); 45989580Smsmith} 46089580Smsmith 46189580Smsmithvoid 46289580Smsmithgdt_mpr_release_event(struct gdt_softc *gdt) 46389580Smsmith{ 46489580Smsmith GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt)); 46589580Smsmith 46689580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 46789580Smsmith} 46889580Smsmith 46989580Smsmithvoid 47089580Smsmithgdt_mpr_set_sema0(struct gdt_softc *gdt) 47189580Smsmith{ 47289580Smsmith GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt)); 47389580Smsmith 47489580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1); 47589580Smsmith} 47689580Smsmith 47789580Smsmithint 47889580Smsmithgdt_mpr_test_busy(struct gdt_softc *gdt) 47989580Smsmith{ 48089580Smsmith GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt)); 48189580Smsmith 48289580Smsmith return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 48389580Smsmith GDT_MPR_SEMA0) & 1); 48489580Smsmith} 485