iir_pci.c revision 127135
1/*- 2 * Copyright (c) 2000-03 ICP vortex GmbH 3 * Copyright (c) 2002-03 Intel Corporation 4 * Copyright (c) 2003 Adaptec Inc. 5 * All Rights Reserved 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#ident "$Id: iir_pci.c 1.2 2003/08/26 12:29:55 achim Exp $" 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/iir/iir_pci.c 127135 2004-03-17 17:50:55Z njl $"); 35 36/* 37 * iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver 38 * 39 * Written by: Achim Leubner <achim.leubner@intel.com> 40 * Written by: Achim Leubner <achim_leubner@adaptec.com> 41 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> 42 * 43 * TODO: 44 */ 45 46/* #include "opt_iir.h" */ 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/endian.h> 51#include <sys/kernel.h> 52#include <sys/lock.h> 53#include <sys/mutex.h> 54#include <sys/module.h> 55#include <sys/bus.h> 56 57#include <machine/bus_memio.h> 58#include <machine/bus_pio.h> 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <machine/clock.h> 62#include <sys/rman.h> 63 64#include <dev/pci/pcireg.h> 65#include <dev/pci/pcivar.h> 66 67#include <cam/scsi/scsi_all.h> 68 69#include <dev/iir/iir.h> 70 71/* Mapping registers for various areas */ 72#define PCI_DPMEM PCIR_BAR(0) 73 74/* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 75#define GDT_PCI_PRODUCT_FC 0x200 76 77/* PCI SRAM structure */ 78#define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 79#define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 80#define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */ 81#define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 82#define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 83#define GDT_SRAM_SZ 0x40 84 85/* DPRAM PCI controllers */ 86#define GDT_DPR_IF 0x00 /* interface area */ 87#define GDT_6SR (0xff0 - GDT_SRAM_SZ) 88#define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 89#define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 90#define GDT_EVENT 0xff8 /* u_int8_t, release event */ 91#define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 92#define GDT_DPRAM_SZ 0x1000 93 94/* PLX register structure (new PCI controllers) */ 95#define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 96#define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 97#define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 98#define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 99#define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */ 100#define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 101#define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 102#define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 103#define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 104#define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 105#define GDT_PLX_SZ 0x80 106 107/* DPRAM new PCI controllers */ 108#define GDT_IC 0x00 /* interface */ 109#define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ) 110 /* SRAM structure */ 111#define GDT_PCINEW_SZ 0x4000 112 113/* i960 register structure (PCI MPR controllers) */ 114#define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 115#define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 116#define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 117#define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */ 118#define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 119#define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 120#define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 121#define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 122#define GDT_SEVERITY 0xefc /* u_int8_t, event severity */ 123#define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */ 124#define GDT_I960_SZ 0x1000 125 126/* DPRAM PCI MPR controllers */ 127#define GDT_I960R 0x00 /* 4KB i960 registers */ 128#define GDT_MPR_IC GDT_I960_SZ 129 /* i960 register area */ 130#define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ) 131 /* DPRAM struct. */ 132#define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ) 133 134static int iir_pci_probe(device_t dev); 135static int iir_pci_attach(device_t dev); 136 137void gdt_pci_enable_intr(struct gdt_softc *); 138 139void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 140u_int8_t gdt_mpr_get_status(struct gdt_softc *); 141void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *); 142void gdt_mpr_release_event(struct gdt_softc *); 143void gdt_mpr_set_sema0(struct gdt_softc *); 144int gdt_mpr_test_busy(struct gdt_softc *); 145 146static device_method_t iir_pci_methods[] = { 147 /* Device interface */ 148 DEVMETHOD(device_probe, iir_pci_probe), 149 DEVMETHOD(device_attach, iir_pci_attach), 150 { 0, 0} 151}; 152 153 154static driver_t iir_pci_driver = 155{ 156 "iir", 157 iir_pci_methods, 158 sizeof(struct gdt_softc) 159}; 160 161static devclass_t iir_devclass; 162 163DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0); 164 165static int 166iir_pci_probe(device_t dev) 167{ 168 if (pci_get_vendor(dev) == INTEL_VENDOR_ID && 169 pci_get_device(dev) == INTEL_DEVICE_ID_IIR) { 170 device_set_desc(dev, "Intel Integrated RAID Controller"); 171 return (0); 172 } 173 if (pci_get_vendor(dev) == GDT_VENDOR_ID && 174 ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN && 175 pci_get_device(dev) <= GDT_DEVICE_ID_MAX) || 176 pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) { 177 device_set_desc(dev, "ICP Disk Array Controller"); 178 return (0); 179 } 180 return (ENXIO); 181} 182 183 184static int 185iir_pci_attach(device_t dev) 186{ 187 struct gdt_softc *gdt; 188 struct resource *io = NULL, *irq = NULL; 189 int retries, rid, error = 0; 190 void *ih; 191 u_int8_t protocol; 192 193 /* map DPMEM */ 194 rid = PCI_DPMEM; 195 io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 196 if (io == NULL) { 197 device_printf(dev, "can't allocate register resources\n"); 198 error = ENOMEM; 199 goto err; 200 } 201 202 /* get IRQ */ 203 rid = 0; 204 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 205 RF_ACTIVE | RF_SHAREABLE); 206 if (io == NULL) { 207 device_printf(dev, "can't find IRQ value\n"); 208 error = ENOMEM; 209 goto err; 210 } 211 212 gdt = device_get_softc(dev); 213 bzero(gdt, sizeof(struct gdt_softc)); 214 gdt->sc_init_level = 0; 215 gdt->sc_dpmemt = rman_get_bustag(io); 216 gdt->sc_dpmemh = rman_get_bushandle(io); 217 gdt->sc_dpmembase = rman_get_start(io); 218 gdt->sc_hanum = device_get_unit(dev); 219 gdt->sc_bus = pci_get_bus(dev); 220 gdt->sc_slot = pci_get_slot(dev); 221 gdt->sc_vendor = pci_get_vendor(dev); 222 gdt->sc_device = pci_get_device(dev); 223 gdt->sc_subdevice = pci_get_subdevice(dev); 224 gdt->sc_class = GDT_MPR; 225/* no FC ctr. 226 if (gdt->sc_device >= GDT_PCI_PRODUCT_FC) 227 gdt->sc_class |= GDT_FC; 228*/ 229 230 /* initialize RP controller */ 231 /* check and reset interface area */ 232 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC, 233 htole32(GDT_MPR_MAGIC)); 234 if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) != 235 htole32(GDT_MPR_MAGIC)) { 236 printf("cannot access DPMEM at 0x%jx (shadowed?)\n", 237 (uintmax_t)gdt->sc_dpmembase); 238 error = ENXIO; 239 goto err; 240 } 241 bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0), 242 GDT_MPR_SZ >> 2); 243 244 /* Disable everything */ 245 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 246 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 247 GDT_EDOOR_EN) | 4); 248 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 249 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 250 0); 251 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX, 252 0); 253 254 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 255 htole32(gdt->sc_dpmembase)); 256 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 257 0xff); 258 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 259 260 DELAY(20); 261 retries = GDT_RETRIES; 262 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 263 GDT_MPR_IC + GDT_S_STATUS) != 0xff) { 264 if (--retries == 0) { 265 printf("DEINIT failed\n"); 266 error = ENXIO; 267 goto err; 268 } 269 DELAY(1); 270 } 271 272 protocol = (uint8_t)le32toh(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 273 GDT_MPR_IC + GDT_S_INFO)); 274 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 275 0); 276 if (protocol != GDT_PROTOCOL_VERSION) { 277 printf("unsupported protocol %d\n", protocol); 278 error = ENXIO; 279 goto err; 280 } 281 282 /* special commnd to controller BIOS */ 283 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 284 htole32(0)); 285 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 286 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0)); 287 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 288 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 289 htole32(1)); 290 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 291 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 292 htole32(0)); 293 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 294 0xfe); 295 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 296 297 DELAY(20); 298 retries = GDT_RETRIES; 299 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 300 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) { 301 if (--retries == 0) { 302 printf("initialization error\n"); 303 error = ENXIO; 304 goto err; 305 } 306 DELAY(1); 307 } 308 309 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 310 0); 311 312 gdt->sc_ic_all_size = GDT_MPR_SZ; 313 314 gdt->sc_copy_cmd = gdt_mpr_copy_cmd; 315 gdt->sc_get_status = gdt_mpr_get_status; 316 gdt->sc_intr = gdt_mpr_intr; 317 gdt->sc_release_event = gdt_mpr_release_event; 318 gdt->sc_set_sema0 = gdt_mpr_set_sema0; 319 gdt->sc_test_busy = gdt_mpr_test_busy; 320 321 /* Allocate a dmatag representing the capabilities of this attachment */ 322 /* XXX Should be a child of the PCI bus dma tag */ 323 if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0, 324 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 325 /*highaddr*/BUS_SPACE_MAXADDR, 326 /*filter*/NULL, /*filterarg*/NULL, 327 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 328 /*nsegments*/GDT_MAXSG, 329 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 330 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 331 /*lockarg*/&Giant, &gdt->sc_parent_dmat) != 0) { 332 error = ENXIO; 333 goto err; 334 } 335 gdt->sc_init_level++; 336 337 if (iir_init(gdt) != 0) { 338 iir_free(gdt); 339 error = ENXIO; 340 goto err; 341 } 342 343 /* Register with the XPT */ 344 iir_attach(gdt); 345 346 /* associate interrupt handler */ 347 if (bus_setup_intr( dev, irq, INTR_TYPE_CAM, 348 iir_intr, gdt, &ih )) { 349 device_printf(dev, "Unable to register interrupt handler\n"); 350 error = ENXIO; 351 goto err; 352 } 353 354 gdt_pci_enable_intr(gdt); 355 return (0); 356 357err: 358 if (irq) 359 bus_release_resource( dev, SYS_RES_IRQ, 0, irq ); 360/* 361 if (io) 362 bus_release_resource( dev, SYS_RES_MEMORY, rid, io ); 363*/ 364 return (error); 365} 366 367 368/* Enable interrupts */ 369void 370gdt_pci_enable_intr(struct gdt_softc *gdt) 371{ 372 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt)); 373 374 switch(GDT_CLASS(gdt)) { 375 case GDT_MPR: 376 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 377 GDT_MPR_EDOOR, 0xff); 378 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 379 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 380 GDT_EDOOR_EN) & ~4); 381 break; 382 } 383} 384 385 386/* 387 * MPR PCI controller-specific functions 388 */ 389 390void 391gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *ccb) 392{ 393 u_int16_t cp_count = roundup(gdt->sc_cmd_len, sizeof (u_int32_t)); 394 u_int16_t dp_offset = gdt->sc_cmd_off; 395 u_int16_t cmd_no = gdt->sc_cmd_cnt++; 396 397 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt)); 398 399 gdt->sc_cmd_off += cp_count; 400 401 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 402 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET, 403 htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset)); 404 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 405 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID, 406 htole16(ccb->gc_service)); 407 bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 408 GDT_MPR_IC + GDT_DPR_CMD + dp_offset, 409 (u_int32_t *)gdt->sc_cmd, cp_count >> 2); 410} 411 412u_int8_t 413gdt_mpr_get_status(struct gdt_softc *gdt) 414{ 415 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt)); 416 417 return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR); 418} 419 420void 421gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx) 422{ 423 int i; 424 425 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt)); 426 427 if (ctx->istatus & 0x80) { /* error flag */ 428 ctx->istatus &= ~0x80; 429 ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt, 430 gdt->sc_dpmemh, GDT_MPR_STATUS); 431 } else /* no error */ 432 ctx->cmd_status = GDT_S_OK; 433 434 ctx->info = 435 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO); 436 ctx->service = 437 bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE); 438 ctx->info2 = 439 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 440 GDT_MPR_INFO + sizeof (u_int32_t)); 441 442 /* event string */ 443 if (ctx->istatus == GDT_ASYNCINDEX) { 444 if (ctx->service != GDT_SCREENSERVICE && 445 (gdt->sc_fw_vers & 0xff) >= 0x1a) { 446 gdt->sc_dvr.severity = 447 bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY); 448 for (i = 0; i < 256; ++i) { 449 gdt->sc_dvr.event_string[i] = 450 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 451 GDT_EVT_BUF + i); 452 if (gdt->sc_dvr.event_string[i] == 0) 453 break; 454 } 455 } 456 } 457 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 458 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0); 459} 460 461void 462gdt_mpr_release_event(struct gdt_softc *gdt) 463{ 464 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt)); 465 466 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 467} 468 469void 470gdt_mpr_set_sema0(struct gdt_softc *gdt) 471{ 472 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt)); 473 474 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1); 475} 476 477int 478gdt_mpr_test_busy(struct gdt_softc *gdt) 479{ 480 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt)); 481 482 return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 483 GDT_MPR_SEMA0) & 1); 484} 485