iir_pci.c revision 114001
189580Smsmith/* $FreeBSD: head/sys/dev/iir/iir_pci.c 114001 2003-04-25 05:37:04Z scottl $ */ 289580Smsmith/* 389580Smsmith * Copyright (c) 2000-01 Intel Corporation 489580Smsmith * All Rights Reserved 589580Smsmith * 689580Smsmith * Redistribution and use in source and binary forms, with or without 789580Smsmith * modification, are permitted provided that the following conditions 889580Smsmith * are met: 989580Smsmith * 1. Redistributions of source code must retain the above copyright 1089580Smsmith * notice, this list of conditions, and the following disclaimer, 1189580Smsmith * without modification, immediately at the beginning of the file. 1289580Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1389580Smsmith * notice, this list of conditions and the following disclaimer in the 1489580Smsmith * documentation and/or other materials provided with the distribution. 1589580Smsmith * 3. The name of the author may not be used to endorse or promote products 1689580Smsmith * derived from this software without specific prior written permission. 1789580Smsmith * 1889580Smsmith * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1989580Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2089580Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2189580Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2289580Smsmith * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2389580Smsmith * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2489580Smsmith * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2589580Smsmith * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2689580Smsmith * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2789580Smsmith * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2889580Smsmith * SUCH DAMAGE. 2989580Smsmith * 3089580Smsmith */ 3189580Smsmith 3289580Smsmith/* 3389580Smsmith * iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver 3489580Smsmith * 3589580Smsmith * Written by: Achim Leubner <achim.leubner@intel.com> 3689580Smsmith * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> 3789580Smsmith * 3889580Smsmith * TODO: 3989580Smsmith */ 4089580Smsmith 4189580Smsmith#ident "$Id: iir_pci.c 1.1 2001/05/22 20:14:12 achim Exp $" 4289580Smsmith 4389580Smsmith/* #include "opt_iir.h" */ 4489580Smsmith 4589580Smsmith#include <sys/param.h> 4689580Smsmith#include <sys/systm.h> 4795533Smike#include <sys/endian.h> 4889580Smsmith#include <sys/kernel.h> 4989580Smsmith#include <sys/module.h> 5089580Smsmith#include <sys/bus.h> 5189580Smsmith 5289580Smsmith#include <machine/bus_memio.h> 5389580Smsmith#include <machine/bus_pio.h> 5489580Smsmith#include <machine/bus.h> 5589580Smsmith#include <machine/resource.h> 5689580Smsmith#include <machine/clock.h> 5789580Smsmith#include <sys/rman.h> 5889580Smsmith 5989580Smsmith#include <pci/pcireg.h> 6089580Smsmith#include <pci/pcivar.h> 6189580Smsmith 6289580Smsmith#include <cam/scsi/scsi_all.h> 6389580Smsmith 6489580Smsmith#include <dev/iir/iir.h> 6589580Smsmith 6689580Smsmith/* Mapping registers for various areas */ 6789580Smsmith#define PCI_DPMEM PCIR_MAPS 6889580Smsmith 6989580Smsmith/* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 7089580Smsmith#define GDT_PCI_PRODUCT_FC 0x200 7189580Smsmith 7289580Smsmith/* PCI SRAM structure */ 7389580Smsmith#define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 7489580Smsmith#define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 7589580Smsmith#define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */ 7689580Smsmith#define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 7789580Smsmith#define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 7889580Smsmith#define GDT_SRAM_SZ 0x40 7989580Smsmith 8089580Smsmith/* DPRAM PCI controllers */ 8189580Smsmith#define GDT_DPR_IF 0x00 /* interface area */ 8289580Smsmith#define GDT_6SR (0xff0 - GDT_SRAM_SZ) 8389580Smsmith#define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 8489580Smsmith#define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 8589580Smsmith#define GDT_EVENT 0xff8 /* u_int8_t, release event */ 8689580Smsmith#define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 8789580Smsmith#define GDT_DPRAM_SZ 0x1000 8889580Smsmith 8989580Smsmith/* PLX register structure (new PCI controllers) */ 9089580Smsmith#define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 9189580Smsmith#define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 9289580Smsmith#define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 9389580Smsmith#define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 9489580Smsmith#define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */ 9589580Smsmith#define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 9689580Smsmith#define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 9789580Smsmith#define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 9889580Smsmith#define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 9989580Smsmith#define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 10089580Smsmith#define GDT_PLX_SZ 0x80 10189580Smsmith 10289580Smsmith/* DPRAM new PCI controllers */ 10389580Smsmith#define GDT_IC 0x00 /* interface */ 10489580Smsmith#define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ) 10589580Smsmith /* SRAM structure */ 10689580Smsmith#define GDT_PCINEW_SZ 0x4000 10789580Smsmith 10889580Smsmith/* i960 register structure (PCI MPR controllers) */ 10989580Smsmith#define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 11089580Smsmith#define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 11189580Smsmith#define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 11289580Smsmith#define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */ 11389580Smsmith#define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 11489580Smsmith#define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 11589580Smsmith#define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 11689580Smsmith#define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 11789580Smsmith#define GDT_SEVERITY 0xefc /* u_int8_t, event severity */ 11889580Smsmith#define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */ 11989580Smsmith#define GDT_I960_SZ 0x1000 12089580Smsmith 12189580Smsmith/* DPRAM PCI MPR controllers */ 12289580Smsmith#define GDT_I960R 0x00 /* 4KB i960 registers */ 12389580Smsmith#define GDT_MPR_IC GDT_I960_SZ 12489580Smsmith /* i960 register area */ 12589580Smsmith#define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ) 12689580Smsmith /* DPRAM struct. */ 12789580Smsmith#define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ) 12889580Smsmith 12992739Salfredstatic int iir_pci_probe(device_t dev); 13092739Salfredstatic int iir_pci_attach(device_t dev); 13189580Smsmith 13292739Salfredvoid gdt_pci_enable_intr(struct gdt_softc *); 13389580Smsmith 13492739Salfredvoid gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 13592739Salfredu_int8_t gdt_mpr_get_status(struct gdt_softc *); 13692739Salfredvoid gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *); 13792739Salfredvoid gdt_mpr_release_event(struct gdt_softc *); 13892739Salfredvoid gdt_mpr_set_sema0(struct gdt_softc *); 13992739Salfredint gdt_mpr_test_busy(struct gdt_softc *); 14089580Smsmith 14189580Smsmithstatic device_method_t iir_pci_methods[] = { 14289580Smsmith /* Device interface */ 14389580Smsmith DEVMETHOD(device_probe, iir_pci_probe), 14489580Smsmith DEVMETHOD(device_attach, iir_pci_attach), 14589580Smsmith { 0, 0} 14689580Smsmith}; 14789580Smsmith 14889580Smsmith 14989580Smsmithstatic driver_t iir_pci_driver = 15089580Smsmith{ 15189580Smsmith "iir", 15289580Smsmith iir_pci_methods, 15389580Smsmith sizeof(struct gdt_softc) 15489580Smsmith}; 15589580Smsmith 15689580Smsmithstatic devclass_t iir_devclass; 15789580Smsmith 15889580SmsmithDRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, 0, 0); 15989580Smsmith 16089580Smsmithstatic int 16189580Smsmithiir_pci_probe(device_t dev) 16289580Smsmith{ 16389580Smsmith if (pci_get_vendor(dev) == INTEL_VENDOR_ID && 16489580Smsmith pci_get_device(dev) == INTEL_DEVICE_ID_IIR) { 16589580Smsmith device_set_desc(dev, "Intel Integrated RAID Controller"); 16689580Smsmith return (0); 16789580Smsmith } 16889580Smsmith if (pci_get_vendor(dev) == GDT_VENDOR_ID && 16989580Smsmith ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN && 17089580Smsmith pci_get_device(dev) <= GDT_DEVICE_ID_MAX) || 17189580Smsmith pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) { 17289580Smsmith device_set_desc(dev, "ICP Disk Array Controller"); 17389580Smsmith return (0); 17489580Smsmith } 17589580Smsmith return (ENXIO); 17689580Smsmith} 17789580Smsmith 17889580Smsmith 17989580Smsmithstatic int 18089580Smsmithiir_pci_attach(device_t dev) 18189580Smsmith{ 18289580Smsmith struct gdt_softc *gdt; 18389580Smsmith struct resource *io = NULL, *irq = NULL; 18489580Smsmith int retries, rid, error = 0; 18589580Smsmith void *ih; 18689580Smsmith u_int8_t protocol; 18789580Smsmith 18889580Smsmith /* map DPMEM */ 18989580Smsmith rid = PCI_DPMEM; 19089580Smsmith io = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, RF_ACTIVE); 19189580Smsmith if (io == NULL) { 19289580Smsmith device_printf(dev, "can't allocate register resources\n"); 19389580Smsmith error = ENOMEM; 19489580Smsmith goto err; 19589580Smsmith } 19689580Smsmith 19789580Smsmith /* get IRQ */ 19889580Smsmith rid = 0; 19989580Smsmith irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 20089580Smsmith RF_ACTIVE | RF_SHAREABLE); 20189580Smsmith if (io == NULL) { 20289580Smsmith device_printf(dev, "can't find IRQ value\n"); 20389580Smsmith error = ENOMEM; 20489580Smsmith goto err; 20589580Smsmith } 20689580Smsmith 20789580Smsmith gdt = device_get_softc(dev); 20889580Smsmith bzero(gdt, sizeof(struct gdt_softc)); 20989580Smsmith gdt->sc_init_level = 0; 21089580Smsmith gdt->sc_dpmemt = rman_get_bustag(io); 21189580Smsmith gdt->sc_dpmemh = rman_get_bushandle(io); 21289580Smsmith gdt->sc_dpmembase = rman_get_start(io); 21389580Smsmith gdt->sc_hanum = device_get_unit(dev); 21489580Smsmith gdt->sc_bus = pci_get_bus(dev); 21589580Smsmith gdt->sc_slot = pci_get_slot(dev); 216114001Sscottl gdt->sc_vendor = pci_get_vendor(dev); 21789580Smsmith gdt->sc_device = pci_get_device(dev); 21889580Smsmith gdt->sc_subdevice = pci_get_subdevice(dev); 21989580Smsmith gdt->sc_class = GDT_MPR; 22089580Smsmith/* no FC ctr. 22189580Smsmith if (gdt->sc_device >= GDT_PCI_PRODUCT_FC) 22289580Smsmith gdt->sc_class |= GDT_FC; 22389580Smsmith*/ 22489580Smsmith 22589580Smsmith /* initialize RP controller */ 22689580Smsmith /* check and reset interface area */ 22789580Smsmith bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC, 22889580Smsmith htole32(GDT_MPR_MAGIC)); 22989580Smsmith if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) != 23089580Smsmith htole32(GDT_MPR_MAGIC)) { 231106591Sjhb printf("cannot access DPMEM at 0x%jx (shadowed?)\n", 232106591Sjhb (uintmax_t)gdt->sc_dpmembase); 23389580Smsmith error = ENXIO; 23489580Smsmith goto err; 23589580Smsmith } 23689580Smsmith bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0), 23789580Smsmith GDT_MPR_SZ >> 2); 23889580Smsmith 23989580Smsmith /* Disable everything */ 24089580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 24189580Smsmith bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 24289580Smsmith GDT_EDOOR_EN) | 4); 24389580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 24489580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 24589580Smsmith 0); 24689580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX, 24789580Smsmith 0); 24889580Smsmith 24989580Smsmith bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 25089580Smsmith htole32(gdt->sc_dpmembase)); 25189580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 25289580Smsmith 0xff); 25389580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 25489580Smsmith 25589580Smsmith DELAY(20); 25689580Smsmith retries = GDT_RETRIES; 25789580Smsmith while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 25889580Smsmith GDT_MPR_IC + GDT_S_STATUS) != 0xff) { 25989580Smsmith if (--retries == 0) { 26089580Smsmith printf("DEINIT failed\n"); 26189580Smsmith error = ENXIO; 26289580Smsmith goto err; 26389580Smsmith } 26489580Smsmith DELAY(1); 26589580Smsmith } 26689580Smsmith 267114001Sscottl protocol = (uint8_t)le32toh(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 26889580Smsmith GDT_MPR_IC + GDT_S_INFO)); 26989580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 27089580Smsmith 0); 27189580Smsmith if (protocol != GDT_PROTOCOL_VERSION) { 27289580Smsmith printf("unsupported protocol %d\n", protocol); 27389580Smsmith error = ENXIO; 27489580Smsmith goto err; 27589580Smsmith } 27689580Smsmith 27789580Smsmith /* special commnd to controller BIOS */ 27889580Smsmith bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO, 27989580Smsmith htole32(0)); 28089580Smsmith bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 28189580Smsmith GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0)); 28289580Smsmith bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 28389580Smsmith GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 28489580Smsmith htole32(1)); 28589580Smsmith bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 28689580Smsmith GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 28789580Smsmith htole32(0)); 28889580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 28989580Smsmith 0xfe); 29089580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 29189580Smsmith 29289580Smsmith DELAY(20); 29389580Smsmith retries = GDT_RETRIES; 29489580Smsmith while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 29589580Smsmith GDT_MPR_IC + GDT_S_STATUS) != 0xfe) { 29689580Smsmith if (--retries == 0) { 29789580Smsmith printf("initialization error\n"); 29889580Smsmith error = ENXIO; 29989580Smsmith goto err; 30089580Smsmith } 30189580Smsmith DELAY(1); 30289580Smsmith } 30389580Smsmith 30489580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS, 30589580Smsmith 0); 30689580Smsmith 30789580Smsmith gdt->sc_ic_all_size = GDT_MPR_SZ; 30889580Smsmith 30989580Smsmith gdt->sc_copy_cmd = gdt_mpr_copy_cmd; 31089580Smsmith gdt->sc_get_status = gdt_mpr_get_status; 31189580Smsmith gdt->sc_intr = gdt_mpr_intr; 31289580Smsmith gdt->sc_release_event = gdt_mpr_release_event; 31389580Smsmith gdt->sc_set_sema0 = gdt_mpr_set_sema0; 31489580Smsmith gdt->sc_test_busy = gdt_mpr_test_busy; 31589580Smsmith 31689580Smsmith /* Allocate a dmatag representing the capabilities of this attachment */ 31789580Smsmith /* XXX Should be a child of the PCI bus dma tag */ 31889580Smsmith if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0, 31989580Smsmith /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 32089580Smsmith /*highaddr*/BUS_SPACE_MAXADDR, 32189580Smsmith /*filter*/NULL, /*filterarg*/NULL, 32289580Smsmith /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 32389580Smsmith /*nsegments*/GDT_MAXSG, 32489580Smsmith /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 32589580Smsmith /*flags*/0, &gdt->sc_parent_dmat) != 0) { 32689580Smsmith error = ENXIO; 32789580Smsmith goto err; 32889580Smsmith } 32989580Smsmith gdt->sc_init_level++; 33089580Smsmith 33189580Smsmith if (iir_init(gdt) != 0) { 33289580Smsmith iir_free(gdt); 33389580Smsmith error = ENXIO; 33489580Smsmith goto err; 33589580Smsmith } 33689580Smsmith 33789580Smsmith /* Register with the XPT */ 33889580Smsmith iir_attach(gdt); 33989580Smsmith 34089580Smsmith /* associate interrupt handler */ 34189580Smsmith if (bus_setup_intr( dev, irq, INTR_TYPE_CAM, 34289580Smsmith iir_intr, gdt, &ih )) { 34389580Smsmith device_printf(dev, "Unable to register interrupt handler\n"); 34489580Smsmith error = ENXIO; 34589580Smsmith goto err; 34689580Smsmith } 34789580Smsmith 34889580Smsmith gdt_pci_enable_intr(gdt); 34989580Smsmith return (0); 35089580Smsmith 35189580Smsmitherr: 35289580Smsmith if (irq) 35389580Smsmith bus_release_resource( dev, SYS_RES_IRQ, 0, irq ); 35489580Smsmith/* 35589580Smsmith if (io) 35689580Smsmith bus_release_resource( dev, SYS_RES_MEMORY, rid, io ); 35789580Smsmith*/ 35889580Smsmith return (error); 35989580Smsmith} 36089580Smsmith 36189580Smsmith 36289580Smsmith/* Enable interrupts */ 36389580Smsmithvoid 36489580Smsmithgdt_pci_enable_intr(struct gdt_softc *gdt) 36589580Smsmith{ 36689580Smsmith GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt)); 36789580Smsmith 36889580Smsmith switch(GDT_CLASS(gdt)) { 36989580Smsmith case GDT_MPR: 37089580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 37189580Smsmith GDT_MPR_EDOOR, 0xff); 37289580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 37389580Smsmith bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 37489580Smsmith GDT_EDOOR_EN) & ~4); 37589580Smsmith break; 37689580Smsmith } 37789580Smsmith} 37889580Smsmith 37989580Smsmith 38089580Smsmith/* 38189580Smsmith * MPR PCI controller-specific functions 38289580Smsmith */ 38389580Smsmith 38489580Smsmithvoid 38589580Smsmithgdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *ccb) 38689580Smsmith{ 38789580Smsmith u_int16_t cp_count = roundup(gdt->sc_cmd_len, sizeof (u_int32_t)); 38889580Smsmith u_int16_t dp_offset = gdt->sc_cmd_off; 38989580Smsmith u_int16_t cmd_no = gdt->sc_cmd_cnt++; 39089580Smsmith 39189580Smsmith GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt)); 39289580Smsmith 39389580Smsmith gdt->sc_cmd_off += cp_count; 39489580Smsmith 39589580Smsmith bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 39689580Smsmith GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET, 39789580Smsmith htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset)); 39889580Smsmith bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 39989580Smsmith GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID, 40089580Smsmith htole16(ccb->gc_service)); 40189580Smsmith bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 40289580Smsmith GDT_MPR_IC + GDT_DPR_CMD + dp_offset, 40389580Smsmith (u_int32_t *)gdt->sc_cmd, cp_count >> 2); 40489580Smsmith} 40589580Smsmith 40689580Smsmithu_int8_t 40789580Smsmithgdt_mpr_get_status(struct gdt_softc *gdt) 40889580Smsmith{ 40989580Smsmith GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt)); 41089580Smsmith 41189580Smsmith return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR); 41289580Smsmith} 41389580Smsmith 41489580Smsmithvoid 41589580Smsmithgdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx) 41689580Smsmith{ 41789580Smsmith int i; 41889580Smsmith 41989580Smsmith GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt)); 42089580Smsmith 42189580Smsmith if (ctx->istatus & 0x80) { /* error flag */ 42289580Smsmith ctx->istatus &= ~0x80; 42389580Smsmith ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt, 42489580Smsmith gdt->sc_dpmemh, GDT_MPR_STATUS); 42589580Smsmith } else /* no error */ 42689580Smsmith ctx->cmd_status = GDT_S_OK; 42789580Smsmith 42889580Smsmith ctx->info = 42989580Smsmith bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO); 43089580Smsmith ctx->service = 43189580Smsmith bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE); 43289580Smsmith ctx->info2 = 43389580Smsmith bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 43489580Smsmith GDT_MPR_INFO + sizeof (u_int32_t)); 43589580Smsmith 43689580Smsmith /* event string */ 43789580Smsmith if (ctx->istatus == GDT_ASYNCINDEX) { 43889580Smsmith if (ctx->service != GDT_SCREENSERVICE && 43989580Smsmith (gdt->sc_fw_vers & 0xff) >= 0x1a) { 44089580Smsmith gdt->sc_dvr.severity = 44189580Smsmith bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY); 44289580Smsmith for (i = 0; i < 256; ++i) { 44389580Smsmith gdt->sc_dvr.event_string[i] = 44489580Smsmith bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 44589580Smsmith GDT_EVT_BUF + i); 44689580Smsmith if (gdt->sc_dvr.event_string[i] == 0) 44789580Smsmith break; 44889580Smsmith } 44989580Smsmith } 45089580Smsmith } 45189580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 45289580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0); 45389580Smsmith} 45489580Smsmith 45589580Smsmithvoid 45689580Smsmithgdt_mpr_release_event(struct gdt_softc *gdt) 45789580Smsmith{ 45889580Smsmith GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt)); 45989580Smsmith 46089580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 46189580Smsmith} 46289580Smsmith 46389580Smsmithvoid 46489580Smsmithgdt_mpr_set_sema0(struct gdt_softc *gdt) 46589580Smsmith{ 46689580Smsmith GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt)); 46789580Smsmith 46889580Smsmith bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1); 46989580Smsmith} 47089580Smsmith 47189580Smsmithint 47289580Smsmithgdt_mpr_test_busy(struct gdt_softc *gdt) 47389580Smsmith{ 47489580Smsmith GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt)); 47589580Smsmith 47689580Smsmith return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 47789580Smsmith GDT_MPR_SEMA0) & 1); 47889580Smsmith} 479