icee.c revision 289666
1/*- 2 * Copyright (c) 2006 Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25#include <sys/cdefs.h> 26__FBSDID("$FreeBSD: stable/10/sys/dev/iicbus/icee.c 289666 2015-10-20 21:20:34Z ian $"); 27/* 28 * Generic IIC eeprom support, modeled after the AT24C family of products. 29 */ 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/conf.h> 34#include <sys/kernel.h> 35#include <sys/module.h> 36#include <sys/resource.h> 37#include <sys/sx.h> 38#include <sys/uio.h> 39#include <machine/bus.h> 40#include <dev/iicbus/iiconf.h> 41#include <dev/iicbus/iicbus.h> 42 43#include "iicbus_if.h" 44 45#define IIC_M_WR 0 /* write operation */ 46#define MAX_RD_SZ 256 /* Largest read size we support */ 47#define MAX_WR_SZ 256 /* Largest write size we support */ 48 49struct icee_softc { 50 device_t sc_dev; /* Myself */ 51 device_t sc_busdev; /* Parent bus */ 52 struct cdev *cdev; /* user interface */ 53 int addr; 54 int size; /* How big am I? */ 55 int type; /* What type 8 or 16 bit? */ 56 int rd_sz; /* What's the read page size */ 57 int wr_sz; /* What's the write page size */ 58}; 59 60#define CDEV2SOFTC(dev) ((dev)->si_drv1) 61 62/* cdev routines */ 63static d_open_t icee_open; 64static d_close_t icee_close; 65static d_read_t icee_read; 66static d_write_t icee_write; 67 68static struct cdevsw icee_cdevsw = 69{ 70 .d_version = D_VERSION, 71 .d_flags = D_TRACKCLOSE, 72 .d_open = icee_open, 73 .d_close = icee_close, 74 .d_read = icee_read, 75 .d_write = icee_write 76}; 77 78static int 79icee_probe(device_t dev) 80{ 81 82 device_set_desc(dev, "I2C EEPROM"); 83 return (BUS_PROBE_NOWILDCARD); 84} 85 86static int 87icee_attach(device_t dev) 88{ 89 struct icee_softc *sc = device_get_softc(dev); 90 const char *dname; 91 int dunit, err; 92 93 sc->sc_dev = dev; 94 sc->sc_busdev = device_get_parent(sc->sc_dev); 95 sc->addr = iicbus_get_addr(dev); 96 err = 0; 97 dname = device_get_name(dev); 98 dunit = device_get_unit(dev); 99 resource_int_value(dname, dunit, "size", &sc->size); 100 resource_int_value(dname, dunit, "type", &sc->type); 101 resource_int_value(dname, dunit, "rd_sz", &sc->rd_sz); 102 if (sc->rd_sz > MAX_RD_SZ) 103 sc->rd_sz = MAX_RD_SZ; 104 resource_int_value(dname, dunit, "wr_sz", &sc->wr_sz); 105 if (bootverbose) 106 device_printf(dev, "size: %d bytes bus_width: %d-bits\n", 107 sc->size, sc->type); 108 sc->cdev = make_dev(&icee_cdevsw, device_get_unit(dev), UID_ROOT, 109 GID_WHEEL, 0600, "icee%d", device_get_unit(dev)); 110 if (sc->cdev == NULL) { 111 err = ENOMEM; 112 goto out; 113 } 114 sc->cdev->si_drv1 = sc; 115out: 116 return (err); 117} 118 119static int 120icee_open(struct cdev *dev, int oflags, int devtype, struct thread *td) 121{ 122 123 return (0); 124} 125 126static int 127icee_close(struct cdev *dev, int fflag, int devtype, struct thread *td) 128{ 129 130 return (0); 131} 132 133static int 134icee_read(struct cdev *dev, struct uio *uio, int ioflag) 135{ 136 struct icee_softc *sc; 137 uint8_t addr[2]; 138 uint8_t data[MAX_RD_SZ]; 139 int error, i, len, slave; 140 struct iic_msg msgs[2] = { 141 { 0, IIC_M_WR, 1, addr }, 142 { 0, IIC_M_RD, 0, data }, 143 }; 144 145 sc = CDEV2SOFTC(dev); 146 if (uio->uio_offset == sc->size) 147 return (0); 148 if (uio->uio_offset > sc->size) 149 return (EIO); 150 if (sc->type != 8 && sc->type != 16) 151 return (EINVAL); 152 error = iicbus_request_bus(sc->sc_busdev, sc->sc_dev, IIC_INTRWAIT); 153 if (error!= 0) 154 return (iic2errno(error)); 155 slave = error = 0; 156 while (uio->uio_resid > 0) { 157 if (uio->uio_offset >= sc->size) 158 break; 159 len = MIN(sc->rd_sz - (uio->uio_offset & (sc->rd_sz - 1)), 160 uio->uio_resid); 161 switch (sc->type) { 162 case 8: 163 slave = (uio->uio_offset >> 7) | sc->addr; 164 msgs[0].len = 1; 165 msgs[1].len = len; 166 addr[0] = uio->uio_offset & 0xff; 167 break; 168 case 16: 169 slave = sc->addr | (uio->uio_offset >> 15); 170 msgs[0].len = 2; 171 msgs[1].len = len; 172 addr[0] = (uio->uio_offset >> 8) & 0xff; 173 addr[1] = uio->uio_offset & 0xff; 174 break; 175 } 176 for (i = 0; i < 2; i++) 177 msgs[i].slave = slave; 178 error = iicbus_transfer(sc->sc_dev, msgs, 2); 179 if (error) { 180 error = iic2errno(error); 181 break; 182 } 183 error = uiomove(data, len, uio); 184 if (error) 185 break; 186 } 187 iicbus_release_bus(sc->sc_busdev, sc->sc_dev); 188 return (error); 189} 190 191/* 192 * Write to the part. We use three transfers here since we're actually 193 * doing a write followed by a read to make sure that the write finished. 194 * It is easier to encode the dummy read here than to break things up 195 * into smaller chunks... 196 */ 197static int 198icee_write(struct cdev *dev, struct uio *uio, int ioflag) 199{ 200 struct icee_softc *sc; 201 int error, len, slave, waitlimit; 202 uint8_t data[MAX_WR_SZ + 2]; 203 struct iic_msg wr[1] = { 204 { 0, IIC_M_WR, 0, data }, 205 }; 206 struct iic_msg rd[1] = { 207 { 0, IIC_M_RD, 1, data }, 208 }; 209 210 sc = CDEV2SOFTC(dev); 211 if (uio->uio_offset >= sc->size) 212 return (EIO); 213 if (sc->type != 8 && sc->type != 16) 214 return (EINVAL); 215 216 error = iicbus_request_bus(sc->sc_busdev, sc->sc_dev, IIC_INTRWAIT); 217 if (error!= 0) 218 return (iic2errno(error)); 219 slave = error = 0; 220 while (uio->uio_resid > 0) { 221 if (uio->uio_offset >= sc->size) 222 break; 223 len = MIN(sc->wr_sz - (uio->uio_offset & (sc->wr_sz - 1)), 224 uio->uio_resid); 225 switch (sc->type) { 226 case 8: 227 slave = (uio->uio_offset >> 7) | sc->addr; 228 wr[0].len = 1 + len; 229 data[0] = uio->uio_offset & 0xff; 230 break; 231 case 16: 232 slave = sc->addr | (uio->uio_offset >> 15); 233 wr[0].len = 2 + len; 234 data[0] = (uio->uio_offset >> 8) & 0xff; 235 data[1] = uio->uio_offset & 0xff; 236 break; 237 } 238 wr[0].slave = slave; 239 error = uiomove(data + sc->type / 8, len, uio); 240 if (error) 241 break; 242 error = iicbus_transfer(sc->sc_dev, wr, 1); 243 if (error) { 244 error = iic2errno(error); 245 break; 246 } 247 /* Read after write to wait for write-done. */ 248 waitlimit = 10000; 249 rd[0].slave = slave; 250 do { 251 error = iicbus_transfer(sc->sc_dev, rd, 1); 252 } while (waitlimit-- > 0 && error != 0); 253 if (error) { 254 error = iic2errno(error); 255 break; 256 } 257 } 258 iicbus_release_bus(sc->sc_busdev, sc->sc_dev); 259 return error; 260} 261 262static device_method_t icee_methods[] = { 263 DEVMETHOD(device_probe, icee_probe), 264 DEVMETHOD(device_attach, icee_attach), 265 266 DEVMETHOD_END 267}; 268 269static driver_t icee_driver = { 270 "icee", 271 icee_methods, 272 sizeof(struct icee_softc), 273}; 274static devclass_t icee_devclass; 275 276DRIVER_MODULE(icee, iicbus, icee_driver, icee_devclass, 0, 0); 277MODULE_VERSION(icee, 1); 278MODULE_DEPEND(icee, iicbus, 1, 1, 1); 279