177962Snyan/*- 277962Snyan * Copyright (c) 1999 FreeBSD Inc. 377962Snyan * All rights reserved. 477962Snyan * 577962Snyan * Redistribution and use in source and binary forms, with or without 677962Snyan * modification, are permitted provided that the following conditions 777962Snyan * are met: 877962Snyan * 1. Redistributions of source code must retain the above copyright 977962Snyan * notice, this list of conditions and the following disclaimer. 1077962Snyan * 2. Redistributions in binary form must reproduce the above copyright 1177962Snyan * notice, this list of conditions and the following disclaimer in the 1277962Snyan * documentation and/or other materials provided with the distribution. 1377962Snyan * 1477962Snyan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1577962Snyan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1677962Snyan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1777962Snyan * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1877962Snyan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1977962Snyan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2077962Snyan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2177962Snyan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2277962Snyan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2377962Snyan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2477962Snyan * SUCH DAMAGE. 2577962Snyan * 2677962Snyan * $FreeBSD$ 2777962Snyan */ 2877962Snyan 2977962Snyan/* 3077962Snyan * RSA Mode Driver Data Sheet 3177962Snyan * 3277962Snyan * <<Register Map>> 3377962Snyan * Base + 0x00 3477962Snyan * Mode Select Register(Read/Write) 3577962Snyan * bit4=interrupt type(1: level, 0: edge) 3677962Snyan * bit3=Auto RTS-CTS Flow Control Enable 3777962Snyan * bit2=External FIFO Enable 3877962Snyan * bit1=Reserved(Default 0)Don't Change!! 3977962Snyan * bit0=Swap Upper 8byte and Lower 8byte in 16byte space. 4077962Snyan * 4177962Snyan * Base + 0x01 4277962Snyan * Interrupt Enable Register(Read/Write) 4377962Snyan * bit4=Hardware Timer Interrupt Enable 4477962Snyan * bit3=Character Time-Out Interrupt Enable 4577962Snyan * bit2=Tx FIFO Empty Interrupt Enable 4677962Snyan * bit1=Tx FIFO Half Full Interrupt Enable 4777962Snyan * bit0=Rx FIFO Half Full Interrupt Enable 4877962Snyan * 4977962Snyan * Base + 0x02 5077962Snyan * Status Read Register(Read) 5177962Snyan * bit7=Hardware Time Out Interrupt Status(1: True, 0: False) 5277962Snyan * bit6=Character Time Out Interrupt Status 5377962Snyan * bit5=Rx FIFO Full Flag(0: True, 1: False) 5477962Snyan * bit4=Rx FIFO Half Full Flag 5577962Snyan * bit3=Rx FIFO Empty Flag 5677962Snyan * bit2=Tx FIFO Full Flag 5777962Snyan * bit1=Tx FIFO Half Full Flag 5877962Snyan * bit0=Tx FIFO Empty Flag 5977962Snyan * 6077962Snyan * Base + 0x02 6177962Snyan * FIFO Reset Register(Write) 6277962Snyan * Reset Extrnal FIFO 6377962Snyan * 6477962Snyan * Base + 0x03 6577962Snyan * Timer Interval Value Set Register(Read/Write) 6677962Snyan * Range of n: 1-255 6777962Snyan * Interval Value: n * 0.2ms 6877962Snyan * 6977962Snyan * Base + 0x04 7077962Snyan * Timer Control Register(Read/Write) 7177962Snyan * bit0=Timer Enable 7277962Snyan * 7377962Snyan * Base + 0x08 - 0x0f 7477962Snyan * Same as UART 16550 7577962Snyan * 7677962Snyan * Special Regisgter in RSA Mode 7777962Snyan * UART Data Register(Base + 0x08) 7877962Snyan * Data transfer between Extrnal FIFO 7977962Snyan * 8077962Snyan * UART MCR(Base + 0x0c) 8177962Snyan * bit3(OUT2[MCR_IENABLE])=1: Diable 16550 to Rx FIFO transfer 8277962Snyan * bit2(OUT1[MCR_DRS])=1: Diable Tx FIFO to 16550 transfer 8377962Snyan * 8477962Snyan * <<Intrrupt and Intrrupt Reset>> 8577962Snyan * o Reciver Line Status(from UART16550) 8677962Snyan * Reset: Read LSR 8777962Snyan * 8877962Snyan * o Modem Status(from UART16550) 8977962Snyan * Reset: Read MSR 9077962Snyan * 9177962Snyan * o Rx FIFO Half Full(from Extrnal FIFO) 9277962Snyan * Reset: Read Rx FIFO under Hall Full 9377962Snyan * 9477962Snyan * o Character Time Out(from Extrnal FIFO) 9577962Snyan * Reset: Read Rx FIFO or SRR 9677962Snyan * 9777962Snyan * o Tx FIFO Empty(from Extrnal FIFO) 9877962Snyan * Reset: Write Tx FIFO or Read SRR 9977962Snyan * 10077962Snyan * o Tx FIFO Half Full(from Extrnal FIFO) 10177962Snyan * Reset: Write Tx FIFO until Hall Full or Read SRR 10277962Snyan * 10377962Snyan * o Hardware Timer(from Extrnal FIFO) 10477962Snyan * Reset: Disable Timer in TCR 10577962Snyan * Notes: If you want to use Timer for next intrrupt, 10677962Snyan * you must enable Timer in TCR 10777962Snyan * 10877962Snyan * <<Used Setting>> 10977962Snyan * Auto RTS-CTS: Enable or Disable 11077962Snyan * External FIFO: Enable 11177962Snyan * Swap 8bytes: Disable 11277962Snyan * Haredware Timer: Disable 11377962Snyan * interrupt type: edge 11477962Snyan * interrupt source: 11577962Snyan * Hareware Timer 11677962Snyan * Character Time Out 11777962Snyan * Tx FIFO Empty 11877962Snyan * Rx FIFO Half Full 11977962Snyan * 12077962Snyan */ 12177962Snyan 12277962Snyan/* I/O-DATA RSA Serise Exrension Register */ 12377962Snyan#define rsa_msr 0 /* Mode Status Register (R/W) */ 12477962Snyan#define rsa_ier 1 /* Interrupt Enable Register (R/W) */ 12577962Snyan#define rsa_srr 2 /* Status Read Register (R) */ 12677962Snyan#define rsa_frr 2 /* FIFO Reset Register (W) */ 12777962Snyan#define rsa_tivsr 3 /* Timer Interval Value Set Register (R/W) */ 12877962Snyan#define rsa_tcr 4 /* Timer Control Register (W) */ 129