1124184Sjhb/*- 2124184Sjhb * Copyright (c) 2003 Peter Wemm 3124184Sjhb * All rights reserved. 4124184Sjhb * 5124184Sjhb * Redistribution and use in source and binary forms, with or without 6124184Sjhb * modification, are permitted provided that the following conditions 7124184Sjhb * are met: 8124184Sjhb * 1. Redistributions of source code must retain the above copyright 9124184Sjhb * notice, this list of conditions and the following disclaimer. 10124184Sjhb * 2. Redistributions in binary form must reproduce the above copyright 11124184Sjhb * notice, this list of conditions and the following disclaimer in the 12124184Sjhb * documentation and/or other materials provided with the distribution. 13124184Sjhb * 14124184Sjhb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15124184Sjhb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16124184Sjhb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17124184Sjhb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18124184Sjhb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19124184Sjhb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20124184Sjhb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21124184Sjhb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22124184Sjhb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23124184Sjhb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24124184Sjhb * SUCH DAMAGE. 25124184Sjhb * 26124184Sjhb * $FreeBSD$ 27124184Sjhb */ 28124184Sjhb 29124184Sjhb/* 30151580Sglebius * Register defintions for the i8259A programmable interrupt controller. 31124184Sjhb */ 32124184Sjhb 33124184Sjhb#ifndef _DEV_IC_I8259_H_ 34124184Sjhb#define _DEV_IC_I8259_H_ 35124184Sjhb 36124184Sjhb/* Initialization control word 1. Written to even address. */ 37124184Sjhb#define ICW1_IC4 0x01 /* ICW4 present */ 38124184Sjhb#define ICW1_SNGL 0x02 /* 1 = single, 0 = cascaded */ 39124184Sjhb#define ICW1_ADI 0x04 /* 1 = 4, 0 = 8 byte vectors */ 40124184Sjhb#define ICW1_LTIM 0x08 /* 1 = level trigger, 0 = edge */ 41124184Sjhb#define ICW1_RESET 0x10 /* must be 1 */ 42124184Sjhb/* 0x20 - 0x80 - in 8080/8085 mode only */ 43124184Sjhb 44124184Sjhb/* Initialization control word 2. Written to the odd address. */ 45124184Sjhb/* No definitions, it is the base vector of the IDT for 8086 mode */ 46124184Sjhb 47124184Sjhb/* Initialization control word 3. Written to the odd address. */ 48124184Sjhb/* For a master PIC, bitfield indicating a slave 8259 on given input */ 49124184Sjhb/* For slave, lower 3 bits are the slave's ID binary id on master */ 50124184Sjhb 51124184Sjhb/* Initialization control word 4. Written to the odd address. */ 52124184Sjhb#define ICW4_8086 0x01 /* 1 = 8086, 0 = 8080 */ 53124184Sjhb#define ICW4_AEOI 0x02 /* 1 = Auto EOI */ 54124184Sjhb#define ICW4_MS 0x04 /* 1 = buffered master, 0 = slave */ 55124184Sjhb#define ICW4_BUF 0x08 /* 1 = enable buffer mode */ 56124184Sjhb#define ICW4_SFNM 0x10 /* 1 = special fully nested mode */ 57124184Sjhb 58124184Sjhb/* Operation control words. Written after initialization. */ 59124184Sjhb 60124184Sjhb/* Operation control word type 1 */ 61124184Sjhb/* 62124184Sjhb * No definitions. Written to the odd address. Bitmask for interrupts. 63124184Sjhb * 1 = disabled. 64124184Sjhb */ 65124184Sjhb 66124184Sjhb/* Operation control word type 2. Bit 3 (0x08) must be zero. Even address. */ 67124184Sjhb#define OCW2_L0 0x01 /* Level */ 68124184Sjhb#define OCW2_L1 0x02 69124184Sjhb#define OCW2_L2 0x04 70124184Sjhb/* 0x08 must be 0 to select OCW2 vs OCW3 */ 71124184Sjhb/* 0x10 must be 0 to select OCW2 vs ICW1 */ 72124184Sjhb#define OCW2_EOI 0x20 /* 1 = EOI */ 73124184Sjhb#define OCW2_SL 0x40 /* EOI mode */ 74124184Sjhb#define OCW2_R 0x80 /* EOI mode */ 75124184Sjhb 76124184Sjhb/* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */ 77124184Sjhb#define OCW3_RIS 0x01 /* 1 = read IS, 0 = read IR */ 78124184Sjhb#define OCW3_RR 0x02 /* register read */ 79124184Sjhb#define OCW3_P 0x04 /* poll mode command */ 80124184Sjhb/* 0x08 must be 1 to select OCW3 vs OCW2 */ 81124184Sjhb#define OCW3_SEL 0x08 /* must be 1 */ 82124184Sjhb/* 0x10 must be 0 to select OCW3 vs ICW1 */ 83124184Sjhb#define OCW3_SMM 0x20 /* special mode mask */ 84124184Sjhb#define OCW3_ESMM 0x40 /* enable SMM */ 85124184Sjhb 86124184Sjhb#endif /* !_DEV_IC_I8259_H_ */ 87