1146211Snyan/*- 2146211Snyan * Copyright (c) 1993 The Regents of the University of California. 3146211Snyan * All rights reserved. 4146211Snyan * 5146211Snyan * Redistribution and use in source and binary forms, with or without 6146211Snyan * modification, are permitted provided that the following conditions 7146211Snyan * are met: 8146211Snyan * 1. Redistributions of source code must retain the above copyright 9146211Snyan * notice, this list of conditions and the following disclaimer. 10146211Snyan * 2. Redistributions in binary form must reproduce the above copyright 11146211Snyan * notice, this list of conditions and the following disclaimer in the 12146211Snyan * documentation and/or other materials provided with the distribution. 13146211Snyan * 4. Neither the name of the University nor the names of its contributors 14146211Snyan * may be used to endorse or promote products derived from this software 15146211Snyan * without specific prior written permission. 16146211Snyan * 17146211Snyan * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18146211Snyan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19146211Snyan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20146211Snyan * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21146211Snyan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22146211Snyan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23146211Snyan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24146211Snyan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25146211Snyan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26146211Snyan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27146211Snyan * SUCH DAMAGE. 28146211Snyan * 29146211Snyan * from: Header: timerreg.h,v 1.2 93/02/28 15:08:58 mccanne Exp 30146211Snyan * $FreeBSD$ 31146211Snyan */ 32146211Snyan 33146211Snyan/* 34146211Snyan * Register definitions for the Intel 8253 Programmable Interval Timer. 35146211Snyan * 36146211Snyan * This chip has three independent 16-bit down counters that can be 37146211Snyan * read on the fly. There are three mode registers and three countdown 38146211Snyan * registers. The countdown registers are addressed directly, via the 39146211Snyan * first three I/O ports. The three mode registers are accessed via 40146211Snyan * the fourth I/O port, with two bits in the mode byte indicating the 41146211Snyan * register. (Why are hardware interfaces always so braindead?). 42146211Snyan * 43146211Snyan * To write a value into the countdown register, the mode register 44146211Snyan * is first programmed with a command indicating the which byte of 45146211Snyan * the two byte register is to be modified. The three possibilities 46146211Snyan * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then 47146211Snyan * msb (TMR_MR_BOTH). 48146211Snyan * 49146211Snyan * To read the current value ("on the fly") from the countdown register, 50146211Snyan * you write a "latch" command into the mode register, then read the stable 51146211Snyan * value from the corresponding I/O port. For example, you write 52146211Snyan * TMR_MR_LATCH into the corresponding mode register. Presumably, 53146211Snyan * after doing this, a write operation to the I/O port would result 54146211Snyan * in undefined behavior (but hopefully not fry the chip). 55146211Snyan * Reading in this manner has no side effects. 56146211Snyan */ 57146211Snyan 58146211Snyan/* 59146211Snyan * Macros for specifying values to be written into a mode register. 60146211Snyan */ 61146211Snyan#define TIMER_REG_CNTR0 0 /* timer 0 counter port */ 62146211Snyan#define TIMER_REG_CNTR1 1 /* timer 1 counter port */ 63146211Snyan#define TIMER_REG_CNTR2 2 /* timer 2 counter port */ 64146215Snyan#define TIMER_REG_MODE 3 /* timer mode port */ 65146211Snyan#define TIMER_SEL0 0x00 /* select counter 0 */ 66146211Snyan#define TIMER_SEL1 0x40 /* select counter 1 */ 67146211Snyan#define TIMER_SEL2 0x80 /* select counter 2 */ 68146211Snyan#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ 69146211Snyan#define TIMER_ONESHOT 0x02 /* mode 1, one shot */ 70146211Snyan#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */ 71146211Snyan#define TIMER_SQWAVE 0x06 /* mode 3, square wave */ 72146211Snyan#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ 73146211Snyan#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ 74146211Snyan#define TIMER_LATCH 0x00 /* latch counter for reading */ 75146211Snyan#define TIMER_LSB 0x10 /* r/w counter LSB */ 76146211Snyan#define TIMER_MSB 0x20 /* r/w counter MSB */ 77146211Snyan#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ 78146211Snyan#define TIMER_BCD 0x01 /* count in BCD */ 79