1169412Sscottl/* 2175942Sscottl * HighPoint RR3xxx/4xxx RAID Driver for FreeBSD 3242086Sdelphij * Copyright (C) 2007-2012 HighPoint Technologies, Inc. All Rights Reserved. 4169412Sscottl * Redistribution and use in source and binary forms, with or without 5169412Sscottl * modification, are permitted provided that the following conditions 6169412Sscottl * are met: 7169412Sscottl * 1. Redistributions of source code must retain the above copyright 8169412Sscottl * notice, this list of conditions and the following disclaimer. 9169412Sscottl * 2. Redistributions in binary form must reproduce the above copyright 10169412Sscottl * notice, this list of conditions and the following disclaimer in the 11169412Sscottl * documentation and/or other materials provided with the distribution. 12169412Sscottl * 13169412Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14169412Sscottl * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15169412Sscottl * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16169412Sscottl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17169412Sscottl * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18169412Sscottl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19169412Sscottl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20169412Sscottl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21169412Sscottl * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22169412Sscottl * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23169412Sscottl * SUCH DAMAGE. 24169412Sscottl */ 25169412Sscottl 26169412Sscottl#ifndef _HPTIOP_H 27169412Sscottl#define _HPTIOP_H 28169412Sscottl 29169412Sscottl#include <sys/cdefs.h> 30169412Sscottl__FBSDID("$FreeBSD$"); 31169412Sscottl 32175942Sscottl#define DBG 0 33175942Sscottl 34169412Sscottl#ifdef DBG 35183590Santoineint hpt_iop_dbg_level = 0; 36183590Santoine#define KdPrint(x) do { if (hpt_iop_dbg_level) printf x; } while (0) 37169412Sscottl#define HPT_ASSERT(x) assert(x) 38169412Sscottl#else 39169412Sscottl#define KdPrint(x) 40169412Sscottl#define HPT_ASSERT(x) 41169412Sscottl#endif 42169412Sscottl 43169412Sscottl#define HPT_SRB_MAX_REQ_SIZE 600 44169412Sscottl#define HPT_SRB_MAX_QUEUE_SIZE 0x100 45169412Sscottl 46169412Sscottl/* beyond 64G mem */ 47169412Sscottl#define HPT_SRB_FLAG_HIGH_MEM_ACESS 0x1 48169412Sscottl#define HPT_SRB_MAX_SIZE ((sizeof(struct hpt_iop_srb) + 0x1f) & ~0x1f) 49175942Sscottl#ifndef offsetof 50175942Sscottl#define offsetof(TYPE, MEM) ((size_t)&((TYPE*)0)->MEM) 51175942Sscottl#endif 52169412Sscottl 53175942Sscottl#ifndef MIN 54175942Sscottl#define MIN(a, b) ((a) < (b) ? (a) : (b)) 55175942Sscottl#endif 56175942Sscottl 57169412Sscottl#define HPT_IOCTL_MAGIC 0xA1B2C3D4 58175942Sscottl#define HPT_IOCTL_MAGIC32 0x1A2B3C4D 59169412Sscottl 60175942Sscottlstruct hpt_iopmu_itl { 61169412Sscottl u_int32_t resrved0[4]; 62169412Sscottl u_int32_t inbound_msgaddr0; 63169412Sscottl u_int32_t inbound_msgaddr1; 64169412Sscottl u_int32_t outbound_msgaddr0; 65169412Sscottl u_int32_t outbound_msgaddr1; 66169412Sscottl u_int32_t inbound_doorbell; 67169412Sscottl u_int32_t inbound_intstatus; 68169412Sscottl u_int32_t inbound_intmask; 69169412Sscottl u_int32_t outbound_doorbell; 70169412Sscottl u_int32_t outbound_intstatus; 71169412Sscottl u_int32_t outbound_intmask; 72169412Sscottl u_int32_t reserved1[2]; 73169412Sscottl u_int32_t inbound_queue; 74169412Sscottl u_int32_t outbound_queue; 75169412Sscottl}; 76169412Sscottl 77169412Sscottl#define IOPMU_QUEUE_EMPTY 0xffffffff 78169412Sscottl#define IOPMU_QUEUE_MASK_HOST_BITS 0xf0000000 79169412Sscottl#define IOPMU_QUEUE_ADDR_HOST_BIT 0x80000000 80169412Sscottl#define IOPMU_QUEUE_REQUEST_SIZE_BIT 0x40000000 81169412Sscottl#define IOPMU_QUEUE_REQUEST_RESULT_BIT 0x40000000 82169412Sscottl#define IOPMU_MAX_MEM_SUPPORT_MASK_64G 0xfffffff000000000ull 83169412Sscottl#define IOPMU_MAX_MEM_SUPPORT_MASK_32G 0xfffffff800000000ull 84169412Sscottl 85169412Sscottl#define IOPMU_OUTBOUND_INT_MSG0 1 86169412Sscottl#define IOPMU_OUTBOUND_INT_MSG1 2 87169412Sscottl#define IOPMU_OUTBOUND_INT_DOORBELL 4 88169412Sscottl#define IOPMU_OUTBOUND_INT_POSTQUEUE 8 89169412Sscottl#define IOPMU_OUTBOUND_INT_PCI 0x10 90169412Sscottl 91169412Sscottl#define IOPMU_INBOUND_INT_MSG0 1 92169412Sscottl#define IOPMU_INBOUND_INT_MSG1 2 93169412Sscottl#define IOPMU_INBOUND_INT_DOORBELL 4 94169412Sscottl#define IOPMU_INBOUND_INT_ERROR 8 95169412Sscottl#define IOPMU_INBOUND_INT_POSTQUEUE 0x10 96169412Sscottl 97175942Sscottl#define MVIOP_QUEUE_LEN 512 98175942Sscottlstruct hpt_iopmu_mv { 99175942Sscottl u_int32_t inbound_head; 100175942Sscottl u_int32_t inbound_tail; 101175942Sscottl u_int32_t outbound_head; 102175942Sscottl u_int32_t outbound_tail; 103175942Sscottl u_int32_t inbound_msg; 104175942Sscottl u_int32_t outbound_msg; 105175942Sscottl u_int32_t reserve[10]; 106175942Sscottl u_int64_t inbound_q[MVIOP_QUEUE_LEN]; 107175942Sscottl u_int64_t outbound_q[MVIOP_QUEUE_LEN]; 108175942Sscottl}; 109175942Sscottl 110175942Sscottlstruct hpt_iopmv_regs { 111175942Sscottl u_int32_t reserved[0x20400 / 4]; 112175942Sscottl u_int32_t inbound_doorbell; 113175942Sscottl u_int32_t inbound_intmask; 114175942Sscottl u_int32_t outbound_doorbell; 115175942Sscottl u_int32_t outbound_intmask; 116175942Sscottl}; 117175942Sscottl 118242086Sdelphij#define CL_POINTER_TOGGLE 0x00004000 119242086Sdelphij#define CPU_TO_F0_DRBL_MSG_A_BIT 0x02000000 120242086Sdelphij 121242086Sdelphij#pragma pack(1) 122242086Sdelphijstruct hpt_iopmu_mvfrey { 123242086Sdelphij u_int32_t reserved[0x4000 / 4]; 124242086Sdelphij 125242086Sdelphij /* hpt_frey_com_reg */ 126242086Sdelphij u_int32_t inbound_base; /* 0x4000 : 0 */ 127242086Sdelphij u_int32_t inbound_base_high; /* 4 */ 128242086Sdelphij u_int32_t reserved2[(0x18 - 8)/ 4]; 129242086Sdelphij u_int32_t inbound_write_ptr; /* 0x18 */ 130242086Sdelphij u_int32_t inbound_read_ptr; /* 0x1c */ 131242086Sdelphij u_int32_t reserved3[(0x2c - 0x20) / 4]; 132242086Sdelphij u_int32_t inbound_conf_ctl; /* 0x2c */ 133242086Sdelphij u_int32_t reserved4[(0x50 - 0x30) / 4]; 134242086Sdelphij u_int32_t outbound_base; /* 0x50 */ 135242086Sdelphij u_int32_t outbound_base_high; /* 0x54 */ 136242086Sdelphij u_int32_t outbound_shadow_base; /* 0x58 */ 137242086Sdelphij u_int32_t outbound_shadow_base_high; /* 0x5c */ 138242086Sdelphij u_int32_t reserved5[(0x68 - 0x60) / 4]; 139242086Sdelphij u_int32_t outbound_write; /* 0x68 */ 140242086Sdelphij u_int32_t reserved6[(0x70 - 0x6c) / 4]; 141242086Sdelphij u_int32_t outbound_read; /* 0x70 */ 142242086Sdelphij u_int32_t reserved7[(0x88 - 0x74) / 4]; 143242086Sdelphij u_int32_t isr_cause; /* 0x88 */ 144242086Sdelphij u_int32_t isr_enable; /* 0x8c */ 145242086Sdelphij 146242086Sdelphij u_int32_t reserved8[(0x10200 - 0x4090) / 4]; 147242086Sdelphij 148242086Sdelphij /* hpt_frey_intr_ctl intr_ctl */ 149242086Sdelphij u_int32_t main_int_cuase; /* 0x10200: 0 */ 150242086Sdelphij u_int32_t main_irq_enable; /* 4 */ 151242086Sdelphij u_int32_t main_fiq_enable; /* 8 */ 152242086Sdelphij u_int32_t pcie_f0_int_enable; /* 0xc */ 153242086Sdelphij u_int32_t pcie_f1_int_enable; /* 0x10 */ 154242086Sdelphij u_int32_t pcie_f2_int_enable; /* 0x14 */ 155242086Sdelphij u_int32_t pcie_f3_int_enable; /* 0x18 */ 156242086Sdelphij 157242086Sdelphij u_int32_t reserved9[(0x10400 - 0x1021c) / 4]; 158242086Sdelphij 159242086Sdelphij /* hpt_frey_msg_drbl */ 160242086Sdelphij u_int32_t f0_to_cpu_msg_a; /* 0x10400: 0 */ 161242086Sdelphij u_int32_t reserved10[(0x20 - 4) / 4]; 162242086Sdelphij u_int32_t cpu_to_f0_msg_a; /* 0x20 */ 163242086Sdelphij u_int32_t reserved11[(0x80 - 0x24) / 4]; 164242086Sdelphij u_int32_t f0_doorbell; /* 0x80 */ 165242086Sdelphij u_int32_t f0_doorbell_enable; /* 0x84 */ 166242086Sdelphij}; 167242086Sdelphij 168242086Sdelphijstruct mvfrey_inlist_entry { 169242086Sdelphij u_int64_t addr; 170242086Sdelphij u_int32_t intrfc_len; 171242086Sdelphij u_int32_t reserved; 172242086Sdelphij}; 173242086Sdelphij 174242086Sdelphijstruct mvfrey_outlist_entry { 175242086Sdelphij u_int32_t val; 176242086Sdelphij}; 177242086Sdelphij 178242086Sdelphij#pragma pack() 179242086Sdelphij 180175942Sscottl#define MVIOP_IOCTLCFG_SIZE 0x800 181175942Sscottl#define MVIOP_MU_QUEUE_ADDR_HOST_MASK (~(0x1full)) 182175942Sscottl#define MVIOP_MU_QUEUE_ADDR_HOST_BIT 4 183175942Sscottl 184175942Sscottl#define MVIOP_MU_QUEUE_ADDR_IOP_HIGH32 0xffffffff 185175942Sscottl#define MVIOP_MU_QUEUE_REQUEST_RESULT_BIT 1 186175942Sscottl#define MVIOP_MU_QUEUE_REQUEST_RETURN_CONTEXT 2 187175942Sscottl 188175942Sscottl#define MVIOP_MU_INBOUND_INT_MSG 1 189175942Sscottl#define MVIOP_MU_INBOUND_INT_POSTQUEUE 2 190175942Sscottl#define MVIOP_MU_OUTBOUND_INT_MSG 1 191175942Sscottl#define MVIOP_MU_OUTBOUND_INT_POSTQUEUE 2 192175942Sscottl 193175942Sscottl#define MVIOP_CMD_TYPE_GET_CONFIG (1 << 5) 194175942Sscottl#define MVIOP_CMD_TYPE_SET_CONFIG (1 << 6) 195175942Sscottl#define MVIOP_CMD_TYPE_SCSI (1 << 7) 196175942Sscottl#define MVIOP_CMD_TYPE_IOCTL (1 << 8) 197175942Sscottl#define MVIOP_CMD_TYPE_BLOCK (1 << 9) 198175942Sscottl 199175942Sscottl#define MVIOP_REQUEST_NUMBER_START_BIT 16 200175942Sscottl 201242086Sdelphij#define MVFREYIOPMU_QUEUE_REQUEST_RESULT_BIT 0x40000000 202242086Sdelphij 203169412Sscottlenum hpt_iopmu_message { 204169412Sscottl /* host-to-iop messages */ 205169412Sscottl IOPMU_INBOUND_MSG0_NOP = 0, 206169412Sscottl IOPMU_INBOUND_MSG0_RESET, 207169412Sscottl IOPMU_INBOUND_MSG0_FLUSH, 208169412Sscottl IOPMU_INBOUND_MSG0_SHUTDOWN, 209169412Sscottl IOPMU_INBOUND_MSG0_STOP_BACKGROUND_TASK, 210169412Sscottl IOPMU_INBOUND_MSG0_START_BACKGROUND_TASK, 211242086Sdelphij IOPMU_INBOUND_MSG0_RESET_COMM, 212169412Sscottl IOPMU_INBOUND_MSG0_MAX = 0xff, 213169412Sscottl /* iop-to-host messages */ 214169412Sscottl IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_0 = 0x100, 215169412Sscottl IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_MAX = 0x1ff, 216169412Sscottl IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_0 = 0x200, 217169412Sscottl IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_MAX = 0x2ff, 218169412Sscottl IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_0 = 0x300, 219169412Sscottl IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_MAX = 0x3ff, 220169412Sscottl}; 221169412Sscottl 222169412Sscottl#define IOP_REQUEST_FLAG_SYNC_REQUEST 1 223169412Sscottl#define IOP_REQUEST_FLAG_BIST_REQUEST 2 224169412Sscottl#define IOP_REQUEST_FLAG_REMAPPED 4 225169412Sscottl#define IOP_REQUEST_FLAG_OUTPUT_CONTEXT 8 226169412Sscottl 227242086Sdelphij#define IOP_REQUEST_FLAG_ADDR_BITS 0x40 /* flags[31:16] is phy_addr[47:32] */ 228242086Sdelphij 229169412Sscottlenum hpt_iop_request_type { 230169412Sscottl IOP_REQUEST_TYPE_GET_CONFIG = 0, 231169412Sscottl IOP_REQUEST_TYPE_SET_CONFIG, 232169412Sscottl IOP_REQUEST_TYPE_BLOCK_COMMAND, 233169412Sscottl IOP_REQUEST_TYPE_SCSI_COMMAND, 234169412Sscottl IOP_REQUEST_TYPE_IOCTL_COMMAND, 235169412Sscottl IOP_REQUEST_TYPE_MAX 236169412Sscottl}; 237169412Sscottl 238169412Sscottlenum hpt_iop_result_type { 239169412Sscottl IOP_RESULT_PENDING = 0, 240169412Sscottl IOP_RESULT_SUCCESS, 241169412Sscottl IOP_RESULT_FAIL, 242169412Sscottl IOP_RESULT_BUSY, 243169412Sscottl IOP_RESULT_RESET, 244169412Sscottl IOP_RESULT_INVALID_REQUEST, 245169412Sscottl IOP_RESULT_BAD_TARGET, 246175942Sscottl IOP_RESULT_CHECK_CONDITION, 247169412Sscottl}; 248169412Sscottl 249242086Sdelphij#pragma pack(1) 250175942Sscottlstruct hpt_iop_request_header { 251175942Sscottl u_int32_t size; 252175942Sscottl u_int32_t type; 253175942Sscottl u_int32_t flags; 254175942Sscottl u_int32_t result; 255175942Sscottl u_int64_t context; /* host context */ 256175942Sscottl}; 257175942Sscottl 258175942Sscottlstruct hpt_iop_request_get_config { 259169412Sscottl struct hpt_iop_request_header header; 260169412Sscottl u_int32_t interface_version; 261169412Sscottl u_int32_t firmware_version; 262169412Sscottl u_int32_t max_requests; 263169412Sscottl u_int32_t request_size; 264169412Sscottl u_int32_t max_sg_count; 265169412Sscottl u_int32_t data_transfer_length; 266169412Sscottl u_int32_t alignment_mask; 267169412Sscottl u_int32_t max_devices; 268169412Sscottl u_int32_t sdram_size; 269169412Sscottl}; 270169412Sscottl 271175942Sscottlstruct hpt_iop_request_set_config { 272169412Sscottl struct hpt_iop_request_header header; 273169412Sscottl u_int32_t iop_id; 274169412Sscottl u_int16_t vbus_id; 275175942Sscottl u_int16_t max_host_request_size; 276169412Sscottl u_int32_t reserve[6]; 277169412Sscottl}; 278169412Sscottl 279175942Sscottlstruct hpt_iopsg { 280169412Sscottl u_int32_t size; 281169412Sscottl u_int32_t eot; /* non-zero: end of table */ 282169412Sscottl u_int64_t pci_address; 283169412Sscottl}; 284169412Sscottl 285175942Sscottl#define IOP_BLOCK_COMMAND_READ 1 286175942Sscottl#define IOP_BLOCK_COMMAND_WRITE 2 287175942Sscottl#define IOP_BLOCK_COMMAND_VERIFY 3 288175942Sscottl#define IOP_BLOCK_COMMAND_FLUSH 4 289175942Sscottl#define IOP_BLOCK_COMMAND_SHUTDOWN 5 290175942Sscottlstruct hpt_iop_request_block_command { 291169412Sscottl struct hpt_iop_request_header header; 292169412Sscottl u_int8_t channel; 293169412Sscottl u_int8_t target; 294169412Sscottl u_int8_t lun; 295169412Sscottl u_int8_t pad1; 296175942Sscottl u_int16_t command; /* IOP_BLOCK_COMMAND_{READ,WRITE} */ 297175942Sscottl u_int16_t sectors; 298175942Sscottl u_int64_t lba; 299169412Sscottl struct hpt_iopsg sg_list[1]; 300169412Sscottl}; 301169412Sscottl 302175942Sscottlstruct hpt_iop_request_scsi_command { 303169412Sscottl struct hpt_iop_request_header header; 304169412Sscottl u_int8_t channel; 305169412Sscottl u_int8_t target; 306169412Sscottl u_int8_t lun; 307169412Sscottl u_int8_t pad1; 308169412Sscottl u_int8_t cdb[16]; 309175942Sscottl u_int32_t dataxfer_length; 310169412Sscottl struct hpt_iopsg sg_list[1]; 311169412Sscottl}; 312169412Sscottl 313175942Sscottlstruct hpt_iop_request_ioctl_command { 314169412Sscottl struct hpt_iop_request_header header; 315169412Sscottl u_int32_t ioctl_code; 316169412Sscottl u_int32_t inbuf_size; 317169412Sscottl u_int32_t outbuf_size; 318169412Sscottl u_int32_t bytes_returned; 319169412Sscottl u_int8_t buf[1]; 320169412Sscottl /* out data should be put at buf[(inbuf_size+3)&~3] */ 321169412Sscottl}; 322169412Sscottl 323175942Sscottlstruct hpt_iop_ioctl_param { 324175942Sscottl u_int32_t Magic; /* used to check if it's a valid ioctl packet */ 325175942Sscottl u_int32_t dwIoControlCode; /* operation control code */ 326175942Sscottl unsigned long lpInBuffer; /* input data buffer */ 327175942Sscottl u_int32_t nInBufferSize; /* size of input data buffer */ 328175942Sscottl unsigned long lpOutBuffer; /* output data buffer */ 329175942Sscottl u_int32_t nOutBufferSize; /* size of output data buffer */ 330175942Sscottl unsigned long lpBytesReturned; /* count of HPT_U8s returned */ 331190405Sdelphij} __packed; 332175942Sscottl 333175942Sscottl#define HPT_IOCTL_FLAG_OPEN 1 334169412Sscottl#define HPT_CTL_CODE_BSD_TO_IOP(x) ((x)-0xff00) 335169412Sscottl 336169412Sscottltypedef struct cdev * ioctl_dev_t; 337169412Sscottl 338169412Sscottltypedef struct thread * ioctl_thread_t; 339169412Sscottl 340169412Sscottlstruct hpt_iop_hba { 341175942Sscottl struct hptiop_adapter_ops *ops; 342175942Sscottl union { 343175942Sscottl struct { 344175942Sscottl struct hpt_iopmu_itl *mu; 345175942Sscottl } itl; 346175942Sscottl struct { 347175942Sscottl struct hpt_iopmv_regs *regs; 348175942Sscottl struct hpt_iopmu_mv *mu; 349175942Sscottl } mv; 350242086Sdelphij struct { 351242086Sdelphij struct hpt_iop_request_get_config *config; 352242086Sdelphij struct hpt_iopmu_mvfrey *mu; 353242086Sdelphij 354242086Sdelphij int internal_mem_size; 355242086Sdelphij int list_count; 356242086Sdelphij struct mvfrey_inlist_entry *inlist; 357242086Sdelphij u_int64_t inlist_phy; 358242086Sdelphij u_int32_t inlist_wptr; 359242086Sdelphij struct mvfrey_outlist_entry *outlist; 360242086Sdelphij u_int64_t outlist_phy; 361242086Sdelphij u_int32_t *outlist_cptr; /* copy pointer shadow */ 362242086Sdelphij u_int64_t outlist_cptr_phy; 363242086Sdelphij u_int32_t outlist_rptr; 364242086Sdelphij } mvfrey; 365175942Sscottl } u; 366169412Sscottl 367175942Sscottl struct hpt_iop_hba *next; 368175942Sscottl 369169412Sscottl u_int32_t firmware_version; 370175942Sscottl u_int32_t interface_version; 371169412Sscottl u_int32_t max_devices; 372169412Sscottl u_int32_t max_requests; 373169412Sscottl u_int32_t max_request_size; 374169412Sscottl u_int32_t max_sg_count; 375169412Sscottl 376175942Sscottl u_int32_t msg_done; 377169412Sscottl 378175942Sscottl device_t pcidev; 379175942Sscottl u_int32_t pciunit; 380175942Sscottl ioctl_dev_t ioctl_dev; 381169412Sscottl 382175942Sscottl bus_dma_tag_t parent_dmat; 383175942Sscottl bus_dma_tag_t io_dmat; 384175942Sscottl bus_dma_tag_t srb_dmat; 385175942Sscottl bus_dma_tag_t ctlcfg_dmat; 386175942Sscottl 387175942Sscottl bus_dmamap_t srb_dmamap; 388175942Sscottl bus_dmamap_t ctlcfg_dmamap; 389169412Sscottl 390175942Sscottl struct resource *bar0_res; 391175942Sscottl bus_space_tag_t bar0t; 392175942Sscottl bus_space_handle_t bar0h; 393175942Sscottl int bar0_rid; 394175942Sscottl 395175942Sscottl struct resource *bar2_res; 396175942Sscottl bus_space_tag_t bar2t; 397175942Sscottl bus_space_handle_t bar2h; 398175942Sscottl int bar2_rid; 399175942Sscottl 400169412Sscottl /* to release */ 401169412Sscottl u_int8_t *uncached_ptr; 402175942Sscottl void *ctlcfg_ptr; 403169412Sscottl /* for scsi request block */ 404175942Sscottl struct hpt_iop_srb *srb_list; 405169412Sscottl /* for interrupt */ 406175942Sscottl struct resource *irq_res; 407175942Sscottl void *irq_handle; 408175942Sscottl 409175942Sscottl /* for ioctl and set/get config */ 410175942Sscottl struct resource *ctlcfg_res; 411175942Sscottl void *ctlcfg_handle; 412175942Sscottl u_int64_t ctlcfgcmd_phy; 413242086Sdelphij u_int32_t config_done; /* can be negative value */ 414242086Sdelphij u_int32_t initialized:1; 415175942Sscottl 416169412Sscottl /* other resources */ 417175942Sscottl struct cam_sim *sim; 418175942Sscottl struct cam_path *path; 419175942Sscottl void *req; 420175942Sscottl struct mtx lock; 421169412Sscottl#define HPT_IOCTL_FLAG_OPEN 1 422169412Sscottl u_int32_t flag; 423169412Sscottl struct hpt_iop_srb* srb[HPT_SRB_MAX_QUEUE_SIZE]; 424169412Sscottl}; 425242086Sdelphij#pragma pack() 426169412Sscottl 427242086Sdelphijenum hptiop_family { 428242086Sdelphij INTEL_BASED_IOP = 0, 429242086Sdelphij MV_BASED_IOP, 430242086Sdelphij MVFREY_BASED_IOP, 431242086Sdelphij UNKNOWN_BASED_IOP = 0xf 432242086Sdelphij}; 433242086Sdelphij 434175942Sscottlstruct hptiop_adapter_ops { 435242086Sdelphij enum hptiop_family family; 436175942Sscottl int (*iop_wait_ready)(struct hpt_iop_hba *hba, u_int32_t millisec); 437175942Sscottl int (*internal_memalloc)(struct hpt_iop_hba *hba); 438175942Sscottl int (*internal_memfree)(struct hpt_iop_hba *hba); 439175942Sscottl int (*alloc_pci_res)(struct hpt_iop_hba *hba); 440175942Sscottl void (*release_pci_res)(struct hpt_iop_hba *hba); 441175942Sscottl void (*enable_intr)(struct hpt_iop_hba *hba); 442175942Sscottl void (*disable_intr)(struct hpt_iop_hba *hba); 443175942Sscottl int (*get_config)(struct hpt_iop_hba *hba, 444175942Sscottl struct hpt_iop_request_get_config *config); 445175942Sscottl int (*set_config)(struct hpt_iop_hba *hba, 446175942Sscottl struct hpt_iop_request_set_config *config); 447175942Sscottl int (*iop_intr)(struct hpt_iop_hba *hba); 448175942Sscottl void (*post_msg)(struct hpt_iop_hba *hba, u_int32_t msg); 449175942Sscottl void (*post_req)(struct hpt_iop_hba *hba, struct hpt_iop_srb *srb, bus_dma_segment_t *segs, int nsegs); 450242086Sdelphij int (*do_ioctl)(struct hpt_iop_hba *hba, struct hpt_iop_ioctl_param * pParams); 451242086Sdelphij int (*reset_comm)(struct hpt_iop_hba *hba); 452175942Sscottl}; 453175942Sscottl 454175942Sscottlstruct hpt_iop_srb { 455175942Sscottl u_int8_t req[HPT_SRB_MAX_REQ_SIZE]; 456175942Sscottl struct hpt_iop_hba *hba; 457175942Sscottl union ccb *ccb; 458175942Sscottl struct hpt_iop_srb *next; 459175942Sscottl bus_dmamap_t dma_map; 460175942Sscottl u_int64_t phy_addr; 461175942Sscottl u_int32_t srb_flag; 462175942Sscottl int index; 463255871Sscottl struct callout_handle timeout_ch; 464175942Sscottl}; 465175942Sscottl 466169412Sscottl#define hptiop_lock_adapter(hba) mtx_lock(&(hba)->lock) 467169412Sscottl#define hptiop_unlock_adapter(hba) mtx_unlock(&(hba)->lock) 468169412Sscottl 469169412Sscottl#define HPT_OSM_TIMEOUT (20*hz) /* timeout value for OS commands */ 470169412Sscottl 471169412Sscottl#define HPT_DO_IOCONTROL _IOW('H', 0, struct hpt_iop_ioctl_param) 472169412Sscottl#define HPT_SCAN_BUS _IO('H', 1) 473169412Sscottl 474169412Sscottlstatic __inline int hptiop_sleep(struct hpt_iop_hba *hba, void *ident, 475169412Sscottl int priority, const char *wmesg, int timo) 476169412Sscottl{ 477169412Sscottl 478169412Sscottl int retval; 479169412Sscottl 480169412Sscottl retval = msleep(ident, &hba->lock, priority, wmesg, timo); 481169412Sscottl 482169412Sscottl return retval; 483169412Sscottl 484169412Sscottl} 485169412Sscottl 486169412Sscottl 487169412Sscottl#define HPT_DEV_MAJOR 200 488169412Sscottl 489169412Sscottl#endif 490169412Sscottl 491