1228940Sdelphij/*- 2228940Sdelphij * Copyright (c) 2011 HighPoint Technologies, Inc. 3228940Sdelphij * All rights reserved. 4228940Sdelphij * 5228940Sdelphij * Redistribution and use in source and binary forms, with or without 6228940Sdelphij * modification, are permitted provided that the following conditions 7228940Sdelphij * are met: 8228940Sdelphij * 1. Redistributions of source code must retain the above copyright 9228940Sdelphij * notice, this list of conditions and the following disclaimer. 10228940Sdelphij * 2. Redistributions in binary form must reproduce the above copyright 11228940Sdelphij * notice, this list of conditions and the following disclaimer in the 12228940Sdelphij * documentation and/or other materials provided with the distribution. 13228940Sdelphij * 14228940Sdelphij * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15228940Sdelphij * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16228940Sdelphij * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17228940Sdelphij * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18228940Sdelphij * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19228940Sdelphij * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20228940Sdelphij * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21228940Sdelphij * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22228940Sdelphij * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23228940Sdelphij * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24228940Sdelphij * SUCH DAMAGE. 25228940Sdelphij * 26228940Sdelphij * $FreeBSD$ 27228940Sdelphij */ 28228940Sdelphij 29228940Sdelphij#include <dev/hpt27xx/hpt27xx_config.h> 30228940Sdelphij 31228940Sdelphij#ifndef _HPT_HIM_H_ 32228940Sdelphij#define _HPT_HIM_H_ 33228940Sdelphij 34228940Sdelphij#define VERMAGIC_HIM 55 35228940Sdelphij 36228940Sdelphij#if defined(__cplusplus) 37228940Sdelphijextern "C" { 38228940Sdelphij#endif 39228940Sdelphij 40228940Sdelphij#include <dev/hpt27xx/list.h> 41228940Sdelphij 42228940Sdelphij#define SECTOR_TO_BYTE_SHIFT 9 43228940Sdelphij#define SECTOR_TO_BYTE(x) ((HPT_U32)(x) << SECTOR_TO_BYTE_SHIFT) 44228940Sdelphij#define BYTE_TO_SECTOR(x) ((x)>>SECTOR_TO_BYTE_SHIFT) 45228940Sdelphij 46228940Sdelphijtypedef struct _PCI_ID 47228940Sdelphij{ 48228940Sdelphij HPT_U16 vid; 49228940Sdelphij HPT_U16 did; 50228940Sdelphij HPT_U32 subsys; 51228940Sdelphij HPT_U8 rev; 52228940Sdelphij HPT_U8 nbase; 53228940Sdelphij HPT_U16 reserve; 54228940Sdelphij} 55228940SdelphijPCI_ID; 56228940Sdelphij 57228940Sdelphijtypedef struct _PCI_ADDRESS 58228940Sdelphij{ 59228940Sdelphij HPT_U8 tree; 60228940Sdelphij HPT_U8 bus; 61228940Sdelphij HPT_U8 device; 62228940Sdelphij HPT_U8 function; 63228940Sdelphij} 64228940SdelphijPCI_ADDRESS; 65228940Sdelphij 66228940Sdelphijtypedef struct _HIM_ADAPTER_CONFIG 67228940Sdelphij{ 68228940Sdelphij PCI_ADDRESS pci_addr; 69228940Sdelphij PCI_ID pci_id; 70228940Sdelphij 71228940Sdelphij HPT_U8 max_devices; 72228940Sdelphij 73228940Sdelphij HPT_U8 bProbeInInitializing:1; 74228940Sdelphij 75228940Sdelphij HPT_U8 bSpinupOneDevEachTime:1; 76228940Sdelphij 77228940Sdelphij HPT_U8 bGlobalNcq:1; 78228940Sdelphij HPT_U8 bSGPIOPartSupport:1; 79228940Sdelphij 80228940Sdelphij HPT_U8 bNeedSASIdleTimer:1; 81228940Sdelphij HPT_U8 reserved:3; 82228940Sdelphij 83228940Sdelphij HPT_U8 bDevsPerBus; 84228940Sdelphij HPT_U8 first_on_slot; 85228940Sdelphij 86228940Sdelphij HPT_U8 bChipType; 87228940Sdelphij HPT_U8 bChipIntrNum; 88228940Sdelphij HPT_U8 bChipFlags; 89228940Sdelphij HPT_U8 bNumBuses; 90228940Sdelphij 91228940Sdelphij HPT_U8 szVendorID[36]; 92228940Sdelphij HPT_U8 szProductID[36]; 93228940Sdelphij HPT_U32 nvramSize; 94228940Sdelphij HPT_U64 nvramAddress; 95228940Sdelphij HPT_U8 slot_index; 96284879Sdelphij HPT_U8 maxWidth; 97284879Sdelphij HPT_U8 currentWidth; 98284879Sdelphij HPT_U8 maxSpeed; 99284879Sdelphij HPT_U8 currentSpeed; 100284879Sdelphij HPT_U8 reserved2[7]; 101228940Sdelphij} 102228940SdelphijHIM_ADAPTER_CONFIG, *PHIM_ADAPTER_CONFIG; 103228940Sdelphij 104228940Sdelphijtypedef struct _HIM_CHANNEL_CONFIG 105228940Sdelphij{ 106228940Sdelphij HPT_U32 io_port; 107228940Sdelphij HPT_U32 ctl_port; 108228940Sdelphij} HIM_CHANNEL_CONFIG, *PHIM_CHANNEL_CONFIG; 109228940Sdelphij 110228940Sdelphijtypedef struct _HIM_DEVICE_FLAGS 111228940Sdelphij{ 112228940Sdelphij HPT_UINT df_atapi :1; 113228940Sdelphij HPT_UINT df_removable_drive :1; 114228940Sdelphij HPT_UINT df_on_line :1; 115228940Sdelphij HPT_UINT df_reduce_mode :1; 116228940Sdelphij HPT_UINT df_sata :1; 117228940Sdelphij HPT_UINT df_on_pm_port :1; 118228940Sdelphij HPT_UINT df_support_read_ahead :1; 119228940Sdelphij HPT_UINT df_read_ahead_enabled :1; 120228940Sdelphij HPT_UINT df_support_write_cache :1; 121228940Sdelphij HPT_UINT df_write_cache_enabled :1; 122228940Sdelphij HPT_UINT df_cdrom_device :1; 123228940Sdelphij HPT_UINT df_tape_device :1; 124284879Sdelphij HPT_UINT df_changer_device :1; 125228940Sdelphij HPT_UINT df_support_tcq :1; 126228940Sdelphij HPT_UINT df_tcq_enabled :1; 127228940Sdelphij HPT_UINT df_support_ncq :1; 128228940Sdelphij HPT_UINT df_ncq_enabled :1; 129228940Sdelphij HPT_UINT df_sas :1; 130228940Sdelphij HPT_UINT df_in_enclosure :1; 131228940Sdelphij HPT_UINT df_ssd :1; 132228940Sdelphij} DEVICE_FLAGS, *PDEVICE_FLAGS; 133228940Sdelphij 134228940Sdelphij#pragma pack(1) 135228940Sdelphijtypedef struct _IDENTIFY_DATA { 136228940Sdelphij HPT_U16 GeneralConfiguration; 137228940Sdelphij HPT_U16 NumberOfCylinders; 138228940Sdelphij HPT_U16 Reserved1; 139228940Sdelphij HPT_U16 NumberOfHeads; 140228940Sdelphij HPT_U16 UnformattedBytesPerTrack; 141228940Sdelphij HPT_U16 UnformattedBytesPerSector; 142228940Sdelphij HPT_U8 SasAddress[8]; 143228940Sdelphij HPT_U16 SerialNumber[10]; 144228940Sdelphij HPT_U16 BufferType; 145228940Sdelphij HPT_U16 BufferSectorSize; 146228940Sdelphij HPT_U16 NumberOfEccBytes; 147228940Sdelphij HPT_U16 FirmwareRevision[4]; 148228940Sdelphij HPT_U16 ModelNumber[20]; 149228940Sdelphij HPT_U8 MaximumBlockTransfer; 150228940Sdelphij HPT_U8 VendorUnique2; 151228940Sdelphij HPT_U16 DoubleWordIo; 152228940Sdelphij HPT_U16 Capabilities; 153228940Sdelphij HPT_U16 Reserved2; 154228940Sdelphij HPT_U8 VendorUnique3; 155228940Sdelphij HPT_U8 PioCycleTimingMode; 156228940Sdelphij HPT_U8 VendorUnique4; 157228940Sdelphij HPT_U8 DmaCycleTimingMode; 158228940Sdelphij HPT_U16 TranslationFieldsValid; 159228940Sdelphij HPT_U16 NumberOfCurrentCylinders; 160228940Sdelphij HPT_U16 NumberOfCurrentHeads; 161228940Sdelphij HPT_U16 CurrentSectorsPerTrack; 162228940Sdelphij HPT_U32 CurrentSectorCapacity; 163228940Sdelphij HPT_U16 CurrentMultiSectorSetting; 164228940Sdelphij HPT_U32 UserAddressableSectors; 165228940Sdelphij HPT_U8 SingleWordDMASupport; 166228940Sdelphij HPT_U8 SingleWordDMAActive; 167228940Sdelphij HPT_U8 MultiWordDMASupport; 168228940Sdelphij HPT_U8 MultiWordDMAActive; 169228940Sdelphij HPT_U8 AdvancedPIOModes; 170228940Sdelphij HPT_U8 Reserved4; 171228940Sdelphij HPT_U16 MinimumMWXferCycleTime; 172228940Sdelphij HPT_U16 RecommendedMWXferCycleTime; 173228940Sdelphij HPT_U16 MinimumPIOCycleTime; 174228940Sdelphij HPT_U16 MinimumPIOCycleTimeIORDY; 175228940Sdelphij HPT_U16 Reserved5[2]; 176228940Sdelphij HPT_U16 ReleaseTimeOverlapped; 177228940Sdelphij HPT_U16 ReleaseTimeServiceCommand; 178228940Sdelphij HPT_U16 MajorRevision; 179228940Sdelphij HPT_U16 MinorRevision; 180228940Sdelphij HPT_U16 MaxQueueDepth; 181228940Sdelphij HPT_U16 SataCapability; 182228940Sdelphij HPT_U16 Reserved6[9]; 183228940Sdelphij HPT_U16 CommandSupport; 184228940Sdelphij HPT_U16 CommandEnable; 185228940Sdelphij HPT_U16 UtralDmaMode; 186228940Sdelphij HPT_U16 Reserved7[11]; 187228940Sdelphij HPT_U32 Lba48BitLow; 188228940Sdelphij HPT_U32 Lba48BitHigh; 189228940Sdelphij HPT_U16 Reserved8[23]; 190228940Sdelphij HPT_U16 SpecialFunctionsEnabled; 191228940Sdelphij HPT_U16 Reserved9[128]; 192228940Sdelphij} 193228940Sdelphij#ifdef __GNUC__ 194228940Sdelphij__attribute__((packed)) 195228940Sdelphij#endif 196228940SdelphijIDENTIFY_DATA, *PIDENTIFY_DATA; 197228940Sdelphij#pragma pack() 198228940Sdelphij 199228940Sdelphijtypedef struct _HIM_DEVICE_CONFIG 200228940Sdelphij{ 201228940Sdelphij HPT_U64 capacity; 202284879Sdelphij HPT_U32 logical_sector_size; 203284879Sdelphij 204228940Sdelphij DEVICE_FLAGS flags; 205228940Sdelphij 206228940Sdelphij HPT_U8 path_id; 207228940Sdelphij HPT_U8 target_id; 208228940Sdelphij HPT_U8 max_queue_depth; 209228940Sdelphij HPT_U8 spin_up_mode; 210228940Sdelphij 211228940Sdelphij HPT_U8 reserved; 212228940Sdelphij HPT_U8 transfer_mode; 213228940Sdelphij HPT_U8 bMaxShowMode; 214228940Sdelphij HPT_U8 bDeUsable_Mode; 215228940Sdelphij 216228940Sdelphij HPT_U16 max_sectors_per_cmd; 217228940Sdelphij 218228940Sdelphij PIDENTIFY_DATA pIdentifyData; 219228940Sdelphij 220228940Sdelphij 221228940Sdelphij HPT_U8 fixed_path_id; /*equals to phy id */ 222228940Sdelphij} 223228940SdelphijHIM_DEVICE_CONFIG, *PHIM_DEVICE_CONFIG; 224228940Sdelphij 225228940Sdelphij 226228940Sdelphij#define _DIT_MODE 0 227228940Sdelphij#define _DIT_601 1 228228940Sdelphij#define _DIT_READ_AHEAD 2 229228940Sdelphij#define _DIT_WRITE_CACHE 3 230228940Sdelphij#define _DIT_TCQ 4 231228940Sdelphij#define _DIT_NCQ 5 232228940Sdelphij#define _DIT_BEEP_OFF 6 233228940Sdelphij#define _DIT_SPIN_UP_MODE 7 234228940Sdelphij#define _DIT_IDLE_STANDBY 8 235228940Sdelphij#define _DIT_IDENTIFY 9 236228940Sdelphij 237228940Sdelphij#define SPIN_UP_MODE_NOSUPPORT 0 238228940Sdelphij#define SPIN_UP_MODE_FULL 1 239228940Sdelphij#define SPIN_UP_MODE_STANDBY 2 240228940Sdelphij 241228940Sdelphijstruct tcq_control { 242228940Sdelphij HPT_U8 enable; 243228940Sdelphij HPT_U8 depth; 244228940Sdelphij}; 245228940Sdelphij 246228940Sdelphijstruct ncq_control { 247228940Sdelphij HPT_U8 enable; 248228940Sdelphij HPT_U8 depth; 249228940Sdelphij}; 250228940Sdelphij 251228940Sdelphijtypedef struct _HIM_ALTERABLE_DEV_INFO{ 252228940Sdelphij HPT_U8 type; 253228940Sdelphij union { 254228940Sdelphij HPT_U8 mode; 255228940Sdelphij HPT_U8 enable_read_ahead; 256228940Sdelphij HPT_U8 enable_read_cache; 257228940Sdelphij HPT_U8 enable_write_cache; 258228940Sdelphij struct tcq_control tcq; 259228940Sdelphij struct ncq_control ncq; 260228940Sdelphij void * adapter; 261228940Sdelphij HPT_U8 spin_up_mode; 262228940Sdelphij HPT_U8 idle_standby_timeout; 263228940Sdelphij HPT_U8 identify_indicator; 264228940Sdelphij }u; 265228940Sdelphij} HIM_ALTERABLE_DEV_INFO, *PHIM_ALTERABLE_DEV_INFO; 266228940Sdelphij 267228940Sdelphijstruct _COMMAND; 268228940Sdelphijstruct _IOCTL_ARG; 269228940Sdelphij 270228940Sdelphijtypedef void (*PROBE_CALLBACK)(void *arg, void *dev, int index); 271228940Sdelphij 272228940Sdelphijtypedef struct _HIM { 273228940Sdelphij char *name; 274228940Sdelphij struct _HIM *next; 275228940Sdelphij HPT_UINT max_sg_descriptors; 276228940Sdelphij #define _HIM_INTERFACE(_type, _fn, _args) _type (* _fn) _args; 277228940Sdelphij #include <dev/hpt27xx/himfuncs.h> 278228940Sdelphij} 279228940SdelphijHIM, *PHIM; 280228940Sdelphij 281228940Sdelphij 282228940Sdelphij#pragma pack(1) 283228940Sdelphij#ifdef SG_FLAG_EOT 284228940Sdelphij#error "don't use SG_FLAG_EOT with _SG.eot. clean the code!" 285228940Sdelphij#endif 286228940Sdelphij 287228940Sdelphijtypedef struct _SG { 288228940Sdelphij HPT_U32 size; 289228940Sdelphij HPT_UINT eot; 290228940Sdelphij union { 291228940Sdelphij HPT_U8 FAR * _logical; 292228940Sdelphij BUS_ADDRESS bus; 293228940Sdelphij } 294228940Sdelphij addr; 295228940Sdelphij} 296228940SdelphijSG, *PSG; 297228940Sdelphij#pragma pack() 298228940Sdelphij 299228940Sdelphijtypedef struct _AtaCommand 300228940Sdelphij{ 301228940Sdelphij HPT_U64 Lba; 302228940Sdelphij HPT_U16 nSectors; 303228940Sdelphij HPT_U16 pad; 304228940Sdelphij} AtaComm, *PAtaComm; 305228940Sdelphij 306228940Sdelphij#define ATA_CMD_NOP 0x0 307228940Sdelphij 308228940Sdelphij#define ATA_CMD_SET_FEATURES 0xef 309228940Sdelphij#define ATA_CMD_FLUSH 0xE7 310228940Sdelphij#define ATA_CMD_VERIFY 0x40 311228940Sdelphij#define ATA_CMD_STANDBY 0xe2 312228940Sdelphij#define ATA_CMD_READ_MULTI 0xC4 313228940Sdelphij#define ATA_CMD_READ_MULTI_EXT 0x29 314228940Sdelphij#define ATA_CMD_WRITE_MULTI 0xC5 315228940Sdelphij#define ATA_CMD_WRITE_MULTI_EXT 0x39 316228940Sdelphij#define ATA_CMD_WRITE_MULTI_FUA_EXT 0xCE 317228940Sdelphij 318228940Sdelphij#define ATA_CMD_READ_DMA 0xc8 /* IDE DMA read command */ 319228940Sdelphij#define ATA_CMD_WRITE_DMA 0xca /* IDE DMA write command */ 320228940Sdelphij#define ATA_CMD_READ_DMA_EXT 0x25 321228940Sdelphij#define ATA_CMD_READ_QUEUE_EXT 0x26 322228940Sdelphij#define ATA_CMD_READ_MAX_ADDR 0x27 323228940Sdelphij#define ATA_CMD_READ_EXT 0x24 324228940Sdelphij#define ATA_CMD_VERIFY_EXT 0x42 325228940Sdelphij#define ATA_CMD_WRITE_DMA_EXT 0x35 326228940Sdelphij#define ATA_CMD_WRITE_QUEUE_EXT 0x36 327228940Sdelphij#define ATA_CMD_WRITE_EXT 0x34 328228940Sdelphij 329228940Sdelphij#define ATA_SET_FEATURES_XFER 0x3 330228940Sdelphij#define ATA_SECTOR_SIZE 512 331228940Sdelphij 332228940Sdelphijtypedef struct _PassthroughCmd { 333228940Sdelphij HPT_U16 bFeaturesReg; 334228940Sdelphij HPT_U16 bSectorCountReg; 335228940Sdelphij HPT_U16 bLbaLowReg; 336228940Sdelphij HPT_U16 bLbaMidReg; 337228940Sdelphij HPT_U16 bLbaHighReg; 338228940Sdelphij HPT_U8 bDriveHeadReg; 339228940Sdelphij HPT_U8 bCommandReg; 340228940Sdelphij HPT_U16 nSectors; 341228940Sdelphij HPT_U8 *pDataBuffer; 342228940Sdelphij} 343228940SdelphijPassthroughCmd; 344228940Sdelphij 345228940Sdelphijtypedef struct _ScsiComm { 346228940Sdelphij HPT_U8 cdbLength; 347228940Sdelphij HPT_U8 senseLength; 348228940Sdelphij HPT_U8 scsiStatus; 349228940Sdelphij HPT_U8 reserve1; 350228940Sdelphij HPT_U32 dataLength; 351284879Sdelphij HPT_U8 cdb[16]; 352228940Sdelphij HPT_U8 *senseBuffer; 353228940Sdelphij} 354228940SdelphijScsiComm; 355228940Sdelphij 356284879Sdelphijtypedef struct _ScsiExtComm { 357284879Sdelphij HPT_U8 cdbLength; 358284879Sdelphij HPT_U8 senseLength; 359284879Sdelphij HPT_U8 scsiStatus; 360284879Sdelphij HPT_U8 reserve1; 361284879Sdelphij HPT_U32 dataLength; 362284879Sdelphij HPT_U8 cdb[16]; 363284879Sdelphij HPT_U8 *senseBuffer; 364284879Sdelphij HPT_U8 lun[8]; 365284879Sdelphij} 366284879SdelphijScsiExtComm; 367228940Sdelphij 368284879Sdelphij 369228940Sdelphij#define CTRL_CMD_REBUILD 1 370228940Sdelphij#define CTRL_CMD_VERIFY 2 371228940Sdelphij#define CTRL_CMD_INIT 3 372228940Sdelphij 373228940Sdelphij 374228940Sdelphijtypedef struct _R5ControlCmd { 375228940Sdelphij HPT_U64 StripeLine; 376228940Sdelphij HPT_U16 Offset; 377228940Sdelphij HPT_U8 Command; 378284879Sdelphij HPT_U8 CmdTarget; 379228940Sdelphij} 380228940SdelphijR5ControlCmd, *PR5ControlCmd; 381228940Sdelphij 382228940Sdelphijtypedef struct _HPT_ADDRESS 383228940Sdelphij{ 384228940Sdelphij HPT_U8 * logical; 385228940Sdelphij BUS_ADDRESS bus; 386228940Sdelphij} 387228940SdelphijHPT_ADDRESS; 388228940Sdelphij 389228940Sdelphij 390228940Sdelphijtypedef struct ctl_pages { 391228940Sdelphij HPT_ADDRESS *pages; 392228940Sdelphij HPT_UINT page_size; 393228940Sdelphij HPT_UINT npages; 394228940Sdelphij HPT_UINT min_sg_descriptors; 395228940Sdelphij} CONTROL_PAGES, *PCONTROL_PAGES; 396228940Sdelphij 397228940Sdelphijtypedef struct _R1ControlCmd { 398228940Sdelphij HPT_U64 Lba; 399228940Sdelphij HPT_U16 nSectors; 400284879Sdelphij HPT_U8 Command; 401284879Sdelphij HPT_U8 CmdTarget; 402228940Sdelphij PCONTROL_PAGES ctl_pages; 403228940Sdelphij} 404228940SdelphijR1ControlCmd, *PR1ControlCmd; 405228940Sdelphij 406228940Sdelphijtypedef void (*TQ_PROC)(void *arg); 407228940Sdelphij 408228940Sdelphijstruct tq_item { 409228940Sdelphij TQ_PROC proc; 410228940Sdelphij void *arg; 411228940Sdelphij struct tq_item *next; 412228940Sdelphij}; 413228940Sdelphij 414228940Sdelphij#define INIT_TQ_ITEM(t, p, a) \ 415228940Sdelphij do { (t)->proc = p; (t)->arg = a; (t)->next = 0; } while (0) 416228940Sdelphij 417228940Sdelphijtypedef struct _COMMAND 418228940Sdelphij{ 419228940Sdelphij 420228940Sdelphij struct _VBUS * vbus; 421228940Sdelphij 422228940Sdelphij struct freelist *grplist; 423228940Sdelphij HPT_UINT grpcnt; 424228940Sdelphij 425228940Sdelphij 426228940Sdelphij struct list_head q_link; 427228940Sdelphij struct tq_item done_dpc; 428228940Sdelphij 429228940Sdelphij HPT_UINT extsize; 430228940Sdelphij void *ext; 431228940Sdelphij 432228940Sdelphij 433228940Sdelphij 434228940Sdelphij void *target; 435228940Sdelphij void *priv; 436228940Sdelphij HPT_UPTR priv2; 437228940Sdelphij 438228940Sdelphij int priority; 439228940Sdelphij struct lock_request *owned_lock; 440228940Sdelphij struct lock_request *lock_req; 441228940Sdelphij void (*dtor)(struct _COMMAND *, void *); 442228940Sdelphij void *dtor_arg; 443228940Sdelphij 444228940Sdelphij union{ 445228940Sdelphij AtaComm Ide; 446228940Sdelphij PassthroughCmd Passthrough; 447228940Sdelphij ScsiComm Scsi; 448284879Sdelphij ScsiExtComm ScsiExt; 449228940Sdelphij R5ControlCmd R5Control; 450228940Sdelphij R1ControlCmd R1Control; 451228940Sdelphij } uCmd; 452228940Sdelphij 453228940Sdelphij HPT_U8 type; /* CMD_TYPE_* */ 454228940Sdelphij 455228940Sdelphij struct { 456228940Sdelphij HPT_U8 physical_sg: 1; 457228940Sdelphij HPT_U8 data_in: 1; 458228940Sdelphij HPT_U8 data_out: 1; 459228940Sdelphij HPT_U8 transform : 1; 460228940Sdelphij HPT_U8 hard_flush: 2; 461228940Sdelphij HPT_U8 from_cc: 1; 462228940Sdelphij HPT_U8 force_cc: 1; 463228940Sdelphij } flags; 464228940Sdelphij 465228940Sdelphij /* return status */ 466228940Sdelphij HPT_U8 Result; 467228940Sdelphij /* retry count */ 468228940Sdelphij HPT_U8 RetryCount; 469228940Sdelphij 470228940Sdelphij 471228940Sdelphij PSG psg; 472228940Sdelphij 473228940Sdelphij 474228940Sdelphij int (*buildsgl)(struct _COMMAND *cmd, PSG psg, int logical); 475228940Sdelphij void (*done)(struct _COMMAND *cmd); 476228940Sdelphij} 477228940SdelphijCOMMAND, *PCOMMAND; 478228940Sdelphij 479228940Sdelphij/* command types */ 480228940Sdelphij#define CMD_TYPE_IO 0 481228940Sdelphij#define CMD_TYPE_CONTROL 1 482228940Sdelphij#define CMD_TYPE_ATAPI 2 483228940Sdelphij#define CMD_TYPE_SCSI CMD_TYPE_ATAPI 484228940Sdelphij#define CMD_TYPE_PASSTHROUGH 3 485228940Sdelphij#define CMD_TYPE_FLUSH 4 486284879Sdelphij#define CMD_TYPE_SCSI_EXT 5 487228940Sdelphij#define CMD_TYPE_IO_INDIRECT 0x80 488228940Sdelphij 489228940Sdelphij/* flush command flags */ 490228940Sdelphij#define CF_HARD_FLUSH_CACHE 1 491228940Sdelphij#define CF_HARD_FLUSH_STANDBY 2 492228940Sdelphij 493228940Sdelphij/* command return values */ 494228940Sdelphij#define RETURN_PENDING 0 495228940Sdelphij#define RETURN_SUCCESS 1 496228940Sdelphij#define RETURN_BAD_DEVICE 2 497228940Sdelphij#define RETURN_BAD_PARAMETER 3 498228940Sdelphij#define RETURN_WRITE_NO_DRQ 4 499228940Sdelphij#define RETURN_DEVICE_BUSY 5 500228940Sdelphij#define RETURN_INVALID_REQUEST 6 501228940Sdelphij#define RETURN_SELECTION_TIMEOUT 7 502228940Sdelphij#define RETURN_IDE_ERROR 8 503228940Sdelphij#define RETURN_NEED_LOGICAL_SG 9 504228940Sdelphij#define RETURN_NEED_PHYSICAL_SG 10 505228940Sdelphij#define RETURN_RETRY 11 506228940Sdelphij#define RETURN_DATA_ERROR 12 507228940Sdelphij#define RETURN_BUS_RESET 13 508228940Sdelphij#define RETURN_BAD_TRANSFER_LENGTH 14 509228940Sdelphij#define RETURN_INSUFFICIENT_MEMORY 15 510228940Sdelphij#define RETURN_SECTOR_ERROR 16 511228940Sdelphij#define RETURN_NEED_SPINUP 17 512228940Sdelphij 513228940Sdelphij#if defined(__cplusplus) 514228940Sdelphij} 515228940Sdelphij#endif 516228940Sdelphij#endif 517