rcvbundl.h revision 145368
1/*- 2Copyright (c) 1999-2001, Intel Corporation 3 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright notice, 13 this list of conditions and the following disclaimer in the documentation 14 and/or other materials provided with the distribution. 15 16 3. Neither the name of Intel Corporation nor the names of its contributors 17 may be used to endorse or promote products derived from this software 18 without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 24INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 25LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 29EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30*/ 31/* 32 * $FreeBSD: head/sys/dev/fxp/rcvbundl.h 145368 2005-04-21 19:34:57Z mux $ 33 */ 34/* 35rcvbundl.h 36 37Author: Patrick J Luhmann (PJL) 38Date: 05/30/2000 39Version: 3.28 40 41This file contains the loadable micro code arrays to implement receive bundling on the 42D101 A-step, D101 B-step, D101M (B-step only), D101S, D102 B-step, 43D102 B-step with TCO work around, D102 C-step and D102 E-step. 44 45Each controller has its own specific micro code array. The array for one controller 46is totally incompatible with any other controller, and if used will most likely 47cause the controller to lock up and stop responding to the driver. Each micro 48code array has its own parameter offsets (described below), and they each have 49their own version number (which should not be confused with the version of the 50rcvbundl.h file given above). 51 52*/ 53 54 55 56/************************************************************************* 57* CPUSaver parameters 58* 59* All CPUSaver parameters are 16-bit literals that are part of a 60* "move immediate value" instruction. By changing the value of 61* the literal in the instruction before the code is loaded, the 62* driver can change algorithm. 63* 64* CPUSAVER_DWORD - This is the location of the instruction that loads 65* the dead-man timer with its inital value. By writing a 16-bit 66* value to the low word of this instruction, the driver can change 67* the timer value. The current default is either x600 or x800; 68* experiments show that the value probably should stay within the 69* range of x200 - x1000. 70* 71* CPUSAVER_BUNDLE_MAX_DWORD - This is the location of the instruction 72* that sets the maximum number of frames that will be bundled. In 73* some situations, such as the TCP windowing algorithm, it may be 74* better to limit the growth of the bundle size than let it go as 75* high as it can, because that could cause too much added latency. 76* The default is six, because this is the number of packets in the 77* default TCP window size. A value of 1 would make CPUSaver indicate 78* an interrupt for every frame received. If you do not want to put 79* a limit on the bundle size, set this value to xFFFF. 80* 81* CPUSAVER_MIN_SIZE_DWORD - This is the location of the instruction 82* that contains a bit-mask describing the minimum size frame that 83* will be bundled. The default masks the lower 7 bits, which means 84* that any frame less than 128 bytes in length will not be bundled, 85* but will instead immediately generate an interrupt. This does 86* not affect the current bundle in any way. Any frame that is 128 87* bytes or large will be bundled normally. This feature is meant 88* to provide immediate indication of ACK frames in a TCP environment. 89* Customers were seeing poor performance when a machine with CPUSaver 90* enabled was sending but not receiving. The delay introduced when 91* the ACKs were received was enough to reduce total throughput, because 92* the sender would sit idle until the ACK was finally seen. 93* 94* The current default is 0xFF80, which masks out the lower 7 bits. 95* This means that any frame which is x7F (127) bytes or smaller 96* will cause an immediate interrupt. Because this value must be a 97* bit mask, there are only a few valid values that can be used. To 98* turn this feature off, the driver can write the value xFFFF to the 99* lower word of this instruction (in the same way that the other 100* parameters are used). Likewise, a value of 0xF800 (2047) would 101* cause an interrupt to be generated for every frame, because all 102* standard Ethernet frames are <= 2047 bytes in length. 103*************************************************************************/ 104 105 106 107/********************************************************/ 108/* CPUSaver micro code for the D101A */ 109/********************************************************/ 110 111/* Version 2.0 */ 112 113/* This value is the same for both A and B step of 558. */ 114#define D101_CPUSAVER_DWORD 72 115 116 117#define D101_A_RCVBUNDLE_UCODE \ 118{\ 1190x03B301BB, \ 1200x0046FFFF, \ 1210xFFFFFFFF, \ 1220x051DFFFF, \ 1230xFFFFFFFF, \ 1240xFFFFFFFF, \ 1250x000C0001, \ 1260x00101212, \ 1270x000C0008, \ 1280x003801BC, \ 1290x00000000, \ 1300x00124818, \ 1310x000C1000, \ 1320x00220809, \ 1330x00010200, \ 1340x00124818, \ 1350x000CFFFC, \ 1360x003803B5, \ 1370x00000000, \ 1380x00000000, \ 1390x00000000, \ 1400x00000000, \ 1410x0010009C, \ 1420x0024B81D, \ 1430x00130836, \ 1440x000C0001, \ 1450x0026081C, \ 1460x0020C81B, \ 1470x00130824, \ 1480x00222819, \ 1490x00101213, \ 1500x00041000, \ 1510x003A03B3, \ 1520x00010200, \ 1530x00101B13, \ 1540x00238081, \ 1550x00213049, \ 1560x0038003B, \ 1570x00000000, \ 1580x00000000, \ 1590x00000000, \ 1600x00000000, \ 1610x00000000, \ 1620x00000000, \ 1630x00000000, \ 1640x00000000, \ 1650x00000000, \ 1660x00000000, \ 1670x00000000, \ 1680x00000000, \ 1690x00000000, \ 1700x00000000, \ 1710x00000000, \ 1720x00000000, \ 1730x0010009C, \ 1740x0024B83E, \ 1750x00130826, \ 1760x000C0001, \ 1770x0026083B, \ 1780x00010200, \ 1790x00134824, \ 1800x000C0001, \ 1810x00101213, \ 1820x00041000, \ 1830x0038051E, \ 1840x00101313, \ 1850x00010400, \ 1860x00380521, \ 1870x00050600, \ 1880x00100824, \ 1890x00101310, \ 1900x00041000, \ 1910x00080600, \ 1920x00101B10, \ 1930x0038051E, \ 1940x00000000, \ 1950x00000000, \ 1960x00000000, \ 1970x00000000, \ 1980x00000000, \ 1990x00000000, \ 2000x00000000, \ 2010x00000000, \ 2020x00000000, \ 2030x00000000, \ 2040x00000000, \ 2050x00000000, \ 2060x00000000, \ 2070x00000000, \ 2080x00000000, \ 2090x00000000, \ 2100x00000000, \ 2110x00000000, \ 2120x00000000, \ 2130x00000000, \ 2140x00000000, \ 2150x00000000, \ 2160x00000000, \ 2170x00000000, \ 2180x00000000, \ 2190x00000000, \ 2200x00000000, \ 221} 222 223 224/********************************************************/ 225/* CPUSaver micro code for the D101B */ 226/********************************************************/ 227 228/* Version 2.0 */ 229 230#define D101_B0_RCVBUNDLE_UCODE \ 231{\ 2320x03B401BC, \ 2330x0047FFFF, \ 2340xFFFFFFFF, \ 2350x051EFFFF, \ 2360xFFFFFFFF, \ 2370xFFFFFFFF, \ 2380x000C0001, \ 2390x00101B92, \ 2400x000C0008, \ 2410x003801BD, \ 2420x00000000, \ 2430x00124818, \ 2440x000C1000, \ 2450x00220809, \ 2460x00010200, \ 2470x00124818, \ 2480x000CFFFC, \ 2490x003803B6, \ 2500x00000000, \ 2510x00000000, \ 2520x00000000, \ 2530x00000000, \ 2540x0010009C, \ 2550x0024B81D, \ 2560x0013082F, \ 2570x000C0001, \ 2580x0026081C, \ 2590x0020C81B, \ 2600x00130837, \ 2610x00222819, \ 2620x00101B93, \ 2630x00041000, \ 2640x003A03B4, \ 2650x00010200, \ 2660x00101793, \ 2670x00238082, \ 2680x0021304A, \ 2690x0038003C, \ 2700x00000000, \ 2710x00000000, \ 2720x00000000, \ 2730x00000000, \ 2740x00000000, \ 2750x00000000, \ 2760x00000000, \ 2770x00000000, \ 2780x00000000, \ 2790x00000000, \ 2800x00000000, \ 2810x00000000, \ 2820x00000000, \ 2830x00000000, \ 2840x00000000, \ 2850x00000000, \ 2860x0010009C, \ 2870x0024B83E, \ 2880x00130826, \ 2890x000C0001, \ 2900x0026083B, \ 2910x00010200, \ 2920x00134837, \ 2930x000C0001, \ 2940x00101B93, \ 2950x00041000, \ 2960x0038051F, \ 2970x00101313, \ 2980x00010400, \ 2990x00380522, \ 3000x00050600, \ 3010x00100837, \ 3020x00101310, \ 3030x00041000, \ 3040x00080600, \ 3050x00101790, \ 3060x0038051F, \ 3070x00000000, \ 3080x00000000, \ 3090x00000000, \ 3100x00000000, \ 3110x00000000, \ 3120x00000000, \ 3130x00000000, \ 3140x00000000, \ 3150x00000000, \ 3160x00000000, \ 3170x00000000, \ 3180x00000000, \ 3190x00000000, \ 3200x00000000, \ 3210x00000000, \ 3220x00000000, \ 3230x00000000, \ 3240x00000000, \ 3250x00000000, \ 3260x00000000, \ 3270x00000000, \ 3280x00000000, \ 3290x00000000, \ 3300x00000000, \ 3310x00000000, \ 3320x00000000, \ 3330x00000000, \ 334} 335 336 337/********************************************************/ 338/* CPUSaver micro code for the D101M (B-step only) */ 339/********************************************************/ 340 341/* Version 2.10 */ 342 343/* Parameter values for the D101M B-step */ 344#define D101M_CPUSAVER_DWORD 78 345#define D101M_CPUSAVER_BUNDLE_MAX_DWORD 65 346#define D101M_CPUSAVER_MIN_SIZE_DWORD 126 347 348 349#define D101M_B_RCVBUNDLE_UCODE \ 350{\ 3510x00550215, \ 3520xFFFF0437, \ 3530xFFFFFFFF, \ 3540x06A70789, \ 3550xFFFFFFFF, \ 3560x0558FFFF, \ 3570x000C0001, \ 3580x00101312, \ 3590x000C0008, \ 3600x00380216, \ 3610x0010009C, \ 3620x00204056, \ 3630x002380CC, \ 3640x00380056, \ 3650x0010009C, \ 3660x00244C0B, \ 3670x00000800, \ 3680x00124818, \ 3690x00380438, \ 3700x00000000, \ 3710x00140000, \ 3720x00380555, \ 3730x00308000, \ 3740x00100662, \ 3750x00100561, \ 3760x000E0408, \ 3770x00134861, \ 3780x000C0002, \ 3790x00103093, \ 3800x00308000, \ 3810x00100624, \ 3820x00100561, \ 3830x000E0408, \ 3840x00100861, \ 3850x000C007E, \ 3860x00222C21, \ 3870x000C0002, \ 3880x00103093, \ 3890x00380C7A, \ 3900x00080000, \ 3910x00103090, \ 3920x00380C7A, \ 3930x00000000, \ 3940x00000000, \ 3950x00000000, \ 3960x00000000, \ 3970x0010009C, \ 3980x00244C2D, \ 3990x00010004, \ 4000x00041000, \ 4010x003A0437, \ 4020x00044010, \ 4030x0038078A, \ 4040x00000000, \ 4050x00100099, \ 4060x00206C7A, \ 4070x0010009C, \ 4080x00244C48, \ 4090x00130824, \ 4100x000C0001, \ 4110x00101213, \ 4120x00260C75, \ 4130x00041000, \ 4140x00010004, \ 4150x00130826, \ 4160x000C0006, \ 4170x002206A8, \ 4180x0013C926, \ 4190x00101313, \ 4200x003806A8, \ 4210x00000000, \ 4220x00000000, \ 4230x00000000, \ 4240x00000000, \ 4250x00000000, \ 4260x00000000, \ 4270x00000000, \ 4280x00000000, \ 4290x00080600, \ 4300x00101B10, \ 4310x00050004, \ 4320x00100826, \ 4330x00101210, \ 4340x00380C34, \ 4350x00000000, \ 4360x00000000, \ 4370x0021155B, \ 4380x00100099, \ 4390x00206559, \ 4400x0010009C, \ 4410x00244559, \ 4420x00130836, \ 4430x000C0000, \ 4440x00220C62, \ 4450x000C0001, \ 4460x00101B13, \ 4470x00229C0E, \ 4480x00210C0E, \ 4490x00226C0E, \ 4500x00216C0E, \ 4510x0022FC0E, \ 4520x00215C0E, \ 4530x00214C0E, \ 4540x00380555, \ 4550x00010004, \ 4560x00041000, \ 4570x00278C67, \ 4580x00040800, \ 4590x00018100, \ 4600x003A0437, \ 4610x00130826, \ 4620x000C0001, \ 4630x00220559, \ 4640x00101313, \ 4650x00380559, \ 4660x00000000, \ 4670x00000000, \ 4680x00000000, \ 4690x00000000, \ 4700x00000000, \ 4710x00000000, \ 4720x00000000, \ 4730x00000000, \ 4740x00130831, \ 4750x0010090B, \ 4760x00124813, \ 4770x000CFF80, \ 4780x002606AB, \ 4790x00041000, \ 4800x003806A8, \ 4810x00000000, \ 4820x00000000, \ 4830x00000000, \ 4840x00000000, \ 485} 486 487 488/********************************************************/ 489/* CPUSaver micro code for the D101S */ 490/********************************************************/ 491 492/* Version 1.20 */ 493 494/* Parameter values for the D101S */ 495#define D101S_CPUSAVER_DWORD 78 496#define D101S_CPUSAVER_BUNDLE_MAX_DWORD 67 497#define D101S_CPUSAVER_MIN_SIZE_DWORD 129 498 499 500#define D101S_RCVBUNDLE_UCODE \ 501{\ 5020x00550242, \ 5030xFFFF047E, \ 5040xFFFFFFFF, \ 5050x06FF0818, \ 5060xFFFFFFFF, \ 5070x05A6FFFF, \ 5080x000C0001, \ 5090x00101312, \ 5100x000C0008, \ 5110x00380243, \ 5120x0010009C, \ 5130x00204056, \ 5140x002380D0, \ 5150x00380056, \ 5160x0010009C, \ 5170x00244F8B, \ 5180x00000800, \ 5190x00124818, \ 5200x0038047F, \ 5210x00000000, \ 5220x00140000, \ 5230x003805A3, \ 5240x00308000, \ 5250x00100610, \ 5260x00100561, \ 5270x000E0408, \ 5280x00134861, \ 5290x000C0002, \ 5300x00103093, \ 5310x00308000, \ 5320x00100624, \ 5330x00100561, \ 5340x000E0408, \ 5350x00100861, \ 5360x000C007E, \ 5370x00222FA1, \ 5380x000C0002, \ 5390x00103093, \ 5400x00380F90, \ 5410x00080000, \ 5420x00103090, \ 5430x00380F90, \ 5440x00000000, \ 5450x00000000, \ 5460x00000000, \ 5470x00000000, \ 5480x0010009C, \ 5490x00244FAD, \ 5500x00010004, \ 5510x00041000, \ 5520x003A047E, \ 5530x00044010, \ 5540x00380819, \ 5550x00000000, \ 5560x00100099, \ 5570x00206FFD, \ 5580x0010009A, \ 5590x0020AFFD, \ 5600x0010009C, \ 5610x00244FC8, \ 5620x00130824, \ 5630x000C0001, \ 5640x00101213, \ 5650x00260FF8, \ 5660x00041000, \ 5670x00010004, \ 5680x00130826, \ 5690x000C0006, \ 5700x00220700, \ 5710x0013C926, \ 5720x00101313, \ 5730x00380700, \ 5740x00000000, \ 5750x00000000, \ 5760x00000000, \ 5770x00000000, \ 5780x00000000, \ 5790x00000000, \ 5800x00080600, \ 5810x00101B10, \ 5820x00050004, \ 5830x00100826, \ 5840x00101210, \ 5850x00380FB6, \ 5860x00000000, \ 5870x00000000, \ 5880x002115A9, \ 5890x00100099, \ 5900x002065A7, \ 5910x0010009A, \ 5920x0020A5A7, \ 5930x0010009C, \ 5940x002445A7, \ 5950x00130836, \ 5960x000C0000, \ 5970x00220FE4, \ 5980x000C0001, \ 5990x00101B13, \ 6000x00229F8E, \ 6010x00210F8E, \ 6020x00226F8E, \ 6030x00216F8E, \ 6040x0022FF8E, \ 6050x00215F8E, \ 6060x00214F8E, \ 6070x003805A3, \ 6080x00010004, \ 6090x00041000, \ 6100x00278FE9, \ 6110x00040800, \ 6120x00018100, \ 6130x003A047E, \ 6140x00130826, \ 6150x000C0001, \ 6160x002205A7, \ 6170x00101313, \ 6180x003805A7, \ 6190x00000000, \ 6200x00000000, \ 6210x00000000, \ 6220x00000000, \ 6230x00000000, \ 6240x00000000, \ 6250x00000000, \ 6260x00000000, \ 6270x00000000, \ 6280x00130831, \ 6290x0010090B, \ 6300x00124813, \ 6310x000CFF80, \ 6320x00260703, \ 6330x00041000, \ 6340x00380700, \ 6350x00000000, \ 636} 637 638 639/********************************************************/ 640/* CPUSaver micro code for the D102 B-step */ 641/********************************************************/ 642 643/* Version 2.0 */ 644 645/* 646 This version of CPUSaver is different from all others in 647 a different way. It combines the CPUSaver algorithm with 648 fixes for bugs in the B-step hardware (specifically, bugs 649 with Inline Receive). 650 Thus, when CPUSaver is disabled, this micro code image will 651 still need to be loaded. Before this happens, the hit addresses 652 for the CPUSaver algorithm must be set to 0x1FFFF. The hit 653 addresses for CPUSaver are (starting with 0, and remember that 654 655*/ 656 657/* Parameter values for the D102 B-step */ 658#define D102_B_CPUSAVER_DWORD 91 659#define D102_B_CPUSAVER_BUNDLE_MAX_DWORD 115 660#define D102_B_CPUSAVER_MIN_SIZE_DWORD 70 661 662 663#define D102_B_RCVBUNDLE_UCODE \ 664{\ 6650x006F0276, \ 6660x02BF0E93, \ 6670x1FFF0ED9, \ 6680x0D2508FA, \ 6690x04D21FFF, \ 6700x0EA10892, \ 6710x00300001, \ 6720x0140D871, \ 6730x00300008, \ 6740x00E00277, \ 6750x01406C57, \ 6760x00816073, \ 6770x008700FA, \ 6780x00E00070, \ 6790x00E00E94, \ 6800x00200004, \ 6810x01410000, \ 6820x014B6F6F, \ 6830x0030FFFF, \ 6840x01486F72, \ 6850x00E81F9B, \ 6860x00E00EA3, \ 6870x003C0040, \ 6880x00380920, \ 6890x00C02000, \ 6900x0150ED38, \ 6910x0150EE39, \ 6920x0150EF3A, \ 6930x003C0040, \ 6940x01506F0D, \ 6950x01600E72, \ 6960x00380AE0, \ 6970x00E002C0, \ 6980x00300001, \ 6990x014C0000, \ 7000x008404DC, \ 7010x014C6F72, \ 7020x00E01F9D, \ 7030x01406C51, \ 7040x0080DFC2, \ 7050x01406C52, \ 7060x00815FC2, \ 7070x01406C57, \ 7080x00917FD5, \ 7090x00E01FE6, \ 7100x00000000, \ 7110x01406C57, \ 7120x00919FAD, \ 7130x00038800, \ 7140x00300000, \ 7150x00E81FF2, \ 7160x014D6FC4, \ 7170x00E008FB, \ 7180x00000000, \ 7190x00822D30, \ 7200x01406C51, \ 7210x0080CD26, \ 7220x01406C52, \ 7230x00814D26, \ 7240x01406C57, \ 7250x00916D26, \ 7260x014C6FD7, \ 7270x00300000, \ 7280x00841FDB, \ 7290x00300001, \ 7300x0140D772, \ 7310x00E012B3, \ 7320x014C6F91, \ 7330x0150710B, \ 7340x01496F72, \ 7350x0030FF80, \ 7360x00940EDD, \ 7370x00102000, \ 7380x00E00EDA, \ 7390x01406C57, \ 7400x00917FFD, \ 7410x00001000, \ 7420x00E01FFD, \ 7430x00138800, \ 7440x00300001, \ 7450x00E81FF2, \ 7460x00202500, \ 7470x00E81F9B, \ 7480x01600EC5, \ 7490x00E00893, \ 7500x00000000, \ 7510x01406CD5, \ 7520x0091EEA3, \ 7530x00904EA3, \ 7540x00901F89, \ 7550x00E00EA3, \ 7560x00200600, \ 7570x0140D76F, \ 7580x00138400, \ 7590x01406FD8, \ 7600x0140D96F, \ 7610x00E01FE6, \ 7620x00038400, \ 7630x00102000, \ 7640x00971FE0, \ 7650x00101000, \ 7660x00050200, \ 7670x00E804D2, \ 7680x014C6FD8, \ 7690x00300001, \ 7700x00840D26, \ 7710x0140D872, \ 7720x00E00D26, \ 7730x014C6FD9, \ 7740x00300001, \ 7750x0140D972, \ 7760x00941FBD, \ 7770x00102000, \ 7780x00038400, \ 7790x014C6FD8, \ 7800x00300006, \ 7810x00840EDA, \ 7820x014F71D8, \ 7830x0140D872, \ 7840x00E00EDA, \ 7850x00340020, \ 7860x014C6FED, \ 7870x01603472, \ 7880x016035EE, \ 7890x016036EF, \ 7900x00300004, \ 7910x01611C71, \ 7920x00300014, \ 7930x00200A00, \ 7940x00E810B9, \ 7950x00600000, \ 7960x01496F50, \ 7970x00E004D3, \ 7980x00000000, \ 799} 800 801 802 803 804/********************************************************/ 805/* TCO micro code for the D102 B-step */ 806/********************************************************/ 807 808/* Version 2.0 */ 809 810/* 811 This version is a fix to TCO bug. This version can be loaded instead 812 the CPUSaver version by modifing the registry key "LoadTcoUCodeInsteadOfCpuSaver" 813 814*/ 815 816 817#define D102_B_TCO_UCODE \ 818{\ 8190x1FFF0ED3, \ 8200x02BF0E93, \ 8210x1FFF1FFF, \ 8220x1FFF08FA, \ 8230x1FFF1FFF, \ 8240x0EA10892, \ 8250x00906ED8, \ 8260x01406C55, \ 8270x00E00ED4, \ 8280x00000000, \ 8290x00000000, \ 8300x00000000, \ 8310x00000000, \ 8320x00000000, \ 8330x00E00E94, \ 8340x00200004, \ 8350x01410000, \ 8360x014B6F6F, \ 8370x0030FFFF, \ 8380x01486F72, \ 8390x00E81F9B, \ 8400x00E00EA3, \ 8410x003C0040, \ 8420x00380920, \ 8430x00C02000, \ 8440x0150ED38, \ 8450x0150EE39, \ 8460x0150EF3A, \ 8470x003C0040, \ 8480x01506F0D, \ 8490x01600E72, \ 8500x00380AE0, \ 8510x00E002C0, \ 8520x00300001, \ 8530x014C0000, \ 8540x008404DC, \ 8550x014C6F72, \ 8560x00E01F9D, \ 8570x00000000, \ 8580x00000000, \ 8590x00000000, \ 8600x00000000, \ 8610x00000000, \ 8620x00000000, \ 8630x00000000, \ 8640x00000000, \ 8650x01406C57, \ 8660x00919FAD, \ 8670x00038800, \ 8680x00300000, \ 8690x00E81FD5, \ 8700x014D6FC4, \ 8710x00E008FB, \ 8720x00000000, \ 8730x00000000, \ 8740x00000000, \ 8750x00000000, \ 8760x00000000, \ 8770x00000000, \ 8780x00000000, \ 8790x00000000, \ 8800x00000000, \ 8810x00000000, \ 8820x00000000, \ 8830x00000000, \ 8840x00000000, \ 8850x00000000, \ 8860x00000000, \ 8870x00000000, \ 8880x00000000, \ 8890x00000000, \ 8900x00000000, \ 8910x00000000, \ 8920x00000000, \ 8930x00000000, \ 8940x00000000, \ 8950x00000000, \ 8960x00000000, \ 8970x00138800, \ 8980x00300001, \ 8990x00E81FD5, \ 9000x00202500, \ 9010x00E81F9B, \ 9020x01600EC5, \ 9030x00E00893, \ 9040x00000000, \ 9050x01406CD5, \ 9060x0091EEA3, \ 9070x00904EA3, \ 9080x00901F89, \ 9090x00E00EA3, \ 9100x00340020, \ 9110x014C6FED, \ 9120x01603472, \ 9130x016035EE, \ 9140x016036EF, \ 9150x00300004, \ 9160x01611C71, \ 9170x00300014, \ 9180x00200A00, \ 9190x00E810B9, \ 9200x00600000, \ 9210x00000000, \ 9220x00000000, \ 9230x00000000, \ 9240x00000000, \ 9250x00000000, \ 9260x00000000, \ 9270x00000000, \ 9280x00000000, \ 9290x00000000, \ 9300x00000000, \ 9310x00000000, \ 9320x00000000, \ 9330x00000000, \ 9340x00000000, \ 9350x00000000, \ 9360x00000000, \ 9370x00000000, \ 9380x00000000, \ 9390x00000000, \ 9400x00000000, \ 9410x00000000, \ 9420x00000000, \ 9430x00000000, \ 9440x00000000, \ 9450x00000000, \ 9460x00000000, \ 9470x00000000, \ 9480x00000000, \ 9490x00000000, \ 9500x00000000, \ 9510x00000000, \ 9520x00000000, \ 953} 954 955 956 957/********************************************************/ 958/* Micro code for the D102 C-step */ 959/********************************************************/ 960 961/* Parameter values for the D102 C-step */ 962#define D102_C_CPUSAVER_DWORD 46 963#define D102_C_CPUSAVER_BUNDLE_MAX_DWORD 54 964#define D102_C_CPUSAVER_MIN_SIZE_DWORD 133 /* not implemented */ 965 966 967 968 969 970#if 0 971// this uCode include the CPU Saver and the TCO work around 972//for IP fregments. 973#endif 974#define D102_C_RCVBUNDLE_UCODE \ 975{ \ 9760x00700279, \ 9770x0E6104E2, \ 9780x02BF0CAE, \ 9790x1519150C, \ 9800x1FFF0E5B, \ 9810x1FFF1FFF, \ 9820x00E014D8, \ 9830x00000000, \ 9840x00000000, \ 9850x00000000, \ 9860x00E014DC, \ 9870x00000000, \ 9880x00000000, \ 9890x00000000, \ 9900x00E014F4, \ 9910x00000000, \ 9920x00000000, \ 9930x00000000, \ 9940x00000000, \ 9950x00000000, \ 9960x00000000, \ 9970x00000000, \ 9980x00E014E0, \ 9990x00000000, \ 10000x00000000, \ 10010x00000000, \ 10020x00000000, \ 10030x00000000, \ 10040x00000000, \ 10050x00000000, \ 10060x00000000, \ 10070x00000000, \ 10080x00000000, \ 10090x00000000, \ 10100x00000000, \ 10110x00000000, \ 10120x00000000, \ 10130x00000000, \ 10140x00E014E7, \ 10150x00000000, \ 10160x00000000, \ 10170x00000000, \ 10180x00141000, \ 10190x015D6F0D, \ 10200x00E002C0, \ 10210x00000000, \ 10220x00200600, \ 10230x00E0150D, \ 10240x00000000, \ 10250x00000000, \ 10260x00000000, \ 10270x00000000, \ 10280x00000000, \ 10290x00000000, \ 10300x00300006, \ 10310x00E0151A, \ 10320x00000000, \ 10330x00000000, \ 10340x00000000, \ 10350x00000000, \ 10360x00000000, \ 10370x00000000, \ 10380x00000000, \ 10390x00000000, \ 10400x00000000, \ 10410x00000000, \ 10420x00000000, \ 10430x00000000, \ 10440x00000000, \ 10450x00000000, \ 10460x00906E65, \ 10470x00800E60, \ 10480x00E00E5D, \ 10490x00000000, \ 10500x00000000, \ 10510x00000000, \ 10520x00000000, \ 10530x00000000, \ 10540x00000000, \ 10550x00000000, \ 10560x00000000, \ 10570x00000000, \ 10580x00000000, \ 10590x00000000, \ 10600x00000000, \ 10610x00000000, \ 10620x00000000, \ 10630x00000000, \ 10640x00000000, \ 10650x00000000, \ 10660x00000000, \ 10670x00000000, \ 10680x00000000, \ 10690x00000000, \ 10700x00000000, \ 10710x00000000, \ 10720x00000000, \ 10730x00000000, \ 10740x00000000, \ 10750x00000000, \ 10760x00000000, \ 10770x00000000, \ 10780x00000000, \ 10790x00000000, \ 10800x00000000, \ 10810x00000000, \ 10820x00000000, \ 10830x00000000, \ 10840x00000000, \ 10850x00000000, \ 10860x00000000, \ 10870x00000000, \ 10880x00000000, \ 10890x00000000, \ 10900x00000000, \ 10910x00000000, \ 10920x00000000, \ 10930x00000000, \ 10940x00000000, \ 10950x00000000, \ 10960x00000000, \ 10970x00000000, \ 10980x00000000, \ 10990x00000000, \ 11000x00000000, \ 11010x00000000, \ 11020x00000000, \ 11030x00000000, \ 11040x00000000, \ 11050x00000000, \ 11060x00000000, \ 11070x00000000, \ 11080x00000000, \ 11090x00000000, \ 1110} 1111 1112/********************************************************/ 1113/* Micro code for the D102 E-step */ 1114/********************************************************/ 1115 1116/* Parameter values for the D102 E-step */ 1117#define D102_E_CPUSAVER_DWORD 42 1118#define D102_E_CPUSAVER_BUNDLE_MAX_DWORD 54 1119#define D102_E_CPUSAVER_MIN_SIZE_DWORD 46 1120 1121#define D102_E_RCVBUNDLE_UCODE \ 1122{\ 11230x007D028F, \ 11240x0E4204F9, \ 11250x14ED0C85, \ 11260x14FA14E9, \ 11270x0EF70E36, \ 11280x1FFF1FFF, \ 11290x00E014B9, \ 11300x00000000, \ 11310x00000000, \ 11320x00000000, \ 11330x00E014BD, \ 11340x00000000, \ 11350x00000000, \ 11360x00000000, \ 11370x00E014D5, \ 11380x00000000, \ 11390x00000000, \ 11400x00000000, \ 11410x00000000, \ 11420x00000000, \ 11430x00000000, \ 11440x00000000, \ 11450x00E014C1, \ 11460x00000000, \ 11470x00000000, \ 11480x00000000, \ 11490x00000000, \ 11500x00000000, \ 11510x00000000, \ 11520x00000000, \ 11530x00000000, \ 11540x00000000, \ 11550x00000000, \ 11560x00000000, \ 11570x00000000, \ 11580x00000000, \ 11590x00000000, \ 11600x00000000, \ 11610x00E014C8, \ 11620x00000000, \ 11630x00000000, \ 11640x00000000, \ 11650x00200600, \ 11660x00E014EE, \ 11670x00000000, \ 11680x00000000, \ 11690x0030FF80, \ 11700x00940E46, \ 11710x00038200, \ 11720x00102000, \ 11730x00E00E43, \ 11740x00000000, \ 11750x00000000, \ 11760x00000000, \ 11770x00300006, \ 11780x00E014FB, \ 11790x00000000, \ 11800x00000000, \ 11810x00000000, \ 11820x00000000, \ 11830x00000000, \ 11840x00000000, \ 11850x00000000, \ 11860x00000000, \ 11870x00000000, \ 11880x00000000, \ 11890x00000000, \ 11900x00000000, \ 11910x00000000, \ 11920x00000000, \ 11930x00906E41, \ 11940x00800E3C, \ 11950x00E00E39, \ 11960x00000000, \ 11970x00906EFD, \ 11980x00900EFD, \ 11990x00E00EF8, \ 12000x00000000, \ 12010x00000000, \ 12020x00000000, \ 12030x00000000, \ 12040x00000000, \ 12050x00000000, \ 12060x00000000, \ 12070x00000000, \ 12080x00000000, \ 12090x00000000, \ 12100x00000000, \ 12110x00000000, \ 12120x00000000, \ 12130x00000000, \ 12140x00000000, \ 12150x00000000, \ 12160x00000000, \ 12170x00000000, \ 12180x00000000, \ 12190x00000000, \ 12200x00000000, \ 12210x00000000, \ 12220x00000000, \ 12230x00000000, \ 12240x00000000, \ 12250x00000000, \ 12260x00000000, \ 12270x00000000, \ 12280x00000000, \ 12290x00000000, \ 12300x00000000, \ 12310x00000000, \ 12320x00000000, \ 12330x00000000, \ 12340x00000000, \ 12350x00000000, \ 12360x00000000, \ 12370x00000000, \ 12380x00000000, \ 12390x00000000, \ 12400x00000000, \ 12410x00000000, \ 12420x00000000, \ 12430x00000000, \ 12440x00000000, \ 12450x00000000, \ 12460x00000000, \ 12470x00000000, \ 12480x00000000, \ 12490x00000000, \ 12500x00000000, \ 12510x00000000, \ 12520x00000000, \ 12530x00000000, \ 12540x00000000, \ 12550x00000000, \ 12560x00000000, \ 1257} 1258