rcvbundl.h revision 139749
1/*- 2Copyright (c) 1999-2001, Intel Corporation 3 4All rights reserved. 5 6Redistribution and use in source and binary forms, with or without 7modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright notice, 13 this list of conditions and the following disclaimer in the documentation 14 and/or other materials provided with the distribution. 15 16 3. Neither the name of Intel Corporation nor the names of its contributors 17 may be used to endorse or promote products derived from this software 18 without specific prior written permission. 19 20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 24INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 25LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 26PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 27LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 28NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 29EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30*/ 31/* 32 * $FreeBSD: head/sys/dev/fxp/rcvbundl.h 139749 2005-01-06 01:43:34Z imp $ 33 */ 34/* 35rcvbundl.h 36 37Author: Patrick J Luhmann (PJL) 38Date: 05/30/2000 39Version: 3.28 40 41This file contains the loadable micro code arrays to implement receive bundling on the 42D101 A-step, D101 B-step, D101M (B-step only), D101S, D102 B-step, 43D102 B-step with TCO work around and D012 C-step. 44 45Each controller has its own specific micro code array. The array for one controller 46is totally incompatible with any other controller, and if used will most likely 47cause the controller to lock up and stop responding to the driver. Each micro 48code array has its own parameter offsets (described below), and they each have 49their own version number (which should not be confused with the version of the 50rcvbundl.h file given above). 51 52*/ 53 54/* Size of loadable micro code image for each supported chip. */ 55#ifndef D100_NUM_MICROCODE_DWORDS 56#define D100_NUM_MICROCODE_DWORDS 66 57#endif 58#ifndef D101_NUM_MICROCODE_DWORDS 59#define D101_NUM_MICROCODE_DWORDS 102 60#endif 61#ifndef D101M_NUM_MICROCODE_DWORDS 62#define D101M_NUM_MICROCODE_DWORDS 134 63#endif 64#ifndef D101S_NUM_MICROCODE_DWORDS 65#define D101S_NUM_MICROCODE_DWORDS 134 66#endif 67#ifndef D102_NUM_MICROCODE_DWORDS 68#define D102_NUM_MICROCODE_DWORDS 134 69#endif 70#ifndef D102_NUM_TCO_MICROCODE_DWORDS 71#define D102_NUM_TCO_MICROCODE_DWORDS 134 72#endif 73 74 75/************************************************************************* 76* CPUSaver parameters 77* 78* All CPUSaver parameters are 16-bit literals that are part of a 79* "move immediate value" instruction. By changing the value of 80* the literal in the instruction before the code is loaded, the 81* driver can change algorithm. 82* 83* CPUSAVER_DWORD - This is the location of the instruction that loads 84* the dead-man timer with its inital value. By writing a 16-bit 85* value to the low word of this instruction, the driver can change 86* the timer value. The current default is either x600 or x800; 87* experiments show that the value probably should stay within the 88* range of x200 - x1000. 89* 90* CPUSAVER_BUNDLE_MAX_DWORD - This is the location of the instruction 91* that sets the maximum number of frames that will be bundled. In 92* some situations, such as the TCP windowing algorithm, it may be 93* better to limit the growth of the bundle size than let it go as 94* high as it can, because that could cause too much added latency. 95* The default is six, because this is the number of packets in the 96* default TCP window size. A value of 1 would make CPUSaver indicate 97* an interrupt for every frame received. If you do not want to put 98* a limit on the bundle size, set this value to xFFFF. 99* 100* CPUSAVER_MIN_SIZE_DWORD - This is the location of the instruction 101* that contains a bit-mask describing the minimum size frame that 102* will be bundled. The default masks the lower 7 bits, which means 103* that any frame less than 128 bytes in length will not be bundled, 104* but will instead immediately generate an interrupt. This does 105* not affect the current bundle in any way. Any frame that is 128 106* bytes or large will be bundled normally. This feature is meant 107* to provide immediate indication of ACK frames in a TCP environment. 108* Customers were seeing poor performance when a machine with CPUSaver 109* enabled was sending but not receiving. The delay introduced when 110* the ACKs were received was enough to reduce total throughput, because 111* the sender would sit idle until the ACK was finally seen. 112* 113* The current default is 0xFF80, which masks out the lower 7 bits. 114* This means that any frame which is x7F (127) bytes or smaller 115* will cause an immediate interrupt. Because this value must be a 116* bit mask, there are only a few valid values that can be used. To 117* turn this feature off, the driver can write the value xFFFF to the 118* lower word of this instruction (in the same way that the other 119* parameters are used). Likewise, a value of 0xF800 (2047) would 120* cause an interrupt to be generated for every frame, because all 121* standard Ethernet frames are <= 2047 bytes in length. 122*************************************************************************/ 123 124 125 126/********************************************************/ 127/* CPUSaver micro code for the D101A */ 128/********************************************************/ 129 130/* Version 2.0 */ 131 132/* This value is the same for both A and B step of 558. */ 133#define D101_CPUSAVER_DWORD 72 134 135 136#define D101_A_RCVBUNDLE_UCODE \ 137{\ 1380x03B301BB, \ 1390x0046FFFF, \ 1400xFFFFFFFF, \ 1410x051DFFFF, \ 1420xFFFFFFFF, \ 1430xFFFFFFFF, \ 1440x000C0001, \ 1450x00101212, \ 1460x000C0008, \ 1470x003801BC, \ 1480x00000000, \ 1490x00124818, \ 1500x000C1000, \ 1510x00220809, \ 1520x00010200, \ 1530x00124818, \ 1540x000CFFFC, \ 1550x003803B5, \ 1560x00000000, \ 1570x00000000, \ 1580x00000000, \ 1590x00000000, \ 1600x0010009C, \ 1610x0024B81D, \ 1620x00130836, \ 1630x000C0001, \ 1640x0026081C, \ 1650x0020C81B, \ 1660x00130824, \ 1670x00222819, \ 1680x00101213, \ 1690x00041000, \ 1700x003A03B3, \ 1710x00010200, \ 1720x00101B13, \ 1730x00238081, \ 1740x00213049, \ 1750x0038003B, \ 1760x00000000, \ 1770x00000000, \ 1780x00000000, \ 1790x00000000, \ 1800x00000000, \ 1810x00000000, \ 1820x00000000, \ 1830x00000000, \ 1840x00000000, \ 1850x00000000, \ 1860x00000000, \ 1870x00000000, \ 1880x00000000, \ 1890x00000000, \ 1900x00000000, \ 1910x00000000, \ 1920x0010009C, \ 1930x0024B83E, \ 1940x00130826, \ 1950x000C0001, \ 1960x0026083B, \ 1970x00010200, \ 1980x00134824, \ 1990x000C0001, \ 2000x00101213, \ 2010x00041000, \ 2020x0038051E, \ 2030x00101313, \ 2040x00010400, \ 2050x00380521, \ 2060x00050600, \ 2070x00100824, \ 2080x00101310, \ 2090x00041000, \ 2100x00080600, \ 2110x00101B10, \ 2120x0038051E, \ 2130x00000000, \ 2140x00000000, \ 2150x00000000, \ 2160x00000000, \ 2170x00000000, \ 2180x00000000, \ 2190x00000000, \ 2200x00000000, \ 2210x00000000, \ 2220x00000000, \ 2230x00000000, \ 2240x00000000, \ 2250x00000000, \ 2260x00000000, \ 2270x00000000, \ 2280x00000000, \ 2290x00000000, \ 2300x00000000, \ 2310x00000000, \ 2320x00000000, \ 2330x00000000, \ 2340x00000000, \ 2350x00000000, \ 2360x00000000, \ 2370x00000000, \ 2380x00000000, \ 2390x00000000, \ 240} 241 242 243/********************************************************/ 244/* CPUSaver micro code for the D101B */ 245/********************************************************/ 246 247/* Version 2.0 */ 248 249#define D101_B0_RCVBUNDLE_UCODE \ 250{\ 2510x03B401BC, \ 2520x0047FFFF, \ 2530xFFFFFFFF, \ 2540x051EFFFF, \ 2550xFFFFFFFF, \ 2560xFFFFFFFF, \ 2570x000C0001, \ 2580x00101B92, \ 2590x000C0008, \ 2600x003801BD, \ 2610x00000000, \ 2620x00124818, \ 2630x000C1000, \ 2640x00220809, \ 2650x00010200, \ 2660x00124818, \ 2670x000CFFFC, \ 2680x003803B6, \ 2690x00000000, \ 2700x00000000, \ 2710x00000000, \ 2720x00000000, \ 2730x0010009C, \ 2740x0024B81D, \ 2750x0013082F, \ 2760x000C0001, \ 2770x0026081C, \ 2780x0020C81B, \ 2790x00130837, \ 2800x00222819, \ 2810x00101B93, \ 2820x00041000, \ 2830x003A03B4, \ 2840x00010200, \ 2850x00101793, \ 2860x00238082, \ 2870x0021304A, \ 2880x0038003C, \ 2890x00000000, \ 2900x00000000, \ 2910x00000000, \ 2920x00000000, \ 2930x00000000, \ 2940x00000000, \ 2950x00000000, \ 2960x00000000, \ 2970x00000000, \ 2980x00000000, \ 2990x00000000, \ 3000x00000000, \ 3010x00000000, \ 3020x00000000, \ 3030x00000000, \ 3040x00000000, \ 3050x0010009C, \ 3060x0024B83E, \ 3070x00130826, \ 3080x000C0001, \ 3090x0026083B, \ 3100x00010200, \ 3110x00134837, \ 3120x000C0001, \ 3130x00101B93, \ 3140x00041000, \ 3150x0038051F, \ 3160x00101313, \ 3170x00010400, \ 3180x00380522, \ 3190x00050600, \ 3200x00100837, \ 3210x00101310, \ 3220x00041000, \ 3230x00080600, \ 3240x00101790, \ 3250x0038051F, \ 3260x00000000, \ 3270x00000000, \ 3280x00000000, \ 3290x00000000, \ 3300x00000000, \ 3310x00000000, \ 3320x00000000, \ 3330x00000000, \ 3340x00000000, \ 3350x00000000, \ 3360x00000000, \ 3370x00000000, \ 3380x00000000, \ 3390x00000000, \ 3400x00000000, \ 3410x00000000, \ 3420x00000000, \ 3430x00000000, \ 3440x00000000, \ 3450x00000000, \ 3460x00000000, \ 3470x00000000, \ 3480x00000000, \ 3490x00000000, \ 3500x00000000, \ 3510x00000000, \ 3520x00000000, \ 353} 354 355 356/********************************************************/ 357/* CPUSaver micro code for the D101M (B-step only) */ 358/********************************************************/ 359 360/* Version 2.10 */ 361 362/* Parameter values for the D101M B-step */ 363#define D101M_CPUSAVER_DWORD 78 364#define D101M_CPUSAVER_BUNDLE_MAX_DWORD 65 365#define D101M_CPUSAVER_MIN_SIZE_DWORD 126 366 367 368#define D101M_B_RCVBUNDLE_UCODE \ 369{\ 3700x00550215, \ 3710xFFFF0437, \ 3720xFFFFFFFF, \ 3730x06A70789, \ 3740xFFFFFFFF, \ 3750x0558FFFF, \ 3760x000C0001, \ 3770x00101312, \ 3780x000C0008, \ 3790x00380216, \ 3800x0010009C, \ 3810x00204056, \ 3820x002380CC, \ 3830x00380056, \ 3840x0010009C, \ 3850x00244C0B, \ 3860x00000800, \ 3870x00124818, \ 3880x00380438, \ 3890x00000000, \ 3900x00140000, \ 3910x00380555, \ 3920x00308000, \ 3930x00100662, \ 3940x00100561, \ 3950x000E0408, \ 3960x00134861, \ 3970x000C0002, \ 3980x00103093, \ 3990x00308000, \ 4000x00100624, \ 4010x00100561, \ 4020x000E0408, \ 4030x00100861, \ 4040x000C007E, \ 4050x00222C21, \ 4060x000C0002, \ 4070x00103093, \ 4080x00380C7A, \ 4090x00080000, \ 4100x00103090, \ 4110x00380C7A, \ 4120x00000000, \ 4130x00000000, \ 4140x00000000, \ 4150x00000000, \ 4160x0010009C, \ 4170x00244C2D, \ 4180x00010004, \ 4190x00041000, \ 4200x003A0437, \ 4210x00044010, \ 4220x0038078A, \ 4230x00000000, \ 4240x00100099, \ 4250x00206C7A, \ 4260x0010009C, \ 4270x00244C48, \ 4280x00130824, \ 4290x000C0001, \ 4300x00101213, \ 4310x00260C75, \ 4320x00041000, \ 4330x00010004, \ 4340x00130826, \ 4350x000C0006, \ 4360x002206A8, \ 4370x0013C926, \ 4380x00101313, \ 4390x003806A8, \ 4400x00000000, \ 4410x00000000, \ 4420x00000000, \ 4430x00000000, \ 4440x00000000, \ 4450x00000000, \ 4460x00000000, \ 4470x00000000, \ 4480x00080600, \ 4490x00101B10, \ 4500x00050004, \ 4510x00100826, \ 4520x00101210, \ 4530x00380C34, \ 4540x00000000, \ 4550x00000000, \ 4560x0021155B, \ 4570x00100099, \ 4580x00206559, \ 4590x0010009C, \ 4600x00244559, \ 4610x00130836, \ 4620x000C0000, \ 4630x00220C62, \ 4640x000C0001, \ 4650x00101B13, \ 4660x00229C0E, \ 4670x00210C0E, \ 4680x00226C0E, \ 4690x00216C0E, \ 4700x0022FC0E, \ 4710x00215C0E, \ 4720x00214C0E, \ 4730x00380555, \ 4740x00010004, \ 4750x00041000, \ 4760x00278C67, \ 4770x00040800, \ 4780x00018100, \ 4790x003A0437, \ 4800x00130826, \ 4810x000C0001, \ 4820x00220559, \ 4830x00101313, \ 4840x00380559, \ 4850x00000000, \ 4860x00000000, \ 4870x00000000, \ 4880x00000000, \ 4890x00000000, \ 4900x00000000, \ 4910x00000000, \ 4920x00000000, \ 4930x00130831, \ 4940x0010090B, \ 4950x00124813, \ 4960x000CFF80, \ 4970x002606AB, \ 4980x00041000, \ 4990x003806A8, \ 5000x00000000, \ 5010x00000000, \ 5020x00000000, \ 5030x00000000, \ 504} 505 506 507/********************************************************/ 508/* CPUSaver micro code for the D101S */ 509/********************************************************/ 510 511/* Version 1.20 */ 512 513/* Parameter values for the D101S */ 514#define D101S_CPUSAVER_DWORD 78 515#define D101S_CPUSAVER_BUNDLE_MAX_DWORD 67 516#define D101S_CPUSAVER_MIN_SIZE_DWORD 129 517 518 519#define D101S_RCVBUNDLE_UCODE \ 520{\ 5210x00550242, \ 5220xFFFF047E, \ 5230xFFFFFFFF, \ 5240x06FF0818, \ 5250xFFFFFFFF, \ 5260x05A6FFFF, \ 5270x000C0001, \ 5280x00101312, \ 5290x000C0008, \ 5300x00380243, \ 5310x0010009C, \ 5320x00204056, \ 5330x002380D0, \ 5340x00380056, \ 5350x0010009C, \ 5360x00244F8B, \ 5370x00000800, \ 5380x00124818, \ 5390x0038047F, \ 5400x00000000, \ 5410x00140000, \ 5420x003805A3, \ 5430x00308000, \ 5440x00100610, \ 5450x00100561, \ 5460x000E0408, \ 5470x00134861, \ 5480x000C0002, \ 5490x00103093, \ 5500x00308000, \ 5510x00100624, \ 5520x00100561, \ 5530x000E0408, \ 5540x00100861, \ 5550x000C007E, \ 5560x00222FA1, \ 5570x000C0002, \ 5580x00103093, \ 5590x00380F90, \ 5600x00080000, \ 5610x00103090, \ 5620x00380F90, \ 5630x00000000, \ 5640x00000000, \ 5650x00000000, \ 5660x00000000, \ 5670x0010009C, \ 5680x00244FAD, \ 5690x00010004, \ 5700x00041000, \ 5710x003A047E, \ 5720x00044010, \ 5730x00380819, \ 5740x00000000, \ 5750x00100099, \ 5760x00206FFD, \ 5770x0010009A, \ 5780x0020AFFD, \ 5790x0010009C, \ 5800x00244FC8, \ 5810x00130824, \ 5820x000C0001, \ 5830x00101213, \ 5840x00260FF8, \ 5850x00041000, \ 5860x00010004, \ 5870x00130826, \ 5880x000C0006, \ 5890x00220700, \ 5900x0013C926, \ 5910x00101313, \ 5920x00380700, \ 5930x00000000, \ 5940x00000000, \ 5950x00000000, \ 5960x00000000, \ 5970x00000000, \ 5980x00000000, \ 5990x00080600, \ 6000x00101B10, \ 6010x00050004, \ 6020x00100826, \ 6030x00101210, \ 6040x00380FB6, \ 6050x00000000, \ 6060x00000000, \ 6070x002115A9, \ 6080x00100099, \ 6090x002065A7, \ 6100x0010009A, \ 6110x0020A5A7, \ 6120x0010009C, \ 6130x002445A7, \ 6140x00130836, \ 6150x000C0000, \ 6160x00220FE4, \ 6170x000C0001, \ 6180x00101B13, \ 6190x00229F8E, \ 6200x00210F8E, \ 6210x00226F8E, \ 6220x00216F8E, \ 6230x0022FF8E, \ 6240x00215F8E, \ 6250x00214F8E, \ 6260x003805A3, \ 6270x00010004, \ 6280x00041000, \ 6290x00278FE9, \ 6300x00040800, \ 6310x00018100, \ 6320x003A047E, \ 6330x00130826, \ 6340x000C0001, \ 6350x002205A7, \ 6360x00101313, \ 6370x003805A7, \ 6380x00000000, \ 6390x00000000, \ 6400x00000000, \ 6410x00000000, \ 6420x00000000, \ 6430x00000000, \ 6440x00000000, \ 6450x00000000, \ 6460x00000000, \ 6470x00130831, \ 6480x0010090B, \ 6490x00124813, \ 6500x000CFF80, \ 6510x00260703, \ 6520x00041000, \ 6530x00380700, \ 6540x00000000, \ 655} 656 657 658/********************************************************/ 659/* CPUSaver micro code for the D102 B-step */ 660/********************************************************/ 661 662/* Version 2.0 */ 663 664/* 665 This version of CPUSaver is different from all others in 666 a different way. It combines the CPUSaver algorithm with 667 fixes for bugs in the B-step hardware (specifically, bugs 668 with Inline Receive). 669 Thus, when CPUSaver is disabled, this micro code image will 670 still need to be loaded. Before this happens, the hit addresses 671 for the CPUSaver algorithm must be set to 0x1FFFF. The hit 672 addresses for CPUSaver are (starting with 0, and remember that 673 674*/ 675 676/* Parameter values for the D102 B-step */ 677#define D102_B_CPUSAVER_DWORD 91 678#define D102_B_CPUSAVER_BUNDLE_MAX_DWORD 115 679#define D102_B_CPUSAVER_MIN_SIZE_DWORD 70 680 681 682#define D102_B_RCVBUNDLE_UCODE \ 683{\ 6840x006F0276, \ 6850x02BF0E93, \ 6860x1FFF0ED9, \ 6870x0D2508FA, \ 6880x04D21FFF, \ 6890x0EA10892, \ 6900x00300001, \ 6910x0140D871, \ 6920x00300008, \ 6930x00E00277, \ 6940x01406C57, \ 6950x00816073, \ 6960x008700FA, \ 6970x00E00070, \ 6980x00E00E94, \ 6990x00200004, \ 7000x01410000, \ 7010x014B6F6F, \ 7020x0030FFFF, \ 7030x01486F72, \ 7040x00E81F9B, \ 7050x00E00EA3, \ 7060x003C0040, \ 7070x00380920, \ 7080x00C02000, \ 7090x0150ED38, \ 7100x0150EE39, \ 7110x0150EF3A, \ 7120x003C0040, \ 7130x01506F0D, \ 7140x01600E72, \ 7150x00380AE0, \ 7160x00E002C0, \ 7170x00300001, \ 7180x014C0000, \ 7190x008404DC, \ 7200x014C6F72, \ 7210x00E01F9D, \ 7220x01406C51, \ 7230x0080DFC2, \ 7240x01406C52, \ 7250x00815FC2, \ 7260x01406C57, \ 7270x00917FD5, \ 7280x00E01FE6, \ 7290x00000000, \ 7300x01406C57, \ 7310x00919FAD, \ 7320x00038800, \ 7330x00300000, \ 7340x00E81FF2, \ 7350x014D6FC4, \ 7360x00E008FB, \ 7370x00000000, \ 7380x00822D30, \ 7390x01406C51, \ 7400x0080CD26, \ 7410x01406C52, \ 7420x00814D26, \ 7430x01406C57, \ 7440x00916D26, \ 7450x014C6FD7, \ 7460x00300000, \ 7470x00841FDB, \ 7480x00300001, \ 7490x0140D772, \ 7500x00E012B3, \ 7510x014C6F91, \ 7520x0150710B, \ 7530x01496F72, \ 7540x0030FF80, \ 7550x00940EDD, \ 7560x00102000, \ 7570x00E00EDA, \ 7580x01406C57, \ 7590x00917FFD, \ 7600x00001000, \ 7610x00E01FFD, \ 7620x00138800, \ 7630x00300001, \ 7640x00E81FF2, \ 7650x00202500, \ 7660x00E81F9B, \ 7670x01600EC5, \ 7680x00E00893, \ 7690x00000000, \ 7700x01406CD5, \ 7710x0091EEA3, \ 7720x00904EA3, \ 7730x00901F89, \ 7740x00E00EA3, \ 7750x00200600, \ 7760x0140D76F, \ 7770x00138400, \ 7780x01406FD8, \ 7790x0140D96F, \ 7800x00E01FE6, \ 7810x00038400, \ 7820x00102000, \ 7830x00971FE0, \ 7840x00101000, \ 7850x00050200, \ 7860x00E804D2, \ 7870x014C6FD8, \ 7880x00300001, \ 7890x00840D26, \ 7900x0140D872, \ 7910x00E00D26, \ 7920x014C6FD9, \ 7930x00300001, \ 7940x0140D972, \ 7950x00941FBD, \ 7960x00102000, \ 7970x00038400, \ 7980x014C6FD8, \ 7990x00300006, \ 8000x00840EDA, \ 8010x014F71D8, \ 8020x0140D872, \ 8030x00E00EDA, \ 8040x00340020, \ 8050x014C6FED, \ 8060x01603472, \ 8070x016035EE, \ 8080x016036EF, \ 8090x00300004, \ 8100x01611C71, \ 8110x00300014, \ 8120x00200A00, \ 8130x00E810B9, \ 8140x00600000, \ 8150x01496F50, \ 8160x00E004D3, \ 8170x00000000, \ 818} 819 820 821 822 823/********************************************************/ 824/* TCO micro code for the D102 B-step */ 825/********************************************************/ 826 827/* Version 2.0 */ 828 829/* 830 This version is a fix to TCO bug. This version can be loaded instead 831 the CPUSaver version by modifing the registry key "LoadTcoUCodeInsteadOfCpuSaver" 832 833*/ 834 835 836#define D102_B_TCO_UCODE \ 837{\ 8380x1FFF0ED3, \ 8390x02BF0E93, \ 8400x1FFF1FFF, \ 8410x1FFF08FA, \ 8420x1FFF1FFF, \ 8430x0EA10892, \ 8440x00906ED8, \ 8450x01406C55, \ 8460x00E00ED4, \ 8470x00000000, \ 8480x00000000, \ 8490x00000000, \ 8500x00000000, \ 8510x00000000, \ 8520x00E00E94, \ 8530x00200004, \ 8540x01410000, \ 8550x014B6F6F, \ 8560x0030FFFF, \ 8570x01486F72, \ 8580x00E81F9B, \ 8590x00E00EA3, \ 8600x003C0040, \ 8610x00380920, \ 8620x00C02000, \ 8630x0150ED38, \ 8640x0150EE39, \ 8650x0150EF3A, \ 8660x003C0040, \ 8670x01506F0D, \ 8680x01600E72, \ 8690x00380AE0, \ 8700x00E002C0, \ 8710x00300001, \ 8720x014C0000, \ 8730x008404DC, \ 8740x014C6F72, \ 8750x00E01F9D, \ 8760x00000000, \ 8770x00000000, \ 8780x00000000, \ 8790x00000000, \ 8800x00000000, \ 8810x00000000, \ 8820x00000000, \ 8830x00000000, \ 8840x01406C57, \ 8850x00919FAD, \ 8860x00038800, \ 8870x00300000, \ 8880x00E81FD5, \ 8890x014D6FC4, \ 8900x00E008FB, \ 8910x00000000, \ 8920x00000000, \ 8930x00000000, \ 8940x00000000, \ 8950x00000000, \ 8960x00000000, \ 8970x00000000, \ 8980x00000000, \ 8990x00000000, \ 9000x00000000, \ 9010x00000000, \ 9020x00000000, \ 9030x00000000, \ 9040x00000000, \ 9050x00000000, \ 9060x00000000, \ 9070x00000000, \ 9080x00000000, \ 9090x00000000, \ 9100x00000000, \ 9110x00000000, \ 9120x00000000, \ 9130x00000000, \ 9140x00000000, \ 9150x00000000, \ 9160x00138800, \ 9170x00300001, \ 9180x00E81FD5, \ 9190x00202500, \ 9200x00E81F9B, \ 9210x01600EC5, \ 9220x00E00893, \ 9230x00000000, \ 9240x01406CD5, \ 9250x0091EEA3, \ 9260x00904EA3, \ 9270x00901F89, \ 9280x00E00EA3, \ 9290x00340020, \ 9300x014C6FED, \ 9310x01603472, \ 9320x016035EE, \ 9330x016036EF, \ 9340x00300004, \ 9350x01611C71, \ 9360x00300014, \ 9370x00200A00, \ 9380x00E810B9, \ 9390x00600000, \ 9400x00000000, \ 9410x00000000, \ 9420x00000000, \ 9430x00000000, \ 9440x00000000, \ 9450x00000000, \ 9460x00000000, \ 9470x00000000, \ 9480x00000000, \ 9490x00000000, \ 9500x00000000, \ 9510x00000000, \ 9520x00000000, \ 9530x00000000, \ 9540x00000000, \ 9550x00000000, \ 9560x00000000, \ 9570x00000000, \ 9580x00000000, \ 9590x00000000, \ 9600x00000000, \ 9610x00000000, \ 9620x00000000, \ 9630x00000000, \ 9640x00000000, \ 9650x00000000, \ 9660x00000000, \ 9670x00000000, \ 9680x00000000, \ 9690x00000000, \ 9700x00000000, \ 9710x00000000, \ 972} 973 974 975 976/********************************************************/ 977/* Micro code for the D102 C-step */ 978/********************************************************/ 979 980/* Parameter values for the D102 C-step */ 981#define D102_C_CPUSAVER_DWORD 46 982#define D102_C_CPUSAVER_BUNDLE_MAX_DWORD 54 983#define D102_C_CPUSAVER_MIN_SIZE_DWORD 133 /* not implemented */ 984 985 986 987 988 989#if 0 990// this uCode include the CPU Saver and the TCO work around 991//for IP fregments. 992#endif 993#define D102_C_RCVBUNDLE_UCODE \ 994{ \ 9950x00700279, \ 9960x0E6104E2, \ 9970x02BF0CAE, \ 9980x1519150C, \ 9990x1FFF0E5B, \ 10000x1FFF1FFF, \ 10010x00E014D8, \ 10020x00000000, \ 10030x00000000, \ 10040x00000000, \ 10050x00E014DC, \ 10060x00000000, \ 10070x00000000, \ 10080x00000000, \ 10090x00E014F4, \ 10100x00000000, \ 10110x00000000, \ 10120x00000000, \ 10130x00000000, \ 10140x00000000, \ 10150x00000000, \ 10160x00000000, \ 10170x00E014E0, \ 10180x00000000, \ 10190x00000000, \ 10200x00000000, \ 10210x00000000, \ 10220x00000000, \ 10230x00000000, \ 10240x00000000, \ 10250x00000000, \ 10260x00000000, \ 10270x00000000, \ 10280x00000000, \ 10290x00000000, \ 10300x00000000, \ 10310x00000000, \ 10320x00000000, \ 10330x00E014E7, \ 10340x00000000, \ 10350x00000000, \ 10360x00000000, \ 10370x00141000, \ 10380x015D6F0D, \ 10390x00E002C0, \ 10400x00000000, \ 10410x00200600, \ 10420x00E0150D, \ 10430x00000000, \ 10440x00000000, \ 10450x00000000, \ 10460x00000000, \ 10470x00000000, \ 10480x00000000, \ 10490x00300006, \ 10500x00E0151A, \ 10510x00000000, \ 10520x00000000, \ 10530x00000000, \ 10540x00000000, \ 10550x00000000, \ 10560x00000000, \ 10570x00000000, \ 10580x00000000, \ 10590x00000000, \ 10600x00000000, \ 10610x00000000, \ 10620x00000000, \ 10630x00000000, \ 10640x00000000, \ 10650x00906E65, \ 10660x00800E60, \ 10670x00E00E5D, \ 10680x00000000, \ 10690x00000000, \ 10700x00000000, \ 10710x00000000, \ 10720x00000000, \ 10730x00000000, \ 10740x00000000, \ 10750x00000000, \ 10760x00000000, \ 10770x00000000, \ 10780x00000000, \ 10790x00000000, \ 10800x00000000, \ 10810x00000000, \ 10820x00000000, \ 10830x00000000, \ 10840x00000000, \ 10850x00000000, \ 10860x00000000, \ 10870x00000000, \ 10880x00000000, \ 10890x00000000, \ 10900x00000000, \ 10910x00000000, \ 10920x00000000, \ 10930x00000000, \ 10940x00000000, \ 10950x00000000, \ 10960x00000000, \ 10970x00000000, \ 10980x00000000, \ 10990x00000000, \ 11000x00000000, \ 11010x00000000, \ 11020x00000000, \ 11030x00000000, \ 11040x00000000, \ 11050x00000000, \ 11060x00000000, \ 11070x00000000, \ 11080x00000000, \ 11090x00000000, \ 11100x00000000, \ 11110x00000000, \ 11120x00000000, \ 11130x00000000, \ 11140x00000000, \ 11150x00000000, \ 11160x00000000, \ 11170x00000000, \ 11180x00000000, \ 11190x00000000, \ 11200x00000000, \ 11210x00000000, \ 11220x00000000, \ 11230x00000000, \ 11240x00000000, \ 11250x00000000, \ 11260x00000000, \ 11270x00000000, \ 11280x00000000, \ 1129} 1130