fwphyreg.h revision 120431 
1/*
2 * Copyright (C) 2003
3 * 	Hidetoshi Shimokawa. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the following acknowledgement:
15 *
16 *	This product includes software developed by Hidetoshi Shimokawa.
17 *
18 * 4. Neither the name of the author nor the names of its contributors
19 *    may be used to endorse or promote products derived from this software
20 *    without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $FreeBSD: head/sys/dev/firewire/fwphyreg.h 120431 2003-09-25 09:27:05Z simokawa $
35 */
36
37struct phyreg_base {
38#if BYTE_ORDER == BIG_ENDIAN
39	u_int8_t	phy_id:6,
40			r:1,
41			cps:1;
42	u_int8_t	rhb:1,
43			ibr:1,
44			gap_count:6;
45	u_int8_t	extended:3,
46			num_ports:5;
47	u_int8_t	phy_speed:3,
48			:1,
49			delay:4;
50	u_int8_t	lctrl:1,
51			c:1,
52			jitter:3,
53			pwr_class:3;
54	u_int8_t	wdie:1,
55			isbr:1,
56			ctoi:1,
57			cpsi:1,
58			stoi:1,
59			pei:1,
60			eaa:1,
61			emc:1;
62	u_int8_t	legacy_spd:3,
63			blink:1,
64			bridge:2,
65			:2;
66	u_int8_t	page_select:3,
67			:1,
68			port_select:4;
69#else
70	u_int8_t	cps:1,
71			r:1,
72			phy_id:6;
73	u_int8_t	gap_count:6,
74			ibr:1,
75			rhb:1;
76	u_int8_t	num_ports:5,
77			extended:3;
78	u_int8_t	delay:4,
79			:1,
80			phy_speed:3;
81	u_int8_t	pwr_class:3,
82			jitter:3,
83			c:1,
84			lctrl:1;
85	u_int8_t	emc:1,
86			eaa:1,
87			pei:1,
88			stoi:1,
89			cpsi:1,
90			ctoi:1,
91			isbr:1,
92			wdie:1;
93	u_int8_t	:2,
94			bridge:2,
95			blink:1,
96			legacy_spd:3;
97	u_int8_t	port_select:4,
98			:1,
99			page_select:3;
100#endif
101};
102
103struct phyreg_page0 {
104#if BYTE_ORDER == BIG_ENDIAN
105	u_int8_t	astat:2,
106			bstat:2,
107			ch:1,
108			con:1,
109			rxok:1,
110			dis:1;
111	u_int8_t	negotiated_speed:3,
112			pie:1,
113			fault:1,
114			stanby_fault:1,
115			disscrm:1,
116			b_only:1;
117	u_int8_t	dc_connected:1,
118			max_port_speed:3,
119			lpp:1,
120			cable_speed:3;
121	u_int8_t	connection_unreliable:1,
122			:3,
123			beta_mode:1,
124			:3;
125	u_int8_t	port_error;
126	u_int8_t	:5,
127			loop_disable:1,
128			in_standby:1,
129			hard_disable:1;
130	u_int8_t	:8;
131	u_int8_t	:8;
132#else
133	u_int8_t	dis:1,
134			rxok:1,
135			con:1,
136			ch:1,
137			bstat:2,
138			astat:2;
139	u_int8_t	b_only:1,
140			disscrm:1,
141			stanby_fault:1,
142			fault:1,
143			pie:1,
144			negotiated_speed:3;
145	u_int8_t	cable_speed:3,
146			lpp:1,
147			max_port_speed:3,
148			dc_connected:1;
149	u_int8_t	:3,
150			beta_mode:1,
151			:3,
152			connection_unreliable:1;
153	u_int8_t	port_error;
154	u_int8_t	hard_disable:1,
155			in_standby:1,
156			loop_disable:1,
157			:5;
158	u_int8_t	:8;
159	u_int8_t	:8;
160#endif
161};
162
163struct phyreg_page1 {
164	u_int8_t	compliance;
165	u_int8_t	:8;
166	u_int8_t	vendor_id[3];
167	u_int8_t	product_id[3];
168};
169