18876Srgrimes/*- 24Srgrimes * Copyright (c) 2001-2003 34Srgrimes * Fraunhofer Institute for Open Communication Systems (FhG Fokus). 44Srgrimes * All rights reserved. 58876Srgrimes * 64Srgrimes * Redistribution and use in source and binary forms, with or without 74Srgrimes * modification, are permitted provided that the following conditions 84Srgrimes * are met: 94Srgrimes * 1. Redistributions of source code must retain the above copyright 104Srgrimes * notice, this list of conditions and the following disclaimer. 118876Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 128876Srgrimes * notice, this list of conditions and the following disclaimer in the 134Srgrimes * documentation and/or other materials provided with the distribution. 144Srgrimes * 158876Srgrimes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 164Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 178876Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 184Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 194Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 204Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 214Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 228876Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 234Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 244Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 254Srgrimes * SUCH DAMAGE. 264Srgrimes * 274Srgrimes * Author: Hartmut Brandt <harti@freebsd.org> 284Srgrimes * 294Srgrimes * $FreeBSD$ 304Srgrimes * 314Srgrimes * Fore PCA200E hardware definitions. 324Srgrimes */ 33116176Sobrien 34116176Sobrien/* 35116176Sobrien * Fore implements some additional PCI registers. One of them is the 36116176Sobrien * master control register. One of the bits allow to automatically byte 372056Swollman * swap accesses to the on-board RAM. 3842654Sjdp */ 3986998Sdd#define FATM_PCIR_MCTL 0x41 40131952Smarcel#define FATM_PCIM_SWAB 0x100 4186998Sdd 4286998Sdd/* 4317848Spst * Operations codes for commands. 4486998Sdd */ 452056Swollmanenum { 4649558Sphk FATM_OP_INITIALIZE = 0x01, /* Initialize the card */ 47126399Sphk FATM_OP_ACTIVATE_VCIN = 0x02, /* Start reassembly on a channel */ 4812734Sbde FATM_OP_ACTIVATE_VCOUT = 0x03, /* (not used) */ 492056Swollman FATM_OP_DEACTIVATE_VCIN = 0x04, /* Stop reassembly on a channel */ 5012473Sbde FATM_OP_DEACTIVATE_VCOUT= 0x05, /* (not used) */ 514Srgrimes FATM_OP_REQUEST_STATS = 0x06, /* Get statistics */ 524Srgrimes FATM_OP_OC3_SET_REG = 0x07, /* Set OC3 chip register */ 534Srgrimes FATM_OP_OC3_GET_REG = 0x08, /* Get OC3 chip registers */ 54118990Smarcel FATM_OP_ZERO_STATS = 0x09, /* Zero out statistics */ 5579418Sjulian FATM_OP_GET_PROM_DATA = 0x0a, /* Return expansion ROM data */ 564Srgrimes FATM_OP_SETVPI_BITS = 0x0b, /* (not used, not implemented) */ 574Srgrimes 584Srgrimes FATM_OP_INTERRUPT_SEL = 0x80, /* Request interrupt on completion */ 594Srgrimes}; 604Srgrimes 6118296Sbde/* 624Srgrimes * Status word definitions. Before initiating an operation the host sets the 634Srgrimes * status word to PENDING. The card sets it to COMPLETE upon completion of 644Srgrimes * the transmit/receive or command. An unused queue entry contains FREE. 654Srgrimes * The ERROR can be ored into the COMPLETE. Note, that there are circumstances 6678161Speter * when ERROR is set without COMPLETE beeing set (when you try to activate 6778161Speter * a bad VCI like, for example, VCI 0). 6878161Speter */ 6912515Sphkenum { 70132002Smarcel FATM_STAT_PENDING = 0x01, 7186998Sdd FATM_STAT_COMPLETE = 0x02, 7285944Speter FATM_STAT_FREE = 0x04, 73132482Smarcel FATM_STAT_ERROR = 0x08, 74126399Sphk}; 7517848Spst 7618296Sbde/* 7718296Sbde * On board queue offsets. There are two fundamentally different queue types: 7818296Sbde * the command queue and all other queues. The command queue has 32 byte 794Srgrimes * entries on the card which contain the operation code, parameters and the 804Srgrimes * DMA pointer to the status word. All other queues have 8 byte entries, which 814Srgrimes * contain a DMA pointer to the i/o block, that contains the parameters, and 824Srgrimes * a DMA pointer to the status word. 834Srgrimes */ 8412515Sphk#define FATMOC_OP 0 /* cmd queue: offset to op code */ 854Srgrimes#define FATMOC_PARAM 4 /* cmd queue: offset to parameters */ 864Srgrimes#define FATMOC_STATP 16 /* cmd queue: offset to status ptr */ 874Srgrimes#define FATMOC_END 32 /* cmd queue: element size */ 884Srgrimes 894Srgrimes#define FATMOC_ACTIN_VPVC (FATMOC_PARAM + 0) 904Srgrimes#define FATMOC_ACTIN_MTU (FATMOC_PARAM + 4) 914Srgrimes#define FATMOC_DEACTIN_VPVC (FATMOC_PARAM + 0) 924Srgrimes#define FATMOC_GETOC3_BUF (FATMOC_PARAM + 0) 934Srgrimes#define FATMOC_GSTAT_BUF (FATMOC_PARAM + 0) 944Srgrimes#define FATMOC_GPROM_BUF (FATMOC_PARAM + 0) 954Srgrimes 964Srgrimes#define FATMOS_IOBLK 0 /* other queues: offset to ioblk ptr */ 974Srgrimes#define FATMOS_STATP 4 /* other queues: offset to status ptr */ 984Srgrimes 994Srgrimes#define FATM_MAKE_SETOC3(REG,VAL,MASK) \ 1004Srgrimes (FATM_OP_OC3_SET_REG | (((REG) & 0xff) << 8) | \ 1014Srgrimes (((VAL) & 0xff) << 16) | (((MASK) & 0xff) << 24)) 1024Srgrimes#define FATM_NREGS 128 1034Srgrimes 1044Srgrimes 1054Srgrimes/* 1064Srgrimes * On board memory layout. 10793009Sbde * 10893009Sbde * The card contains up to 2MByte memory that is mapped at virtual offset 0. 10992756Salfred * It is followed by three registers. The memory contains two areas at 11093009Sbde * fixed addresses: the mon960 area that is used for communication with 11193009Sbde * the card's operating system and the common block that is used by the 11292756Salfred * firmware to communicate with the driver. 11393009Sbde */ 11493009Sbde#define FATM_RAM_SIZE (256 * 1024) /* normal RAM size */ 11512473Sbde 1164Srgrimes#define FATMO_RAM (0x0) /* virtual RAM start */ 1174Srgrimes#define FATMO_MON960 (0x400) /* mon960 communication area */ 1184Srgrimes#define FATMO_COMMON_ORIGIN (0x4d40) /* firmware comm. area */ 11912515Sphk 12078161Speter#define FATMO_HCR (0x100000) /* host control registers */ 1214Srgrimes#define FATMO_HIMR (0x100004) /* host interrupt mask */ 1224Srgrimes#define FATMO_PSR (0x100008) /* PCI control register */ 12318296Sbde 12478161Speter#define FATMO_END (0x200000) /* end of mapped area */ 1254Srgrimes 1264Srgrimes/* 1274Srgrimes * The mon960 area contains two cells that are used as a virtual serial 12818296Sbde * interface, a status word, the base for loading the application (i.e. 1294Srgrimes * firmware) and a version number. 1304Srgrimes */ 1314Srgrimes#define FATMO_UART_TO_960 (FATMO_MON960 + 0) 1324Srgrimes#define FATMO_UART_TO_HOST (FATMO_MON960 + 4) 1334Srgrimes#define FATMO_BOOT_STATUS (FATMO_MON960 + 8) 1344Srgrimes#define FATMO_APP_BASE (FATMO_MON960 + 12) 1354Srgrimes#define FATMO_VERSION (FATMO_MON960 + 16) 1364Srgrimes 1374Srgrimes 1384Srgrimes/* 1394Srgrimes * The host control register allows to hold the i960 or send it interrupts. 1404Srgrimes * The bits have different meaning on read and write. 1414Srgrimes */ 1424Srgrimes#define FATM_HCR_RESET 0x01 /* (W) reset the card */ 1434Srgrimes#define FATM_HCR_LOCK_HOLD 0x02 /* (W) hold the i960 */ 1444Srgrimes#define FATM_HCR_I960FAIL 0x04 /* (R) internal self-test failed */ 1454Srgrimes#define FATM_HCR_INTR2 0x04 /* (W) assert i960 interrupt 2 */ 1464Srgrimes#define FATM_HCR_HOLDA 0x08 /* (R) hold ack from i960 */ 1474Srgrimes#define FATM_HCR_INTR1 0x08 /* (W) assert i960 interrupt 1 */ 1484Srgrimes#define FATM_HCR_OFIFO 0x10 /* (R) DMA request FIFO full */ 1494Srgrimes#define FATM_HCR_CLRIRQ 0x10 /* (W) clear interrupt request */ 1504Srgrimes#define FATM_HCR_ESP_HOLD 0x20 /* (R) SAR chip holds i960 */ 1514Srgrimes#define FATM_HCR_IFIFO 0x40 /* (R) input FIFO full */ 1524Srgrimes#define FATM_HCR_TESTMODE 0x80 /* (R) board is in test mode */ 1534Srgrimes 1544Srgrimes/* 1554Srgrimes * The mon960 area contains a virtual UART and a status word. 1564Srgrimes * The UART uses a simple protocol: a zero means, that there is no 1574Srgrimes * character available from the i960 or that one can write the next 1584Srgrimes * character to the i960. This character has to be ored with 0x1000000 1594Srgrimes * to signal to the i960 that there is a new character. 1604Srgrimes * The cold_start values must be written to the status word, the others 16118296Sbde * denote certain stages of initializing. 16218296Sbde */ 16378161Speter#define XMIT_READY 0 16418296Sbde#define CHAR_AVAIL 0x1000000 16518296Sbde 16618296Sbde#define COLD_START 0xc01dc01d 16718296Sbde#define SELF_TEST_OK 0x02201958 16818296Sbde#define SELF_TEST_FAIL 0xadbadbad 16918296Sbde#define CP_RUNNING 0xce11feed 17018296Sbde#define MON906_TOO_BIG 0x10aded00 17118296Sbde 17218296Sbde/* 17318296Sbde * The firmware communication area contains a big structure most of which 17418296Sbde * is used only during initialisation. 17518296Sbde */ 17618296Sbde/* 17718296Sbde * These are the offsets to the onboard queues that are valid after the 17818296Sbde * initialisation command has completed. 17918296Sbde */ 18018296Sbde#define FATMO_COMMAND_QUEUE (FATMO_COMMON_ORIGIN + 0) 18118296Sbde#define FATMO_TRANSMIT_QUEUE (FATMO_COMMON_ORIGIN + 4) 18218296Sbde#define FATMO_RECEIVE_QUEUE (FATMO_COMMON_ORIGIN + 8) 18318296Sbde#define FATMO_SMALL_B1_QUEUE (FATMO_COMMON_ORIGIN + 12) 18418296Sbde#define FATMO_LARGE_B1_QUEUE (FATMO_COMMON_ORIGIN + 16) 18518296Sbde#define FATMO_SMALL_B2_QUEUE (FATMO_COMMON_ORIGIN + 20) 18618296Sbde#define FATMO_LARGE_B2_QUEUE (FATMO_COMMON_ORIGIN + 24) 18718296Sbde 18818296Sbde/* 18918296Sbde * If the interrupt mask is set to 1, interrupts to the host are queued, but 19018296Sbde * inhbited. The istat variable is set, when this card has posted an interrupt. 19118296Sbde */ 19218296Sbde#define FATMO_IMASK (FATMO_COMMON_ORIGIN + 28) 1934Srgrimes#define FATMO_ISTAT (FATMO_COMMON_ORIGIN + 32) 1944Srgrimes 1954Srgrimes/* 1964Srgrimes * This is the offset and the size of the queue area. Could be used to 1974Srgrimes * dynamically compute queue sizes. 1984Srgrimes */ 1994Srgrimes#define FATMO_HEAP_BASE (FATMO_COMMON_ORIGIN + 36) 2004Srgrimes#define FATMO_HEAP_SIZE (FATMO_COMMON_ORIGIN + 40) 2014Srgrimes 20212515Sphk#define FATMO_HLOGGER (FATMO_COMMON_ORIGIN + 44) 20378161Speter 2044Srgrimes/* 20518296Sbde * The heartbeat variable is incremented in each loop of the normal processing. 20678161Speter * If it is stuck this means, that the card had a fatal error. In this case 2074Srgrimes * it may set the word to a number of values of the form 0xdeadXXXX where 2084Srgrimes * XXXX is an error code. 20918296Sbde */ 2104Srgrimes#define FATMO_HEARTBEAT (FATMO_COMMON_ORIGIN + 48) 2114Srgrimes 2124Srgrimes#define FATMO_FIRMWARE_RELEASE (FATMO_COMMON_ORIGIN + 52) 2134Srgrimes#define FATMO_MON960_RELEASE (FATMO_COMMON_ORIGIN + 56) 2144Srgrimes#define FATMO_TQ_PLEN (FATMO_COMMON_ORIGIN + 60) 21518296Sbde 21618296Sbde/* 21778161Speter * At this offset the init command block is located. The init command cannot 21818296Sbde * use the normal queue mechanism because it is used to initialize the 21918296Sbde * queues. For this reason it is located at this fixed offset. 22018296Sbde */ 2214Srgrimes#define FATMO_INIT (FATMO_COMMON_ORIGIN + 64) 2224Srgrimes 22312515Sphk/* 22478161Speter * physical media type 2254Srgrimes */ 2264Srgrimes#define FATMO_MEDIA_TYPE (FATMO_COMMON_ORIGIN + 176) 22718296Sbde#define FATMO_OC3_REVISION (FATMO_COMMON_ORIGIN + 180) 22878161Speter 2294Srgrimes/* 2304Srgrimes * End of the common block 2314Srgrimes */ 2324Srgrimes#define FATMO_COMMON_END (FATMO_COMMON_ORIGIN + 184) 2334Srgrimes 234798Swollman/* 2354Srgrimes * The INITIALIZE command block. This is embedded into the above common 2364Srgrimes * block. The offsets are from the beginning of the command block. 2374Srgrimes */ 2384Srgrimes#define FATMOI_OP 0 /* operation code */ 2394Srgrimes#define FATMOI_STATUS 4 /* status word */ 2404Srgrimes#define FATMOI_RECEIVE_TRESHOLD 8 /* when to start interrupting */ 2414Srgrimes#define FATMOI_NUM_CONNECT 12 /* max number of VCIs */ 2424Srgrimes#define FATMOI_CQUEUE_LEN 16 /* length of command queue */ 2434Srgrimes#define FATMOI_TQUEUE_LEN 20 /* length of transmit queue */ 2444Srgrimes#define FATMOI_RQUEUE_LEN 24 /* length of receive queue */ 2454Srgrimes#define FATMOI_RPD_EXTENSION 28 /* additional 32 byte blocks */ 2464Srgrimes#define FATMOI_TPD_EXTENSION 32 /* additional 32 byte blocks */ 24710348Sbde#define FATMOI_CONLESS_VPVC 36 /* (not used) */ 2484Srgrimes#define FATMOI_SMALL_B1 48 /* small buffer 1 pool */ 2494Srgrimes#define FATMOI_LARGE_B1 64 /* small buffer 2 pool */ 2504Srgrimes#define FATMOI_SMALL_B2 80 /* large buffer 1 pool */ 2514Srgrimes#define FATMOI_LARGE_B2 96 /* large buffer 2 pool */ 2524Srgrimes#define FATMOI_END 112 /* size of init block */ 2534Srgrimes 2544Srgrimes/* 2554Srgrimes * Each of the four buffer schemes is initialized with a block that 2564Srgrimes * contains four words: 2574Srgrimes */ 2584Srgrimes#define FATMOB_QUEUE_LENGTH 0 /* supply queue length */ 2594Srgrimes#define FATMOB_BUFFER_SIZE 4 /* size of each buffer */ 2604Srgrimes#define FATMOB_POOL_SIZE 8 /* size of on-board pool */ 2614Srgrimes#define FATMOB_SUPPLY_BLKSIZE 12 /* number of buffers/supply */ 26218296Sbde 26378161Speter/* 2644Srgrimes * The fore firmware is a binary file, that starts with a header. The 2654Srgrimes * header contains the offset to where the file must be loaded and the 2664Srgrimes * entry for execution. The header must also be loaded onto the card! 2674Srgrimes */ 2684Srgrimesstruct firmware { 2694Srgrimes uint32_t id; /* "FORE" */ 2704Srgrimes uint32_t version; /* firmware version */ 2714Srgrimes uint32_t offset; /* load offset */ 2724Srgrimes uint32_t entry; /* entry point */ 2734Srgrimes}; 2744Srgrimes#define FATM_FWID 0x65726f66 /* "FORE" */ 27578161Speter#define FATM_FWVERSION 0x100 /* supported version */ 2764Srgrimes 2774Srgrimes/* 2784Srgrimes * PDUs to be transmitted are described by Transmit PDU Descriptors. 2794Srgrimes * These descriptors are held in host memory, but referenced from the ioblk 2804Srgrimes * member of the queue structure on the card. The card DMAs the descriptor 2814Srgrimes * and than gather-DMAs the PDU transmitting it on-the-fly. Tpds are variable 28218296Sbde * length in blocks of 32 byte (8 words). The minimum length is one block, 28318296Sbde * maximum 15. The number of blocks beyond 1 is configured during the 284104321Sphk * initialisation command (tpd_extension). 28578161Speter * Each gather-DMA segment is described by a segment descriptor. The buffer 28678161Speter * address and the length must be a multiple of four. 287104321Sphk * Tpd must also be 4 byte aligned. 28818296Sbde * Because of the minimum length of 32 byte, the first blocks contains already 2894Srgrimes * 2 segement descriptors. Each extension block holds four descriptors. 2904Srgrimes */ 29178161Speter#define TXD_FIXED 2 2924Srgrimes#define SEGS_PER_BLOCK 4 /* segment descriptors per extension block */ 2934Srgrimesstruct txseg { 2944Srgrimes uint32_t buffer; /* DMA buffer address */ 2954Srgrimes uint32_t length; /* and length */ 2964Srgrimes}; 2974Srgrimesstruct tpd { 2984Srgrimes uint32_t atm_header; /* header for the transmitted cells */ 2994Srgrimes uint32_t spec; /* PDU description */ 3004Srgrimes uint32_t stream; /* traffic shaping word */ 3014Srgrimes uint32_t pad[1]; 3024Srgrimes struct txseg segment[TXD_FIXED]; 3034Srgrimes}; 3044Srgrimes 3054Srgrimes#define TDX_MKSPEC(INTR,AAL,NSEG,LEN) \ 3064Srgrimes (((INTR) << 28) | ((AAL) << 24) | ((NSEG) << 16) | (LEN)) 3074Srgrimes#define TDX_MKSTR(DATA,IDLE) \ 3084Srgrimes (((DATA) << 16) | (IDLE)) 3094Srgrimes#define TDX_MKHDR(VPI,VCI,PT,CLP) \ 3104Srgrimes (((VPI) << 20) | ((VCI) << 4) | ((PT) << 1) | (CLP)) 3114Srgrimes#define TDX_SEGS2BLKS(SEGS) \ 3124Srgrimes (1 + ((SEGS)-TXD_FIXED+SEGS_PER_BLOCK-1)/SEGS_PER_BLOCK) 3134Srgrimes 3144Srgrimes/* 3154Srgrimes * We want probably support scatter transmission, so we use the maximum 3164Srgrimes * transmit descriptor extension that is possible. Because the size of the 3174Srgrimes * Tpd is encoded in 32-byte blocks in a 4-bit field, the maximum extension 3184Srgrimes * is 14 such blocks. The value for the init command is the number of 3194Srgrimes * additional descriptor entries NOT the number of 32 byte blocks. 3204Srgrimes */ 3214Srgrimes#define TPD_EXTENSION_BLOCKS 14 3224Srgrimes#define TPD_EXTENSIONS (TPD_EXTENSION_BLOCKS * 4) 3234Srgrimes#define TPD_SIZE ((size_t)((TPD_EXTENSION_BLOCKS+1) * 32)) 3244Srgrimes 3254Srgrimes/* 3264Srgrimes * Received PDUs are handed from the card to the host by means of Receive 3274Srgrimes * PDU descriptors. Each segment describes on part of the PDU. The buffer 3284Srgrimes * handle is a 32 bit value that is supplied by the host and passed 3294Srgrimes * transparently back to the host by the card. It is used to locate the buffer. 3304Srgrimes * The length field is the number of actual bytes in that buffer. 3314Srgrimes */ 3324Srgrimes#define RXD_FIXED 3 3334Srgrimesstruct rxseg { 3344Srgrimes uint32_t handle; /* buffer handle */ 3354Srgrimes uint32_t length; /* number of bytes */ 3364Srgrimes}; 3374Srgrimesstruct rpd { 3384Srgrimes uint32_t atm_header; 3394Srgrimes uint32_t nseg; 3404Srgrimes struct rxseg segment[RXD_FIXED]; 3414Srgrimes}; 3424Srgrimes 3434Srgrimes/* 3444Srgrimes * PDUs received are stored in buffers supplied to the card. We use only 3454Srgrimes * buffer scheme 1: small buffers are normal mbuf's which can hold three 3464Srgrimes * cells in their default size (256 byte) and mbuf clusters which can 3474Srgrimes * hold 42 cells (2 kbyte). 3484Srgrimes * The number of receive segments can be computed from these sizes: 3494Srgrimes */ 350118268Sjhb#define FATM_MAXPDU 65535 3514Srgrimes#define MAXPDU_CELLS ((FATM_MAXPDU+47)/48) 3524Srgrimes 3534Srgrimes#define SMALL_BUFFER_CELLS (MHLEN/48) 3544Srgrimes#define LARGE_BUFFER_CELLS (MCLBYTES/48) 3554Srgrimes 3564Srgrimes#define SMALL_BUFFER_LEN (SMALL_BUFFER_CELLS * 48) 3574Srgrimes#define LARGE_BUFFER_LEN (LARGE_BUFFER_CELLS * 48) 3584Srgrimes 3594Srgrimes/* 3604Srgrimes * The card first alloctes a small buffer and the switches to large 3614Srgrimes * buffers. So the number of large buffers needed to store the maximum 3624Srgrimes * PDU is: 3634Srgrimes */ 3644Srgrimes#define MAX_LARGE_BUFFERS ((MAXPDU_CELLS - SMALL_BUFFER_CELLS \ 3654Srgrimes + LARGE_BUFFER_CELLS - 1) \ 3664Srgrimes / LARGE_BUFFER_CELLS) \ 3674Srgrimes 3684Srgrimes/* 3694Srgrimes * From this we get the number of extension blocks for the Rpds as: 3704Srgrimes */ 3714Srgrimes#define RPD_EXTENSION_BLOCKS ((MAX_LARGE_BUFFERS + 1 - RXD_FIXED \ 3724Srgrimes + SEGS_PER_BLOCK - 1) \ 3734Srgrimes / SEGS_PER_BLOCK) 3744Srgrimes#define RPD_EXTENSIONS (RPD_EXTENSION_BLOCKS * 4) 3754Srgrimes#define RPD_SIZE ((size_t)((RPD_EXTENSION_BLOCKS+1) * 32)) 3764Srgrimes 3772112Swollman/* 37812515Sphk * Buffers are supplied to the card prior receiving by the supply queues. 3791549Srgrimes * We use two queues: scheme 1 small buffers and scheme 1 large buffers. 3804Srgrimes * The queues and on-card pools are initialized by the initialize command. 3814Srgrimes * Buffers are supplied in chunks. Each chunk can contain from 4 to 124 3824Srgrimes * buffers in multiples of four. The chunk sizes are configured by the 38312515Sphk * initialize command. Each buffer in a chunk is described by a Receive 3844Srgrimes * Buffer Descriptor that is held in host memory and given as the ioblk 3854Srgrimes * to the card. 3864Srgrimes */ 387131952Smarcel#define BSUP_BLK2SIZE(CHUNK) (8 * (CHUNK)) 3884Srgrimes 3894Srgrimesstruct rbd { 3904Srgrimes uint32_t handle; 39112515Sphk uint32_t buffer; /* DMA address for card */ 3924Srgrimes}; 3936920Sjoerg 3944Srgrimes/* 3954Srgrimes * The PCA200E has an expansion ROM that contains version information and 3964Srgrimes * the FORE-assigned MAC address. It can be read via the get_prom_data 3974Srgrimes * operation. 3984Srgrimes */ 3994Srgrimesstruct prom { 4004Srgrimes uint32_t version; 4014Srgrimes uint32_t serial; 4024Srgrimes uint8_t mac[8]; 4034Srgrimes}; 4044Srgrimes 40579573Sbsd/* 40679573Sbsd * The media type member of the firmware communication block contains a 4074Srgrimes * code that describes the physical medium and physical protocol. 4084Srgrimes */ 4094Srgrimes#define FORE_MT_TAXI_100 0x04 4104Srgrimes#define FORE_MT_TAXI_140 0x05 4114Srgrimes#define FORE_MT_UTP_SONET 0x06 4124Srgrimes#define FORE_MT_MM_OC3_ST 0x16 4134Srgrimes#define FORE_MT_MM_OC3_SC 0x26 414132484Smarcel#define FORE_MT_SM_OC3_ST 0x36 415132484Smarcel#define FORE_MT_SM_OC3_SC 0x46 4164Srgrimes 4174Srgrimes/* 4181147Sguido * Assorted constants 419132002Smarcel */ 42085944Speter#define FORE_MAX_VCC 1024 /* max. number of VCIs supported */ 42186998Sdd#define FORE_VCIBITS 10 422126399Sphk 423131952Smarcel#define FATM_STATE_TIMEOUT 500 /* msec */ 4244Srgrimes 4254Srgrimes/* 4264Srgrimes * Statistics as delivered by the FORE cards 42712515Sphk */ 4284Srgrimesstruct fatm_stats { 42933296Sbde struct { 43033296Sbde uint32_t crc_header_errors; 43133296Sbde uint32_t framing_errors; 43233296Sbde uint32_t pad[2]; 43333296Sbde } phy_4b5b; 4346204Sphk 4357170Sdg struct { 4366204Sphk uint32_t section_bip8_errors; 4376204Sphk uint32_t path_bip8_errors; 4386204Sphk uint32_t line_bip24_errors; 4394Srgrimes uint32_t line_febe_errors; 4404Srgrimes uint32_t path_febe_errors; 4414Srgrimes uint32_t corr_hcs_errors; 4424Srgrimes uint32_t ucorr_hcs_errors; 4434Srgrimes uint32_t pad[1]; 4444Srgrimes } phy_oc3; 4454Srgrimes 4464Srgrimes struct { 4474Srgrimes uint32_t cells_transmitted; 4484Srgrimes uint32_t cells_received; 4494Srgrimes uint32_t vpi_bad_range; 4504Srgrimes uint32_t vpi_no_conn; 4514Srgrimes uint32_t vci_bad_range; 4524Srgrimes uint32_t vci_no_conn; 4534Srgrimes uint32_t pad[2]; 4544Srgrimes } atm; 45518296Sbde 45678161Speter struct { 4574Srgrimes uint32_t cells_transmitted; 4584Srgrimes uint32_t cells_received; 4594Srgrimes uint32_t cells_dropped; 4604Srgrimes uint32_t pad[1]; 4614Srgrimes } aal0; 462103746Smarkm 4634Srgrimes struct { 4644Srgrimes uint32_t cells_transmitted; 46579884Skris uint32_t cells_received; 4664Srgrimes uint32_t cells_crc_errors; 467131952Smarcel uint32_t cels_protocol_errors; 4684Srgrimes uint32_t cells_dropped; 4694Srgrimes uint32_t cspdus_transmitted; 4704Srgrimes uint32_t cspdus_received; 4714Srgrimes uint32_t cspdus_protocol_errors; 4724Srgrimes uint32_t cspdus_dropped; 4734Srgrimes uint32_t pad[3]; 4744Srgrimes } aal4; 47512515Sphk 47610348Sbde struct { 47710348Sbde uint32_t cells_transmitted; 47810348Sbde uint32_t cells_received; 47910348Sbde uint32_t congestion_experienced; 48010348Sbde uint32_t cells_dropped; 4814Srgrimes uint32_t cspdus_transmitted; 4824Srgrimes uint32_t cspdus_received; 48312473Sbde uint32_t cspdus_crc_errors; 4844Srgrimes uint32_t cspdus_protocol_errors; 4854Srgrimes uint32_t cspdus_dropped; 4864Srgrimes uint32_t pad[3]; 48792756Salfred } aal5; 48893009Sbde 48993009Sbde struct { 49012473Sbde uint32_t small_b1_failed; 4914Srgrimes uint32_t large_b1_failed; 4924Srgrimes uint32_t small_b2_failed; 4934Srgrimes uint32_t large_b2_failed; 4944Srgrimes uint32_t rpd_alloc_failed; 4954Srgrimes uint32_t receive_carrier; 4964Srgrimes uint32_t pad[2]; 4974Srgrimes } aux; 49812473Sbde}; 4994Srgrimes#define FATM_NSTATS 42 5004Srgrimes