if_edreg.h revision 172
16Sdg/* 26Sdg * National Semiconductor DS8390 NIC register definitions 343Sdg * 443Sdg * $Log: if_edreg.h,v $ 5172Sdg * Revision 1.3 93/07/20 15:25:25 davidg 6172Sdg * added config flags for forcing 8/16bit mode and disabling double 7172Sdg * xmit buffers. 8172Sdg * 943Sdg * Revision 1.2 93/06/23 03:03:05 davidg 1043Sdg * added some additional definitions for the 83C584 bus interface 1143Sdg * chip (SMC/WD boards) 1243Sdg * 1343Sdg * Revision 1.1 93/06/23 03:01:07 davidg 1443Sdg * Initial revision 1543Sdg * 166Sdg */ 176Sdg 186Sdg/* 196Sdg * Page 0 register offsets 206Sdg */ 216Sdg#define ED_P0_CR 0x00 /* Command Register */ 226Sdg 236Sdg#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 246Sdg#define ED_P0_PSTART 0x01 /* Page Start register (write) */ 256Sdg 266Sdg#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 276Sdg#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 286Sdg 296Sdg#define ED_P0_BNRY 0x03 /* Boundary Pointer */ 306Sdg 316Sdg#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 326Sdg#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 336Sdg 346Sdg#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 356Sdg#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 366Sdg 376Sdg#define ED_P0_FIFO 0x06 /* FIFO register (read) */ 386Sdg#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 396Sdg 406Sdg#define ED_P0_ISR 0x07 /* Interrupt Status Register */ 416Sdg 426Sdg#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 436Sdg#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 446Sdg 456Sdg#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 466Sdg#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 476Sdg 486Sdg#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 496Sdg 506Sdg#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 516Sdg 526Sdg#define ED_P0_RSR 0x0c /* Receive Status (read) */ 536Sdg#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 546Sdg 556Sdg#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 566Sdg#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 576Sdg 586Sdg#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 596Sdg#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 606Sdg 616Sdg#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 626Sdg#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 636Sdg 646Sdg/* 656Sdg * Page 1 register offsets 666Sdg */ 676Sdg#define ED_P1_CR 0x00 /* Command Register */ 686Sdg#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 696Sdg#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 706Sdg#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 716Sdg#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 726Sdg#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 736Sdg#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 746Sdg#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 756Sdg#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 766Sdg#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 776Sdg#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 786Sdg#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 796Sdg#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 806Sdg#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 816Sdg#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 826Sdg#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 836Sdg 846Sdg/* 856Sdg * Page 2 register offsets 866Sdg */ 876Sdg#define ED_P2_CR 0x00 /* Command Register */ 886Sdg#define ED_P2_PSTART 0x01 /* Page Start (read) */ 896Sdg#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 906Sdg#define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 916Sdg#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 926Sdg#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 936Sdg#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 946Sdg#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 956Sdg#define ED_P2_ACU 0x06 /* Address Counter Upper */ 966Sdg#define ED_P2_ACL 0x07 /* Address Counter Lower */ 976Sdg#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 986Sdg#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 996Sdg#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 1006Sdg#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 1016Sdg 1026Sdg/* 1036Sdg * Command Register (CR) definitions 1046Sdg */ 1056Sdg 1066Sdg/* 1076Sdg * STP: SToP. Software reset command. Takes the controller offline. No 1086Sdg * packets will be received or transmitted. Any reception or 1096Sdg * transmission in progress will continue to completion before 1106Sdg * entering reset state. To exit this state, the STP bit must 1116Sdg * reset and the STA bit must be set. The software reset has 1126Sdg * executed only when indicated by the RST bit in the ISR being 1136Sdg * set. 1146Sdg */ 1156Sdg#define ED_CR_STP 0x01 1166Sdg 1176Sdg/* 1186Sdg * STA: STArt. This bit is used to activate the NIC after either power-up, 1196Sdg * or when the NIC has been put in reset mode by software command 1206Sdg * or error. 1216Sdg */ 1226Sdg#define ED_CR_STA 0x02 1236Sdg 1246Sdg/* 1256Sdg * TXP: Transmit Packet. This bit must be set to indicate transmission of 1266Sdg * a packet. TXP is internally reset either after the transmission is 1276Sdg * completed or aborted. This bit should be set only after the Transmit 1286Sdg * Byte Count and Transmit Page Start register have been programmed. 1296Sdg */ 1306Sdg#define ED_CR_TXP 0x04 1316Sdg 1326Sdg/* 1336Sdg * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 1346Sdg * of the remote DMA channel. RD2 can be set to abort any remote DMA 1356Sdg * command in progress. The Remote Byte Count registers should be cleared 1366Sdg * when a remote DMA has been aborted. The Remote Start Addresses are not 1376Sdg * restored to the starting address if the remote DMA is aborted. 1386Sdg * 1396Sdg * RD2 RD1 RD0 function 1406Sdg * 0 0 0 not allowed 1416Sdg * 0 0 1 remote read 1426Sdg * 0 1 0 remote write 1436Sdg * 0 1 1 send packet 1446Sdg * 1 X X abort 1456Sdg */ 1466Sdg#define ED_CR_RD0 0x08 1476Sdg#define ED_CR_RD1 0x10 1486Sdg#define ED_CR_RD2 0x20 1496Sdg 1506Sdg/* 1516Sdg * PS0, PS1: Page Select. The two bits select which register set or 'page' to 1526Sdg * access. 1536Sdg * 1546Sdg * PS1 PS0 page 1556Sdg * 0 0 0 1566Sdg * 0 1 1 1576Sdg * 1 0 2 1586Sdg * 1 1 reserved 1596Sdg */ 1606Sdg#define ED_CR_PS0 0x40 1616Sdg#define ED_CR_PS1 0x80 1626Sdg/* bit encoded aliases */ 1636Sdg#define ED_CR_PAGE_0 0x00 /* (for consistency) */ 1646Sdg#define ED_CR_PAGE_1 0x40 1656Sdg#define ED_CR_PAGE_2 0x80 1666Sdg 1676Sdg/* 1686Sdg * Interrupt Status Register (ISR) definitions 1696Sdg */ 1706Sdg 1716Sdg/* 1726Sdg * PRX: Packet Received. Indicates packet received with no errors. 1736Sdg */ 1746Sdg#define ED_ISR_PRX 0x01 1756Sdg 1766Sdg/* 1776Sdg * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 1786Sdg */ 1796Sdg#define ED_ISR_PTX 0x02 1806Sdg 1816Sdg/* 1826Sdg * RXE: Receive Error. Indicates that a packet was received with one or more 1836Sdg * the following errors: CRC error, frame alignment error, FIFO overrun, 1846Sdg * missed packet. 1856Sdg */ 1866Sdg#define ED_ISR_RXE 0x04 1876Sdg 1886Sdg/* 1896Sdg * TXE: Transmission Error. Indicates that an attempt to transmit a packet 1906Sdg * resulted in one or more of the following errors: excessive 1916Sdg * collisions, FIFO underrun. 1926Sdg */ 1936Sdg#define ED_ISR_TXE 0x08 1946Sdg 1956Sdg/* 1966Sdg * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 1976Sdg * would exceed (has exceeded?) the boundry pointer, resulting in data 1986Sdg * that was previously received and not yet read from the buffer to be 1996Sdg * overwritten. 2006Sdg */ 2016Sdg#define ED_ISR_OVW 0x10 2026Sdg 2036Sdg/* 2046Sdg * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley 2056Sdg * Counters has been set. 2066Sdg */ 2076Sdg#define ED_ISR_CNT 0x20 2086Sdg 2096Sdg/* 2106Sdg * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. 2116Sdg */ 2126Sdg#define ED_ISR_RDC 0x40 2136Sdg 2146Sdg/* 2156Sdg * RST: Reset status. Set when the NIC enters the reset state and cleared when a 2166Sdg * Start Command is issued to the CR. This bit is also set when a receive 2176Sdg * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 2186Sdg * packets have been removed from the ring. This is a read-only bit. 2196Sdg */ 2206Sdg#define ED_ISR_RST 0x80 2216Sdg 2226Sdg/* 2236Sdg * Interrupt Mask Register (IMR) definitions 2246Sdg */ 2256Sdg 2266Sdg/* 2276Sdg * PRXE: Packet Received interrupt Enable. If set, a received packet will cause 2286Sdg * an interrupt. 2296Sdg */ 2306Sdg#define ED_IMR_PRXE 0x01 2316Sdg 2326Sdg/* 2336Sdg * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when 2346Sdg * a packet transmission completes. 2356Sdg */ 2366Sdg#define ED_IMR_PTXE 0x02 2376Sdg 2386Sdg/* 2396Sdg * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a 2406Sdg * packet is received with an error. 2416Sdg */ 2426Sdg#define ED_IMR_RXEE 0x04 2436Sdg 2446Sdg/* 2456Sdg * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever 2466Sdg * a transmission results in an error. 2476Sdg */ 2486Sdg#define ED_IMR_TXEE 0x08 2496Sdg 2506Sdg/* 2516Sdg * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever 2526Sdg * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded. 2536Sdg */ 2546Sdg#define ED_IMR_OVWE 0x10 2556Sdg 2566Sdg/* 2576Sdg * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever 2586Sdg * the MSB of one or more of the Network Statistics counters has been set. 2596Sdg */ 2606Sdg#define ED_IMR_CNTE 0x20 2616Sdg 2626Sdg/* 2636Sdg * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated 2646Sdg * when a remote DMA transfer has completed. 2656Sdg */ 2666Sdg#define ED_IMR_RDCE 0x40 2676Sdg 2686Sdg/* 2696Sdg * bit 7 is unused/reserved 2706Sdg */ 2716Sdg 2726Sdg/* 2736Sdg * Data Configuration Register (DCR) definitions 2746Sdg */ 2756Sdg 2766Sdg/* 2776Sdg * WTS: Word Transfer Select. WTS establishes byte or word transfers for 2786Sdg * both remote and local DMA transfers 2796Sdg */ 2806Sdg#define ED_DCR_WTS 0x01 2816Sdg 2826Sdg/* 2836Sdg * BOS: Byte Order Select. BOS sets the byte order for the host. 2846Sdg * Should be 0 for 80x86, and 1 for 68000 series processors 2856Sdg */ 2866Sdg#define ED_DCR_BOS 0x02 2876Sdg 2886Sdg/* 2896Sdg * LAS: Long Address Select. When LAS is 1, the contents of the remote 2906Sdg * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 2916Sdg */ 2926Sdg#define ED_DCR_LAS 0x04 2936Sdg 2946Sdg/* 2956Sdg * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 2966Sdg * of the TCR must also be programmed for loopback operation. 2976Sdg * When 1, normal operation is selected. 2986Sdg */ 2996Sdg#define ED_DCR_LS 0x08 3006Sdg 3016Sdg/* 3026Sdg * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 3036Sdg * under program control. When 1, remote DMA is automatically initiated 3046Sdg * and the boundry pointer is automatically updated 3056Sdg */ 3066Sdg#define ED_DCR_AR 0x10 3076Sdg 3086Sdg/* 3096Sdg * FT0, FT1: Fifo Threshold select. 3106Sdg * FT1 FT0 Word-width Byte-width 3116Sdg * 0 0 1 word 2 bytes 3126Sdg * 0 1 2 words 4 bytes 3136Sdg * 1 0 4 words 8 bytes 3146Sdg * 1 1 8 words 12 bytes 3156Sdg * 3166Sdg * During transmission, the FIFO threshold indicates the number of bytes 3176Sdg * or words that the FIFO has filled from the local DMA before BREQ is 3186Sdg * asserted. The transmission threshold is 16 bytes minus the receiver 3196Sdg * threshold. 3206Sdg */ 3216Sdg#define ED_DCR_FT0 0x20 3226Sdg#define ED_DCR_FT1 0x40 3236Sdg 3246Sdg/* 3256Sdg * bit 7 (0x80) is unused/reserved 3266Sdg */ 3276Sdg 3286Sdg/* 3296Sdg * Transmit Configuration Register (TCR) definitions 3306Sdg */ 3316Sdg 3326Sdg/* 3336Sdg * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 3346Sdg * is not appended by the transmitter. 3356Sdg */ 3366Sdg#define ED_TCR_CRC 0x01 3376Sdg 3386Sdg/* 3396Sdg * LB0, LB1: Loopback control. These two bits set the type of loopback that is 3406Sdg * to be performed. 3416Sdg * 3426Sdg * LB1 LB0 mode 3436Sdg * 0 0 0 - normal operation (DCR_LS = 0) 3446Sdg * 0 1 1 - internal loopback (DCR_LS = 0) 3456Sdg * 1 0 2 - external loopback (DCR_LS = 1) 3466Sdg * 1 1 3 - external loopback (DCR_LS = 0) 3476Sdg */ 3486Sdg#define ED_TCR_LB0 0x02 3496Sdg#define ED_TCR_LB1 0x04 3506Sdg 3516Sdg/* 3526Sdg * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 3536Sdg * another station to disable the NIC's transmitter by transmitting to 3546Sdg * a multicast address hashing to bit 62. Reception of a multicast address 3556Sdg * hashing to bit 63 enables the transmitter. 3566Sdg */ 3576Sdg#define ED_TCR_ATD 0x08 3586Sdg 3596Sdg/* 3606Sdg * OFST: Collision Offset enable. This bit when set modifies the backoff 3616Sdg * algorithm to allow prioritization of nodes. 3626Sdg */ 3636Sdg#define ED_TCR_OFST 0x10 3646Sdg 3656Sdg/* 3666Sdg * bits 5, 6, and 7 are unused/reserved 3676Sdg */ 3686Sdg 3696Sdg/* 3706Sdg * Transmit Status Register (TSR) definitions 3716Sdg */ 3726Sdg 3736Sdg/* 3746Sdg * PTX: Packet Transmitted. Indicates successful transmission of packet. 3756Sdg */ 3766Sdg#define ED_TSR_PTX 0x01 3776Sdg 3786Sdg/* 3796Sdg * bit 1 (0x02) is unused/reserved 3806Sdg */ 3816Sdg 3826Sdg/* 3836Sdg * COL: Transmit Collided. Indicates that the transmission collided at least 3846Sdg * once with another station on the network. 3856Sdg */ 3866Sdg#define ED_TSR_COL 0x04 3876Sdg 3886Sdg/* 3896Sdg * ABT: Transmit aborted. Indicates that the transmission was aborted due to 3906Sdg * excessive collisions. 3916Sdg */ 3926Sdg#define ED_TSR_ABT 0x08 3936Sdg 3946Sdg/* 3956Sdg * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 3966Sdg * transmission of the packet. (Transmission is not aborted because 3976Sdg * of a loss of carrier) 3986Sdg */ 3996Sdg#define ED_TSR_CRS 0x10 4006Sdg 4016Sdg/* 4026Sdg * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 4036Sdg * transmission memory before the FIFO emptied. Transmission of the 4046Sdg * packet was aborted. 4056Sdg */ 4066Sdg#define ED_TSR_FU 0x20 4076Sdg 4086Sdg/* 4096Sdg * CDH: CD Heartbeat. Indicates that the collision detection circuitry 4106Sdg * isn't working correctly during a collision heartbeat test. 4116Sdg */ 4126Sdg#define ED_TSR_CDH 0x40 4136Sdg 4146Sdg/* 4156Sdg * OWC: Out of Window Collision: Indicates that a collision occurred after 4166Sdg * a slot time (51.2us). The transmission is rescheduled just as in 4176Sdg * normal collisions. 4186Sdg */ 4196Sdg#define ED_TSR_OWC 0x80 4206Sdg 4216Sdg/* 4226Sdg * Receiver Configuration Register (RCR) definitions 4236Sdg */ 4246Sdg 4256Sdg/* 4266Sdg * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 4276Sdg * packets with CRC and frame errors are not discarded. 4286Sdg */ 4296Sdg#define ED_RCR_SEP 0x01 4306Sdg 4316Sdg/* 4326Sdg * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 4336Sdg * If set to 1, packets with less than 64 byte are not discarded. 4346Sdg */ 4356Sdg#define ED_RCR_AR 0x02 4366Sdg 4376Sdg/* 4386Sdg * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 4396Sdg * accepted. 4406Sdg */ 4416Sdg#define ED_RCR_AB 0x04 4426Sdg 4436Sdg/* 4446Sdg * AM: Accept Multicast. If set, packets sent to a multicast address are checked 4456Sdg * for a match in the hashing array. If clear, multicast packets are ignored. 4466Sdg */ 4476Sdg#define ED_RCR_AM 0x08 4486Sdg 4496Sdg/* 4506Sdg * PRO: Promiscuous Physical. If set, all packets with a physical addresses are 4516Sdg * accepted. If clear, a physical destination address must match this 4526Sdg * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM 4536Sdg * must also be set. In addition, the multicast hashing array must be set 4546Sdg * to all 1's so that all multicast addresses are accepted. 4556Sdg */ 4566Sdg#define ED_RCR_PRO 0x10 4576Sdg 4586Sdg/* 4596Sdg * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, 4606Sdg * but are not stored in the ring-buffer. If clear, packets are stored (normal 4616Sdg * operation). 4626Sdg */ 4636Sdg#define ED_RCR_MON 0x20 4646Sdg 4656Sdg/* 4666Sdg * bits 6 and 7 are unused/reserved. 4676Sdg */ 4686Sdg 4696Sdg/* 4706Sdg * Receiver Status Register (RSR) definitions 4716Sdg */ 4726Sdg 4736Sdg/* 4746Sdg * PRX: Packet Received without error. 4756Sdg */ 4766Sdg#define ED_RSR_PRX 0x01 4776Sdg 4786Sdg/* 4796Sdg * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame 4806Sdg * alignment errors. 4816Sdg */ 4826Sdg#define ED_RSR_CRC 0x02 4836Sdg 4846Sdg/* 4856Sdg * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on 4866Sdg * a byte boundry and the CRC did not match at the last byte boundry. 4876Sdg */ 4886Sdg#define ED_RSR_FAE 0x04 4896Sdg 4906Sdg/* 4916Sdg * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) 4926Sdg * causing it to overrun. Reception of the packet is aborted. 4936Sdg */ 4946Sdg#define ED_RSR_FO 0x08 4956Sdg 4966Sdg/* 4976Sdg * MPA: Missed Packet. Indicates that the received packet couldn't be stored in 4986Sdg * the ring-buffer because of insufficient buffer space (exceeding the 4996Sdg * boundry pointer), or because the transfer to the ring-buffer was inhibited 5006Sdg * by RCR_MON - monitor mode. 5016Sdg */ 5026Sdg#define ED_RSR_MPA 0x10 5036Sdg 5046Sdg/* 5056Sdg * PHY: Physical address. If 0, the packet received was sent to a physical address. 5066Sdg * If 1, the packet was accepted because of a multicast/broadcast address 5076Sdg * match. 5086Sdg */ 5096Sdg#define ED_RSR_PHY 0x20 5106Sdg 5116Sdg/* 5126Sdg * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor 5136Sdg * mode. Cleared when the receiver exits monitor mode. 5146Sdg */ 5156Sdg#define ED_RSR_DIS 0x40 5166Sdg 5176Sdg/* 5186Sdg * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs 5196Sdg * are active, and the transceiver has set the CD line as a result of the 5206Sdg * jabber. 5216Sdg */ 5226Sdg#define ED_RSR_DFR 0x80 5236Sdg 5246Sdg/* 5256Sdg * receive ring discriptor 5266Sdg * 5276Sdg * The National Semiconductor DS8390 Network interface controller uses 5286Sdg * the following receive ring headers. The way this works is that the 5296Sdg * memory on the interface card is chopped up into 256 bytes blocks. 5306Sdg * A contiguous portion of those blocks are marked for receive packets 5316Sdg * by setting start and end block #'s in the NIC. For each packet that 5326Sdg * is put into the receive ring, one of these headers (4 bytes each) is 5336Sdg * tacked onto the front. 5346Sdg */ 5356Sdgstruct ed_ring { 5366Sdg struct edr_status { /* received packet status */ 5376Sdg u_char rs_prx:1, /* packet received intack */ 5386Sdg rs_crc:1, /* crc error */ 5396Sdg rs_fae:1, /* frame alignment error */ 5406Sdg rs_fo:1, /* fifo overrun */ 5416Sdg rs_mpa:1, /* packet received intack */ 5426Sdg rs_phy:1, /* packet received intack */ 5436Sdg rs_dis:1, /* packet received intack */ 5446Sdg rs_dfr:1; /* packet received intack */ 5456Sdg } ed_rcv_status; /* received packet status */ 5466Sdg u_char next_packet; /* pointer to next packet */ 5476Sdg u_short count; /* bytes in packet (length + 4) */ 5486Sdg}; 5496Sdg 5506Sdg/* 5516Sdg * Common constants 5526Sdg */ 5536Sdg#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 5546Sdg#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 5556Sdg 5566Sdg/* 5576Sdg * Vendor types 5586Sdg */ 5596Sdg#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 5606Sdg#define ED_VENDOR_3COM 0x01 /* 3Com */ 5616Sdg 5626Sdg/* 56342Sdg * Compile-time config flags 56442Sdg */ 56542Sdg/* 56642Sdg * this sets the default for enabling/disablng the tranceiver 56742Sdg */ 568172Sdg#define ED_FLAGS_DISABLE_TRANCEIVER 0x01 56942Sdg 57042Sdg/* 571172Sdg * This forces the board to be used in 8/16bit mode even if it 572172Sdg * autoconfigs differently 573172Sdg */ 574172Sdg#define ED_FLAGS_FORCE_8BIT_MODE 0x02 575172Sdg#define ED_FLAGS_FORCE_16BIT_MODE 0x04 576172Sdg 577172Sdg/* 578172Sdg * This disables the use of double transmit buffers. 579172Sdg */ 580172Sdg#define ED_FLAGS_NO_DOUBLE_BUFFERING 0x08 581172Sdg 582172Sdg/* 5836Sdg * Definitions for Western digital/SMC WD80x3 series ASIC 5846Sdg */ 5856Sdg/* 5866Sdg * Memory Select Register (MSR) 5876Sdg */ 5886Sdg#define ED_WD_MSR 0 5896Sdg 5906Sdg#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 5916Sdg#define ED_WD_MSR_MENB 0x40 /* Memory enable */ 5926Sdg#define ED_WD_MSR_RST 0x80 /* Reset board */ 5936Sdg 5946Sdg/* 5956Sdg * Interface Configuration Register (ICR) 5966Sdg */ 5976Sdg#define ED_WD_ICR 1 5986Sdg 5996Sdg#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ 6006Sdg#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */ 60143Sdg#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 6026Sdg#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 6036Sdg#define ED_WD_ICR_RLA 0x10 /* recall LAN address */ 6046Sdg#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 6056Sdg#define ED_WD_ICR_RIO 0x40 /* recall i/o address */ 6066Sdg#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ 6076Sdg 6086Sdg/* 60943Sdg * IO Address Register (IAR) 61043Sdg */ 61143Sdg#define ED_WD_IAR 2 61243Sdg 61343Sdg/* 61443Sdg * EEROM Address Register 61543Sdg */ 61643Sdg#define ED_WD_EAR 3 61743Sdg 61843Sdg/* 6196Sdg * Interrupt Request Register (IRR) 6206Sdg */ 6216Sdg#define ED_WD_IRR 4 6226Sdg 6236Sdg#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 6246Sdg#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 6256Sdg#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 6266Sdg#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 6276Sdg#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 62843Sdg 62943Sdg/* 63043Sdg * The three bit of the encoded IRQ are decoded as follows: 63143Sdg * 63243Sdg * IR2 IR1 IR0 IRQ 63343Sdg * 0 0 0 2/9 63443Sdg * 0 0 1 3 63543Sdg * 0 1 0 5 63643Sdg * 0 1 1 7 63743Sdg * 1 0 0 10 63843Sdg * 1 0 1 11 63943Sdg * 1 1 0 15 64043Sdg * 1 1 1 4 64143Sdg */ 64243Sdg#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 64343Sdg#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 6446Sdg#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ 6456Sdg 6466Sdg/* 6476Sdg * LA Address Register (LAAR) 6486Sdg */ 6496Sdg#define ED_WD_LAAR 5 6506Sdg 6516Sdg#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 6526Sdg#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 6536Sdg#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ 6546Sdg#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 6556Sdg 6566Sdg/* i/o base offset to station address/card-ID PROM */ 6576Sdg#define ED_WD_PROM 8 6586Sdg 6596Sdg/* i/o base offset to CARD ID */ 6606Sdg#define ED_WD_CARD_ID ED_WD_PROM+6 6616Sdg 6626Sdg#define ED_TYPE_WD8003S 0x02 6636Sdg#define ED_TYPE_WD8003E 0x03 6646Sdg#define ED_TYPE_WD8013EBT 0x05 6656Sdg#define ED_TYPE_WD8013EB 0x27 6666Sdg#define ED_TYPE_WD8013EBP 0x2c 6676Sdg#define ED_TYPE_WD8013EPC 0x29 6686Sdg 6696Sdg/* Bit definitions in card ID */ 6706Sdg#define ED_WD_REV_MASK 0x1f /* Revision mask */ 6716Sdg#define ED_WD_SOFTCONFIG 0x20 /* Soft config */ 6726Sdg#define ED_WD_LARGERAM 0x40 /* Large RAM */ 6736Sdg#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 6746Sdg 6756Sdg/* 6766Sdg * Checksum total. All 8 bytes in station address PROM will add up to this 6776Sdg */ 6786Sdg#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF 6796Sdg 6806Sdg#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 6816Sdg#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 6826Sdg#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ 6836Sdg 6846Sdg#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 6856Sdg 6866Sdg/* 6876Sdg * Definitions for 3Com 3c503 6886Sdg */ 6896Sdg#define ED_3COM_NIC_OFFSET 0 6906Sdg#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 6916Sdg 6926Sdg/* 6936Sdg * XXX - The I/O address range is fragmented in the 3c503; this is the 6946Sdg * number of regs at iobase. 6956Sdg */ 6966Sdg#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ 6976Sdg 6986Sdg#define ED_3COM_PAGE_OFFSET 0x20 /* memory starts in second bank */ 6996Sdg 7006Sdg/* 7016Sdg * Page Start Register. Must match PSTART in NIC 7026Sdg */ 7036Sdg#define ED_3COM_PSTR 0 7046Sdg 7056Sdg/* 7066Sdg * Page Stop Register. Must match PSTOP in NIC 7076Sdg */ 7086Sdg#define ED_3COM_PSPR 1 7096Sdg 7106Sdg/* 7116Sdg * Drq Timer Register. Determines number of bytes to be transfered during 7126Sdg * a DMA burst. 7136Sdg */ 7146Sdg#define ED_3COM_DQTR 2 7156Sdg 7166Sdg/* 7176Sdg * Base Configuration Register. Read-only register which contains the 7186Sdg * board-configured I/O base address of the adapter. Bit encoded. 7196Sdg */ 7206Sdg#define ED_3COM_BCFR 3 7216Sdg 7226Sdg#define ED_3COM_BCFR_2E0 0x01 7236Sdg#define ED_3COM_BCFR_2A0 0x02 7246Sdg#define ED_3COM_BCFR_280 0x04 7256Sdg#define ED_3COM_BCFR_250 0x08 7266Sdg#define ED_3COM_BCFR_350 0x10 7276Sdg#define ED_3COM_BCFR_330 0x20 7286Sdg#define ED_3COM_BCFR_310 0x40 7296Sdg#define ED_3COM_BCFR_300 0x80 7306Sdg 7316Sdg/* 7326Sdg * EPROM Configuration Register. Read-only register which contains the 7336Sdg * board-configured memory base address. Bit encoded. 7346Sdg */ 7356Sdg#define ED_3COM_PCFR 4 7366Sdg 7376Sdg#define ED_3COM_PCFR_C8000 0x10 7386Sdg#define ED_3COM_PCFR_CC000 0x20 7396Sdg#define ED_3COM_PCFR_D8000 0x40 7406Sdg#define ED_3COM_PCFR_DC000 0x80 7416Sdg 7426Sdg/* 7436Sdg * GA Configuration Register. Gate-Array Configuration Register. 7446Sdg */ 7456Sdg#define ED_3COM_GACFR 5 7466Sdg 7476Sdg/* 7486Sdg * mbs2 mbs1 mbs0 start address 7496Sdg * 0 0 0 0x0000 7506Sdg * 0 0 1 0x2000 7516Sdg * 0 1 0 0x4000 7526Sdg * 0 1 1 0x6000 7536Sdg * 7546Sdg * Note that with adapters with only 8K, the setting for 0x2000 must 7556Sdg * always be used. 7566Sdg */ 7576Sdg#define ED_3COM_GACFR_MBS0 0x01 7586Sdg#define ED_3COM_GACFR_MBS1 0x02 7596Sdg#define ED_3COM_GACFR_MBS2 0x04 7606Sdg 7616Sdg#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ 7626Sdg#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ 7636Sdg#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 7646Sdg#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 7656Sdg#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 7666Sdg 7676Sdg/* 7686Sdg * Control Register. Miscellaneous control functions. 7696Sdg */ 7706Sdg#define ED_3COM_CR 6 7716Sdg 7726Sdg#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ 7736Sdg#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 7746Sdg#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 7756Sdg#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 7766Sdg#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 7776Sdg#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ 7786Sdg#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ 7796Sdg#define ED_3COM_CR_START 0x80 /* Start DMA controller */ 7806Sdg 7816Sdg/* 7826Sdg * Status Register. Miscellaneous status information. 7836Sdg */ 7846Sdg#define ED_3COM_STREG 7 7856Sdg 7866Sdg#define ED_3COM_STREG_REV 0x07 /* GA revision */ 7876Sdg#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ 7886Sdg#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ 7896Sdg#define ED_3COM_STREG_OFLW 0x20 /* Overflow */ 7906Sdg#define ED_3COM_STREG_UFLW 0x40 /* Underflow */ 7916Sdg#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ 7926Sdg 7936Sdg/* 7946Sdg * Interrupt/DMA Configuration Register 7956Sdg */ 7966Sdg#define ED_3COM_IDCFR 8 7976Sdg 7986Sdg#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ 7996Sdg#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ 8006Sdg#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ 8016Sdg#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ 8026Sdg#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 8036Sdg#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 8046Sdg#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 8056Sdg#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 8066Sdg 8076Sdg/* 8086Sdg * DMA Address Register MSB 8096Sdg */ 8106Sdg#define ED_3COM_DAMSB 9 8116Sdg 8126Sdg/* 8136Sdg * DMA Address Register LSB 8146Sdg */ 8156Sdg#define ED_3COM_DALSB 0x0a 8166Sdg 8176Sdg/* 8186Sdg * Vector Pointer Register 2 8196Sdg */ 8206Sdg#define ED_3COM_VPTR2 0x0b 8216Sdg 8226Sdg/* 8236Sdg * Vector Pointer Register 1 8246Sdg */ 8256Sdg#define ED_3COM_VPTR1 0x0c 8266Sdg 8276Sdg/* 8286Sdg * Vector Pointer Register 0 8296Sdg */ 8306Sdg#define ED_3COM_VPTR0 0x0d 8316Sdg 8326Sdg/* 8336Sdg * Register File Access MSB 8346Sdg */ 8356Sdg#define ED_3COM_RFMSB 0x0e 8366Sdg 8376Sdg/* 8386Sdg * Register File Access LSB 8396Sdg */ 8406Sdg#define ED_3COM_RFLSB 0x0f 841