if_edreg.h revision 1073
16Sdg/* 26Sdg * National Semiconductor DS8390 NIC register definitions 343Sdg * 41073Sdg * $Id: if_edreg.h,v 1.11 1994/01/25 22:52:09 ats Exp $ 5498Sdg * 6498Sdg * Modification history 7498Sdg * 8808Sdg * Revision 2.2 1993/11/29 16:33:39 davidg 9808Sdg * From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk> 10808Sdg * Add support for the 8013W board type 11808Sdg * 12791Sdg * Revision 2.1 1993/11/22 10:52:33 davidg 13791Sdg * patch to add support for SMC8216 (Elite-Ultra) boards 14791Sdg * from Glen H. Lowe 15791Sdg * 16520Sdg * Revision 2.0 93/09/29 00:37:15 davidg 17520Sdg * changed double buffering flag to multi buffering 18520Sdg * made changes/additions for 3c503 multi-buffering 19520Sdg * ...companion to Rev. 2.0 of 'ed' driver. 20520Sdg * 2143Sdg * Revision 1.1 93/06/23 03:01:07 davidg 2243Sdg * Initial revision 2343Sdg * 246Sdg */ 256Sdg 266Sdg/* 276Sdg * Page 0 register offsets 286Sdg */ 296Sdg#define ED_P0_CR 0x00 /* Command Register */ 306Sdg 316Sdg#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 326Sdg#define ED_P0_PSTART 0x01 /* Page Start register (write) */ 336Sdg 346Sdg#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 356Sdg#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 366Sdg 376Sdg#define ED_P0_BNRY 0x03 /* Boundary Pointer */ 386Sdg 396Sdg#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 406Sdg#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 416Sdg 426Sdg#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 436Sdg#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 446Sdg 456Sdg#define ED_P0_FIFO 0x06 /* FIFO register (read) */ 466Sdg#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 476Sdg 486Sdg#define ED_P0_ISR 0x07 /* Interrupt Status Register */ 496Sdg 506Sdg#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 516Sdg#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 526Sdg 536Sdg#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 546Sdg#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 556Sdg 566Sdg#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 576Sdg 586Sdg#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 596Sdg 606Sdg#define ED_P0_RSR 0x0c /* Receive Status (read) */ 616Sdg#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 626Sdg 636Sdg#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 646Sdg#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 656Sdg 666Sdg#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 676Sdg#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 686Sdg 696Sdg#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 706Sdg#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 716Sdg 726Sdg/* 736Sdg * Page 1 register offsets 746Sdg */ 756Sdg#define ED_P1_CR 0x00 /* Command Register */ 766Sdg#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 776Sdg#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 786Sdg#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 796Sdg#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 806Sdg#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 816Sdg#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 826Sdg#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 836Sdg#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 846Sdg#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 856Sdg#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 866Sdg#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 876Sdg#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 886Sdg#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 896Sdg#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 906Sdg#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 916Sdg 926Sdg/* 936Sdg * Page 2 register offsets 946Sdg */ 956Sdg#define ED_P2_CR 0x00 /* Command Register */ 966Sdg#define ED_P2_PSTART 0x01 /* Page Start (read) */ 976Sdg#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 986Sdg#define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 996Sdg#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 1006Sdg#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 1016Sdg#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 1026Sdg#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 1036Sdg#define ED_P2_ACU 0x06 /* Address Counter Upper */ 1046Sdg#define ED_P2_ACL 0x07 /* Address Counter Lower */ 1056Sdg#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 1066Sdg#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 1076Sdg#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 1086Sdg#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 1096Sdg 1106Sdg/* 1116Sdg * Command Register (CR) definitions 1126Sdg */ 1136Sdg 1146Sdg/* 1156Sdg * STP: SToP. Software reset command. Takes the controller offline. No 1166Sdg * packets will be received or transmitted. Any reception or 1176Sdg * transmission in progress will continue to completion before 1186Sdg * entering reset state. To exit this state, the STP bit must 1196Sdg * reset and the STA bit must be set. The software reset has 1206Sdg * executed only when indicated by the RST bit in the ISR being 1216Sdg * set. 1226Sdg */ 1236Sdg#define ED_CR_STP 0x01 1246Sdg 1256Sdg/* 1266Sdg * STA: STArt. This bit is used to activate the NIC after either power-up, 1276Sdg * or when the NIC has been put in reset mode by software command 1286Sdg * or error. 1296Sdg */ 1306Sdg#define ED_CR_STA 0x02 1316Sdg 1326Sdg/* 1336Sdg * TXP: Transmit Packet. This bit must be set to indicate transmission of 1346Sdg * a packet. TXP is internally reset either after the transmission is 1356Sdg * completed or aborted. This bit should be set only after the Transmit 1366Sdg * Byte Count and Transmit Page Start register have been programmed. 1376Sdg */ 1386Sdg#define ED_CR_TXP 0x04 1396Sdg 1406Sdg/* 1416Sdg * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 1426Sdg * of the remote DMA channel. RD2 can be set to abort any remote DMA 1436Sdg * command in progress. The Remote Byte Count registers should be cleared 1446Sdg * when a remote DMA has been aborted. The Remote Start Addresses are not 1456Sdg * restored to the starting address if the remote DMA is aborted. 1466Sdg * 1476Sdg * RD2 RD1 RD0 function 1486Sdg * 0 0 0 not allowed 1496Sdg * 0 0 1 remote read 1506Sdg * 0 1 0 remote write 1516Sdg * 0 1 1 send packet 1526Sdg * 1 X X abort 1536Sdg */ 1546Sdg#define ED_CR_RD0 0x08 1556Sdg#define ED_CR_RD1 0x10 1566Sdg#define ED_CR_RD2 0x20 1576Sdg 1586Sdg/* 1596Sdg * PS0, PS1: Page Select. The two bits select which register set or 'page' to 1606Sdg * access. 1616Sdg * 1626Sdg * PS1 PS0 page 1636Sdg * 0 0 0 1646Sdg * 0 1 1 1656Sdg * 1 0 2 1666Sdg * 1 1 reserved 1676Sdg */ 1686Sdg#define ED_CR_PS0 0x40 1696Sdg#define ED_CR_PS1 0x80 1706Sdg/* bit encoded aliases */ 1716Sdg#define ED_CR_PAGE_0 0x00 /* (for consistency) */ 1726Sdg#define ED_CR_PAGE_1 0x40 1736Sdg#define ED_CR_PAGE_2 0x80 1746Sdg 1756Sdg/* 1766Sdg * Interrupt Status Register (ISR) definitions 1776Sdg */ 1786Sdg 1796Sdg/* 1806Sdg * PRX: Packet Received. Indicates packet received with no errors. 1816Sdg */ 1826Sdg#define ED_ISR_PRX 0x01 1836Sdg 1846Sdg/* 1856Sdg * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 1866Sdg */ 1876Sdg#define ED_ISR_PTX 0x02 1886Sdg 1896Sdg/* 1906Sdg * RXE: Receive Error. Indicates that a packet was received with one or more 1916Sdg * the following errors: CRC error, frame alignment error, FIFO overrun, 1926Sdg * missed packet. 1936Sdg */ 1946Sdg#define ED_ISR_RXE 0x04 1956Sdg 1966Sdg/* 1976Sdg * TXE: Transmission Error. Indicates that an attempt to transmit a packet 1986Sdg * resulted in one or more of the following errors: excessive 1996Sdg * collisions, FIFO underrun. 2006Sdg */ 2016Sdg#define ED_ISR_TXE 0x08 2026Sdg 2036Sdg/* 2046Sdg * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 2056Sdg * would exceed (has exceeded?) the boundry pointer, resulting in data 2066Sdg * that was previously received and not yet read from the buffer to be 2076Sdg * overwritten. 2086Sdg */ 2096Sdg#define ED_ISR_OVW 0x10 2106Sdg 2116Sdg/* 2126Sdg * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley 2136Sdg * Counters has been set. 2146Sdg */ 2156Sdg#define ED_ISR_CNT 0x20 2166Sdg 2176Sdg/* 2186Sdg * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. 2196Sdg */ 2206Sdg#define ED_ISR_RDC 0x40 2216Sdg 2226Sdg/* 2236Sdg * RST: Reset status. Set when the NIC enters the reset state and cleared when a 2246Sdg * Start Command is issued to the CR. This bit is also set when a receive 2256Sdg * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 2266Sdg * packets have been removed from the ring. This is a read-only bit. 2276Sdg */ 2286Sdg#define ED_ISR_RST 0x80 2296Sdg 2306Sdg/* 2316Sdg * Interrupt Mask Register (IMR) definitions 2326Sdg */ 2336Sdg 2346Sdg/* 2356Sdg * PRXE: Packet Received interrupt Enable. If set, a received packet will cause 2366Sdg * an interrupt. 2376Sdg */ 2386Sdg#define ED_IMR_PRXE 0x01 2396Sdg 2406Sdg/* 2416Sdg * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when 2426Sdg * a packet transmission completes. 2436Sdg */ 2446Sdg#define ED_IMR_PTXE 0x02 2456Sdg 2466Sdg/* 2476Sdg * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a 2486Sdg * packet is received with an error. 2496Sdg */ 2506Sdg#define ED_IMR_RXEE 0x04 2516Sdg 2526Sdg/* 2536Sdg * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever 2546Sdg * a transmission results in an error. 2556Sdg */ 2566Sdg#define ED_IMR_TXEE 0x08 2576Sdg 2586Sdg/* 2596Sdg * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever 2606Sdg * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded. 2616Sdg */ 2626Sdg#define ED_IMR_OVWE 0x10 2636Sdg 2646Sdg/* 2656Sdg * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever 2666Sdg * the MSB of one or more of the Network Statistics counters has been set. 2676Sdg */ 2686Sdg#define ED_IMR_CNTE 0x20 2696Sdg 2706Sdg/* 2716Sdg * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated 2726Sdg * when a remote DMA transfer has completed. 2736Sdg */ 2746Sdg#define ED_IMR_RDCE 0x40 2756Sdg 2766Sdg/* 2776Sdg * bit 7 is unused/reserved 2786Sdg */ 2796Sdg 2806Sdg/* 2816Sdg * Data Configuration Register (DCR) definitions 2826Sdg */ 2836Sdg 2846Sdg/* 2856Sdg * WTS: Word Transfer Select. WTS establishes byte or word transfers for 2866Sdg * both remote and local DMA transfers 2876Sdg */ 2886Sdg#define ED_DCR_WTS 0x01 2896Sdg 2906Sdg/* 2916Sdg * BOS: Byte Order Select. BOS sets the byte order for the host. 2926Sdg * Should be 0 for 80x86, and 1 for 68000 series processors 2936Sdg */ 2946Sdg#define ED_DCR_BOS 0x02 2956Sdg 2966Sdg/* 2976Sdg * LAS: Long Address Select. When LAS is 1, the contents of the remote 2986Sdg * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 2996Sdg */ 3006Sdg#define ED_DCR_LAS 0x04 3016Sdg 3026Sdg/* 3036Sdg * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 3046Sdg * of the TCR must also be programmed for loopback operation. 3056Sdg * When 1, normal operation is selected. 3066Sdg */ 3076Sdg#define ED_DCR_LS 0x08 3086Sdg 3096Sdg/* 3106Sdg * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 3116Sdg * under program control. When 1, remote DMA is automatically initiated 3126Sdg * and the boundry pointer is automatically updated 3136Sdg */ 3146Sdg#define ED_DCR_AR 0x10 3156Sdg 3166Sdg/* 3176Sdg * FT0, FT1: Fifo Threshold select. 3186Sdg * FT1 FT0 Word-width Byte-width 3196Sdg * 0 0 1 word 2 bytes 3206Sdg * 0 1 2 words 4 bytes 3216Sdg * 1 0 4 words 8 bytes 3226Sdg * 1 1 8 words 12 bytes 3236Sdg * 3246Sdg * During transmission, the FIFO threshold indicates the number of bytes 3256Sdg * or words that the FIFO has filled from the local DMA before BREQ is 3266Sdg * asserted. The transmission threshold is 16 bytes minus the receiver 3276Sdg * threshold. 3286Sdg */ 3296Sdg#define ED_DCR_FT0 0x20 3306Sdg#define ED_DCR_FT1 0x40 3316Sdg 3326Sdg/* 3336Sdg * bit 7 (0x80) is unused/reserved 3346Sdg */ 3356Sdg 3366Sdg/* 3376Sdg * Transmit Configuration Register (TCR) definitions 3386Sdg */ 3396Sdg 3406Sdg/* 3416Sdg * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 3426Sdg * is not appended by the transmitter. 3436Sdg */ 3446Sdg#define ED_TCR_CRC 0x01 3456Sdg 3466Sdg/* 3476Sdg * LB0, LB1: Loopback control. These two bits set the type of loopback that is 3486Sdg * to be performed. 3496Sdg * 3506Sdg * LB1 LB0 mode 3516Sdg * 0 0 0 - normal operation (DCR_LS = 0) 3526Sdg * 0 1 1 - internal loopback (DCR_LS = 0) 3536Sdg * 1 0 2 - external loopback (DCR_LS = 1) 3546Sdg * 1 1 3 - external loopback (DCR_LS = 0) 3556Sdg */ 3566Sdg#define ED_TCR_LB0 0x02 3576Sdg#define ED_TCR_LB1 0x04 3586Sdg 3596Sdg/* 3606Sdg * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 3616Sdg * another station to disable the NIC's transmitter by transmitting to 3626Sdg * a multicast address hashing to bit 62. Reception of a multicast address 3636Sdg * hashing to bit 63 enables the transmitter. 3646Sdg */ 3656Sdg#define ED_TCR_ATD 0x08 3666Sdg 3676Sdg/* 3686Sdg * OFST: Collision Offset enable. This bit when set modifies the backoff 3696Sdg * algorithm to allow prioritization of nodes. 3706Sdg */ 3716Sdg#define ED_TCR_OFST 0x10 3726Sdg 3736Sdg/* 3746Sdg * bits 5, 6, and 7 are unused/reserved 3756Sdg */ 3766Sdg 3776Sdg/* 3786Sdg * Transmit Status Register (TSR) definitions 3796Sdg */ 3806Sdg 3816Sdg/* 3826Sdg * PTX: Packet Transmitted. Indicates successful transmission of packet. 3836Sdg */ 3846Sdg#define ED_TSR_PTX 0x01 3856Sdg 3866Sdg/* 3876Sdg * bit 1 (0x02) is unused/reserved 3886Sdg */ 3896Sdg 3906Sdg/* 3916Sdg * COL: Transmit Collided. Indicates that the transmission collided at least 3926Sdg * once with another station on the network. 3936Sdg */ 3946Sdg#define ED_TSR_COL 0x04 3956Sdg 3966Sdg/* 3976Sdg * ABT: Transmit aborted. Indicates that the transmission was aborted due to 3986Sdg * excessive collisions. 3996Sdg */ 4006Sdg#define ED_TSR_ABT 0x08 4016Sdg 4026Sdg/* 4036Sdg * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 4046Sdg * transmission of the packet. (Transmission is not aborted because 4056Sdg * of a loss of carrier) 4066Sdg */ 4076Sdg#define ED_TSR_CRS 0x10 4086Sdg 4096Sdg/* 4106Sdg * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 4116Sdg * transmission memory before the FIFO emptied. Transmission of the 4126Sdg * packet was aborted. 4136Sdg */ 4146Sdg#define ED_TSR_FU 0x20 4156Sdg 4166Sdg/* 4176Sdg * CDH: CD Heartbeat. Indicates that the collision detection circuitry 4186Sdg * isn't working correctly during a collision heartbeat test. 4196Sdg */ 4206Sdg#define ED_TSR_CDH 0x40 4216Sdg 4226Sdg/* 4236Sdg * OWC: Out of Window Collision: Indicates that a collision occurred after 4246Sdg * a slot time (51.2us). The transmission is rescheduled just as in 4256Sdg * normal collisions. 4266Sdg */ 4276Sdg#define ED_TSR_OWC 0x80 4286Sdg 4296Sdg/* 4306Sdg * Receiver Configuration Register (RCR) definitions 4316Sdg */ 4326Sdg 4336Sdg/* 4346Sdg * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 4356Sdg * packets with CRC and frame errors are not discarded. 4366Sdg */ 4376Sdg#define ED_RCR_SEP 0x01 4386Sdg 4396Sdg/* 4406Sdg * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 4416Sdg * If set to 1, packets with less than 64 byte are not discarded. 4426Sdg */ 4436Sdg#define ED_RCR_AR 0x02 4446Sdg 4456Sdg/* 4466Sdg * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 4476Sdg * accepted. 4486Sdg */ 4496Sdg#define ED_RCR_AB 0x04 4506Sdg 4516Sdg/* 4526Sdg * AM: Accept Multicast. If set, packets sent to a multicast address are checked 4536Sdg * for a match in the hashing array. If clear, multicast packets are ignored. 4546Sdg */ 4556Sdg#define ED_RCR_AM 0x08 4566Sdg 4576Sdg/* 4586Sdg * PRO: Promiscuous Physical. If set, all packets with a physical addresses are 4596Sdg * accepted. If clear, a physical destination address must match this 4606Sdg * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM 4616Sdg * must also be set. In addition, the multicast hashing array must be set 4626Sdg * to all 1's so that all multicast addresses are accepted. 4636Sdg */ 4646Sdg#define ED_RCR_PRO 0x10 4656Sdg 4666Sdg/* 4676Sdg * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, 4686Sdg * but are not stored in the ring-buffer. If clear, packets are stored (normal 4696Sdg * operation). 4706Sdg */ 4716Sdg#define ED_RCR_MON 0x20 4726Sdg 4736Sdg/* 4746Sdg * bits 6 and 7 are unused/reserved. 4756Sdg */ 4766Sdg 4776Sdg/* 4786Sdg * Receiver Status Register (RSR) definitions 4796Sdg */ 4806Sdg 4816Sdg/* 4826Sdg * PRX: Packet Received without error. 4836Sdg */ 4846Sdg#define ED_RSR_PRX 0x01 4856Sdg 4866Sdg/* 4876Sdg * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame 4886Sdg * alignment errors. 4896Sdg */ 4906Sdg#define ED_RSR_CRC 0x02 4916Sdg 4926Sdg/* 4936Sdg * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on 4946Sdg * a byte boundry and the CRC did not match at the last byte boundry. 4956Sdg */ 4966Sdg#define ED_RSR_FAE 0x04 4976Sdg 4986Sdg/* 4996Sdg * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) 5006Sdg * causing it to overrun. Reception of the packet is aborted. 5016Sdg */ 5026Sdg#define ED_RSR_FO 0x08 5036Sdg 5046Sdg/* 5056Sdg * MPA: Missed Packet. Indicates that the received packet couldn't be stored in 5066Sdg * the ring-buffer because of insufficient buffer space (exceeding the 5076Sdg * boundry pointer), or because the transfer to the ring-buffer was inhibited 5086Sdg * by RCR_MON - monitor mode. 5096Sdg */ 5106Sdg#define ED_RSR_MPA 0x10 5116Sdg 5126Sdg/* 5136Sdg * PHY: Physical address. If 0, the packet received was sent to a physical address. 5146Sdg * If 1, the packet was accepted because of a multicast/broadcast address 5156Sdg * match. 5166Sdg */ 5176Sdg#define ED_RSR_PHY 0x20 5186Sdg 5196Sdg/* 5206Sdg * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor 5216Sdg * mode. Cleared when the receiver exits monitor mode. 5226Sdg */ 5236Sdg#define ED_RSR_DIS 0x40 5246Sdg 5256Sdg/* 5266Sdg * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs 5276Sdg * are active, and the transceiver has set the CD line as a result of the 5286Sdg * jabber. 5296Sdg */ 5306Sdg#define ED_RSR_DFR 0x80 5316Sdg 5326Sdg/* 5336Sdg * receive ring discriptor 5346Sdg * 5356Sdg * The National Semiconductor DS8390 Network interface controller uses 5366Sdg * the following receive ring headers. The way this works is that the 5376Sdg * memory on the interface card is chopped up into 256 bytes blocks. 5386Sdg * A contiguous portion of those blocks are marked for receive packets 5396Sdg * by setting start and end block #'s in the NIC. For each packet that 5406Sdg * is put into the receive ring, one of these headers (4 bytes each) is 5416Sdg * tacked onto the front. 5426Sdg */ 5436Sdgstruct ed_ring { 5446Sdg struct edr_status { /* received packet status */ 5456Sdg u_char rs_prx:1, /* packet received intack */ 5466Sdg rs_crc:1, /* crc error */ 5476Sdg rs_fae:1, /* frame alignment error */ 5486Sdg rs_fo:1, /* fifo overrun */ 5496Sdg rs_mpa:1, /* packet received intack */ 5506Sdg rs_phy:1, /* packet received intack */ 5516Sdg rs_dis:1, /* packet received intack */ 5526Sdg rs_dfr:1; /* packet received intack */ 5536Sdg } ed_rcv_status; /* received packet status */ 5546Sdg u_char next_packet; /* pointer to next packet */ 5556Sdg u_short count; /* bytes in packet (length + 4) */ 5566Sdg}; 5576Sdg 5586Sdg/* 5596Sdg * Common constants 5606Sdg */ 5616Sdg#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 5626Sdg#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 5636Sdg 5646Sdg/* 5656Sdg * Vendor types 5666Sdg */ 5676Sdg#define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 5686Sdg#define ED_VENDOR_3COM 0x01 /* 3Com */ 569520Sdg#define ED_VENDOR_NOVELL 0x02 /* Novell */ 5706Sdg 5716Sdg/* 57242Sdg * Compile-time config flags 57342Sdg */ 57442Sdg/* 57542Sdg * this sets the default for enabling/disablng the tranceiver 57642Sdg */ 577520Sdg#define ED_FLAGS_DISABLE_TRANCEIVER 0x0001 57842Sdg 57942Sdg/* 580172Sdg * This forces the board to be used in 8/16bit mode even if it 581172Sdg * autoconfigs differently 582172Sdg */ 583520Sdg#define ED_FLAGS_FORCE_8BIT_MODE 0x0002 584520Sdg#define ED_FLAGS_FORCE_16BIT_MODE 0x0004 585172Sdg 586172Sdg/* 587172Sdg * This disables the use of double transmit buffers. 588172Sdg */ 589520Sdg#define ED_FLAGS_NO_MULTI_BUFFERING 0x0008 590172Sdg 591172Sdg/* 592520Sdg * This forces all operations with the NIC memory to use Programmed 593520Sdg * I/O (i.e. not via shared memory) 594520Sdg */ 595520Sdg#define ED_FLAGS_FORCE_PIO 0x0010 596520Sdg 597520Sdg/* 5986Sdg * Definitions for Western digital/SMC WD80x3 series ASIC 5996Sdg */ 6006Sdg/* 6016Sdg * Memory Select Register (MSR) 6026Sdg */ 6036Sdg#define ED_WD_MSR 0 6046Sdg 6056Sdg#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 6066Sdg#define ED_WD_MSR_MENB 0x40 /* Memory enable */ 6076Sdg#define ED_WD_MSR_RST 0x80 /* Reset board */ 6081015Sats#ifdef TOSH_ETHER 6091015Sats#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */ 6101015Sats#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */ 6111015Sats#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits, 6121015Sats 1 = 8 bits (R/W) */ 6131015Sats#endif 6146Sdg 6151015Sats 6166Sdg/* 6176Sdg * Interface Configuration Register (ICR) 6186Sdg */ 6196Sdg#define ED_WD_ICR 1 6206Sdg 6216Sdg#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ 6226Sdg#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */ 62343Sdg#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 6246Sdg#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 6256Sdg#define ED_WD_ICR_RLA 0x10 /* recall LAN address */ 6266Sdg#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 6276Sdg#define ED_WD_ICR_RIO 0x40 /* recall i/o address */ 6286Sdg#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ 6291015Sats#ifdef TOSH_ETHER 6301015Sats#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */ 6311015Sats#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K, 6321015Sats 0x02 = 16K, 0x01 = 8K */ 6331015Sats /* 64K can only be used if mem address 6341015Sats above 1Mb */ 6351015Sats /* IAR holds address A23-A16 (R/W) */ 6361015Sats#endif 6376Sdg 6386Sdg/* 63943Sdg * IO Address Register (IAR) 64043Sdg */ 64143Sdg#define ED_WD_IAR 2 64243Sdg 64343Sdg/* 64443Sdg * EEROM Address Register 64543Sdg */ 64643Sdg#define ED_WD_EAR 3 64743Sdg 64843Sdg/* 6496Sdg * Interrupt Request Register (IRR) 6506Sdg */ 6516Sdg#define ED_WD_IRR 4 6526Sdg 6536Sdg#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 6546Sdg#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 6556Sdg#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 6566Sdg#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 6576Sdg#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 65843Sdg 65943Sdg/* 66043Sdg * The three bit of the encoded IRQ are decoded as follows: 66143Sdg * 66243Sdg * IR2 IR1 IR0 IRQ 66343Sdg * 0 0 0 2/9 66443Sdg * 0 0 1 3 66543Sdg * 0 1 0 5 66643Sdg * 0 1 1 7 66743Sdg * 1 0 0 10 66843Sdg * 1 0 1 11 66943Sdg * 1 1 0 15 67043Sdg * 1 1 1 4 67143Sdg */ 67243Sdg#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 67343Sdg#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 6746Sdg#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ 6756Sdg 6766Sdg/* 6776Sdg * LA Address Register (LAAR) 6786Sdg */ 6796Sdg#define ED_WD_LAAR 5 6806Sdg 6816Sdg#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 6826Sdg#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 6836Sdg#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ 6846Sdg#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 6856Sdg 6866Sdg/* i/o base offset to station address/card-ID PROM */ 6876Sdg#define ED_WD_PROM 8 6886Sdg 6896Sdg/* i/o base offset to CARD ID */ 6906Sdg#define ED_WD_CARD_ID ED_WD_PROM+6 6916Sdg 692520Sdg/* Board type codes in card ID */ 6936Sdg#define ED_TYPE_WD8003S 0x02 6946Sdg#define ED_TYPE_WD8003E 0x03 6956Sdg#define ED_TYPE_WD8013EBT 0x05 6961015Sats#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */ 6971015Sats#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */ 6981015Sats#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */ 6991015Sats#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */ 7001073Sdg#define ED_TYPE_WD8003W 0x24 701808Sdg#define ED_TYPE_WD8013W 0x26 702426Sdg#define ED_TYPE_WD8013EP 0x27 703426Sdg#define ED_TYPE_WD8013WC 0x28 7046Sdg#define ED_TYPE_WD8013EPC 0x29 705791Sdg#define ED_TYPE_SMC8216T 0x2a 706791Sdg#define ED_TYPE_SMC8216C 0x2b 7071073Sdg#define ED_TYPE_WD8013EBP 0x2c 7086Sdg 7096Sdg/* Bit definitions in card ID */ 7106Sdg#define ED_WD_REV_MASK 0x1f /* Revision mask */ 7116Sdg#define ED_WD_SOFTCONFIG 0x20 /* Soft config */ 7126Sdg#define ED_WD_LARGERAM 0x40 /* Large RAM */ 7136Sdg#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 7146Sdg 7156Sdg/* 7166Sdg * Checksum total. All 8 bytes in station address PROM will add up to this 7176Sdg */ 718968Sats#ifdef TOSH_ETHER 719968Sats#define ED_WD_ROM_CHECKSUM_TOTAL 0xA5 720968Sats#else 7216Sdg#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF 722968Sats#endif 7236Sdg 7246Sdg#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 7256Sdg#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 7266Sdg#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ 7276Sdg 7286Sdg#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 7296Sdg 7306Sdg/* 7316Sdg * Definitions for 3Com 3c503 7326Sdg */ 7336Sdg#define ED_3COM_NIC_OFFSET 0 7346Sdg#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 7356Sdg 7366Sdg/* 7376Sdg * XXX - The I/O address range is fragmented in the 3c503; this is the 7386Sdg * number of regs at iobase. 7396Sdg */ 7406Sdg#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ 7416Sdg 742520Sdg/* tx memory starts in second bank on 8bit cards */ 743520Sdg#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20 7446Sdg 745520Sdg/* tx memory starts in first bank on 16bit cards */ 746520Sdg#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0 747520Sdg 748520Sdg/* ...and rx memory starts in second bank */ 749520Sdg#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20 750520Sdg 751520Sdg 7526Sdg/* 7536Sdg * Page Start Register. Must match PSTART in NIC 7546Sdg */ 7556Sdg#define ED_3COM_PSTR 0 7566Sdg 7576Sdg/* 7586Sdg * Page Stop Register. Must match PSTOP in NIC 7596Sdg */ 7606Sdg#define ED_3COM_PSPR 1 7616Sdg 7626Sdg/* 7636Sdg * Drq Timer Register. Determines number of bytes to be transfered during 7646Sdg * a DMA burst. 7656Sdg */ 7666Sdg#define ED_3COM_DQTR 2 7676Sdg 7686Sdg/* 7696Sdg * Base Configuration Register. Read-only register which contains the 7706Sdg * board-configured I/O base address of the adapter. Bit encoded. 7716Sdg */ 7726Sdg#define ED_3COM_BCFR 3 7736Sdg 7746Sdg#define ED_3COM_BCFR_2E0 0x01 7756Sdg#define ED_3COM_BCFR_2A0 0x02 7766Sdg#define ED_3COM_BCFR_280 0x04 7776Sdg#define ED_3COM_BCFR_250 0x08 7786Sdg#define ED_3COM_BCFR_350 0x10 7796Sdg#define ED_3COM_BCFR_330 0x20 7806Sdg#define ED_3COM_BCFR_310 0x40 7816Sdg#define ED_3COM_BCFR_300 0x80 7826Sdg 7836Sdg/* 7846Sdg * EPROM Configuration Register. Read-only register which contains the 7856Sdg * board-configured memory base address. Bit encoded. 7866Sdg */ 7876Sdg#define ED_3COM_PCFR 4 7886Sdg 7896Sdg#define ED_3COM_PCFR_C8000 0x10 7906Sdg#define ED_3COM_PCFR_CC000 0x20 7916Sdg#define ED_3COM_PCFR_D8000 0x40 7926Sdg#define ED_3COM_PCFR_DC000 0x80 7936Sdg 7946Sdg/* 7956Sdg * GA Configuration Register. Gate-Array Configuration Register. 7966Sdg */ 7976Sdg#define ED_3COM_GACFR 5 7986Sdg 7996Sdg/* 8006Sdg * mbs2 mbs1 mbs0 start address 8016Sdg * 0 0 0 0x0000 8026Sdg * 0 0 1 0x2000 8036Sdg * 0 1 0 0x4000 8046Sdg * 0 1 1 0x6000 8056Sdg * 8066Sdg * Note that with adapters with only 8K, the setting for 0x2000 must 8076Sdg * always be used. 8086Sdg */ 8096Sdg#define ED_3COM_GACFR_MBS0 0x01 8106Sdg#define ED_3COM_GACFR_MBS1 0x02 8116Sdg#define ED_3COM_GACFR_MBS2 0x04 8126Sdg 8136Sdg#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ 8146Sdg#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ 8156Sdg#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 8166Sdg#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 8176Sdg#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 8186Sdg 8196Sdg/* 8206Sdg * Control Register. Miscellaneous control functions. 8216Sdg */ 8226Sdg#define ED_3COM_CR 6 8236Sdg 8246Sdg#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ 8256Sdg#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 8266Sdg#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 8276Sdg#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 8286Sdg#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 8296Sdg#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ 8306Sdg#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ 8316Sdg#define ED_3COM_CR_START 0x80 /* Start DMA controller */ 8326Sdg 8336Sdg/* 8346Sdg * Status Register. Miscellaneous status information. 8356Sdg */ 8366Sdg#define ED_3COM_STREG 7 8376Sdg 8386Sdg#define ED_3COM_STREG_REV 0x07 /* GA revision */ 8396Sdg#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ 8406Sdg#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ 8416Sdg#define ED_3COM_STREG_OFLW 0x20 /* Overflow */ 8426Sdg#define ED_3COM_STREG_UFLW 0x40 /* Underflow */ 8436Sdg#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ 8446Sdg 8456Sdg/* 8466Sdg * Interrupt/DMA Configuration Register 8476Sdg */ 8486Sdg#define ED_3COM_IDCFR 8 8496Sdg 8506Sdg#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ 8516Sdg#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ 8526Sdg#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ 8536Sdg#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ 8546Sdg#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 8556Sdg#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 8566Sdg#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 8576Sdg#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 8586Sdg 8596Sdg/* 8606Sdg * DMA Address Register MSB 8616Sdg */ 8626Sdg#define ED_3COM_DAMSB 9 8636Sdg 8646Sdg/* 8656Sdg * DMA Address Register LSB 8666Sdg */ 8676Sdg#define ED_3COM_DALSB 0x0a 8686Sdg 8696Sdg/* 8706Sdg * Vector Pointer Register 2 8716Sdg */ 8726Sdg#define ED_3COM_VPTR2 0x0b 8736Sdg 8746Sdg/* 8756Sdg * Vector Pointer Register 1 8766Sdg */ 8776Sdg#define ED_3COM_VPTR1 0x0c 8786Sdg 8796Sdg/* 8806Sdg * Vector Pointer Register 0 8816Sdg */ 8826Sdg#define ED_3COM_VPTR0 0x0d 8836Sdg 8846Sdg/* 8856Sdg * Register File Access MSB 8866Sdg */ 8876Sdg#define ED_3COM_RFMSB 0x0e 8886Sdg 8896Sdg/* 8906Sdg * Register File Access LSB 8916Sdg */ 8926Sdg#define ED_3COM_RFLSB 0x0f 893520Sdg 894520Sdg/* 895520Sdg * Definitions for Novell NE1000/2000 boards 896520Sdg */ 897520Sdg 898520Sdg/* 899520Sdg * Board type codes 900520Sdg */ 901520Sdg#define ED_TYPE_NE1000 0x01 902520Sdg#define ED_TYPE_NE2000 0x02 903520Sdg 904520Sdg/* 905520Sdg * Register offsets/total 906520Sdg */ 907520Sdg#define ED_NOVELL_NIC_OFFSET 0x00 908520Sdg#define ED_NOVELL_ASIC_OFFSET 0x10 909520Sdg#define ED_NOVELL_IO_PORTS 32 910520Sdg 911520Sdg/* 912520Sdg * Remote DMA data register; for reading or writing to the NIC mem 913520Sdg * via programmed I/O (offset from ASIC base) 914520Sdg */ 915520Sdg#define ED_NOVELL_DATA 0x00 916520Sdg 917520Sdg/* 918520Sdg * Reset register; reading from this register causes a board reset 919520Sdg */ 920520Sdg#define ED_NOVELL_RESET 0x0f 921