1139749Simp/*- 21817Sdg * Copyright (C) 1993, David Greenman. This software may be used, modified, 31817Sdg * copied, distributed, and sold, in both source and binary form provided 41817Sdg * that the above copyright and these terms are retained. Under no 51817Sdg * circumstances is the author responsible for the proper functioning 61817Sdg * of this software, nor does the author assume any responsibility 71817Sdg * for damages incurred with its use. 81817Sdg * 950477Speter * $FreeBSD$ 101817Sdg */ 111817Sdg/* 128876Srgrimes * National Semiconductor DS8390 NIC register definitions 1343Sdg * 14498Sdg * 15498Sdg * Modification history 16498Sdg * 17808Sdg * Revision 2.2 1993/11/29 16:33:39 davidg 18808Sdg * From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk> 19808Sdg * Add support for the 8013W board type 20808Sdg * 21791Sdg * Revision 2.1 1993/11/22 10:52:33 davidg 22791Sdg * patch to add support for SMC8216 (Elite-Ultra) boards 23791Sdg * from Glen H. Lowe 24791Sdg * 25520Sdg * Revision 2.0 93/09/29 00:37:15 davidg 26520Sdg * changed double buffering flag to multi buffering 27520Sdg * made changes/additions for 3c503 multi-buffering 28520Sdg * ...companion to Rev. 2.0 of 'ed' driver. 298876Srgrimes * 3043Sdg * Revision 1.1 93/06/23 03:01:07 davidg 3143Sdg * Initial revision 328876Srgrimes * 336Sdg */ 346Sdg 356Sdg/* 366Sdg * Page 0 register offsets 376Sdg */ 386Sdg#define ED_P0_CR 0x00 /* Command Register */ 396Sdg 406Sdg#define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ 416Sdg#define ED_P0_PSTART 0x01 /* Page Start register (write) */ 426Sdg 436Sdg#define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ 446Sdg#define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ 456Sdg 466Sdg#define ED_P0_BNRY 0x03 /* Boundary Pointer */ 476Sdg 486Sdg#define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ 496Sdg#define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ 506Sdg 516Sdg#define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ 526Sdg#define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ 536Sdg 546Sdg#define ED_P0_FIFO 0x06 /* FIFO register (read) */ 556Sdg#define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ 566Sdg 576Sdg#define ED_P0_ISR 0x07 /* Interrupt Status Register */ 586Sdg 596Sdg#define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ 606Sdg#define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ 616Sdg 626Sdg#define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ 636Sdg#define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ 646Sdg 656Sdg#define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ 666Sdg 676Sdg#define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ 686Sdg 696Sdg#define ED_P0_RSR 0x0c /* Receive Status (read) */ 706Sdg#define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ 716Sdg 726Sdg#define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ 736Sdg#define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ 746Sdg 756Sdg#define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ 766Sdg#define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ 776Sdg 786Sdg#define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ 796Sdg#define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ 806Sdg 816Sdg/* 826Sdg * Page 1 register offsets 836Sdg */ 846Sdg#define ED_P1_CR 0x00 /* Command Register */ 856Sdg#define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ 866Sdg#define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ 876Sdg#define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ 886Sdg#define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ 896Sdg#define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ 906Sdg#define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ 9150808Skato#define ED_P1_PAR(i) (ED_P1_PAR0 + i) 926Sdg#define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ 936Sdg#define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ 946Sdg#define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ 956Sdg#define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ 966Sdg#define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ 976Sdg#define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ 986Sdg#define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ 996Sdg#define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ 1006Sdg#define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ 10150808Skato#define ED_P1_MAR(i) (ED_P1_MAR0 + i) 1026Sdg 1036Sdg/* 1046Sdg * Page 2 register offsets 1056Sdg */ 1066Sdg#define ED_P2_CR 0x00 /* Command Register */ 1076Sdg#define ED_P2_PSTART 0x01 /* Page Start (read) */ 1086Sdg#define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ 1096Sdg#define ED_P2_PSTOP 0x02 /* Page Stop (read) */ 1106Sdg#define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ 1116Sdg#define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ 1126Sdg#define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ 1136Sdg#define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ 1146Sdg#define ED_P2_ACU 0x06 /* Address Counter Upper */ 1156Sdg#define ED_P2_ACL 0x07 /* Address Counter Lower */ 1166Sdg#define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ 1176Sdg#define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ 1186Sdg#define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ 1196Sdg#define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ 1206Sdg 1216Sdg/* 1226Sdg * Command Register (CR) definitions 1236Sdg */ 1246Sdg 1256Sdg/* 1266Sdg * STP: SToP. Software reset command. Takes the controller offline. No 1276Sdg * packets will be received or transmitted. Any reception or 1286Sdg * transmission in progress will continue to completion before 1296Sdg * entering reset state. To exit this state, the STP bit must 1306Sdg * reset and the STA bit must be set. The software reset has 1316Sdg * executed only when indicated by the RST bit in the ISR being 1326Sdg * set. 1336Sdg */ 1346Sdg#define ED_CR_STP 0x01 1356Sdg 1366Sdg/* 1376Sdg * STA: STArt. This bit is used to activate the NIC after either power-up, 1386Sdg * or when the NIC has been put in reset mode by software command 1396Sdg * or error. 1406Sdg */ 1416Sdg#define ED_CR_STA 0x02 1426Sdg 1436Sdg/* 1446Sdg * TXP: Transmit Packet. This bit must be set to indicate transmission of 1456Sdg * a packet. TXP is internally reset either after the transmission is 1466Sdg * completed or aborted. This bit should be set only after the Transmit 1476Sdg * Byte Count and Transmit Page Start register have been programmed. 1486Sdg */ 1496Sdg#define ED_CR_TXP 0x04 1506Sdg 1516Sdg/* 1526Sdg * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation 1536Sdg * of the remote DMA channel. RD2 can be set to abort any remote DMA 1546Sdg * command in progress. The Remote Byte Count registers should be cleared 1556Sdg * when a remote DMA has been aborted. The Remote Start Addresses are not 1566Sdg * restored to the starting address if the remote DMA is aborted. 1576Sdg * 1586Sdg * RD2 RD1 RD0 function 1596Sdg * 0 0 0 not allowed 1606Sdg * 0 0 1 remote read 1616Sdg * 0 1 0 remote write 1626Sdg * 0 1 1 send packet 1636Sdg * 1 X X abort 1646Sdg */ 1656Sdg#define ED_CR_RD0 0x08 1666Sdg#define ED_CR_RD1 0x10 1676Sdg#define ED_CR_RD2 0x20 1686Sdg 1696Sdg/* 1706Sdg * PS0, PS1: Page Select. The two bits select which register set or 'page' to 1716Sdg * access. 1726Sdg * 1736Sdg * PS1 PS0 page 1746Sdg * 0 0 0 1756Sdg * 0 1 1 1766Sdg * 1 0 2 177150957Simp * 1 1 3 (some chips it is reserved) 1786Sdg */ 1796Sdg#define ED_CR_PS0 0x40 1806Sdg#define ED_CR_PS1 0x80 1816Sdg/* bit encoded aliases */ 1826Sdg#define ED_CR_PAGE_0 0x00 /* (for consistency) */ 1836Sdg#define ED_CR_PAGE_1 0x40 1846Sdg#define ED_CR_PAGE_2 0x80 185150957Simp#define ED_CR_PAGE_3 0xc0 1866Sdg 1876Sdg/* 1886Sdg * Interrupt Status Register (ISR) definitions 1896Sdg */ 1906Sdg 1916Sdg/* 1926Sdg * PRX: Packet Received. Indicates packet received with no errors. 1936Sdg */ 1946Sdg#define ED_ISR_PRX 0x01 1956Sdg 1966Sdg/* 1976Sdg * PTX: Packet Transmitted. Indicates packet transmitted with no errors. 1986Sdg */ 1996Sdg#define ED_ISR_PTX 0x02 2006Sdg 2016Sdg/* 2026Sdg * RXE: Receive Error. Indicates that a packet was received with one or more 2036Sdg * the following errors: CRC error, frame alignment error, FIFO overrun, 2046Sdg * missed packet. 2056Sdg */ 2066Sdg#define ED_ISR_RXE 0x04 2076Sdg 2086Sdg/* 2096Sdg * TXE: Transmission Error. Indicates that an attempt to transmit a packet 2106Sdg * resulted in one or more of the following errors: excessive 2116Sdg * collisions, FIFO underrun. 2126Sdg */ 2136Sdg#define ED_ISR_TXE 0x08 2146Sdg 2156Sdg/* 2166Sdg * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network 21713765Smpp * would exceed (has exceeded?) the boundary pointer, resulting in data 2186Sdg * that was previously received and not yet read from the buffer to be 2196Sdg * overwritten. 2206Sdg */ 2216Sdg#define ED_ISR_OVW 0x10 2226Sdg 2236Sdg/* 2246Sdg * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley 2256Sdg * Counters has been set. 2266Sdg */ 2276Sdg#define ED_ISR_CNT 0x20 2286Sdg 2296Sdg/* 2306Sdg * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. 2316Sdg */ 2326Sdg#define ED_ISR_RDC 0x40 2336Sdg 2346Sdg/* 2356Sdg * RST: Reset status. Set when the NIC enters the reset state and cleared when a 2366Sdg * Start Command is issued to the CR. This bit is also set when a receive 2376Sdg * ring-buffer overrun (OverWrite) occurs and is cleared when one or more 2386Sdg * packets have been removed from the ring. This is a read-only bit. 2396Sdg */ 2406Sdg#define ED_ISR_RST 0x80 2416Sdg 2426Sdg/* 2436Sdg * Interrupt Mask Register (IMR) definitions 2446Sdg */ 2456Sdg 2466Sdg/* 2476Sdg * PRXE: Packet Received interrupt Enable. If set, a received packet will cause 2486Sdg * an interrupt. 2496Sdg */ 2506Sdg#define ED_IMR_PRXE 0x01 2516Sdg 2526Sdg/* 2536Sdg * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when 2546Sdg * a packet transmission completes. 2556Sdg */ 2566Sdg#define ED_IMR_PTXE 0x02 2576Sdg 2586Sdg/* 2596Sdg * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a 2606Sdg * packet is received with an error. 2616Sdg */ 2626Sdg#define ED_IMR_RXEE 0x04 2636Sdg 2646Sdg/* 2656Sdg * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever 2666Sdg * a transmission results in an error. 2676Sdg */ 2686Sdg#define ED_IMR_TXEE 0x08 2696Sdg 2706Sdg/* 2716Sdg * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever 27213765Smpp * the receive ring-buffer is overrun. i.e. when the boundary pointer is exceeded. 2736Sdg */ 2746Sdg#define ED_IMR_OVWE 0x10 2756Sdg 2766Sdg/* 2776Sdg * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever 2786Sdg * the MSB of one or more of the Network Statistics counters has been set. 2796Sdg */ 2806Sdg#define ED_IMR_CNTE 0x20 2816Sdg 2826Sdg/* 2836Sdg * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated 2846Sdg * when a remote DMA transfer has completed. 2856Sdg */ 2866Sdg#define ED_IMR_RDCE 0x40 2876Sdg 2886Sdg/* 2896Sdg * bit 7 is unused/reserved 2906Sdg */ 2916Sdg 2926Sdg/* 2936Sdg * Data Configuration Register (DCR) definitions 2946Sdg */ 2956Sdg 2966Sdg/* 2976Sdg * WTS: Word Transfer Select. WTS establishes byte or word transfers for 2986Sdg * both remote and local DMA transfers 2996Sdg */ 3006Sdg#define ED_DCR_WTS 0x01 3016Sdg 3026Sdg/* 3036Sdg * BOS: Byte Order Select. BOS sets the byte order for the host. 3046Sdg * Should be 0 for 80x86, and 1 for 68000 series processors 3056Sdg */ 3066Sdg#define ED_DCR_BOS 0x02 3076Sdg 3086Sdg/* 3096Sdg * LAS: Long Address Select. When LAS is 1, the contents of the remote 3106Sdg * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 3116Sdg */ 3126Sdg#define ED_DCR_LAS 0x04 3136Sdg 3146Sdg/* 3156Sdg * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 3166Sdg * of the TCR must also be programmed for loopback operation. 3176Sdg * When 1, normal operation is selected. 3186Sdg */ 3196Sdg#define ED_DCR_LS 0x08 3206Sdg 3216Sdg/* 3226Sdg * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer 3236Sdg * under program control. When 1, remote DMA is automatically initiated 32413765Smpp * and the boundary pointer is automatically updated 3256Sdg */ 3266Sdg#define ED_DCR_AR 0x10 3276Sdg 3286Sdg/* 3296Sdg * FT0, FT1: Fifo Threshold select. 3306Sdg * FT1 FT0 Word-width Byte-width 3316Sdg * 0 0 1 word 2 bytes 3326Sdg * 0 1 2 words 4 bytes 3336Sdg * 1 0 4 words 8 bytes 3346Sdg * 1 1 8 words 12 bytes 3356Sdg * 3366Sdg * During transmission, the FIFO threshold indicates the number of bytes 3376Sdg * or words that the FIFO has filled from the local DMA before BREQ is 3386Sdg * asserted. The transmission threshold is 16 bytes minus the receiver 3396Sdg * threshold. 3406Sdg */ 3416Sdg#define ED_DCR_FT0 0x20 3426Sdg#define ED_DCR_FT1 0x40 3436Sdg 3446Sdg/* 3456Sdg * bit 7 (0x80) is unused/reserved 3466Sdg */ 3476Sdg 3486Sdg/* 3496Sdg * Transmit Configuration Register (TCR) definitions 3506Sdg */ 3516Sdg 3526Sdg/* 3536Sdg * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC 3546Sdg * is not appended by the transmitter. 3556Sdg */ 3566Sdg#define ED_TCR_CRC 0x01 3576Sdg 3586Sdg/* 3596Sdg * LB0, LB1: Loopback control. These two bits set the type of loopback that is 3606Sdg * to be performed. 3616Sdg * 3626Sdg * LB1 LB0 mode 3636Sdg * 0 0 0 - normal operation (DCR_LS = 0) 3646Sdg * 0 1 1 - internal loopback (DCR_LS = 0) 3656Sdg * 1 0 2 - external loopback (DCR_LS = 1) 3666Sdg * 1 1 3 - external loopback (DCR_LS = 0) 3676Sdg */ 3686Sdg#define ED_TCR_LB0 0x02 3696Sdg#define ED_TCR_LB1 0x04 3706Sdg 3716Sdg/* 3726Sdg * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows 3736Sdg * another station to disable the NIC's transmitter by transmitting to 3746Sdg * a multicast address hashing to bit 62. Reception of a multicast address 3756Sdg * hashing to bit 63 enables the transmitter. 3766Sdg */ 3776Sdg#define ED_TCR_ATD 0x08 3786Sdg 3796Sdg/* 3806Sdg * OFST: Collision Offset enable. This bit when set modifies the backoff 3816Sdg * algorithm to allow prioritization of nodes. 3826Sdg */ 3836Sdg#define ED_TCR_OFST 0x10 3848876Srgrimes 3856Sdg/* 3866Sdg * bits 5, 6, and 7 are unused/reserved 3876Sdg */ 3886Sdg 3896Sdg/* 3906Sdg * Transmit Status Register (TSR) definitions 3916Sdg */ 3926Sdg 3936Sdg/* 3946Sdg * PTX: Packet Transmitted. Indicates successful transmission of packet. 3956Sdg */ 3966Sdg#define ED_TSR_PTX 0x01 3976Sdg 3986Sdg/* 3996Sdg * bit 1 (0x02) is unused/reserved 4006Sdg */ 4016Sdg 4026Sdg/* 4036Sdg * COL: Transmit Collided. Indicates that the transmission collided at least 4046Sdg * once with another station on the network. 4056Sdg */ 4066Sdg#define ED_TSR_COL 0x04 4076Sdg 4086Sdg/* 4096Sdg * ABT: Transmit aborted. Indicates that the transmission was aborted due to 4106Sdg * excessive collisions. 4116Sdg */ 4126Sdg#define ED_TSR_ABT 0x08 4136Sdg 4146Sdg/* 4156Sdg * CRS: Carrier Sense Lost. Indicates that carrier was lost during the 4166Sdg * transmission of the packet. (Transmission is not aborted because 4176Sdg * of a loss of carrier) 4186Sdg */ 4196Sdg#define ED_TSR_CRS 0x10 4206Sdg 4216Sdg/* 4226Sdg * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ 4236Sdg * transmission memory before the FIFO emptied. Transmission of the 4246Sdg * packet was aborted. 4256Sdg */ 4266Sdg#define ED_TSR_FU 0x20 4276Sdg 4286Sdg/* 4296Sdg * CDH: CD Heartbeat. Indicates that the collision detection circuitry 4306Sdg * isn't working correctly during a collision heartbeat test. 4316Sdg */ 4326Sdg#define ED_TSR_CDH 0x40 4336Sdg 4346Sdg/* 4356Sdg * OWC: Out of Window Collision: Indicates that a collision occurred after 4366Sdg * a slot time (51.2us). The transmission is rescheduled just as in 4376Sdg * normal collisions. 4386Sdg */ 4396Sdg#define ED_TSR_OWC 0x80 4406Sdg 4416Sdg/* 4426Sdg * Receiver Configuration Register (RCR) definitions 4436Sdg */ 4446Sdg 4456Sdg/* 4466Sdg * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, 4476Sdg * packets with CRC and frame errors are not discarded. 4486Sdg */ 4496Sdg#define ED_RCR_SEP 0x01 4506Sdg 4516Sdg/* 4526Sdg * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. 4536Sdg * If set to 1, packets with less than 64 byte are not discarded. 4546Sdg */ 4556Sdg#define ED_RCR_AR 0x02 4566Sdg 4576Sdg/* 4586Sdg * AB: Accept Broadcast. If set, packets sent to the broadcast address will be 4596Sdg * accepted. 4606Sdg */ 4616Sdg#define ED_RCR_AB 0x04 4626Sdg 4636Sdg/* 4646Sdg * AM: Accept Multicast. If set, packets sent to a multicast address are checked 4656Sdg * for a match in the hashing array. If clear, multicast packets are ignored. 4666Sdg */ 4676Sdg#define ED_RCR_AM 0x08 4686Sdg 4696Sdg/* 4706Sdg * PRO: Promiscuous Physical. If set, all packets with a physical addresses are 4716Sdg * accepted. If clear, a physical destination address must match this 4726Sdg * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM 4736Sdg * must also be set. In addition, the multicast hashing array must be set 4746Sdg * to all 1's so that all multicast addresses are accepted. 4756Sdg */ 4766Sdg#define ED_RCR_PRO 0x10 4776Sdg 4786Sdg/* 4796Sdg * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, 4806Sdg * but are not stored in the ring-buffer. If clear, packets are stored (normal 4816Sdg * operation). 4826Sdg */ 4836Sdg#define ED_RCR_MON 0x20 4846Sdg 4856Sdg/* 48663775Stanimura * INTT: Interrupt Trigger Mode for AX88190. 4876Sdg */ 48863775Stanimura#define ED_RCR_INTT 0x40 4896Sdg 4906Sdg/* 49163775Stanimura * bit 7 is unused/reserved. 49263775Stanimura */ 49363775Stanimura 49463775Stanimura/* 4956Sdg * Receiver Status Register (RSR) definitions 4966Sdg */ 4976Sdg 4986Sdg/* 4996Sdg * PRX: Packet Received without error. 5006Sdg */ 5016Sdg#define ED_RSR_PRX 0x01 5026Sdg 5036Sdg/* 5046Sdg * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame 5056Sdg * alignment errors. 5066Sdg */ 5076Sdg#define ED_RSR_CRC 0x02 5086Sdg 5096Sdg/* 5106Sdg * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on 51113765Smpp * a byte boundary and the CRC did not match at the last byte boundary. 5126Sdg */ 5136Sdg#define ED_RSR_FAE 0x04 5146Sdg 5156Sdg/* 5166Sdg * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) 5176Sdg * causing it to overrun. Reception of the packet is aborted. 5186Sdg */ 5196Sdg#define ED_RSR_FO 0x08 5206Sdg 5216Sdg/* 5226Sdg * MPA: Missed Packet. Indicates that the received packet couldn't be stored in 5236Sdg * the ring-buffer because of insufficient buffer space (exceeding the 52413765Smpp * boundary pointer), or because the transfer to the ring-buffer was inhibited 5256Sdg * by RCR_MON - monitor mode. 5266Sdg */ 5276Sdg#define ED_RSR_MPA 0x10 5286Sdg 5296Sdg/* 5306Sdg * PHY: Physical address. If 0, the packet received was sent to a physical address. 5316Sdg * If 1, the packet was accepted because of a multicast/broadcast address 5326Sdg * match. 5336Sdg */ 5346Sdg#define ED_RSR_PHY 0x20 5356Sdg 5366Sdg/* 53713765Smpp * DIS: Receiver Disabled. Set to indicate that the receiver has entered monitor 5386Sdg * mode. Cleared when the receiver exits monitor mode. 5396Sdg */ 5406Sdg#define ED_RSR_DIS 0x40 5416Sdg 5426Sdg/* 5436Sdg * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs 5446Sdg * are active, and the transceiver has set the CD line as a result of the 5456Sdg * jabber. 5466Sdg */ 5476Sdg#define ED_RSR_DFR 0x80 5486Sdg 5496Sdg/* 55013765Smpp * receive ring descriptor 5516Sdg * 5526Sdg * The National Semiconductor DS8390 Network interface controller uses 5536Sdg * the following receive ring headers. The way this works is that the 5546Sdg * memory on the interface card is chopped up into 256 bytes blocks. 5556Sdg * A contiguous portion of those blocks are marked for receive packets 5566Sdg * by setting start and end block #'s in the NIC. For each packet that 5576Sdg * is put into the receive ring, one of these headers (4 bytes each) is 5581831Sdg * tacked onto the front. The first byte is a copy of the receiver status 5591831Sdg * register at the time the packet was received. 5606Sdg */ 5616Sdgstruct ed_ring { 5621831Sdg u_char rsr; /* receiver status */ 5636Sdg u_char next_packet; /* pointer to next packet */ 5646Sdg u_short count; /* bytes in packet (length + 4) */ 5656Sdg}; 5666Sdg 5676Sdg/* 5686Sdg * Common constants 5696Sdg */ 5706Sdg#define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ 5716Sdg#define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ 5726Sdg 5736Sdg/* 5746Sdg * Definitions for Western digital/SMC WD80x3 series ASIC 5756Sdg */ 5766Sdg/* 5776Sdg * Memory Select Register (MSR) 5786Sdg */ 5796Sdg#define ED_WD_MSR 0 5806Sdg 5811349Sdg/* next three definitions for Toshiba */ 5821015Sats#define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */ 5831015Sats#define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */ 5841015Sats#define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits, 5851015Sats 1 = 8 bits (R/W) */ 5861349Sdg#define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 5871349Sdg#define ED_WD_MSR_MENB 0x40 /* Memory enable */ 5881349Sdg#define ED_WD_MSR_RST 0x80 /* Reset board */ 5896Sdg 5906Sdg/* 5916Sdg * Interface Configuration Register (ICR) 5926Sdg */ 5936Sdg#define ED_WD_ICR 1 5946Sdg 5956Sdg#define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ 5966Sdg#define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */ 59743Sdg#define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 5986Sdg#define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 5996Sdg#define ED_WD_ICR_RLA 0x10 /* recall LAN address */ 6006Sdg#define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 6016Sdg#define ED_WD_ICR_RIO 0x40 /* recall i/o address */ 6026Sdg#define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ 6031015Sats#define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */ 6041015Sats#define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K, 6051015Sats 0x02 = 16K, 0x01 = 8K */ 6061015Sats /* 64K can only be used if mem address 6071015Sats above 1Mb */ 6081015Sats /* IAR holds address A23-A16 (R/W) */ 6096Sdg 6106Sdg/* 61143Sdg * IO Address Register (IAR) 61243Sdg */ 61343Sdg#define ED_WD_IAR 2 61443Sdg 61543Sdg/* 61643Sdg * EEROM Address Register 61743Sdg */ 61843Sdg#define ED_WD_EAR 3 61943Sdg 62043Sdg/* 6216Sdg * Interrupt Request Register (IRR) 6226Sdg */ 6236Sdg#define ED_WD_IRR 4 6246Sdg 6256Sdg#define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 6266Sdg#define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 6276Sdg#define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 6286Sdg#define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 6296Sdg#define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 63043Sdg 63143Sdg/* 6321349Sdg * The three bits of the encoded IRQ are decoded as follows: 63343Sdg * 63443Sdg * IR2 IR1 IR0 IRQ 63543Sdg * 0 0 0 2/9 63643Sdg * 0 0 1 3 63743Sdg * 0 1 0 5 63843Sdg * 0 1 1 7 63943Sdg * 1 0 0 10 64043Sdg * 1 0 1 11 64143Sdg * 1 1 0 15 64243Sdg * 1 1 1 4 64343Sdg */ 64443Sdg#define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 64543Sdg#define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 6466Sdg#define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ 6476Sdg 6486Sdg/* 6496Sdg * LA Address Register (LAAR) 6506Sdg */ 6516Sdg#define ED_WD_LAAR 5 6526Sdg 6536Sdg#define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 6546Sdg#define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 6556Sdg#define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ 6566Sdg#define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 6576Sdg 6586Sdg/* i/o base offset to station address/card-ID PROM */ 6596Sdg#define ED_WD_PROM 8 6606Sdg 6611349Sdg/* 6621349Sdg * 83C790 specific registers 6631349Sdg */ 6641349Sdg/* 6651349Sdg * Hardware Support Register (HWR) ('790) 6661349Sdg */ 6671349Sdg#define ED_WD790_HWR 4 6681349Sdg 6691349Sdg#define WD_WD790_HWR_NUKE 0x10 /* hardware reset */ 6701349Sdg#define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */ 6711349Sdg#define ED_WD790_HWR_SWH 0x80 /* switch register set */ 6721349Sdg 6731349Sdg/* 6741349Sdg * ICR790 Interrupt Control Register for the 83C790 6751349Sdg */ 6761349Sdg#define ED_WD790_ICR 6 6771349Sdg 6781349Sdg#define ED_WD790_ICR_EIL 0x01 /* enable interrupts */ 6791349Sdg 6801349Sdg/* 6815807Sdg * REV/IOPA Revision / I/O Pipe register for the 83C79X 6825807Sdg */ 6835807Sdg#define ED_WD790_REV 7 6845807Sdg 6855807Sdg#define ED_WD790 0x20 6865807Sdg#define ED_WD795 0x40 6875807Sdg 6885807Sdg/* 6895807Sdg * 79X RAM Address Register (RAR) 6905807Sdg * Enabled with SWH bit=1 in HWR register 6915807Sdg */ 6925807Sdg#define ED_WD790_RAR 0x0b 6935807Sdg 6945807Sdg#define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */ 6955807Sdg#define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */ 6965807Sdg#define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */ 6975807Sdg#define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */ 6985807Sdg 6995807Sdg/* 7001349Sdg * General Control Register (GCR) 7011349Sdg * Enabled with SWH bit=1 in HWR register 7021349Sdg */ 7031349Sdg#define ED_WD790_GCR 0x0d 7041349Sdg 7051349Sdg#define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */ 7061349Sdg#define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */ 7071349Sdg#define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */ 7081349Sdg#define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */ 7095807Sdg#define ED_WD790_GCR_LIT 0x01 /* Link Integrity Test Enable */ 7101349Sdg/* 7111349Sdg * The three bits of the encoded IRQ are decoded as follows: 7121349Sdg * 7131349Sdg * IR2 IR1 IR0 IRQ 7141349Sdg * 0 0 0 none 7151349Sdg * 0 0 1 9 7161349Sdg * 0 1 0 3 7171349Sdg * 0 1 1 5 7181349Sdg * 1 0 0 7 7191349Sdg * 1 0 1 10 7201349Sdg * 1 1 0 11 7211349Sdg * 1 1 1 15 7221349Sdg */ 7231349Sdg 7246Sdg/* i/o base offset to CARD ID */ 7256Sdg#define ED_WD_CARD_ID ED_WD_PROM+6 7266Sdg 727520Sdg/* Board type codes in card ID */ 7286Sdg#define ED_TYPE_WD8003S 0x02 7296Sdg#define ED_TYPE_WD8003E 0x03 7306Sdg#define ED_TYPE_WD8013EBT 0x05 7311015Sats#define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */ 7321015Sats#define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */ 7331015Sats#define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */ 7341015Sats#define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */ 7351073Sdg#define ED_TYPE_WD8003W 0x24 7361075Sdg#define ED_TYPE_WD8003EB 0x25 737808Sdg#define ED_TYPE_WD8013W 0x26 738426Sdg#define ED_TYPE_WD8013EP 0x27 739426Sdg#define ED_TYPE_WD8013WC 0x28 7406Sdg#define ED_TYPE_WD8013EPC 0x29 741791Sdg#define ED_TYPE_SMC8216T 0x2a 742791Sdg#define ED_TYPE_SMC8216C 0x2b 7431073Sdg#define ED_TYPE_WD8013EBP 0x2c 7446Sdg 7456Sdg/* Bit definitions in card ID */ 7466Sdg#define ED_WD_REV_MASK 0x1f /* Revision mask */ 7476Sdg#define ED_WD_SOFTCONFIG 0x20 /* Soft config */ 7486Sdg#define ED_WD_LARGERAM 0x40 /* Large RAM */ 7496Sdg#define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 7506Sdg 7516Sdg/* 7526Sdg * Checksum total. All 8 bytes in station address PROM will add up to this 7536Sdg */ 75463775Stanimura#define ED_WD_ROM_CHECKSUM_TOTAL 0xFF 75563775Stanimura#define ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER 0xA5 7566Sdg 7576Sdg#define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 7586Sdg#define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 7596Sdg#define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ 7606Sdg 7616Sdg#define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 7626Sdg 7636Sdg/* 7646Sdg * Definitions for 3Com 3c503 7656Sdg */ 7666Sdg#define ED_3COM_NIC_OFFSET 0 7676Sdg#define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 7686Sdg 7696Sdg/* 7706Sdg * XXX - The I/O address range is fragmented in the 3c503; this is the 7716Sdg * number of regs at iobase. 7726Sdg */ 7736Sdg#define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ 7746Sdg 775520Sdg/* tx memory starts in second bank on 8bit cards */ 776520Sdg#define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20 7776Sdg 778520Sdg/* tx memory starts in first bank on 16bit cards */ 779520Sdg#define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0 780520Sdg 781520Sdg/* ...and rx memory starts in second bank */ 782520Sdg#define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20 783520Sdg 784520Sdg 7856Sdg/* 7866Sdg * Page Start Register. Must match PSTART in NIC 7876Sdg */ 7886Sdg#define ED_3COM_PSTR 0 7896Sdg 7906Sdg/* 7916Sdg * Page Stop Register. Must match PSTOP in NIC 7926Sdg */ 7936Sdg#define ED_3COM_PSPR 1 7946Sdg 7956Sdg/* 7966Sdg * Drq Timer Register. Determines number of bytes to be transfered during 7976Sdg * a DMA burst. 7986Sdg */ 7996Sdg#define ED_3COM_DQTR 2 8006Sdg 8016Sdg/* 8026Sdg * Base Configuration Register. Read-only register which contains the 8036Sdg * board-configured I/O base address of the adapter. Bit encoded. 8046Sdg */ 8056Sdg#define ED_3COM_BCFR 3 8066Sdg 8076Sdg#define ED_3COM_BCFR_2E0 0x01 8086Sdg#define ED_3COM_BCFR_2A0 0x02 8096Sdg#define ED_3COM_BCFR_280 0x04 8106Sdg#define ED_3COM_BCFR_250 0x08 8116Sdg#define ED_3COM_BCFR_350 0x10 8126Sdg#define ED_3COM_BCFR_330 0x20 8136Sdg#define ED_3COM_BCFR_310 0x40 8146Sdg#define ED_3COM_BCFR_300 0x80 8156Sdg 8166Sdg/* 8176Sdg * EPROM Configuration Register. Read-only register which contains the 8186Sdg * board-configured memory base address. Bit encoded. 8196Sdg */ 8206Sdg#define ED_3COM_PCFR 4 8216Sdg 8226Sdg#define ED_3COM_PCFR_C8000 0x10 8236Sdg#define ED_3COM_PCFR_CC000 0x20 8246Sdg#define ED_3COM_PCFR_D8000 0x40 8256Sdg#define ED_3COM_PCFR_DC000 0x80 8266Sdg 8276Sdg/* 8286Sdg * GA Configuration Register. Gate-Array Configuration Register. 8296Sdg */ 8306Sdg#define ED_3COM_GACFR 5 8316Sdg 8326Sdg/* 8336Sdg * mbs2 mbs1 mbs0 start address 8346Sdg * 0 0 0 0x0000 8356Sdg * 0 0 1 0x2000 8366Sdg * 0 1 0 0x4000 8376Sdg * 0 1 1 0x6000 8386Sdg * 8396Sdg * Note that with adapters with only 8K, the setting for 0x2000 must 8406Sdg * always be used. 8416Sdg */ 8426Sdg#define ED_3COM_GACFR_MBS0 0x01 8436Sdg#define ED_3COM_GACFR_MBS1 0x02 8446Sdg#define ED_3COM_GACFR_MBS2 0x04 8456Sdg 8466Sdg#define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ 8476Sdg#define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ 8486Sdg#define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 8496Sdg#define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 8506Sdg#define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 8516Sdg 8526Sdg/* 8536Sdg * Control Register. Miscellaneous control functions. 8546Sdg */ 8556Sdg#define ED_3COM_CR 6 8566Sdg 8576Sdg#define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ 8586Sdg#define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 8596Sdg#define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 8606Sdg#define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 8616Sdg#define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 8626Sdg#define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ 8636Sdg#define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ 8646Sdg#define ED_3COM_CR_START 0x80 /* Start DMA controller */ 8656Sdg 8666Sdg/* 8676Sdg * Status Register. Miscellaneous status information. 8686Sdg */ 8696Sdg#define ED_3COM_STREG 7 8706Sdg 8716Sdg#define ED_3COM_STREG_REV 0x07 /* GA revision */ 8726Sdg#define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ 8736Sdg#define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ 8746Sdg#define ED_3COM_STREG_OFLW 0x20 /* Overflow */ 8756Sdg#define ED_3COM_STREG_UFLW 0x40 /* Underflow */ 8766Sdg#define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ 8776Sdg 8786Sdg/* 8796Sdg * Interrupt/DMA Configuration Register 8806Sdg */ 8816Sdg#define ED_3COM_IDCFR 8 8826Sdg 8836Sdg#define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ 8846Sdg#define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ 8856Sdg#define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ 8866Sdg#define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ 8876Sdg#define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 8886Sdg#define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 8896Sdg#define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 8906Sdg#define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 8916Sdg 8926Sdg/* 8936Sdg * DMA Address Register MSB 8946Sdg */ 8956Sdg#define ED_3COM_DAMSB 9 8966Sdg 8976Sdg/* 8986Sdg * DMA Address Register LSB 8996Sdg */ 9006Sdg#define ED_3COM_DALSB 0x0a 9016Sdg 9026Sdg/* 9036Sdg * Vector Pointer Register 2 9046Sdg */ 9056Sdg#define ED_3COM_VPTR2 0x0b 9066Sdg 9076Sdg/* 9086Sdg * Vector Pointer Register 1 9096Sdg */ 9106Sdg#define ED_3COM_VPTR1 0x0c 9116Sdg 9126Sdg/* 9136Sdg * Vector Pointer Register 0 9146Sdg */ 9156Sdg#define ED_3COM_VPTR0 0x0d 9166Sdg 9176Sdg/* 9186Sdg * Register File Access MSB 9196Sdg */ 9206Sdg#define ED_3COM_RFMSB 0x0e 9216Sdg 9226Sdg/* 9236Sdg * Register File Access LSB 9246Sdg */ 9256Sdg#define ED_3COM_RFLSB 0x0f 926520Sdg 927520Sdg/* 928520Sdg * Definitions for Novell NE1000/2000 boards 929520Sdg */ 930520Sdg 931520Sdg/* 932520Sdg * Board type codes 933520Sdg */ 934520Sdg#define ED_TYPE_NE1000 0x01 935520Sdg#define ED_TYPE_NE2000 0x02 936520Sdg 937520Sdg/* 938520Sdg * Register offsets/total 939520Sdg */ 940520Sdg#define ED_NOVELL_NIC_OFFSET 0x00 941520Sdg#define ED_NOVELL_ASIC_OFFSET 0x10 942520Sdg#define ED_NOVELL_IO_PORTS 32 943520Sdg 944520Sdg/* 945520Sdg * Remote DMA data register; for reading or writing to the NIC mem 946520Sdg * via programmed I/O (offset from ASIC base) 947520Sdg */ 948520Sdg#define ED_NOVELL_DATA 0x00 949520Sdg 950520Sdg/* 951520Sdg * Reset register; reading from this register causes a board reset 952520Sdg */ 953520Sdg#define ED_NOVELL_RESET 0x0f 95411016Sphk 95511016Sphk/* 95611016Sphk * Definitions for PCCARD 95711016Sphk */ 95811016Sphk#define ED_PC_PAGE_OFFSET 0x40 /* page offset for NIC access to mem */ 95911016Sphk#define ED_PC_IO_PORTS 32 96050808Skato#define ED_PC_ASIC_OFFSET 0x10 96150808Skato#define ED_PC_RESET 0x0f /* Reset(offset from ASIC base) */ 96250808Skato#define ED_PC_MISC 0x08 /* Misc (offset from ASIC base) */ 96311016Sphk 96411016Sphk/* 96511016Sphk * if_ze.h constants 96611016Sphk */ 96711016Sphk 96811016Sphk#define ZE_PAGE_OFFSET 0x40 /* mem buffer starts at 0x4000 */ 96911016Sphk 97011016Sphk#define ZE_DATA_IO 0x10 97111016Sphk#define ZE_MISC 0x18 97211016Sphk#define ZE_RESET 0x1F 97311016Sphk 97417465Sdg/* 97517465Sdg * Definitions for HP PC LAN Adapter Plus; based on the CRYNWR packet 97617465Sdg * driver for the card. 97717465Sdg */ 97817465Sdg 97917465Sdg#define ED_HPP_ASIC_OFFSET 0x00 /* Offset to ASIC registers */ 98017465Sdg#define ED_HPP_NIC_OFFSET 0x10 /* Offset to 8390 registers */ 98117465Sdg 98217465Sdg#define ED_HPP_ID 0x00 /* ID register, always 0x4850 */ 98317465Sdg#define ED_HPP_PAGING 0x02 /* Page select register */ 98417465Sdg#define ED_HPP_OPTION 0x04 /* Bitmask of supported options */ 98517465Sdg#define ED_HPP_PAGE_0 0x08 /* Page 0 */ 98617465Sdg#define ED_HPP_PAGE_2 0x0A /* Page 2 */ 98717465Sdg#define ED_HPP_PAGE_4 0x0C /* Page 4 */ 98817465Sdg#define ED_HPP_PAGE_6 0x0E /* Page 6 */ 98917465Sdg 99017465Sdg/* PERF PAGE */ 99117465Sdg#define ED_HPP_OUT_ADDR ED_HPP_PAGE_0 /* I/O output location */ 99217465Sdg#define ED_HPP_IN_ADDR ED_HPP_PAGE_2 /* I/O input location */ 99317465Sdg#define ED_HPP_DATAPORT ED_HPP_PAGE_4 /* I/O data transfer */ 99417465Sdg/* MAC PAGE */ 99517465Sdg#define ED_HPP_MAC_ADDR 0x08 /* Offset of MAC address in MAC page */ 99617465Sdg 99717465Sdg#define ED_HPP_IO_PORTS 32 /* Number of IO ports */ 99817465Sdg 99917465Sdg#define ED_HPP_TX_PAGE_OFFSET 0x00 /* first page of TX buffer */ 100017465Sdg#define ED_HPP_RX_PAGE_START 0x06 /* start at page 6 */ 100117465Sdg#define ED_HPP_RX_PAGE_STOP 0x80 /* end at page 128 */ 100217465Sdg 100317465Sdg/* 100417465Sdg * Register pages supported. 100517465Sdg */ 100617465Sdg 100717465Sdg#define ED_HPP_PAGE_PERF 0 /* Normal operation */ 100817465Sdg#define ED_HPP_PAGE_MAC 1 /* The ethernet address and checksum */ 100917465Sdg#define ED_HPP_PAGE_HW 2 /* Hardware parameters in EEPROM */ 101017465Sdg#define ED_HPP_PAGE_LAN 4 /* Transciever selection etc */ 101117465Sdg#define ED_HPP_PAGE_ID 6 /* ID */ 101217465Sdg 101317465Sdg/* 101417465Sdg * Options supported. 101517465Sdg */ 101617465Sdg 101717465Sdg#define ED_HPP_OPTION_NIC_RESET 0x0001 /* active low */ 101817465Sdg#define ED_HPP_OPTION_CHIP_RESET 0x0002 /* active low */ 101917465Sdg#define ED_HPP_OPTION_ENABLE_IRQ 0x0004 102017465Sdg#define ED_HPP_OPTION_FAKE_INTR 0x0008 102117465Sdg#define ED_HPP_OPTION_BOOT_ROM_ENB 0x0010 102217465Sdg#define ED_HPP_OPTION_IO_ENB 0x0020 102317465Sdg#define ED_HPP_OPTION_MEM_ENABLE 0x0040 102417465Sdg#define ED_HPP_OPTION_ZERO_WAIT 0x0080 102517465Sdg#define ED_HPP_OPTION_MEM_DISABLE 0x1000 102617465Sdg 102717465Sdg/* 102817465Sdg * Page ID configuration. 102917465Sdg */ 103017465Sdg 103117465Sdg#define ED_HPP_ID_REVISION_MASK 0x0300 /* revision id */ 103217465Sdg#define ED_HPP_ID_SOFT_MODEL_MASK 0xFC00 /* soft model number */ 103317465Sdg#define ED_HPP_ID_16_BIT_ACCESS 0x0010 /* if set use 16 bit accesses */ 103417465Sdg#define ED_HPP_ID_TWISTED_PAIR 0x0040 103517465Sdg 103617465Sdg/* 103717465Sdg * Hardware configuration. 103817465Sdg */ 103917465Sdg 104017465Sdg#define ED_HPP_HW_MEM_MAP 0x09 /* low mem map location in HW page */ 104117465Sdg#define ED_HPP_HW_ID 0x0C /* revision number, capabilities */ 104217465Sdg#define ED_HPP_HW_IRQ 0x0D /* IRQ channel register in HW page */ 104317465Sdg#define ED_HPP_HW_WRAP 0x0E /* mem wrap page for rcv */ 104417465Sdg 104517465Sdg/* 104617465Sdg * Lan configuration 104717465Sdg */ 104817465Sdg 104917465Sdg#define ED_HPP_LAN_AUI 0x01 /* Use AUI */ 105017465Sdg#define ED_HPP_LAN_TL 0x40 /* Don't use AUI */ 105117465Sdg 105217465Sdg/* 105317465Sdg * Card types. 105417465Sdg */ 105517465Sdg 105617465Sdg#define ED_TYPE_HP_PCLANPLUS 0x00 105763775Stanimura 105863775Stanimura/* 1059121118Sshiba * Definitions for Allied-Telesis SIC 1060121118Sshiba */ 1061121118Sshiba#define ED_SIC_NIC_OFFSET 0 1062121118Sshiba#define ED_SIC_ASIC_OFFSET 0x10 /* offset to nic i/o regs */ 1063121118Sshiba 1064121118Sshiba#define ED_SIC_IO_PORTS 17 /* # of i/o addresses used */ 1065121118Sshiba 1066121118Sshiba/* 106763775Stanimura * Chip types. 106863775Stanimura */ 1069190811Simp#define ED_CHIP_TYPE_AX88190 0 1070190811Simp#define ED_CHIP_TYPE_AX88790 1 1071190811Simp#define ED_CHIP_TYPE_DL10019 2 1072190811Simp#define ED_CHIP_TYPE_DL10022 3 1073190811Simp#define ED_CHIP_TYPE_DP8390 4 1074190811Simp#define ED_CHIP_TYPE_NS83903 5 1075190811Simp#define ED_CHIP_TYPE_NS83926 6 1076190811Simp#define ED_CHIP_TYPE_RTL8019 7 1077190811Simp#define ED_CHIP_TYPE_RTL8029 8 1078190811Simp#define ED_CHIP_TYPE_TC3299 9 1079190811Simp#define ED_CHIP_TYPE_TC5299J 10 1080190811Simp#define ED_CHIP_TYPE_W89C926 11 1081190811Simp#define ED_CHIP_TYPE_WD790 12 1082