1205869Sjfv/****************************************************************************** 2205869Sjfv 3294958Smarius Copyright (c) 2001-2015, Intel Corporation 4205869Sjfv All rights reserved. 5205869Sjfv 6205869Sjfv Redistribution and use in source and binary forms, with or without 7205869Sjfv modification, are permitted provided that the following conditions are met: 8205869Sjfv 9205869Sjfv 1. Redistributions of source code must retain the above copyright notice, 10205869Sjfv this list of conditions and the following disclaimer. 11205869Sjfv 12205869Sjfv 2. Redistributions in binary form must reproduce the above copyright 13205869Sjfv notice, this list of conditions and the following disclaimer in the 14205869Sjfv documentation and/or other materials provided with the distribution. 15205869Sjfv 16205869Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17205869Sjfv contributors may be used to endorse or promote products derived from 18205869Sjfv this software without specific prior written permission. 19205869Sjfv 20205869Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21205869Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22205869Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23205869Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24205869Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25205869Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26205869Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27205869Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28205869Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29205869Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30205869Sjfv POSSIBILITY OF SUCH DAMAGE. 31205869Sjfv 32205869Sjfv******************************************************************************/ 33205869Sjfv/*$FreeBSD: stable/10/sys/dev/e1000/if_lem.h 342790 2019-01-05 19:35:10Z marius $*/ 34205869Sjfv 35205869Sjfv 36205869Sjfv#ifndef _LEM_H_DEFINED_ 37205869Sjfv#define _LEM_H_DEFINED_ 38205869Sjfv 39205869Sjfv 40205869Sjfv/* Tunables */ 41205869Sjfv 42205869Sjfv/* 43205869Sjfv * EM_TXD: Maximum number of Transmit Descriptors 44205869Sjfv * Valid Range: 80-256 for 82542 and 82543-based adapters 45205869Sjfv * 80-4096 for others 46205869Sjfv * Default Value: 256 47205869Sjfv * This value is the number of transmit descriptors allocated by the driver. 48205869Sjfv * Increasing this value allows the driver to queue more transmits. Each 49205869Sjfv * descriptor is 16 bytes. 50205869Sjfv * Since TDLEN should be multiple of 128bytes, the number of transmit 51205869Sjfv * desscriptors should meet the following condition. 52205869Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 53205869Sjfv */ 54205869Sjfv#define EM_MIN_TXD 80 55205869Sjfv#define EM_MAX_TXD_82543 256 56205869Sjfv#define EM_MAX_TXD 4096 57205869Sjfv#define EM_DEFAULT_TXD EM_MAX_TXD_82543 58205869Sjfv 59205869Sjfv/* 60205869Sjfv * EM_RXD - Maximum number of receive Descriptors 61205869Sjfv * Valid Range: 80-256 for 82542 and 82543-based adapters 62205869Sjfv * 80-4096 for others 63205869Sjfv * Default Value: 256 64205869Sjfv * This value is the number of receive descriptors allocated by the driver. 65205869Sjfv * Increasing this value allows the driver to buffer more incoming packets. 66205869Sjfv * Each descriptor is 16 bytes. A receive buffer is also allocated for each 67205869Sjfv * descriptor. The maximum MTU size is 16110. 68205869Sjfv * Since TDLEN should be multiple of 128bytes, the number of transmit 69205869Sjfv * desscriptors should meet the following condition. 70205869Sjfv * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 71205869Sjfv */ 72205869Sjfv#define EM_MIN_RXD 80 73205869Sjfv#define EM_MAX_RXD_82543 256 74205869Sjfv#define EM_MAX_RXD 4096 75205869Sjfv#define EM_DEFAULT_RXD EM_MAX_RXD_82543 76205869Sjfv 77205869Sjfv/* 78205869Sjfv * EM_TIDV - Transmit Interrupt Delay Value 79205869Sjfv * Valid Range: 0-65535 (0=off) 80205869Sjfv * Default Value: 64 81205869Sjfv * This value delays the generation of transmit interrupts in units of 82205869Sjfv * 1.024 microseconds. Transmit interrupt reduction can improve CPU 83205869Sjfv * efficiency if properly tuned for specific network traffic. If the 84205869Sjfv * system is reporting dropped transmits, this value may be set too high 85205869Sjfv * causing the driver to run out of available transmit descriptors. 86205869Sjfv */ 87205869Sjfv#define EM_TIDV 64 88205869Sjfv 89205869Sjfv/* 90205869Sjfv * EM_TADV - Transmit Absolute Interrupt Delay Value 91205869Sjfv * (Not valid for 82542/82543/82544) 92205869Sjfv * Valid Range: 0-65535 (0=off) 93205869Sjfv * Default Value: 64 94205869Sjfv * This value, in units of 1.024 microseconds, limits the delay in which a 95205869Sjfv * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 96205869Sjfv * this value ensures that an interrupt is generated after the initial 97205869Sjfv * packet is sent on the wire within the set amount of time. Proper tuning, 98205869Sjfv * along with EM_TIDV, may improve traffic throughput in specific 99205869Sjfv * network conditions. 100205869Sjfv */ 101205869Sjfv#define EM_TADV 64 102205869Sjfv 103205869Sjfv/* 104205869Sjfv * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 105205869Sjfv * Valid Range: 0-65535 (0=off) 106205869Sjfv * Default Value: 0 107205869Sjfv * This value delays the generation of receive interrupts in units of 1.024 108205869Sjfv * microseconds. Receive interrupt reduction can improve CPU efficiency if 109205869Sjfv * properly tuned for specific network traffic. Increasing this value adds 110205869Sjfv * extra latency to frame reception and can end up decreasing the throughput 111205869Sjfv * of TCP traffic. If the system is reporting dropped receives, this value 112205869Sjfv * may be set too high, causing the driver to run out of available receive 113205869Sjfv * descriptors. 114205869Sjfv * 115205869Sjfv * CAUTION: When setting EM_RDTR to a value other than 0, adapters 116205869Sjfv * may hang (stop transmitting) under certain network conditions. 117205869Sjfv * If this occurs a WATCHDOG message is logged in the system 118205869Sjfv * event log. In addition, the controller is automatically reset, 119205869Sjfv * restoring the network connection. To eliminate the potential 120205869Sjfv * for the hang ensure that EM_RDTR is set to 0. 121205869Sjfv */ 122205869Sjfv#define EM_RDTR 0 123205869Sjfv 124205869Sjfv/* 125205869Sjfv * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 126205869Sjfv * Valid Range: 0-65535 (0=off) 127205869Sjfv * Default Value: 64 128205869Sjfv * This value, in units of 1.024 microseconds, limits the delay in which a 129205869Sjfv * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 130205869Sjfv * this value ensures that an interrupt is generated after the initial 131205869Sjfv * packet is received within the set amount of time. Proper tuning, 132205869Sjfv * along with EM_RDTR, may improve traffic throughput in specific network 133205869Sjfv * conditions. 134205869Sjfv */ 135205869Sjfv#define EM_RADV 64 136205869Sjfv 137205869Sjfv/* 138205869Sjfv * This parameter controls the max duration of transmit watchdog. 139205869Sjfv */ 140205869Sjfv#define EM_WATCHDOG (10 * hz) 141205869Sjfv 142205869Sjfv/* 143205869Sjfv * This parameter controls when the driver calls the routine to reclaim 144205869Sjfv * transmit descriptors. 145205869Sjfv */ 146205869Sjfv#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 147205869Sjfv#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 148205869Sjfv 149205869Sjfv/* 150205869Sjfv * This parameter controls whether or not autonegotation is enabled. 151205869Sjfv * 0 - Disable autonegotiation 152205869Sjfv * 1 - Enable autonegotiation 153205869Sjfv */ 154205869Sjfv#define DO_AUTO_NEG 1 155205869Sjfv 156205869Sjfv/* 157205869Sjfv * This parameter control whether or not the driver will wait for 158205869Sjfv * autonegotiation to complete. 159205869Sjfv * 1 - Wait for autonegotiation to complete 160205869Sjfv * 0 - Don't wait for autonegotiation to complete 161205869Sjfv */ 162205869Sjfv#define WAIT_FOR_AUTO_NEG_DEFAULT 0 163205869Sjfv 164205869Sjfv/* Tunables -- End */ 165205869Sjfv 166205869Sjfv#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 167205869Sjfv ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 168205869Sjfv ADVERTISE_1000_FULL) 169205869Sjfv 170205869Sjfv#define AUTO_ALL_MODES 0 171205869Sjfv 172205869Sjfv/* PHY master/slave setting */ 173205869Sjfv#define EM_MASTER_SLAVE e1000_ms_hw_default 174205869Sjfv 175205869Sjfv/* 176205869Sjfv * Micellaneous constants 177205869Sjfv */ 178205869Sjfv#define EM_VENDOR_ID 0x8086 179205869Sjfv#define EM_FLASH 0x0014 180205869Sjfv 181205869Sjfv#define EM_JUMBO_PBA 0x00000028 182205869Sjfv#define EM_DEFAULT_PBA 0x00000030 183205869Sjfv#define EM_SMARTSPEED_DOWNSHIFT 3 184205869Sjfv#define EM_SMARTSPEED_MAX 15 185205869Sjfv#define EM_MAX_LOOP 10 186205869Sjfv 187205869Sjfv#define MAX_NUM_MULTICAST_ADDRESSES 128 188205869Sjfv#define PCI_ANY_ID (~0U) 189205869Sjfv#define ETHER_ALIGN 2 190205869Sjfv#define EM_FC_PAUSE_TIME 0x0680 191205869Sjfv#define EM_EEPROM_APME 0x400; 192205869Sjfv#define EM_82544_APME 0x0004; 193205869Sjfv 194205869Sjfv/* Code compatilbility between 6 and 7 */ 195205869Sjfv#ifndef ETHER_BPF_MTAP 196205869Sjfv#define ETHER_BPF_MTAP BPF_MTAP 197205869Sjfv#endif 198205869Sjfv 199205869Sjfv/* 200205869Sjfv * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 201205869Sjfv * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 202205869Sjfv * also optimize cache line size effect. H/W supports up to cache line size 128. 203205869Sjfv */ 204205869Sjfv#define EM_DBA_ALIGN 128 205205869Sjfv 206205869Sjfv#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 207205869Sjfv 208205869Sjfv/* PCI Config defines */ 209205869Sjfv#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 210205869Sjfv#define EM_BAR_TYPE_MASK 0x00000001 211205869Sjfv#define EM_BAR_TYPE_MMEM 0x00000000 212205869Sjfv#define EM_BAR_TYPE_IO 0x00000001 213205869Sjfv#define EM_BAR_TYPE_FLASH 0x0014 214205869Sjfv#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 215205869Sjfv#define EM_BAR_MEM_TYPE_MASK 0x00000006 216205869Sjfv#define EM_BAR_MEM_TYPE_32BIT 0x00000000 217205869Sjfv#define EM_BAR_MEM_TYPE_64BIT 0x00000004 218205869Sjfv#define EM_MSIX_BAR 3 /* On 82575 */ 219205869Sjfv 220228387Sjfv#if __FreeBSD_version < 900000 221219753Sjfv#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 222219753Sjfv#endif 223219753Sjfv 224205869Sjfv/* Defines for printing debug information */ 225205869Sjfv#define DEBUG_INIT 0 226205869Sjfv#define DEBUG_IOCTL 0 227205869Sjfv#define DEBUG_HW 0 228205869Sjfv 229205869Sjfv#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 230205869Sjfv#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 231205869Sjfv#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 232205869Sjfv#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 233205869Sjfv#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 234205869Sjfv#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 235205869Sjfv#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 236205869Sjfv#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 237205869Sjfv#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 238205869Sjfv 239296073Smarius#define EM_MAX_SCATTER 40 240205869Sjfv#define EM_VFTA_SIZE 128 241205869Sjfv#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 242205869Sjfv#define ETH_ZLEN 60 243205869Sjfv#define ETH_ADDR_LEN 6 244342790Smarius#define CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP) /* Offload bits in mbuf flag */ 245205869Sjfv 246205869Sjfv/* 247205869Sjfv * 82574 has a nonstandard address for EIAC 248205869Sjfv * and since its only used in MSIX, and in 249205869Sjfv * the em driver only 82574 uses MSIX we can 250205869Sjfv * solve it just using this define. 251205869Sjfv */ 252205869Sjfv#define EM_EIAC 0x000DC 253205869Sjfv 254205869Sjfv/* Used in for 82547 10Mb Half workaround */ 255205869Sjfv#define EM_PBA_BYTES_SHIFT 0xA 256205869Sjfv#define EM_TX_HEAD_ADDR_SHIFT 7 257205869Sjfv#define EM_PBA_TX_MASK 0xFFFF0000 258205869Sjfv#define EM_FIFO_HDR 0x10 259205869Sjfv#define EM_82547_PKT_THRESH 0x3e0 260205869Sjfv 261205869Sjfv/* Precision Time Sync (IEEE 1588) defines */ 262205869Sjfv#define ETHERTYPE_IEEE1588 0x88F7 263205869Sjfv#define PICOSECS_PER_TICK 20833 264205869Sjfv#define TSYNC_PORT 319 /* UDP port for the protocol */ 265205869Sjfv 266289386Sadrian#ifdef NIC_PARAVIRT 267294958Smarius#define E1000_PARA_SUBDEV 0x1101 /* special id */ 268294958Smarius#define E1000_CSBAL 0x02830 /* csb phys. addr. low */ 269294958Smarius#define E1000_CSBAH 0x02834 /* csb phys. addr. hi */ 270289386Sadrian#include <net/paravirt.h> 271294958Smarius#endif /* NIC_PARAVIRT */ 272289386Sadrian 273205869Sjfv/* 274205869Sjfv * Bus dma allocation structure used by 275205869Sjfv * e1000_dma_malloc and e1000_dma_free. 276205869Sjfv */ 277205869Sjfvstruct em_dma_alloc { 278205869Sjfv bus_addr_t dma_paddr; 279205869Sjfv caddr_t dma_vaddr; 280205869Sjfv bus_dma_tag_t dma_tag; 281205869Sjfv bus_dmamap_t dma_map; 282205869Sjfv bus_dma_segment_t dma_seg; 283205869Sjfv int dma_nseg; 284205869Sjfv}; 285205869Sjfv 286205869Sjfvstruct adapter; 287205869Sjfv 288205869Sjfvstruct em_int_delay_info { 289205869Sjfv struct adapter *adapter; /* Back-pointer to the adapter struct */ 290205869Sjfv int offset; /* Register offset to read/write */ 291205869Sjfv int value; /* Current value in usecs */ 292205869Sjfv}; 293205869Sjfv 294205869Sjfv/* Our adapter structure */ 295205869Sjfvstruct adapter { 296205869Sjfv struct ifnet *ifp; 297205869Sjfv struct e1000_hw hw; 298205869Sjfv 299205869Sjfv /* FreeBSD operating-system-specific structures. */ 300205869Sjfv struct e1000_osdep osdep; 301205869Sjfv struct device *dev; 302206001Smarius struct cdev *led_dev; 303205869Sjfv 304205869Sjfv struct resource *memory; 305205869Sjfv struct resource *flash; 306205869Sjfv struct resource *msix; 307205869Sjfv 308205869Sjfv struct resource *ioport; 309205869Sjfv int io_rid; 310205869Sjfv 311205869Sjfv /* 82574 may use 3 int vectors */ 312205869Sjfv struct resource *res[3]; 313205869Sjfv void *tag[3]; 314205869Sjfv int rid[3]; 315205869Sjfv 316205869Sjfv struct ifmedia media; 317205869Sjfv struct callout timer; 318205869Sjfv struct callout tx_fifo_timer; 319205869Sjfv bool watchdog_check; 320205869Sjfv int watchdog_time; 321205869Sjfv int msi; 322205869Sjfv int if_flags; 323205869Sjfv int max_frame_size; 324205869Sjfv int min_frame_size; 325205869Sjfv struct mtx core_mtx; 326205869Sjfv struct mtx tx_mtx; 327205869Sjfv struct mtx rx_mtx; 328205869Sjfv int em_insert_vlan_header; 329205869Sjfv 330205869Sjfv /* Task for FAST handling */ 331205869Sjfv struct task link_task; 332205869Sjfv struct task rxtx_task; 333205869Sjfv struct task rx_task; 334205869Sjfv struct task tx_task; 335205869Sjfv struct taskqueue *tq; /* private task queue */ 336205869Sjfv 337205869Sjfv eventhandler_tag vlan_attach; 338205869Sjfv eventhandler_tag vlan_detach; 339205869Sjfv u32 num_vlans; 340205869Sjfv 341205869Sjfv /* Management and WOL features */ 342205869Sjfv u32 wol; 343205869Sjfv bool has_manage; 344205869Sjfv bool has_amt; 345205869Sjfv 346211913Syongari /* Multicast array memory */ 347211913Syongari u8 *mta; 348214646Sjfv 349214646Sjfv /* 350214646Sjfv ** Shadow VFTA table, this is needed because 351214646Sjfv ** the real vlan filter table gets cleared during 352214646Sjfv ** a soft reset and the driver needs to be able 353214646Sjfv ** to repopulate it. 354214646Sjfv */ 355214646Sjfv u32 shadow_vfta[EM_VFTA_SIZE]; 356214646Sjfv 357214646Sjfv /* Info about the interface */ 358205869Sjfv uint8_t link_active; 359205869Sjfv uint16_t link_speed; 360205869Sjfv uint16_t link_duplex; 361205869Sjfv uint32_t smartspeed; 362214646Sjfv uint32_t fc_setting; 363214646Sjfv 364205869Sjfv struct em_int_delay_info tx_int_delay; 365205869Sjfv struct em_int_delay_info tx_abs_int_delay; 366205869Sjfv struct em_int_delay_info rx_int_delay; 367205869Sjfv struct em_int_delay_info rx_abs_int_delay; 368250414Sluigi struct em_int_delay_info tx_itr; 369205869Sjfv 370205869Sjfv /* 371205869Sjfv * Transmit definitions 372205869Sjfv * 373205869Sjfv * We have an array of num_tx_desc descriptors (handled 374205869Sjfv * by the controller) paired with an array of tx_buffers 375205869Sjfv * (at tx_buffer_area). 376205869Sjfv * The index of the next available descriptor is next_avail_tx_desc. 377205869Sjfv * The number of remaining tx_desc is num_tx_desc_avail. 378205869Sjfv */ 379205869Sjfv struct em_dma_alloc txdma; /* bus_dma glue for tx desc */ 380205869Sjfv struct e1000_tx_desc *tx_desc_base; 381205869Sjfv uint32_t next_avail_tx_desc; 382205869Sjfv uint32_t next_tx_to_clean; 383205869Sjfv volatile uint16_t num_tx_desc_avail; 384205869Sjfv uint16_t num_tx_desc; 385205869Sjfv uint16_t last_hw_offload; 386205869Sjfv uint32_t txd_cmd; 387205869Sjfv struct em_buffer *tx_buffer_area; 388205869Sjfv bus_dma_tag_t txtag; /* dma tag for tx */ 389205869Sjfv uint32_t tx_tso; /* last tx was tso */ 390205869Sjfv 391205869Sjfv /* 392205869Sjfv * Receive definitions 393205869Sjfv * 394205869Sjfv * we have an array of num_rx_desc rx_desc (handled by the 395205869Sjfv * controller), and paired with an array of rx_buffers 396205869Sjfv * (at rx_buffer_area). 397205869Sjfv * The next pair to check on receive is at offset next_rx_desc_to_check 398205869Sjfv */ 399205869Sjfv struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */ 400205869Sjfv struct e1000_rx_desc *rx_desc_base; 401205869Sjfv uint32_t next_rx_desc_to_check; 402205869Sjfv uint32_t rx_buffer_len; 403205869Sjfv uint16_t num_rx_desc; 404205869Sjfv int rx_process_limit; 405205869Sjfv struct em_buffer *rx_buffer_area; 406205869Sjfv bus_dma_tag_t rxtag; 407205869Sjfv bus_dmamap_t rx_sparemap; 408205869Sjfv 409205869Sjfv /* 410205869Sjfv * First/last mbuf pointers, for 411205869Sjfv * collecting multisegment RX packets. 412205869Sjfv */ 413205869Sjfv struct mbuf *fmp; 414205869Sjfv struct mbuf *lmp; 415205869Sjfv 416205869Sjfv /* Misc stats maintained by the driver */ 417205869Sjfv unsigned long dropped_pkts; 418294958Smarius unsigned long link_irq; 419205869Sjfv unsigned long mbuf_cluster_failed; 420294958Smarius unsigned long mbuf_defrag_failed; 421205869Sjfv unsigned long no_tx_desc_avail1; 422205869Sjfv unsigned long no_tx_desc_avail2; 423294958Smarius unsigned long no_tx_dma_setup; 424205869Sjfv unsigned long no_tx_map_avail; 425205869Sjfv unsigned long watchdog_events; 426294958Smarius unsigned long rx_irq; 427205869Sjfv unsigned long rx_overruns; 428214646Sjfv unsigned long tx_irq; 429205869Sjfv 430205869Sjfv /* 82547 workaround */ 431205869Sjfv uint32_t tx_fifo_size; 432205869Sjfv uint32_t tx_fifo_head; 433205869Sjfv uint32_t tx_fifo_head_addr; 434205869Sjfv uint64_t tx_fifo_reset_cnt; 435205869Sjfv uint64_t tx_fifo_wrk_cnt; 436205869Sjfv uint32_t tx_head_addr; 437205869Sjfv 438205869Sjfv /* For 82544 PCIX Workaround */ 439205869Sjfv boolean_t pcix_82544; 440205869Sjfv boolean_t in_detach; 441205869Sjfv 442294958Smarius#ifdef NIC_SEND_COMBINING 443294958Smarius /* 0 = idle; 1xxxx int-pending; 3xxxx int + d pending + tdt */ 444294958Smarius#define MIT_PENDING_INT 0x10000 /* pending interrupt */ 445294958Smarius#define MIT_PENDING_TDT 0x30000 /* both intr and tdt write are pending */ 446294958Smarius uint32_t shadow_tdt; 447294958Smarius uint32_t sc_enable; 448294958Smarius#endif /* NIC_SEND_COMBINING */ 449294958Smarius#ifdef BATCH_DISPATCH 450294958Smarius uint32_t batch_enable; 451294958Smarius#endif /* BATCH_DISPATCH */ 452294958Smarius 453289386Sadrian#ifdef NIC_PARAVIRT 454294958Smarius struct em_dma_alloc csb_mem; /* phys address */ 455294958Smarius struct paravirt_csb *csb; /* virtual addr */ 456294958Smarius uint32_t rx_retries; /* optimize rx loop */ 457294958Smarius uint32_t tdt_csb_count;// XXX stat 458294958Smarius uint32_t tdt_reg_count;// XXX stat 459294958Smarius uint32_t tdt_int_count;// XXX stat 460294958Smarius uint32_t guest_need_kick_count;// XXX stat 461294958Smarius#endif /* NIC_PARAVIRT */ 462205869Sjfv 463205869Sjfv struct e1000_hw_stats stats; 464205869Sjfv}; 465205869Sjfv 466205869Sjfv/* ****************************************************************************** 467205869Sjfv * vendor_info_array 468205869Sjfv * 469205869Sjfv * This array contains the list of Subvendor/Subdevice IDs on which the driver 470205869Sjfv * should load. 471205869Sjfv * 472205869Sjfv * ******************************************************************************/ 473205869Sjfvtypedef struct _em_vendor_info_t { 474205869Sjfv unsigned int vendor_id; 475205869Sjfv unsigned int device_id; 476205869Sjfv unsigned int subvendor_id; 477205869Sjfv unsigned int subdevice_id; 478205869Sjfv unsigned int index; 479205869Sjfv} em_vendor_info_t; 480205869Sjfv 481205869Sjfvstruct em_buffer { 482205869Sjfv int next_eop; /* Index of the desc to watch */ 483205869Sjfv struct mbuf *m_head; 484205869Sjfv bus_dmamap_t map; /* bus_dma map for packet */ 485205869Sjfv}; 486205869Sjfv 487205869Sjfv/* For 82544 PCIX Workaround */ 488205869Sjfvtypedef struct _ADDRESS_LENGTH_PAIR 489205869Sjfv{ 490205869Sjfv uint64_t address; 491205869Sjfv uint32_t length; 492205869Sjfv} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR; 493205869Sjfv 494205869Sjfvtypedef struct _DESCRIPTOR_PAIR 495205869Sjfv{ 496205869Sjfv ADDRESS_LENGTH_PAIR descriptor[4]; 497205869Sjfv uint32_t elements; 498205869Sjfv} DESC_ARRAY, *PDESC_ARRAY; 499205869Sjfv 500205869Sjfv#define EM_CORE_LOCK_INIT(_sc, _name) \ 501205869Sjfv mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 502205869Sjfv#define EM_TX_LOCK_INIT(_sc, _name) \ 503205869Sjfv mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 504205869Sjfv#define EM_RX_LOCK_INIT(_sc, _name) \ 505205869Sjfv mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF) 506205869Sjfv#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 507205869Sjfv#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 508205869Sjfv#define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 509205869Sjfv#define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 510205869Sjfv#define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 511205869Sjfv#define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 512205869Sjfv#define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 513205869Sjfv#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 514205869Sjfv#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 515205869Sjfv#define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 516205869Sjfv#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 517205869Sjfv#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 518205869Sjfv 519205869Sjfv#endif /* _LEM_H_DEFINED_ */ 520