1177867Sjfv/****************************************************************************** 2169240Sjfv 3294958Smarius Copyright (c) 2001-2015, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: stable/10/sys/dev/e1000/e1000_phy.c 333216 2018-05-03 15:47:49Z marius $*/ 34169240Sjfv 35169589Sjfv#include "e1000_api.h" 36169240Sjfv 37247064Sjfvstatic s32 e1000_wait_autoneg(struct e1000_hw *hw); 38185353Sjfvstatic s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39228386Sjfv u16 *data, bool read, bool page_set); 40194865Sjfvstatic u32 e1000_get_phy_addr_for_hv_page(u32 page); 41194865Sjfvstatic s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42228386Sjfv u16 *data, bool read); 43194865Sjfv 44169240Sjfv/* Cable length tables */ 45218530Sjfvstatic const u16 e1000_m88_cable_length_table[] = { 46218530Sjfv 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47169240Sjfv#define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48228386Sjfv (sizeof(e1000_m88_cable_length_table) / \ 49228386Sjfv sizeof(e1000_m88_cable_length_table[0])) 50169240Sjfv 51218530Sjfvstatic const u16 e1000_igp_2_cable_length_table[] = { 52218530Sjfv 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 53218530Sjfv 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 54218530Sjfv 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 55218530Sjfv 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 56218530Sjfv 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 57218530Sjfv 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 58218530Sjfv 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 59218530Sjfv 124}; 60169240Sjfv#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61228386Sjfv (sizeof(e1000_igp_2_cable_length_table) / \ 62228386Sjfv sizeof(e1000_igp_2_cable_length_table[0])) 63169240Sjfv 64169240Sjfv/** 65177867Sjfv * e1000_init_phy_ops_generic - Initialize PHY function pointers 66177867Sjfv * @hw: pointer to the HW structure 67177867Sjfv * 68177867Sjfv * Setups up the function pointers to no-op functions 69177867Sjfv **/ 70177867Sjfvvoid e1000_init_phy_ops_generic(struct e1000_hw *hw) 71177867Sjfv{ 72177867Sjfv struct e1000_phy_info *phy = &hw->phy; 73177867Sjfv DEBUGFUNC("e1000_init_phy_ops_generic"); 74177867Sjfv 75177867Sjfv /* Initialize function pointers */ 76177867Sjfv phy->ops.init_params = e1000_null_ops_generic; 77177867Sjfv phy->ops.acquire = e1000_null_ops_generic; 78177867Sjfv phy->ops.check_polarity = e1000_null_ops_generic; 79177867Sjfv phy->ops.check_reset_block = e1000_null_ops_generic; 80177867Sjfv phy->ops.commit = e1000_null_ops_generic; 81177867Sjfv phy->ops.force_speed_duplex = e1000_null_ops_generic; 82177867Sjfv phy->ops.get_cfg_done = e1000_null_ops_generic; 83177867Sjfv phy->ops.get_cable_length = e1000_null_ops_generic; 84177867Sjfv phy->ops.get_info = e1000_null_ops_generic; 85228386Sjfv phy->ops.set_page = e1000_null_set_page; 86177867Sjfv phy->ops.read_reg = e1000_null_read_reg; 87200243Sjfv phy->ops.read_reg_locked = e1000_null_read_reg; 88228386Sjfv phy->ops.read_reg_page = e1000_null_read_reg; 89177867Sjfv phy->ops.release = e1000_null_phy_generic; 90177867Sjfv phy->ops.reset = e1000_null_ops_generic; 91177867Sjfv phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 92177867Sjfv phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 93177867Sjfv phy->ops.write_reg = e1000_null_write_reg; 94200243Sjfv phy->ops.write_reg_locked = e1000_null_write_reg; 95228386Sjfv phy->ops.write_reg_page = e1000_null_write_reg; 96177867Sjfv phy->ops.power_up = e1000_null_phy_generic; 97177867Sjfv phy->ops.power_down = e1000_null_phy_generic; 98238148Sjfv phy->ops.read_i2c_byte = e1000_read_i2c_byte_null; 99238148Sjfv phy->ops.write_i2c_byte = e1000_write_i2c_byte_null; 100185353Sjfv phy->ops.cfg_on_link_up = e1000_null_ops_generic; 101177867Sjfv} 102177867Sjfv 103177867Sjfv/** 104228386Sjfv * e1000_null_set_page - No-op function, return 0 105228386Sjfv * @hw: pointer to the HW structure 106228386Sjfv **/ 107256200Sjfvs32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw, 108256200Sjfv u16 E1000_UNUSEDARG data) 109228386Sjfv{ 110228386Sjfv DEBUGFUNC("e1000_null_set_page"); 111228386Sjfv return E1000_SUCCESS; 112228386Sjfv} 113228386Sjfv 114228386Sjfv/** 115177867Sjfv * e1000_null_read_reg - No-op function, return 0 116177867Sjfv * @hw: pointer to the HW structure 117177867Sjfv **/ 118256200Sjfvs32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw, 119256200Sjfv u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data) 120177867Sjfv{ 121177867Sjfv DEBUGFUNC("e1000_null_read_reg"); 122177867Sjfv return E1000_SUCCESS; 123177867Sjfv} 124177867Sjfv 125177867Sjfv/** 126177867Sjfv * e1000_null_phy_generic - No-op function, return void 127177867Sjfv * @hw: pointer to the HW structure 128177867Sjfv **/ 129256200Sjfvvoid e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw) 130177867Sjfv{ 131177867Sjfv DEBUGFUNC("e1000_null_phy_generic"); 132177867Sjfv return; 133177867Sjfv} 134177867Sjfv 135177867Sjfv/** 136177867Sjfv * e1000_null_lplu_state - No-op function, return 0 137177867Sjfv * @hw: pointer to the HW structure 138177867Sjfv **/ 139256200Sjfvs32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw, 140256200Sjfv bool E1000_UNUSEDARG active) 141177867Sjfv{ 142177867Sjfv DEBUGFUNC("e1000_null_lplu_state"); 143177867Sjfv return E1000_SUCCESS; 144177867Sjfv} 145177867Sjfv 146177867Sjfv/** 147177867Sjfv * e1000_null_write_reg - No-op function, return 0 148177867Sjfv * @hw: pointer to the HW structure 149177867Sjfv **/ 150256200Sjfvs32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw, 151256200Sjfv u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data) 152177867Sjfv{ 153177867Sjfv DEBUGFUNC("e1000_null_write_reg"); 154177867Sjfv return E1000_SUCCESS; 155177867Sjfv} 156177867Sjfv 157177867Sjfv/** 158238148Sjfv * e1000_read_i2c_byte_null - No-op function, return 0 159238148Sjfv * @hw: pointer to hardware structure 160238148Sjfv * @byte_offset: byte offset to write 161238148Sjfv * @dev_addr: device address 162238148Sjfv * @data: data value read 163238148Sjfv * 164238148Sjfv **/ 165256200Sjfvs32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw, 166256200Sjfv u8 E1000_UNUSEDARG byte_offset, 167256200Sjfv u8 E1000_UNUSEDARG dev_addr, 168256200Sjfv u8 E1000_UNUSEDARG *data) 169238148Sjfv{ 170238148Sjfv DEBUGFUNC("e1000_read_i2c_byte_null"); 171238148Sjfv return E1000_SUCCESS; 172238148Sjfv} 173238148Sjfv 174238148Sjfv/** 175238148Sjfv * e1000_write_i2c_byte_null - No-op function, return 0 176238148Sjfv * @hw: pointer to hardware structure 177238148Sjfv * @byte_offset: byte offset to write 178238148Sjfv * @dev_addr: device address 179238148Sjfv * @data: data value to write 180238148Sjfv * 181238148Sjfv **/ 182256200Sjfvs32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw, 183256200Sjfv u8 E1000_UNUSEDARG byte_offset, 184256200Sjfv u8 E1000_UNUSEDARG dev_addr, 185256200Sjfv u8 E1000_UNUSEDARG data) 186238148Sjfv{ 187238148Sjfv DEBUGFUNC("e1000_write_i2c_byte_null"); 188238148Sjfv return E1000_SUCCESS; 189238148Sjfv} 190238148Sjfv 191238148Sjfv/** 192169240Sjfv * e1000_check_reset_block_generic - Check if PHY reset is blocked 193169589Sjfv * @hw: pointer to the HW structure 194169240Sjfv * 195169240Sjfv * Read the PHY management control register and check whether a PHY reset 196169240Sjfv * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 197169240Sjfv * return E1000_BLK_PHY_RESET (12). 198169240Sjfv **/ 199173788Sjfvs32 e1000_check_reset_block_generic(struct e1000_hw *hw) 200169240Sjfv{ 201169240Sjfv u32 manc; 202169240Sjfv 203169240Sjfv DEBUGFUNC("e1000_check_reset_block"); 204169240Sjfv 205169240Sjfv manc = E1000_READ_REG(hw, E1000_MANC); 206169240Sjfv 207169240Sjfv return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 208169240Sjfv E1000_BLK_PHY_RESET : E1000_SUCCESS; 209169240Sjfv} 210169240Sjfv 211169240Sjfv/** 212169240Sjfv * e1000_get_phy_id - Retrieve the PHY ID and revision 213169589Sjfv * @hw: pointer to the HW structure 214169240Sjfv * 215169240Sjfv * Reads the PHY registers and stores the PHY ID and possibly the PHY 216169240Sjfv * revision in the hardware structure. 217169240Sjfv **/ 218173788Sjfvs32 e1000_get_phy_id(struct e1000_hw *hw) 219169240Sjfv{ 220169240Sjfv struct e1000_phy_info *phy = &hw->phy; 221169240Sjfv s32 ret_val = E1000_SUCCESS; 222169240Sjfv u16 phy_id; 223194865Sjfv u16 retry_count = 0; 224169240Sjfv 225169240Sjfv DEBUGFUNC("e1000_get_phy_id"); 226169240Sjfv 227238148Sjfv if (!phy->ops.read_reg) 228238148Sjfv return E1000_SUCCESS; 229177867Sjfv 230194865Sjfv while (retry_count < 2) { 231194865Sjfv ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 232194865Sjfv if (ret_val) 233238148Sjfv return ret_val; 234169240Sjfv 235194865Sjfv phy->id = (u32)(phy_id << 16); 236194865Sjfv usec_delay(20); 237194865Sjfv ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 238194865Sjfv if (ret_val) 239238148Sjfv return ret_val; 240169240Sjfv 241194865Sjfv phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 242194865Sjfv phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 243169240Sjfv 244194865Sjfv if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 245238148Sjfv return E1000_SUCCESS; 246194865Sjfv 247194865Sjfv retry_count++; 248194865Sjfv } 249238148Sjfv 250238148Sjfv return E1000_SUCCESS; 251169240Sjfv} 252169240Sjfv 253169240Sjfv/** 254169240Sjfv * e1000_phy_reset_dsp_generic - Reset PHY DSP 255169589Sjfv * @hw: pointer to the HW structure 256169240Sjfv * 257169240Sjfv * Reset the digital signal processor. 258169240Sjfv **/ 259173788Sjfvs32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 260169240Sjfv{ 261238148Sjfv s32 ret_val; 262169240Sjfv 263169240Sjfv DEBUGFUNC("e1000_phy_reset_dsp_generic"); 264169240Sjfv 265238148Sjfv if (!hw->phy.ops.write_reg) 266238148Sjfv return E1000_SUCCESS; 267177867Sjfv 268177867Sjfv ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 269169240Sjfv if (ret_val) 270238148Sjfv return ret_val; 271169240Sjfv 272238148Sjfv return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 273169240Sjfv} 274169240Sjfv 275169240Sjfv/** 276169240Sjfv * e1000_read_phy_reg_mdic - Read MDI control register 277169589Sjfv * @hw: pointer to the HW structure 278169589Sjfv * @offset: register offset to be read 279169589Sjfv * @data: pointer to the read data 280169240Sjfv * 281176667Sjfv * Reads the MDI control register in the PHY at offset and stores the 282169240Sjfv * information read to data. 283169240Sjfv **/ 284176667Sjfvs32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 285169240Sjfv{ 286169240Sjfv struct e1000_phy_info *phy = &hw->phy; 287169240Sjfv u32 i, mdic = 0; 288169240Sjfv 289169240Sjfv DEBUGFUNC("e1000_read_phy_reg_mdic"); 290169240Sjfv 291203049Sjfv if (offset > MAX_PHY_REG_ADDRESS) { 292203049Sjfv DEBUGOUT1("PHY Address %d is out of range\n", offset); 293203049Sjfv return -E1000_ERR_PARAM; 294203049Sjfv } 295203049Sjfv 296247064Sjfv /* Set up Op-code, Phy Address, and register offset in the MDI 297169240Sjfv * Control register. The MAC will take care of interfacing with the 298169240Sjfv * PHY to retrieve the desired data. 299169240Sjfv */ 300169240Sjfv mdic = ((offset << E1000_MDIC_REG_SHIFT) | 301228386Sjfv (phy->addr << E1000_MDIC_PHY_SHIFT) | 302228386Sjfv (E1000_MDIC_OP_READ)); 303169240Sjfv 304169240Sjfv E1000_WRITE_REG(hw, E1000_MDIC, mdic); 305169240Sjfv 306247064Sjfv /* Poll the ready bit to see if the MDI read completed 307173788Sjfv * Increasing the time out as testing showed failures with 308173788Sjfv * the lower time out 309173788Sjfv */ 310173788Sjfv for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 311256200Sjfv usec_delay_irq(50); 312169240Sjfv mdic = E1000_READ_REG(hw, E1000_MDIC); 313169240Sjfv if (mdic & E1000_MDIC_READY) 314169240Sjfv break; 315169240Sjfv } 316169240Sjfv if (!(mdic & E1000_MDIC_READY)) { 317169240Sjfv DEBUGOUT("MDI Read did not complete\n"); 318238148Sjfv return -E1000_ERR_PHY; 319169240Sjfv } 320169240Sjfv if (mdic & E1000_MDIC_ERROR) { 321169240Sjfv DEBUGOUT("MDI Error\n"); 322238148Sjfv return -E1000_ERR_PHY; 323169240Sjfv } 324247064Sjfv if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 325247064Sjfv DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", 326247064Sjfv offset, 327247064Sjfv (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 328247064Sjfv return -E1000_ERR_PHY; 329247064Sjfv } 330169240Sjfv *data = (u16) mdic; 331218530Sjfv 332247064Sjfv /* Allow some time after each MDIC transaction to avoid 333213234Sjfv * reading duplicate data in the next MDIC transaction. 334213234Sjfv */ 335213234Sjfv if (hw->mac.type == e1000_pch2lan) 336256200Sjfv usec_delay_irq(100); 337169240Sjfv 338238148Sjfv return E1000_SUCCESS; 339169240Sjfv} 340169240Sjfv 341169240Sjfv/** 342169240Sjfv * e1000_write_phy_reg_mdic - Write MDI control register 343169589Sjfv * @hw: pointer to the HW structure 344169589Sjfv * @offset: register offset to write to 345169589Sjfv * @data: data to write to register at offset 346169240Sjfv * 347169240Sjfv * Writes data to MDI control register in the PHY at offset. 348169240Sjfv **/ 349176667Sjfvs32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 350169240Sjfv{ 351169240Sjfv struct e1000_phy_info *phy = &hw->phy; 352169240Sjfv u32 i, mdic = 0; 353169240Sjfv 354169240Sjfv DEBUGFUNC("e1000_write_phy_reg_mdic"); 355169240Sjfv 356203049Sjfv if (offset > MAX_PHY_REG_ADDRESS) { 357203049Sjfv DEBUGOUT1("PHY Address %d is out of range\n", offset); 358203049Sjfv return -E1000_ERR_PARAM; 359203049Sjfv } 360203049Sjfv 361247064Sjfv /* Set up Op-code, Phy Address, and register offset in the MDI 362169240Sjfv * Control register. The MAC will take care of interfacing with the 363169240Sjfv * PHY to retrieve the desired data. 364169240Sjfv */ 365169240Sjfv mdic = (((u32)data) | 366228386Sjfv (offset << E1000_MDIC_REG_SHIFT) | 367228386Sjfv (phy->addr << E1000_MDIC_PHY_SHIFT) | 368228386Sjfv (E1000_MDIC_OP_WRITE)); 369169240Sjfv 370169240Sjfv E1000_WRITE_REG(hw, E1000_MDIC, mdic); 371169240Sjfv 372247064Sjfv /* Poll the ready bit to see if the MDI read completed 373173788Sjfv * Increasing the time out as testing showed failures with 374173788Sjfv * the lower time out 375173788Sjfv */ 376173788Sjfv for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 377256200Sjfv usec_delay_irq(50); 378169240Sjfv mdic = E1000_READ_REG(hw, E1000_MDIC); 379169240Sjfv if (mdic & E1000_MDIC_READY) 380169240Sjfv break; 381169240Sjfv } 382169240Sjfv if (!(mdic & E1000_MDIC_READY)) { 383169240Sjfv DEBUGOUT("MDI Write did not complete\n"); 384238148Sjfv return -E1000_ERR_PHY; 385169240Sjfv } 386173788Sjfv if (mdic & E1000_MDIC_ERROR) { 387173788Sjfv DEBUGOUT("MDI Error\n"); 388238148Sjfv return -E1000_ERR_PHY; 389173788Sjfv } 390247064Sjfv if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 391247064Sjfv DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n", 392247064Sjfv offset, 393247064Sjfv (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 394247064Sjfv return -E1000_ERR_PHY; 395247064Sjfv } 396169240Sjfv 397247064Sjfv /* Allow some time after each MDIC transaction to avoid 398213234Sjfv * reading duplicate data in the next MDIC transaction. 399213234Sjfv */ 400213234Sjfv if (hw->mac.type == e1000_pch2lan) 401256200Sjfv usec_delay_irq(100); 402213234Sjfv 403238148Sjfv return E1000_SUCCESS; 404169240Sjfv} 405169240Sjfv 406169240Sjfv/** 407200243Sjfv * e1000_read_phy_reg_i2c - Read PHY register using i2c 408200243Sjfv * @hw: pointer to the HW structure 409200243Sjfv * @offset: register offset to be read 410200243Sjfv * @data: pointer to the read data 411200243Sjfv * 412200243Sjfv * Reads the PHY register at offset using the i2c interface and stores the 413200243Sjfv * retrieved information in data. 414200243Sjfv **/ 415200243Sjfvs32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 416200243Sjfv{ 417200243Sjfv struct e1000_phy_info *phy = &hw->phy; 418200243Sjfv u32 i, i2ccmd = 0; 419200243Sjfv 420200243Sjfv DEBUGFUNC("e1000_read_phy_reg_i2c"); 421200243Sjfv 422247064Sjfv /* Set up Op-code, Phy Address, and register address in the I2CCMD 423200243Sjfv * register. The MAC will take care of interfacing with the 424200243Sjfv * PHY to retrieve the desired data. 425200243Sjfv */ 426200243Sjfv i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 427228386Sjfv (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 428228386Sjfv (E1000_I2CCMD_OPCODE_READ)); 429200243Sjfv 430200243Sjfv E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 431200243Sjfv 432200243Sjfv /* Poll the ready bit to see if the I2C read completed */ 433200243Sjfv for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 434200243Sjfv usec_delay(50); 435200243Sjfv i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 436200243Sjfv if (i2ccmd & E1000_I2CCMD_READY) 437200243Sjfv break; 438200243Sjfv } 439200243Sjfv if (!(i2ccmd & E1000_I2CCMD_READY)) { 440200243Sjfv DEBUGOUT("I2CCMD Read did not complete\n"); 441200243Sjfv return -E1000_ERR_PHY; 442200243Sjfv } 443200243Sjfv if (i2ccmd & E1000_I2CCMD_ERROR) { 444200243Sjfv DEBUGOUT("I2CCMD Error bit set\n"); 445200243Sjfv return -E1000_ERR_PHY; 446200243Sjfv } 447200243Sjfv 448200243Sjfv /* Need to byte-swap the 16-bit value. */ 449200243Sjfv *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 450200243Sjfv 451200243Sjfv return E1000_SUCCESS; 452200243Sjfv} 453200243Sjfv 454200243Sjfv/** 455200243Sjfv * e1000_write_phy_reg_i2c - Write PHY register using i2c 456200243Sjfv * @hw: pointer to the HW structure 457200243Sjfv * @offset: register offset to write to 458200243Sjfv * @data: data to write at register offset 459200243Sjfv * 460200243Sjfv * Writes the data to PHY register at the offset using the i2c interface. 461200243Sjfv **/ 462200243Sjfvs32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 463200243Sjfv{ 464200243Sjfv struct e1000_phy_info *phy = &hw->phy; 465200243Sjfv u32 i, i2ccmd = 0; 466200243Sjfv u16 phy_data_swapped; 467200243Sjfv 468200243Sjfv DEBUGFUNC("e1000_write_phy_reg_i2c"); 469200243Sjfv 470228386Sjfv /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 471228386Sjfv if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 472228386Sjfv DEBUGOUT1("PHY I2C Address %d is out of range.\n", 473228386Sjfv hw->phy.addr); 474228386Sjfv return -E1000_ERR_CONFIG; 475228386Sjfv } 476228386Sjfv 477200243Sjfv /* Swap the data bytes for the I2C interface */ 478200243Sjfv phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 479200243Sjfv 480247064Sjfv /* Set up Op-code, Phy Address, and register address in the I2CCMD 481200243Sjfv * register. The MAC will take care of interfacing with the 482200243Sjfv * PHY to retrieve the desired data. 483200243Sjfv */ 484200243Sjfv i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 485228386Sjfv (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 486228386Sjfv E1000_I2CCMD_OPCODE_WRITE | 487228386Sjfv phy_data_swapped); 488200243Sjfv 489200243Sjfv E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 490200243Sjfv 491200243Sjfv /* Poll the ready bit to see if the I2C read completed */ 492200243Sjfv for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 493200243Sjfv usec_delay(50); 494200243Sjfv i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 495200243Sjfv if (i2ccmd & E1000_I2CCMD_READY) 496200243Sjfv break; 497200243Sjfv } 498200243Sjfv if (!(i2ccmd & E1000_I2CCMD_READY)) { 499200243Sjfv DEBUGOUT("I2CCMD Write did not complete\n"); 500200243Sjfv return -E1000_ERR_PHY; 501200243Sjfv } 502200243Sjfv if (i2ccmd & E1000_I2CCMD_ERROR) { 503200243Sjfv DEBUGOUT("I2CCMD Error bit set\n"); 504200243Sjfv return -E1000_ERR_PHY; 505200243Sjfv } 506200243Sjfv 507200243Sjfv return E1000_SUCCESS; 508200243Sjfv} 509200243Sjfv 510200243Sjfv/** 511228386Sjfv * e1000_read_sfp_data_byte - Reads SFP module data. 512228386Sjfv * @hw: pointer to the HW structure 513228386Sjfv * @offset: byte location offset to be read 514228386Sjfv * @data: read data buffer pointer 515228386Sjfv * 516228386Sjfv * Reads one byte from SFP module data stored 517228386Sjfv * in SFP resided EEPROM memory or SFP diagnostic area. 518228386Sjfv * Function should be called with 519228386Sjfv * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 520228386Sjfv * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 521228386Sjfv * access 522228386Sjfv **/ 523228386Sjfvs32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 524228386Sjfv{ 525228386Sjfv u32 i = 0; 526228386Sjfv u32 i2ccmd = 0; 527228386Sjfv u32 data_local = 0; 528228386Sjfv 529228386Sjfv DEBUGFUNC("e1000_read_sfp_data_byte"); 530228386Sjfv 531228386Sjfv if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 532228386Sjfv DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 533228386Sjfv return -E1000_ERR_PHY; 534228386Sjfv } 535228386Sjfv 536247064Sjfv /* Set up Op-code, EEPROM Address,in the I2CCMD 537228386Sjfv * register. The MAC will take care of interfacing with the 538228386Sjfv * EEPROM to retrieve the desired data. 539228386Sjfv */ 540228386Sjfv i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 541228386Sjfv E1000_I2CCMD_OPCODE_READ); 542228386Sjfv 543228386Sjfv E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 544228386Sjfv 545228386Sjfv /* Poll the ready bit to see if the I2C read completed */ 546228386Sjfv for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 547228386Sjfv usec_delay(50); 548228386Sjfv data_local = E1000_READ_REG(hw, E1000_I2CCMD); 549228386Sjfv if (data_local & E1000_I2CCMD_READY) 550228386Sjfv break; 551228386Sjfv } 552228386Sjfv if (!(data_local & E1000_I2CCMD_READY)) { 553228386Sjfv DEBUGOUT("I2CCMD Read did not complete\n"); 554228386Sjfv return -E1000_ERR_PHY; 555228386Sjfv } 556228386Sjfv if (data_local & E1000_I2CCMD_ERROR) { 557228386Sjfv DEBUGOUT("I2CCMD Error bit set\n"); 558228386Sjfv return -E1000_ERR_PHY; 559228386Sjfv } 560228386Sjfv *data = (u8) data_local & 0xFF; 561228386Sjfv 562228386Sjfv return E1000_SUCCESS; 563228386Sjfv} 564228386Sjfv 565228386Sjfv/** 566228386Sjfv * e1000_write_sfp_data_byte - Writes SFP module data. 567228386Sjfv * @hw: pointer to the HW structure 568228386Sjfv * @offset: byte location offset to write to 569228386Sjfv * @data: data to write 570228386Sjfv * 571228386Sjfv * Writes one byte to SFP module data stored 572228386Sjfv * in SFP resided EEPROM memory or SFP diagnostic area. 573228386Sjfv * Function should be called with 574228386Sjfv * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 575228386Sjfv * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 576228386Sjfv * access 577228386Sjfv **/ 578228386Sjfvs32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) 579228386Sjfv{ 580228386Sjfv u32 i = 0; 581228386Sjfv u32 i2ccmd = 0; 582228386Sjfv u32 data_local = 0; 583228386Sjfv 584228386Sjfv DEBUGFUNC("e1000_write_sfp_data_byte"); 585228386Sjfv 586228386Sjfv if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 587228386Sjfv DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 588228386Sjfv return -E1000_ERR_PHY; 589228386Sjfv } 590247064Sjfv /* The programming interface is 16 bits wide 591228386Sjfv * so we need to read the whole word first 592228386Sjfv * then update appropriate byte lane and write 593228386Sjfv * the updated word back. 594228386Sjfv */ 595247064Sjfv /* Set up Op-code, EEPROM Address,in the I2CCMD 596228386Sjfv * register. The MAC will take care of interfacing 597228386Sjfv * with an EEPROM to write the data given. 598228386Sjfv */ 599228386Sjfv i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 600228386Sjfv E1000_I2CCMD_OPCODE_READ); 601228386Sjfv /* Set a command to read single word */ 602228386Sjfv E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 603228386Sjfv for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 604228386Sjfv usec_delay(50); 605247064Sjfv /* Poll the ready bit to see if lastly 606228386Sjfv * launched I2C operation completed 607228386Sjfv */ 608228386Sjfv i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 609228386Sjfv if (i2ccmd & E1000_I2CCMD_READY) { 610228386Sjfv /* Check if this is READ or WRITE phase */ 611228386Sjfv if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) == 612228386Sjfv E1000_I2CCMD_OPCODE_READ) { 613247064Sjfv /* Write the selected byte 614228386Sjfv * lane and update whole word 615228386Sjfv */ 616228386Sjfv data_local = i2ccmd & 0xFF00; 617228386Sjfv data_local |= data; 618228386Sjfv i2ccmd = ((offset << 619228386Sjfv E1000_I2CCMD_REG_ADDR_SHIFT) | 620228386Sjfv E1000_I2CCMD_OPCODE_WRITE | data_local); 621228386Sjfv E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 622228386Sjfv } else { 623228386Sjfv break; 624228386Sjfv } 625228386Sjfv } 626228386Sjfv } 627228386Sjfv if (!(i2ccmd & E1000_I2CCMD_READY)) { 628228386Sjfv DEBUGOUT("I2CCMD Write did not complete\n"); 629228386Sjfv return -E1000_ERR_PHY; 630228386Sjfv } 631228386Sjfv if (i2ccmd & E1000_I2CCMD_ERROR) { 632228386Sjfv DEBUGOUT("I2CCMD Error bit set\n"); 633228386Sjfv return -E1000_ERR_PHY; 634228386Sjfv } 635228386Sjfv return E1000_SUCCESS; 636228386Sjfv} 637228386Sjfv 638228386Sjfv/** 639169240Sjfv * e1000_read_phy_reg_m88 - Read m88 PHY register 640169589Sjfv * @hw: pointer to the HW structure 641169589Sjfv * @offset: register offset to be read 642169589Sjfv * @data: pointer to the read data 643169240Sjfv * 644169240Sjfv * Acquires semaphore, if necessary, then reads the PHY register at offset 645169240Sjfv * and storing the retrieved information in data. Release any acquired 646169240Sjfv * semaphores before exiting. 647169240Sjfv **/ 648173788Sjfvs32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 649169240Sjfv{ 650238148Sjfv s32 ret_val; 651169240Sjfv 652169240Sjfv DEBUGFUNC("e1000_read_phy_reg_m88"); 653169240Sjfv 654238148Sjfv if (!hw->phy.ops.acquire) 655238148Sjfv return E1000_SUCCESS; 656177867Sjfv 657177867Sjfv ret_val = hw->phy.ops.acquire(hw); 658169240Sjfv if (ret_val) 659238148Sjfv return ret_val; 660169240Sjfv 661185353Sjfv ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 662228386Sjfv data); 663169240Sjfv 664177867Sjfv hw->phy.ops.release(hw); 665169240Sjfv 666169240Sjfv return ret_val; 667169240Sjfv} 668169240Sjfv 669169240Sjfv/** 670169240Sjfv * e1000_write_phy_reg_m88 - Write m88 PHY register 671169589Sjfv * @hw: pointer to the HW structure 672169589Sjfv * @offset: register offset to write to 673169589Sjfv * @data: data to write at register offset 674169240Sjfv * 675169240Sjfv * Acquires semaphore, if necessary, then writes the data to PHY register 676169240Sjfv * at the offset. Release any acquired semaphores before exiting. 677169240Sjfv **/ 678173788Sjfvs32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 679169240Sjfv{ 680238148Sjfv s32 ret_val; 681169240Sjfv 682169240Sjfv DEBUGFUNC("e1000_write_phy_reg_m88"); 683169240Sjfv 684238148Sjfv if (!hw->phy.ops.acquire) 685238148Sjfv return E1000_SUCCESS; 686177867Sjfv 687177867Sjfv ret_val = hw->phy.ops.acquire(hw); 688169240Sjfv if (ret_val) 689238148Sjfv return ret_val; 690169240Sjfv 691185353Sjfv ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 692228386Sjfv data); 693169240Sjfv 694177867Sjfv hw->phy.ops.release(hw); 695169240Sjfv 696169240Sjfv return ret_val; 697169240Sjfv} 698169240Sjfv 699169240Sjfv/** 700228386Sjfv * e1000_set_page_igp - Set page as on IGP-like PHY(s) 701228386Sjfv * @hw: pointer to the HW structure 702228386Sjfv * @page: page to set (shifted left when necessary) 703228386Sjfv * 704228386Sjfv * Sets PHY page required for PHY register access. Assumes semaphore is 705228386Sjfv * already acquired. Note, this function sets phy.addr to 1 so the caller 706228386Sjfv * must set it appropriately (if necessary) after this function returns. 707228386Sjfv **/ 708228386Sjfvs32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 709228386Sjfv{ 710228386Sjfv DEBUGFUNC("e1000_set_page_igp"); 711228386Sjfv 712228386Sjfv DEBUGOUT1("Setting page 0x%x\n", page); 713228386Sjfv 714228386Sjfv hw->phy.addr = 1; 715228386Sjfv 716228386Sjfv return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 717228386Sjfv} 718228386Sjfv 719228386Sjfv/** 720200243Sjfv * __e1000_read_phy_reg_igp - Read igp PHY register 721169589Sjfv * @hw: pointer to the HW structure 722169589Sjfv * @offset: register offset to be read 723169589Sjfv * @data: pointer to the read data 724200243Sjfv * @locked: semaphore has already been acquired or not 725169240Sjfv * 726169240Sjfv * Acquires semaphore, if necessary, then reads the PHY register at offset 727200243Sjfv * and stores the retrieved information in data. Release any acquired 728169240Sjfv * semaphores before exiting. 729169240Sjfv **/ 730200243Sjfvstatic s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 731228386Sjfv bool locked) 732169240Sjfv{ 733177867Sjfv s32 ret_val = E1000_SUCCESS; 734169240Sjfv 735200243Sjfv DEBUGFUNC("__e1000_read_phy_reg_igp"); 736169240Sjfv 737200243Sjfv if (!locked) { 738238148Sjfv if (!hw->phy.ops.acquire) 739238148Sjfv return E1000_SUCCESS; 740177867Sjfv 741200243Sjfv ret_val = hw->phy.ops.acquire(hw); 742200243Sjfv if (ret_val) 743238148Sjfv return ret_val; 744200243Sjfv } 745169240Sjfv 746238148Sjfv if (offset > MAX_PHY_MULTI_PAGE_REG) 747169240Sjfv ret_val = e1000_write_phy_reg_mdic(hw, 748228386Sjfv IGP01E1000_PHY_PAGE_SELECT, 749228386Sjfv (u16)offset); 750238148Sjfv if (!ret_val) 751238148Sjfv ret_val = e1000_read_phy_reg_mdic(hw, 752238148Sjfv MAX_PHY_REG_ADDRESS & offset, 753238148Sjfv data); 754200243Sjfv if (!locked) 755200243Sjfv hw->phy.ops.release(hw); 756238148Sjfv 757169240Sjfv return ret_val; 758169240Sjfv} 759169240Sjfv 760169240Sjfv/** 761200243Sjfv * e1000_read_phy_reg_igp - Read igp PHY register 762200243Sjfv * @hw: pointer to the HW structure 763200243Sjfv * @offset: register offset to be read 764200243Sjfv * @data: pointer to the read data 765200243Sjfv * 766200243Sjfv * Acquires semaphore then reads the PHY register at offset and stores the 767200243Sjfv * retrieved information in data. 768200243Sjfv * Release the acquired semaphore before exiting. 769200243Sjfv **/ 770200243Sjfvs32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 771200243Sjfv{ 772200243Sjfv return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); 773200243Sjfv} 774200243Sjfv 775200243Sjfv/** 776200243Sjfv * e1000_read_phy_reg_igp_locked - Read igp PHY register 777200243Sjfv * @hw: pointer to the HW structure 778200243Sjfv * @offset: register offset to be read 779200243Sjfv * @data: pointer to the read data 780200243Sjfv * 781200243Sjfv * Reads the PHY register at offset and stores the retrieved information 782200243Sjfv * in data. Assumes semaphore already acquired. 783200243Sjfv **/ 784200243Sjfvs32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 785200243Sjfv{ 786200243Sjfv return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); 787200243Sjfv} 788200243Sjfv 789200243Sjfv/** 790169240Sjfv * e1000_write_phy_reg_igp - Write igp PHY register 791169589Sjfv * @hw: pointer to the HW structure 792169589Sjfv * @offset: register offset to write to 793169589Sjfv * @data: data to write at register offset 794200243Sjfv * @locked: semaphore has already been acquired or not 795169240Sjfv * 796169240Sjfv * Acquires semaphore, if necessary, then writes the data to PHY register 797169240Sjfv * at the offset. Release any acquired semaphores before exiting. 798169240Sjfv **/ 799200243Sjfvstatic s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 800228386Sjfv bool locked) 801169240Sjfv{ 802177867Sjfv s32 ret_val = E1000_SUCCESS; 803169240Sjfv 804169240Sjfv DEBUGFUNC("e1000_write_phy_reg_igp"); 805169240Sjfv 806200243Sjfv if (!locked) { 807238148Sjfv if (!hw->phy.ops.acquire) 808238148Sjfv return E1000_SUCCESS; 809177867Sjfv 810200243Sjfv ret_val = hw->phy.ops.acquire(hw); 811200243Sjfv if (ret_val) 812238148Sjfv return ret_val; 813200243Sjfv } 814169240Sjfv 815238148Sjfv if (offset > MAX_PHY_MULTI_PAGE_REG) 816169240Sjfv ret_val = e1000_write_phy_reg_mdic(hw, 817228386Sjfv IGP01E1000_PHY_PAGE_SELECT, 818228386Sjfv (u16)offset); 819238148Sjfv if (!ret_val) 820238148Sjfv ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & 821238148Sjfv offset, 822238148Sjfv data); 823200243Sjfv if (!locked) 824200243Sjfv hw->phy.ops.release(hw); 825169240Sjfv 826169240Sjfv return ret_val; 827169240Sjfv} 828169240Sjfv 829169240Sjfv/** 830200243Sjfv * e1000_write_phy_reg_igp - Write igp PHY register 831169589Sjfv * @hw: pointer to the HW structure 832200243Sjfv * @offset: register offset to write to 833200243Sjfv * @data: data to write at register offset 834200243Sjfv * 835200243Sjfv * Acquires semaphore then writes the data to PHY register 836200243Sjfv * at the offset. Release any acquired semaphores before exiting. 837200243Sjfv **/ 838200243Sjfvs32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 839200243Sjfv{ 840200243Sjfv return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); 841200243Sjfv} 842200243Sjfv 843200243Sjfv/** 844200243Sjfv * e1000_write_phy_reg_igp_locked - Write igp PHY register 845200243Sjfv * @hw: pointer to the HW structure 846200243Sjfv * @offset: register offset to write to 847200243Sjfv * @data: data to write at register offset 848200243Sjfv * 849200243Sjfv * Writes the data to PHY register at the offset. 850200243Sjfv * Assumes semaphore already acquired. 851200243Sjfv **/ 852200243Sjfvs32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 853200243Sjfv{ 854200243Sjfv return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); 855200243Sjfv} 856200243Sjfv 857200243Sjfv/** 858200243Sjfv * __e1000_read_kmrn_reg - Read kumeran register 859200243Sjfv * @hw: pointer to the HW structure 860169589Sjfv * @offset: register offset to be read 861169589Sjfv * @data: pointer to the read data 862200243Sjfv * @locked: semaphore has already been acquired or not 863169240Sjfv * 864169240Sjfv * Acquires semaphore, if necessary. Then reads the PHY register at offset 865169240Sjfv * using the kumeran interface. The information retrieved is stored in data. 866169240Sjfv * Release any acquired semaphores before exiting. 867169240Sjfv **/ 868200243Sjfvstatic s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 869228386Sjfv bool locked) 870169240Sjfv{ 871169240Sjfv u32 kmrnctrlsta; 872169240Sjfv 873200243Sjfv DEBUGFUNC("__e1000_read_kmrn_reg"); 874169240Sjfv 875200243Sjfv if (!locked) { 876238148Sjfv s32 ret_val = E1000_SUCCESS; 877177867Sjfv 878238148Sjfv if (!hw->phy.ops.acquire) 879238148Sjfv return E1000_SUCCESS; 880238148Sjfv 881200243Sjfv ret_val = hw->phy.ops.acquire(hw); 882200243Sjfv if (ret_val) 883238148Sjfv return ret_val; 884200243Sjfv } 885169240Sjfv 886169240Sjfv kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 887228386Sjfv E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 888169240Sjfv E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 889228386Sjfv E1000_WRITE_FLUSH(hw); 890169240Sjfv 891169240Sjfv usec_delay(2); 892169240Sjfv 893169240Sjfv kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 894169240Sjfv *data = (u16)kmrnctrlsta; 895169240Sjfv 896200243Sjfv if (!locked) 897200243Sjfv hw->phy.ops.release(hw); 898169240Sjfv 899238148Sjfv return E1000_SUCCESS; 900169240Sjfv} 901169240Sjfv 902169240Sjfv/** 903200243Sjfv * e1000_read_kmrn_reg_generic - Read kumeran register 904169589Sjfv * @hw: pointer to the HW structure 905200243Sjfv * @offset: register offset to be read 906200243Sjfv * @data: pointer to the read data 907200243Sjfv * 908200243Sjfv * Acquires semaphore then reads the PHY register at offset using the 909200243Sjfv * kumeran interface. The information retrieved is stored in data. 910200243Sjfv * Release the acquired semaphore before exiting. 911200243Sjfv **/ 912200243Sjfvs32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 913200243Sjfv{ 914200243Sjfv return __e1000_read_kmrn_reg(hw, offset, data, FALSE); 915200243Sjfv} 916200243Sjfv 917200243Sjfv/** 918200243Sjfv * e1000_read_kmrn_reg_locked - Read kumeran register 919200243Sjfv * @hw: pointer to the HW structure 920200243Sjfv * @offset: register offset to be read 921200243Sjfv * @data: pointer to the read data 922200243Sjfv * 923200243Sjfv * Reads the PHY register at offset using the kumeran interface. The 924200243Sjfv * information retrieved is stored in data. 925200243Sjfv * Assumes semaphore already acquired. 926200243Sjfv **/ 927200243Sjfvs32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 928200243Sjfv{ 929200243Sjfv return __e1000_read_kmrn_reg(hw, offset, data, TRUE); 930200243Sjfv} 931200243Sjfv 932200243Sjfv/** 933200243Sjfv * __e1000_write_kmrn_reg - Write kumeran register 934200243Sjfv * @hw: pointer to the HW structure 935169589Sjfv * @offset: register offset to write to 936169589Sjfv * @data: data to write at register offset 937200243Sjfv * @locked: semaphore has already been acquired or not 938169240Sjfv * 939169240Sjfv * Acquires semaphore, if necessary. Then write the data to PHY register 940169240Sjfv * at the offset using the kumeran interface. Release any acquired semaphores 941169240Sjfv * before exiting. 942169240Sjfv **/ 943200243Sjfvstatic s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 944228386Sjfv bool locked) 945169240Sjfv{ 946169240Sjfv u32 kmrnctrlsta; 947169240Sjfv 948169240Sjfv DEBUGFUNC("e1000_write_kmrn_reg_generic"); 949169240Sjfv 950200243Sjfv if (!locked) { 951238148Sjfv s32 ret_val = E1000_SUCCESS; 952177867Sjfv 953238148Sjfv if (!hw->phy.ops.acquire) 954238148Sjfv return E1000_SUCCESS; 955238148Sjfv 956200243Sjfv ret_val = hw->phy.ops.acquire(hw); 957200243Sjfv if (ret_val) 958238148Sjfv return ret_val; 959200243Sjfv } 960169240Sjfv 961169240Sjfv kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 962228386Sjfv E1000_KMRNCTRLSTA_OFFSET) | data; 963169240Sjfv E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 964228386Sjfv E1000_WRITE_FLUSH(hw); 965169240Sjfv 966169240Sjfv usec_delay(2); 967169240Sjfv 968200243Sjfv if (!locked) 969200243Sjfv hw->phy.ops.release(hw); 970200243Sjfv 971238148Sjfv return E1000_SUCCESS; 972169240Sjfv} 973169240Sjfv 974169240Sjfv/** 975200243Sjfv * e1000_write_kmrn_reg_generic - Write kumeran register 976200243Sjfv * @hw: pointer to the HW structure 977200243Sjfv * @offset: register offset to write to 978200243Sjfv * @data: data to write at register offset 979200243Sjfv * 980200243Sjfv * Acquires semaphore then writes the data to the PHY register at the offset 981200243Sjfv * using the kumeran interface. Release the acquired semaphore before exiting. 982200243Sjfv **/ 983200243Sjfvs32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 984200243Sjfv{ 985200243Sjfv return __e1000_write_kmrn_reg(hw, offset, data, FALSE); 986200243Sjfv} 987200243Sjfv 988200243Sjfv/** 989200243Sjfv * e1000_write_kmrn_reg_locked - Write kumeran register 990200243Sjfv * @hw: pointer to the HW structure 991200243Sjfv * @offset: register offset to write to 992200243Sjfv * @data: data to write at register offset 993200243Sjfv * 994200243Sjfv * Write the data to PHY register at the offset using the kumeran interface. 995200243Sjfv * Assumes semaphore already acquired. 996200243Sjfv **/ 997200243Sjfvs32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 998200243Sjfv{ 999200243Sjfv return __e1000_write_kmrn_reg(hw, offset, data, TRUE); 1000200243Sjfv} 1001200243Sjfv 1002200243Sjfv/** 1003238148Sjfv * e1000_set_master_slave_mode - Setup PHY for Master/slave mode 1004238148Sjfv * @hw: pointer to the HW structure 1005238148Sjfv * 1006238148Sjfv * Sets up Master/slave mode 1007238148Sjfv **/ 1008238148Sjfvstatic s32 e1000_set_master_slave_mode(struct e1000_hw *hw) 1009238148Sjfv{ 1010238148Sjfv s32 ret_val; 1011238148Sjfv u16 phy_data; 1012238148Sjfv 1013238148Sjfv /* Resolve Master/Slave mode */ 1014238148Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 1015238148Sjfv if (ret_val) 1016238148Sjfv return ret_val; 1017238148Sjfv 1018238148Sjfv /* load defaults for future use */ 1019238148Sjfv hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 1020238148Sjfv ((phy_data & CR_1000T_MS_VALUE) ? 1021238148Sjfv e1000_ms_force_master : 1022238148Sjfv e1000_ms_force_slave) : e1000_ms_auto; 1023238148Sjfv 1024238148Sjfv switch (hw->phy.ms_type) { 1025238148Sjfv case e1000_ms_force_master: 1026238148Sjfv phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1027238148Sjfv break; 1028238148Sjfv case e1000_ms_force_slave: 1029238148Sjfv phy_data |= CR_1000T_MS_ENABLE; 1030238148Sjfv phy_data &= ~(CR_1000T_MS_VALUE); 1031238148Sjfv break; 1032238148Sjfv case e1000_ms_auto: 1033238148Sjfv phy_data &= ~CR_1000T_MS_ENABLE; 1034238148Sjfv /* fall-through */ 1035238148Sjfv default: 1036238148Sjfv break; 1037238148Sjfv } 1038238148Sjfv 1039238148Sjfv return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 1040238148Sjfv} 1041238148Sjfv 1042238148Sjfv/** 1043194865Sjfv * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 1044194865Sjfv * @hw: pointer to the HW structure 1045194865Sjfv * 1046194865Sjfv * Sets up Carrier-sense on Transmit and downshift values. 1047194865Sjfv **/ 1048194865Sjfvs32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 1049194865Sjfv{ 1050194865Sjfv s32 ret_val; 1051194865Sjfv u16 phy_data; 1052194865Sjfv 1053194865Sjfv DEBUGFUNC("e1000_copper_link_setup_82577"); 1054194865Sjfv 1055203049Sjfv if (hw->phy.type == e1000_phy_82580) { 1056200243Sjfv ret_val = hw->phy.ops.reset(hw); 1057200243Sjfv if (ret_val) { 1058200243Sjfv DEBUGOUT("Error resetting the PHY.\n"); 1059238148Sjfv return ret_val; 1060200243Sjfv } 1061200243Sjfv } 1062200243Sjfv 1063256200Sjfv /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1064203049Sjfv ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); 1065194865Sjfv if (ret_val) 1066238148Sjfv return ret_val; 1067194865Sjfv 1068256200Sjfv phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 1069194865Sjfv 1070194865Sjfv /* Enable downshift */ 1071194865Sjfv phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 1072194865Sjfv 1073203049Sjfv ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 1074228386Sjfv if (ret_val) 1075238148Sjfv return ret_val; 1076194865Sjfv 1077238148Sjfv /* Set MDI/MDIX mode */ 1078238148Sjfv ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); 1079228386Sjfv if (ret_val) 1080238148Sjfv return ret_val; 1081238148Sjfv phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; 1082247064Sjfv /* Options: 1083238148Sjfv * 0 - Auto (default) 1084238148Sjfv * 1 - MDI mode 1085238148Sjfv * 2 - MDI-X mode 1086238148Sjfv */ 1087238148Sjfv switch (hw->phy.mdix) { 1088238148Sjfv case 1: 1089228386Sjfv break; 1090238148Sjfv case 2: 1091238148Sjfv phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; 1092228386Sjfv break; 1093238148Sjfv case 0: 1094228386Sjfv default: 1095238148Sjfv phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; 1096228386Sjfv break; 1097228386Sjfv } 1098238148Sjfv ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); 1099228386Sjfv if (ret_val) 1100238148Sjfv return ret_val; 1101228386Sjfv 1102238148Sjfv return e1000_set_master_slave_mode(hw); 1103194865Sjfv} 1104194865Sjfv 1105194865Sjfv/** 1106169240Sjfv * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 1107169589Sjfv * @hw: pointer to the HW structure 1108169240Sjfv * 1109169240Sjfv * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 1110169240Sjfv * and downshift values are set also. 1111169240Sjfv **/ 1112173788Sjfvs32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 1113169240Sjfv{ 1114169240Sjfv struct e1000_phy_info *phy = &hw->phy; 1115169240Sjfv s32 ret_val; 1116169240Sjfv u16 phy_data; 1117169240Sjfv 1118169240Sjfv DEBUGFUNC("e1000_copper_link_setup_m88"); 1119169240Sjfv 1120169240Sjfv 1121203049Sjfv /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1122177867Sjfv ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1123169240Sjfv if (ret_val) 1124238148Sjfv return ret_val; 1125169240Sjfv 1126190872Sjfv /* For BM PHY this bit is downshift enable */ 1127218530Sjfv if (phy->type != e1000_phy_bm) 1128218530Sjfv phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1129169240Sjfv 1130247064Sjfv /* Options: 1131169240Sjfv * MDI/MDI-X = 0 (default) 1132169240Sjfv * 0 - Auto for all speeds 1133169240Sjfv * 1 - MDI mode 1134169240Sjfv * 2 - MDI-X mode 1135169240Sjfv * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1136169240Sjfv */ 1137169240Sjfv phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1138169240Sjfv 1139169240Sjfv switch (phy->mdix) { 1140185353Sjfv case 1: 1141185353Sjfv phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1142185353Sjfv break; 1143185353Sjfv case 2: 1144185353Sjfv phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1145185353Sjfv break; 1146185353Sjfv case 3: 1147185353Sjfv phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1148185353Sjfv break; 1149185353Sjfv case 0: 1150185353Sjfv default: 1151185353Sjfv phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1152185353Sjfv break; 1153169240Sjfv } 1154169240Sjfv 1155247064Sjfv /* Options: 1156169240Sjfv * disable_polarity_correction = 0 (default) 1157169240Sjfv * Automatic Correction for Reversed Cable Polarity 1158169240Sjfv * 0 - Disabled 1159169240Sjfv * 1 - Enabled 1160169240Sjfv */ 1161169240Sjfv phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1162238148Sjfv if (phy->disable_polarity_correction) 1163169240Sjfv phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1164169240Sjfv 1165176667Sjfv /* Enable downshift on BM (disabled by default) */ 1166238148Sjfv if (phy->type == e1000_phy_bm) { 1167238148Sjfv /* For 82574/82583, first disable then enable downshift */ 1168238148Sjfv if (phy->id == BME1000_E_PHY_ID_R2) { 1169238148Sjfv phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; 1170238148Sjfv ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1171238148Sjfv phy_data); 1172238148Sjfv if (ret_val) 1173238148Sjfv return ret_val; 1174238148Sjfv /* Commit the changes. */ 1175238148Sjfv ret_val = phy->ops.commit(hw); 1176238148Sjfv if (ret_val) { 1177238148Sjfv DEBUGOUT("Error committing the PHY changes\n"); 1178238148Sjfv return ret_val; 1179238148Sjfv } 1180238148Sjfv } 1181238148Sjfv 1182176667Sjfv phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 1183238148Sjfv } 1184176667Sjfv 1185177867Sjfv ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1186169240Sjfv if (ret_val) 1187238148Sjfv return ret_val; 1188169240Sjfv 1189178523Sjfv if ((phy->type == e1000_phy_m88) && 1190178523Sjfv (phy->revision < E1000_REVISION_4) && 1191178523Sjfv (phy->id != BME1000_E_PHY_ID_R2)) { 1192247064Sjfv /* Force TX_CLK in the Extended PHY Specific Control Register 1193169240Sjfv * to 25MHz clock. 1194169240Sjfv */ 1195185353Sjfv ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1196228386Sjfv &phy_data); 1197169240Sjfv if (ret_val) 1198238148Sjfv return ret_val; 1199169240Sjfv 1200169240Sjfv phy_data |= M88E1000_EPSCR_TX_CLK_25; 1201169240Sjfv 1202169240Sjfv if ((phy->revision == E1000_REVISION_2) && 1203169240Sjfv (phy->id == M88E1111_I_PHY_ID)) { 1204169240Sjfv /* 82573L PHY - set the downshift counter to 5x. */ 1205169240Sjfv phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 1206169240Sjfv phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1207169240Sjfv } else { 1208169240Sjfv /* Configure Master and Slave downshift values */ 1209169240Sjfv phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1210228386Sjfv M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1211169240Sjfv phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1212228386Sjfv M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1213169240Sjfv } 1214185353Sjfv ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1215228386Sjfv phy_data); 1216169240Sjfv if (ret_val) 1217238148Sjfv return ret_val; 1218169240Sjfv } 1219169240Sjfv 1220181027Sjfv if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 1221181027Sjfv /* Set PHY page 0, register 29 to 0x0003 */ 1222181027Sjfv ret_val = phy->ops.write_reg(hw, 29, 0x0003); 1223181027Sjfv if (ret_val) 1224238148Sjfv return ret_val; 1225181027Sjfv 1226181027Sjfv /* Set PHY page 0, register 30 to 0x0000 */ 1227181027Sjfv ret_val = phy->ops.write_reg(hw, 30, 0x0000); 1228181027Sjfv if (ret_val) 1229238148Sjfv return ret_val; 1230181027Sjfv } 1231181027Sjfv 1232169240Sjfv /* Commit the changes. */ 1233177867Sjfv ret_val = phy->ops.commit(hw); 1234169240Sjfv if (ret_val) { 1235169240Sjfv DEBUGOUT("Error committing the PHY changes\n"); 1236238148Sjfv return ret_val; 1237169240Sjfv } 1238169240Sjfv 1239194865Sjfv if (phy->type == e1000_phy_82578) { 1240194865Sjfv ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1241228386Sjfv &phy_data); 1242194865Sjfv if (ret_val) 1243238148Sjfv return ret_val; 1244194865Sjfv 1245194865Sjfv /* 82578 PHY - set the downshift count to 1x. */ 1246194865Sjfv phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 1247194865Sjfv phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 1248194865Sjfv ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1249228386Sjfv phy_data); 1250194865Sjfv if (ret_val) 1251238148Sjfv return ret_val; 1252194865Sjfv } 1253194865Sjfv 1254238148Sjfv return E1000_SUCCESS; 1255169240Sjfv} 1256169240Sjfv 1257169240Sjfv/** 1258218530Sjfv * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 1259218530Sjfv * @hw: pointer to the HW structure 1260218530Sjfv * 1261218530Sjfv * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 1262218530Sjfv * Also enables and sets the downshift parameters. 1263218530Sjfv **/ 1264218530Sjfvs32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) 1265218530Sjfv{ 1266218530Sjfv struct e1000_phy_info *phy = &hw->phy; 1267218530Sjfv s32 ret_val; 1268218530Sjfv u16 phy_data; 1269218530Sjfv 1270218530Sjfv DEBUGFUNC("e1000_copper_link_setup_m88_gen2"); 1271218530Sjfv 1272218530Sjfv 1273218530Sjfv /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1274218530Sjfv ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1275218530Sjfv if (ret_val) 1276238148Sjfv return ret_val; 1277218530Sjfv 1278247064Sjfv /* Options: 1279218530Sjfv * MDI/MDI-X = 0 (default) 1280218530Sjfv * 0 - Auto for all speeds 1281218530Sjfv * 1 - MDI mode 1282218530Sjfv * 2 - MDI-X mode 1283218530Sjfv * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1284218530Sjfv */ 1285218530Sjfv phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1286218530Sjfv 1287218530Sjfv switch (phy->mdix) { 1288218530Sjfv case 1: 1289218530Sjfv phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1290218530Sjfv break; 1291218530Sjfv case 2: 1292218530Sjfv phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1293218530Sjfv break; 1294218530Sjfv case 3: 1295218530Sjfv /* M88E1112 does not support this mode) */ 1296218530Sjfv if (phy->id != M88E1112_E_PHY_ID) { 1297218530Sjfv phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1298218530Sjfv break; 1299218530Sjfv } 1300333216Smarius /* FALLTHROUGH */ 1301218530Sjfv case 0: 1302218530Sjfv default: 1303218530Sjfv phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1304218530Sjfv break; 1305218530Sjfv } 1306218530Sjfv 1307247064Sjfv /* Options: 1308218530Sjfv * disable_polarity_correction = 0 (default) 1309218530Sjfv * Automatic Correction for Reversed Cable Polarity 1310218530Sjfv * 0 - Disabled 1311218530Sjfv * 1 - Enabled 1312218530Sjfv */ 1313218530Sjfv phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1314238148Sjfv if (phy->disable_polarity_correction) 1315218530Sjfv phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1316218530Sjfv 1317218530Sjfv /* Enable downshift and setting it to X6 */ 1318256200Sjfv if (phy->id == M88E1543_E_PHY_ID) { 1319256200Sjfv phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE; 1320256200Sjfv ret_val = 1321256200Sjfv phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1322256200Sjfv if (ret_val) 1323256200Sjfv return ret_val; 1324256200Sjfv 1325256200Sjfv ret_val = phy->ops.commit(hw); 1326256200Sjfv if (ret_val) { 1327256200Sjfv DEBUGOUT("Error committing the PHY changes\n"); 1328256200Sjfv return ret_val; 1329256200Sjfv } 1330256200Sjfv } 1331256200Sjfv 1332218530Sjfv phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 1333218530Sjfv phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 1334218530Sjfv phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 1335218530Sjfv 1336218530Sjfv ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1337218530Sjfv if (ret_val) 1338238148Sjfv return ret_val; 1339218530Sjfv 1340218530Sjfv /* Commit the changes. */ 1341218530Sjfv ret_val = phy->ops.commit(hw); 1342218530Sjfv if (ret_val) { 1343218530Sjfv DEBUGOUT("Error committing the PHY changes\n"); 1344238148Sjfv return ret_val; 1345218530Sjfv } 1346218530Sjfv 1347256200Sjfv ret_val = e1000_set_master_slave_mode(hw); 1348256200Sjfv if (ret_val) 1349256200Sjfv return ret_val; 1350256200Sjfv 1351238148Sjfv return E1000_SUCCESS; 1352218530Sjfv} 1353218530Sjfv 1354218530Sjfv/** 1355169240Sjfv * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 1356169589Sjfv * @hw: pointer to the HW structure 1357169240Sjfv * 1358169240Sjfv * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 1359169240Sjfv * igp PHY's. 1360169240Sjfv **/ 1361173788Sjfvs32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 1362169240Sjfv{ 1363169240Sjfv struct e1000_phy_info *phy = &hw->phy; 1364169240Sjfv s32 ret_val; 1365169240Sjfv u16 data; 1366169240Sjfv 1367169240Sjfv DEBUGFUNC("e1000_copper_link_setup_igp"); 1368169240Sjfv 1369169240Sjfv 1370181027Sjfv ret_val = hw->phy.ops.reset(hw); 1371169240Sjfv if (ret_val) { 1372169240Sjfv DEBUGOUT("Error resetting the PHY.\n"); 1373238148Sjfv return ret_val; 1374169240Sjfv } 1375169240Sjfv 1376247064Sjfv /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 1377177867Sjfv * timeout issues when LFS is enabled. 1378177867Sjfv */ 1379177867Sjfv msec_delay(100); 1380169240Sjfv 1381247064Sjfv /* The NVM settings will configure LPLU in D3 for 1382173788Sjfv * non-IGP1 PHYs. 1383173788Sjfv */ 1384169240Sjfv if (phy->type == e1000_phy_igp) { 1385169240Sjfv /* disable lplu d3 during driver init */ 1386181027Sjfv ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 1387169240Sjfv if (ret_val) { 1388169240Sjfv DEBUGOUT("Error Disabling LPLU D3\n"); 1389238148Sjfv return ret_val; 1390169240Sjfv } 1391169240Sjfv } 1392169240Sjfv 1393169240Sjfv /* disable lplu d0 during driver init */ 1394181027Sjfv if (hw->phy.ops.set_d0_lplu_state) { 1395181027Sjfv ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 1396181027Sjfv if (ret_val) { 1397181027Sjfv DEBUGOUT("Error Disabling LPLU D0\n"); 1398238148Sjfv return ret_val; 1399181027Sjfv } 1400169240Sjfv } 1401169240Sjfv /* Configure mdi-mdix settings */ 1402177867Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1403169240Sjfv if (ret_val) 1404238148Sjfv return ret_val; 1405169240Sjfv 1406169240Sjfv data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1407169240Sjfv 1408169240Sjfv switch (phy->mdix) { 1409169240Sjfv case 1: 1410169240Sjfv data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1411169240Sjfv break; 1412169240Sjfv case 2: 1413169240Sjfv data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1414169240Sjfv break; 1415169240Sjfv case 0: 1416169240Sjfv default: 1417169240Sjfv data |= IGP01E1000_PSCR_AUTO_MDIX; 1418169240Sjfv break; 1419169240Sjfv } 1420177867Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1421169240Sjfv if (ret_val) 1422238148Sjfv return ret_val; 1423169240Sjfv 1424169240Sjfv /* set auto-master slave resolution settings */ 1425169240Sjfv if (hw->mac.autoneg) { 1426247064Sjfv /* when autonegotiation advertisement is only 1000Mbps then we 1427169240Sjfv * should disable SmartSpeed and enable Auto MasterSlave 1428173788Sjfv * resolution as hardware default. 1429173788Sjfv */ 1430169240Sjfv if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1431169240Sjfv /* Disable SmartSpeed */ 1432177867Sjfv ret_val = phy->ops.read_reg(hw, 1433228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 1434228386Sjfv &data); 1435169240Sjfv if (ret_val) 1436238148Sjfv return ret_val; 1437169240Sjfv 1438169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1439177867Sjfv ret_val = phy->ops.write_reg(hw, 1440228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 1441228386Sjfv data); 1442169240Sjfv if (ret_val) 1443238148Sjfv return ret_val; 1444169240Sjfv 1445169240Sjfv /* Set auto Master/Slave resolution process */ 1446177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1447169240Sjfv if (ret_val) 1448238148Sjfv return ret_val; 1449169240Sjfv 1450169240Sjfv data &= ~CR_1000T_MS_ENABLE; 1451177867Sjfv ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1452169240Sjfv if (ret_val) 1453238148Sjfv return ret_val; 1454169240Sjfv } 1455169240Sjfv 1456238148Sjfv ret_val = e1000_set_master_slave_mode(hw); 1457169240Sjfv } 1458169240Sjfv 1459169240Sjfv return ret_val; 1460169240Sjfv} 1461169240Sjfv 1462169240Sjfv/** 1463169240Sjfv * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1464169589Sjfv * @hw: pointer to the HW structure 1465169240Sjfv * 1466169240Sjfv * Reads the MII auto-neg advertisement register and/or the 1000T control 1467169240Sjfv * register and if the PHY is already setup for auto-negotiation, then 1468169240Sjfv * return successful. Otherwise, setup advertisement and flow control to 1469169240Sjfv * the appropriate values for the wanted auto-negotiation. 1470169240Sjfv **/ 1471173788Sjfvs32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1472169240Sjfv{ 1473169240Sjfv struct e1000_phy_info *phy = &hw->phy; 1474169240Sjfv s32 ret_val; 1475169240Sjfv u16 mii_autoneg_adv_reg; 1476169240Sjfv u16 mii_1000t_ctrl_reg = 0; 1477169240Sjfv 1478169240Sjfv DEBUGFUNC("e1000_phy_setup_autoneg"); 1479169240Sjfv 1480169240Sjfv phy->autoneg_advertised &= phy->autoneg_mask; 1481169240Sjfv 1482169240Sjfv /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1483177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1484169240Sjfv if (ret_val) 1485238148Sjfv return ret_val; 1486169240Sjfv 1487169240Sjfv if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1488169240Sjfv /* Read the MII 1000Base-T Control Register (Address 9). */ 1489185353Sjfv ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1490228386Sjfv &mii_1000t_ctrl_reg); 1491169240Sjfv if (ret_val) 1492238148Sjfv return ret_val; 1493169240Sjfv } 1494169240Sjfv 1495247064Sjfv /* Need to parse both autoneg_advertised and fc and set up 1496169240Sjfv * the appropriate PHY registers. First we will parse for 1497169240Sjfv * autoneg_advertised software override. Since we can advertise 1498169240Sjfv * a plethora of combinations, we need to check each bit 1499169240Sjfv * individually. 1500169240Sjfv */ 1501169240Sjfv 1502247064Sjfv /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1503169240Sjfv * Advertisement Register (Address 4) and the 1000 mb speed bits in 1504169240Sjfv * the 1000Base-T Control Register (Address 9). 1505169240Sjfv */ 1506169240Sjfv mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1507228386Sjfv NWAY_AR_100TX_HD_CAPS | 1508228386Sjfv NWAY_AR_10T_FD_CAPS | 1509228386Sjfv NWAY_AR_10T_HD_CAPS); 1510169240Sjfv mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1511169240Sjfv 1512169240Sjfv DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1513169240Sjfv 1514169240Sjfv /* Do we want to advertise 10 Mb Half Duplex? */ 1515169240Sjfv if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1516169240Sjfv DEBUGOUT("Advertise 10mb Half duplex\n"); 1517169240Sjfv mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1518169240Sjfv } 1519169240Sjfv 1520169240Sjfv /* Do we want to advertise 10 Mb Full Duplex? */ 1521169240Sjfv if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1522169240Sjfv DEBUGOUT("Advertise 10mb Full duplex\n"); 1523169240Sjfv mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1524169240Sjfv } 1525169240Sjfv 1526169240Sjfv /* Do we want to advertise 100 Mb Half Duplex? */ 1527169240Sjfv if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1528169240Sjfv DEBUGOUT("Advertise 100mb Half duplex\n"); 1529169240Sjfv mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1530169240Sjfv } 1531169240Sjfv 1532169240Sjfv /* Do we want to advertise 100 Mb Full Duplex? */ 1533169240Sjfv if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1534169240Sjfv DEBUGOUT("Advertise 100mb Full duplex\n"); 1535169240Sjfv mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1536169240Sjfv } 1537169240Sjfv 1538169240Sjfv /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1539185353Sjfv if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1540169240Sjfv DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1541169240Sjfv 1542169240Sjfv /* Do we want to advertise 1000 Mb Full Duplex? */ 1543169240Sjfv if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1544169240Sjfv DEBUGOUT("Advertise 1000mb Full duplex\n"); 1545169240Sjfv mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1546169240Sjfv } 1547169240Sjfv 1548247064Sjfv /* Check for a software override of the flow control settings, and 1549169240Sjfv * setup the PHY advertisement registers accordingly. If 1550169240Sjfv * auto-negotiation is enabled, then software will have to set the 1551169240Sjfv * "PAUSE" bits to the correct value in the Auto-Negotiation 1552169240Sjfv * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1553169240Sjfv * negotiation. 1554169240Sjfv * 1555169240Sjfv * The possible values of the "fc" parameter are: 1556169240Sjfv * 0: Flow control is completely disabled 1557169240Sjfv * 1: Rx flow control is enabled (we can receive pause frames 1558169240Sjfv * but not send pause frames). 1559169240Sjfv * 2: Tx flow control is enabled (we can send pause frames 1560169240Sjfv * but we do not support receiving pause frames). 1561173788Sjfv * 3: Both Rx and Tx flow control (symmetric) are enabled. 1562169240Sjfv * other: No software override. The flow control configuration 1563169240Sjfv * in the EEPROM is used. 1564169240Sjfv */ 1565185353Sjfv switch (hw->fc.current_mode) { 1566169240Sjfv case e1000_fc_none: 1567247064Sjfv /* Flow control (Rx & Tx) is completely disabled by a 1568169240Sjfv * software over-ride. 1569169240Sjfv */ 1570169240Sjfv mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1571169240Sjfv break; 1572169240Sjfv case e1000_fc_rx_pause: 1573247064Sjfv /* Rx Flow control is enabled, and Tx Flow control is 1574169240Sjfv * disabled, by a software over-ride. 1575173788Sjfv * 1576173788Sjfv * Since there really isn't a way to advertise that we are 1577173788Sjfv * capable of Rx Pause ONLY, we will advertise that we 1578173788Sjfv * support both symmetric and asymmetric Rx PAUSE. Later 1579169240Sjfv * (in e1000_config_fc_after_link_up) we will disable the 1580169240Sjfv * hw's ability to send PAUSE frames. 1581169240Sjfv */ 1582169240Sjfv mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1583169240Sjfv break; 1584169240Sjfv case e1000_fc_tx_pause: 1585247064Sjfv /* Tx Flow control is enabled, and Rx Flow control is 1586169240Sjfv * disabled, by a software over-ride. 1587169240Sjfv */ 1588169240Sjfv mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1589169240Sjfv mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1590169240Sjfv break; 1591169240Sjfv case e1000_fc_full: 1592247064Sjfv /* Flow control (both Rx and Tx) is enabled by a software 1593169240Sjfv * over-ride. 1594169240Sjfv */ 1595169240Sjfv mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1596169240Sjfv break; 1597169240Sjfv default: 1598169240Sjfv DEBUGOUT("Flow control param set incorrectly\n"); 1599238148Sjfv return -E1000_ERR_CONFIG; 1600169240Sjfv } 1601169240Sjfv 1602177867Sjfv ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1603169240Sjfv if (ret_val) 1604238148Sjfv return ret_val; 1605169240Sjfv 1606169240Sjfv DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1607169240Sjfv 1608238148Sjfv if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1609228386Sjfv ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 1610228386Sjfv mii_1000t_ctrl_reg); 1611238148Sjfv 1612238148Sjfv return ret_val; 1613238148Sjfv} 1614238148Sjfv 1615238148Sjfv/** 1616238148Sjfv * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1617238148Sjfv * @hw: pointer to the HW structure 1618238148Sjfv * 1619238148Sjfv * Performs initial bounds checking on autoneg advertisement parameter, then 1620238148Sjfv * configure to advertise the full capability. Setup the PHY to autoneg 1621238148Sjfv * and restart the negotiation process between the link partner. If 1622238148Sjfv * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1623238148Sjfv **/ 1624238148Sjfvs32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1625238148Sjfv{ 1626238148Sjfv struct e1000_phy_info *phy = &hw->phy; 1627238148Sjfv s32 ret_val; 1628238148Sjfv u16 phy_ctrl; 1629238148Sjfv 1630238148Sjfv DEBUGFUNC("e1000_copper_link_autoneg"); 1631238148Sjfv 1632247064Sjfv /* Perform some bounds checking on the autoneg advertisement 1633238148Sjfv * parameter. 1634238148Sjfv */ 1635238148Sjfv phy->autoneg_advertised &= phy->autoneg_mask; 1636238148Sjfv 1637247064Sjfv /* If autoneg_advertised is zero, we assume it was not defaulted 1638238148Sjfv * by the calling code so we set to advertise full capability. 1639238148Sjfv */ 1640238148Sjfv if (!phy->autoneg_advertised) 1641238148Sjfv phy->autoneg_advertised = phy->autoneg_mask; 1642238148Sjfv 1643238148Sjfv DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1644238148Sjfv ret_val = e1000_phy_setup_autoneg(hw); 1645238148Sjfv if (ret_val) { 1646238148Sjfv DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1647238148Sjfv return ret_val; 1648169240Sjfv } 1649238148Sjfv DEBUGOUT("Restarting Auto-Neg\n"); 1650169240Sjfv 1651247064Sjfv /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1652238148Sjfv * the Auto Neg Restart bit in the PHY control register. 1653238148Sjfv */ 1654238148Sjfv ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1655238148Sjfv if (ret_val) 1656238148Sjfv return ret_val; 1657238148Sjfv 1658238148Sjfv phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1659238148Sjfv ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1660238148Sjfv if (ret_val) 1661238148Sjfv return ret_val; 1662238148Sjfv 1663247064Sjfv /* Does the user want to wait for Auto-Neg to complete here, or 1664238148Sjfv * check at a later time (for example, callback routine). 1665238148Sjfv */ 1666238148Sjfv if (phy->autoneg_wait_to_complete) { 1667247064Sjfv ret_val = e1000_wait_autoneg(hw); 1668238148Sjfv if (ret_val) { 1669238148Sjfv DEBUGOUT("Error while waiting for autoneg to complete\n"); 1670238148Sjfv return ret_val; 1671238148Sjfv } 1672238148Sjfv } 1673238148Sjfv 1674238148Sjfv hw->mac.get_link_status = TRUE; 1675238148Sjfv 1676169240Sjfv return ret_val; 1677169240Sjfv} 1678169240Sjfv 1679169240Sjfv/** 1680169240Sjfv * e1000_setup_copper_link_generic - Configure copper link settings 1681169589Sjfv * @hw: pointer to the HW structure 1682169240Sjfv * 1683169240Sjfv * Calls the appropriate function to configure the link for auto-neg or forced 1684169240Sjfv * speed and duplex. Then we check for link, once link is established calls 1685169240Sjfv * to configure collision distance and flow control are called. If link is 1686169240Sjfv * not established, we return -E1000_ERR_PHY (-2). 1687169240Sjfv **/ 1688173788Sjfvs32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1689169240Sjfv{ 1690169240Sjfv s32 ret_val; 1691173788Sjfv bool link; 1692169240Sjfv 1693169240Sjfv DEBUGFUNC("e1000_setup_copper_link_generic"); 1694169240Sjfv 1695169240Sjfv if (hw->mac.autoneg) { 1696247064Sjfv /* Setup autoneg and flow control advertisement and perform 1697173788Sjfv * autonegotiation. 1698173788Sjfv */ 1699169240Sjfv ret_val = e1000_copper_link_autoneg(hw); 1700169240Sjfv if (ret_val) 1701238148Sjfv return ret_val; 1702169240Sjfv } else { 1703247064Sjfv /* PHY will be set to 10H, 10F, 100H or 100F 1704173788Sjfv * depending on user settings. 1705173788Sjfv */ 1706169240Sjfv DEBUGOUT("Forcing Speed and Duplex\n"); 1707177867Sjfv ret_val = hw->phy.ops.force_speed_duplex(hw); 1708169240Sjfv if (ret_val) { 1709169240Sjfv DEBUGOUT("Error Forcing Speed and Duplex\n"); 1710238148Sjfv return ret_val; 1711169240Sjfv } 1712169240Sjfv } 1713169240Sjfv 1714247064Sjfv /* Check link status. Wait up to 100 microseconds for link to become 1715169240Sjfv * valid. 1716169240Sjfv */ 1717228386Sjfv ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1718228386Sjfv &link); 1719169240Sjfv if (ret_val) 1720238148Sjfv return ret_val; 1721169240Sjfv 1722169240Sjfv if (link) { 1723169240Sjfv DEBUGOUT("Valid link established!!!\n"); 1724238148Sjfv hw->mac.ops.config_collision_dist(hw); 1725169240Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1726169240Sjfv } else { 1727169240Sjfv DEBUGOUT("Unable to establish link!!!\n"); 1728169240Sjfv } 1729169240Sjfv 1730169240Sjfv return ret_val; 1731169240Sjfv} 1732169240Sjfv 1733169240Sjfv/** 1734169240Sjfv * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1735169589Sjfv * @hw: pointer to the HW structure 1736169240Sjfv * 1737169240Sjfv * Calls the PHY setup function to force speed and duplex. Clears the 1738169240Sjfv * auto-crossover to force MDI manually. Waits for link and returns 1739169240Sjfv * successful if link up is successful, else -E1000_ERR_PHY (-2). 1740169240Sjfv **/ 1741173788Sjfvs32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1742169240Sjfv{ 1743169240Sjfv struct e1000_phy_info *phy = &hw->phy; 1744169240Sjfv s32 ret_val; 1745169240Sjfv u16 phy_data; 1746173788Sjfv bool link; 1747169240Sjfv 1748169240Sjfv DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1749169240Sjfv 1750177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1751169240Sjfv if (ret_val) 1752238148Sjfv return ret_val; 1753169240Sjfv 1754169240Sjfv e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1755169240Sjfv 1756177867Sjfv ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1757169240Sjfv if (ret_val) 1758238148Sjfv return ret_val; 1759169240Sjfv 1760247064Sjfv /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1761169240Sjfv * forced whenever speed and duplex are forced. 1762169240Sjfv */ 1763177867Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1764169240Sjfv if (ret_val) 1765238148Sjfv return ret_val; 1766169240Sjfv 1767169240Sjfv phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1768169240Sjfv phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1769169240Sjfv 1770177867Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1771169240Sjfv if (ret_val) 1772238148Sjfv return ret_val; 1773169240Sjfv 1774169240Sjfv DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1775169240Sjfv 1776169240Sjfv usec_delay(1); 1777169240Sjfv 1778173788Sjfv if (phy->autoneg_wait_to_complete) { 1779169240Sjfv DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1780169240Sjfv 1781228386Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1782228386Sjfv 100000, &link); 1783169240Sjfv if (ret_val) 1784238148Sjfv return ret_val; 1785169240Sjfv 1786185353Sjfv if (!link) 1787169240Sjfv DEBUGOUT("Link taking longer than expected.\n"); 1788169240Sjfv 1789169240Sjfv /* Try once more */ 1790228386Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1791228386Sjfv 100000, &link); 1792169240Sjfv } 1793169240Sjfv 1794169240Sjfv return ret_val; 1795169240Sjfv} 1796169240Sjfv 1797169240Sjfv/** 1798169240Sjfv * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1799169589Sjfv * @hw: pointer to the HW structure 1800169240Sjfv * 1801169240Sjfv * Calls the PHY setup function to force speed and duplex. Clears the 1802169240Sjfv * auto-crossover to force MDI manually. Resets the PHY to commit the 1803169240Sjfv * changes. If time expires while waiting for link up, we reset the DSP. 1804173788Sjfv * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1805169240Sjfv * successful completion, else return corresponding error code. 1806169240Sjfv **/ 1807173788Sjfvs32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1808169240Sjfv{ 1809169240Sjfv struct e1000_phy_info *phy = &hw->phy; 1810169240Sjfv s32 ret_val; 1811169240Sjfv u16 phy_data; 1812173788Sjfv bool link; 1813169240Sjfv 1814169240Sjfv DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1815169240Sjfv 1816247064Sjfv /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1817247064Sjfv if (phy->type != e1000_phy_i210) { 1818247064Sjfv /* Clear Auto-Crossover to force MDI manually. M88E1000 1819247064Sjfv * requires MDI forced whenever speed and duplex are forced. 1820247064Sjfv */ 1821247064Sjfv ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1822247064Sjfv &phy_data); 1823247064Sjfv if (ret_val) 1824247064Sjfv return ret_val; 1825169240Sjfv 1826247064Sjfv phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1827247064Sjfv ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1828247064Sjfv phy_data); 1829247064Sjfv if (ret_val) 1830247064Sjfv return ret_val; 1831296055Serj 1832296055Serj DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1833247064Sjfv } 1834169240Sjfv 1835177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1836169240Sjfv if (ret_val) 1837238148Sjfv return ret_val; 1838169240Sjfv 1839169240Sjfv e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1840169240Sjfv 1841177867Sjfv ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1842169240Sjfv if (ret_val) 1843238148Sjfv return ret_val; 1844169240Sjfv 1845181027Sjfv /* Reset the phy to commit changes. */ 1846181027Sjfv ret_val = hw->phy.ops.commit(hw); 1847181027Sjfv if (ret_val) 1848238148Sjfv return ret_val; 1849169240Sjfv 1850173788Sjfv if (phy->autoneg_wait_to_complete) { 1851169240Sjfv DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1852169240Sjfv 1853185353Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1854228386Sjfv 100000, &link); 1855169240Sjfv if (ret_val) 1856238148Sjfv return ret_val; 1857169240Sjfv 1858169240Sjfv if (!link) { 1859238148Sjfv bool reset_dsp = TRUE; 1860238148Sjfv 1861238148Sjfv switch (hw->phy.id) { 1862238148Sjfv case I347AT4_E_PHY_ID: 1863238148Sjfv case M88E1340M_E_PHY_ID: 1864238148Sjfv case M88E1112_E_PHY_ID: 1865256200Sjfv case M88E1543_E_PHY_ID: 1866256200Sjfv case M88E1512_E_PHY_ID: 1867238148Sjfv case I210_I_PHY_ID: 1868238148Sjfv reset_dsp = FALSE; 1869238148Sjfv break; 1870238148Sjfv default: 1871238148Sjfv if (hw->phy.type != e1000_phy_m88) 1872238148Sjfv reset_dsp = FALSE; 1873238148Sjfv break; 1874238148Sjfv } 1875238148Sjfv 1876238148Sjfv if (!reset_dsp) { 1877200243Sjfv DEBUGOUT("Link taking longer than expected.\n"); 1878200243Sjfv } else { 1879247064Sjfv /* We didn't get link. 1880200243Sjfv * Reset the DSP and cross our fingers. 1881200243Sjfv */ 1882200243Sjfv ret_val = phy->ops.write_reg(hw, 1883200243Sjfv M88E1000_PHY_PAGE_SELECT, 1884200243Sjfv 0x001d); 1885200243Sjfv if (ret_val) 1886238148Sjfv return ret_val; 1887200243Sjfv ret_val = e1000_phy_reset_dsp_generic(hw); 1888200243Sjfv if (ret_val) 1889238148Sjfv return ret_val; 1890200243Sjfv } 1891169240Sjfv } 1892169240Sjfv 1893169240Sjfv /* Try once more */ 1894185353Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1895228386Sjfv 100000, &link); 1896169240Sjfv if (ret_val) 1897238148Sjfv return ret_val; 1898169240Sjfv } 1899169240Sjfv 1900238148Sjfv if (hw->phy.type != e1000_phy_m88) 1901238148Sjfv return E1000_SUCCESS; 1902200243Sjfv 1903238148Sjfv if (hw->phy.id == I347AT4_E_PHY_ID || 1904238148Sjfv hw->phy.id == M88E1340M_E_PHY_ID || 1905238148Sjfv hw->phy.id == M88E1112_E_PHY_ID) 1906238148Sjfv return E1000_SUCCESS; 1907238148Sjfv if (hw->phy.id == I210_I_PHY_ID) 1908238148Sjfv return E1000_SUCCESS; 1909256200Sjfv if ((hw->phy.id == M88E1543_E_PHY_ID) || 1910256200Sjfv (hw->phy.id == M88E1512_E_PHY_ID)) 1911256200Sjfv return E1000_SUCCESS; 1912177867Sjfv ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1913169240Sjfv if (ret_val) 1914238148Sjfv return ret_val; 1915169240Sjfv 1916247064Sjfv /* Resetting the phy means we need to re-force TX_CLK in the 1917169240Sjfv * Extended PHY Specific Control Register to 25MHz clock from 1918169240Sjfv * the reset value of 2.5MHz. 1919169240Sjfv */ 1920169240Sjfv phy_data |= M88E1000_EPSCR_TX_CLK_25; 1921177867Sjfv ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1922169240Sjfv if (ret_val) 1923238148Sjfv return ret_val; 1924169240Sjfv 1925247064Sjfv /* In addition, we must re-enable CRS on Tx for both half and full 1926169240Sjfv * duplex. 1927169240Sjfv */ 1928177867Sjfv ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1929169240Sjfv if (ret_val) 1930238148Sjfv return ret_val; 1931169240Sjfv 1932169240Sjfv phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1933177867Sjfv ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1934169240Sjfv 1935169240Sjfv return ret_val; 1936169240Sjfv} 1937169240Sjfv 1938169240Sjfv/** 1939194865Sjfv * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1940194865Sjfv * @hw: pointer to the HW structure 1941194865Sjfv * 1942194865Sjfv * Forces the speed and duplex settings of the PHY. 1943194865Sjfv * This is a function pointer entry point only called by 1944194865Sjfv * PHY setup routines. 1945194865Sjfv **/ 1946194865Sjfvs32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1947194865Sjfv{ 1948194865Sjfv struct e1000_phy_info *phy = &hw->phy; 1949194865Sjfv s32 ret_val; 1950194865Sjfv u16 data; 1951194865Sjfv bool link; 1952194865Sjfv 1953194865Sjfv DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1954194865Sjfv 1955194865Sjfv ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1956194865Sjfv if (ret_val) 1957238148Sjfv return ret_val; 1958194865Sjfv 1959194865Sjfv e1000_phy_force_speed_duplex_setup(hw, &data); 1960194865Sjfv 1961194865Sjfv ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1962194865Sjfv if (ret_val) 1963238148Sjfv return ret_val; 1964194865Sjfv 1965194865Sjfv /* Disable MDI-X support for 10/100 */ 1966194865Sjfv ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1967194865Sjfv if (ret_val) 1968238148Sjfv return ret_val; 1969194865Sjfv 1970194865Sjfv data &= ~IFE_PMC_AUTO_MDIX; 1971194865Sjfv data &= ~IFE_PMC_FORCE_MDIX; 1972194865Sjfv 1973194865Sjfv ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1974194865Sjfv if (ret_val) 1975238148Sjfv return ret_val; 1976194865Sjfv 1977194865Sjfv DEBUGOUT1("IFE PMC: %X\n", data); 1978194865Sjfv 1979194865Sjfv usec_delay(1); 1980194865Sjfv 1981194865Sjfv if (phy->autoneg_wait_to_complete) { 1982194865Sjfv DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1983194865Sjfv 1984228386Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1985228386Sjfv 100000, &link); 1986194865Sjfv if (ret_val) 1987238148Sjfv return ret_val; 1988194865Sjfv 1989194865Sjfv if (!link) 1990194865Sjfv DEBUGOUT("Link taking longer than expected.\n"); 1991194865Sjfv 1992194865Sjfv /* Try once more */ 1993228386Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1994228386Sjfv 100000, &link); 1995194865Sjfv if (ret_val) 1996238148Sjfv return ret_val; 1997194865Sjfv } 1998194865Sjfv 1999238148Sjfv return E1000_SUCCESS; 2000194865Sjfv} 2001194865Sjfv 2002194865Sjfv/** 2003169240Sjfv * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 2004169589Sjfv * @hw: pointer to the HW structure 2005169589Sjfv * @phy_ctrl: pointer to current value of PHY_CONTROL 2006169240Sjfv * 2007169240Sjfv * Forces speed and duplex on the PHY by doing the following: disable flow 2008169240Sjfv * control, force speed/duplex on the MAC, disable auto speed detection, 2009169240Sjfv * disable auto-negotiation, configure duplex, configure speed, configure 2010169240Sjfv * the collision distance, write configuration to CTRL register. The 2011169240Sjfv * caller must write to the PHY_CONTROL register for these settings to 2012169240Sjfv * take affect. 2013169240Sjfv **/ 2014173788Sjfvvoid e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 2015169240Sjfv{ 2016169240Sjfv struct e1000_mac_info *mac = &hw->mac; 2017169240Sjfv u32 ctrl; 2018169240Sjfv 2019169240Sjfv DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 2020169240Sjfv 2021169240Sjfv /* Turn off flow control when forcing speed/duplex */ 2022185353Sjfv hw->fc.current_mode = e1000_fc_none; 2023169240Sjfv 2024169240Sjfv /* Force speed/duplex on the mac */ 2025169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2026169240Sjfv ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2027169240Sjfv ctrl &= ~E1000_CTRL_SPD_SEL; 2028169240Sjfv 2029169240Sjfv /* Disable Auto Speed Detection */ 2030169240Sjfv ctrl &= ~E1000_CTRL_ASDE; 2031169240Sjfv 2032169240Sjfv /* Disable autoneg on the phy */ 2033169240Sjfv *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 2034169240Sjfv 2035169240Sjfv /* Forcing Full or Half Duplex? */ 2036169240Sjfv if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 2037169240Sjfv ctrl &= ~E1000_CTRL_FD; 2038169240Sjfv *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 2039169240Sjfv DEBUGOUT("Half Duplex\n"); 2040169240Sjfv } else { 2041169240Sjfv ctrl |= E1000_CTRL_FD; 2042169240Sjfv *phy_ctrl |= MII_CR_FULL_DUPLEX; 2043169240Sjfv DEBUGOUT("Full Duplex\n"); 2044169240Sjfv } 2045169240Sjfv 2046169240Sjfv /* Forcing 10mb or 100mb? */ 2047169240Sjfv if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 2048169240Sjfv ctrl |= E1000_CTRL_SPD_100; 2049169240Sjfv *phy_ctrl |= MII_CR_SPEED_100; 2050247064Sjfv *phy_ctrl &= ~MII_CR_SPEED_1000; 2051169240Sjfv DEBUGOUT("Forcing 100mb\n"); 2052169240Sjfv } else { 2053169240Sjfv ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2054169240Sjfv *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 2055169240Sjfv DEBUGOUT("Forcing 10mb\n"); 2056169240Sjfv } 2057169240Sjfv 2058238148Sjfv hw->mac.ops.config_collision_dist(hw); 2059169240Sjfv 2060169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2061169240Sjfv} 2062169240Sjfv 2063169240Sjfv/** 2064169240Sjfv * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 2065169589Sjfv * @hw: pointer to the HW structure 2066169589Sjfv * @active: boolean used to enable/disable lplu 2067169240Sjfv * 2068169240Sjfv * Success returns 0, Failure returns 1 2069169240Sjfv * 2070169240Sjfv * The low power link up (lplu) state is set to the power management level D3 2071177867Sjfv * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 2072169240Sjfv * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 2073169240Sjfv * is used during Dx states where the power conservation is most important. 2074169240Sjfv * During driver activity, SmartSpeed should be enabled so performance is 2075169240Sjfv * maintained. 2076169240Sjfv **/ 2077173788Sjfvs32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 2078169240Sjfv{ 2079169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2080238148Sjfv s32 ret_val; 2081169240Sjfv u16 data; 2082169240Sjfv 2083169240Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 2084169240Sjfv 2085238148Sjfv if (!hw->phy.ops.read_reg) 2086238148Sjfv return E1000_SUCCESS; 2087177867Sjfv 2088177867Sjfv ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 2089169240Sjfv if (ret_val) 2090238148Sjfv return ret_val; 2091169240Sjfv 2092169240Sjfv if (!active) { 2093169240Sjfv data &= ~IGP02E1000_PM_D3_LPLU; 2094185353Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2095228386Sjfv data); 2096169240Sjfv if (ret_val) 2097238148Sjfv return ret_val; 2098247064Sjfv /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2099169240Sjfv * during Dx states where the power conservation is most 2100169240Sjfv * important. During driver activity we should enable 2101173788Sjfv * SmartSpeed, so performance is maintained. 2102173788Sjfv */ 2103169240Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 2104177867Sjfv ret_val = phy->ops.read_reg(hw, 2105228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 2106228386Sjfv &data); 2107169240Sjfv if (ret_val) 2108238148Sjfv return ret_val; 2109169240Sjfv 2110169240Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 2111177867Sjfv ret_val = phy->ops.write_reg(hw, 2112228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 2113228386Sjfv data); 2114169240Sjfv if (ret_val) 2115238148Sjfv return ret_val; 2116169240Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 2117177867Sjfv ret_val = phy->ops.read_reg(hw, 2118228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 2119228386Sjfv &data); 2120169240Sjfv if (ret_val) 2121238148Sjfv return ret_val; 2122169240Sjfv 2123169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2124177867Sjfv ret_val = phy->ops.write_reg(hw, 2125228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 2126228386Sjfv data); 2127169240Sjfv if (ret_val) 2128238148Sjfv return ret_val; 2129169240Sjfv } 2130169240Sjfv } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2131228386Sjfv (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2132228386Sjfv (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2133169240Sjfv data |= IGP02E1000_PM_D3_LPLU; 2134185353Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2135228386Sjfv data); 2136169240Sjfv if (ret_val) 2137238148Sjfv return ret_val; 2138169240Sjfv 2139169240Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 2140185353Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2141228386Sjfv &data); 2142169240Sjfv if (ret_val) 2143238148Sjfv return ret_val; 2144169240Sjfv 2145169240Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2146185353Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2147228386Sjfv data); 2148169240Sjfv } 2149169240Sjfv 2150169240Sjfv return ret_val; 2151169240Sjfv} 2152169240Sjfv 2153169240Sjfv/** 2154176667Sjfv * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 2155169589Sjfv * @hw: pointer to the HW structure 2156169240Sjfv * 2157169240Sjfv * Success returns 0, Failure returns 1 2158169240Sjfv * 2159169240Sjfv * A downshift is detected by querying the PHY link health. 2160169240Sjfv **/ 2161173788Sjfvs32 e1000_check_downshift_generic(struct e1000_hw *hw) 2162169240Sjfv{ 2163169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2164169240Sjfv s32 ret_val; 2165169240Sjfv u16 phy_data, offset, mask; 2166169240Sjfv 2167169240Sjfv DEBUGFUNC("e1000_check_downshift_generic"); 2168169240Sjfv 2169169240Sjfv switch (phy->type) { 2170238148Sjfv case e1000_phy_i210: 2171169240Sjfv case e1000_phy_m88: 2172169240Sjfv case e1000_phy_gg82563: 2173176667Sjfv case e1000_phy_bm: 2174194865Sjfv case e1000_phy_82578: 2175228386Sjfv offset = M88E1000_PHY_SPEC_STATUS; 2176228386Sjfv mask = M88E1000_PSSR_DOWNSHIFT; 2177169240Sjfv break; 2178200243Sjfv case e1000_phy_igp: 2179169240Sjfv case e1000_phy_igp_2: 2180169240Sjfv case e1000_phy_igp_3: 2181228386Sjfv offset = IGP01E1000_PHY_LINK_HEALTH; 2182228386Sjfv mask = IGP01E1000_PLHR_SS_DOWNGRADE; 2183169240Sjfv break; 2184169240Sjfv default: 2185169240Sjfv /* speed downshift not supported */ 2186169240Sjfv phy->speed_downgraded = FALSE; 2187238148Sjfv return E1000_SUCCESS; 2188169240Sjfv } 2189169240Sjfv 2190177867Sjfv ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2191169240Sjfv 2192169240Sjfv if (!ret_val) 2193238148Sjfv phy->speed_downgraded = !!(phy_data & mask); 2194169240Sjfv 2195169240Sjfv return ret_val; 2196169240Sjfv} 2197169240Sjfv 2198169240Sjfv/** 2199169240Sjfv * e1000_check_polarity_m88 - Checks the polarity. 2200169589Sjfv * @hw: pointer to the HW structure 2201169240Sjfv * 2202169240Sjfv * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2203169240Sjfv * 2204169240Sjfv * Polarity is determined based on the PHY specific status register. 2205169240Sjfv **/ 2206173788Sjfvs32 e1000_check_polarity_m88(struct e1000_hw *hw) 2207169240Sjfv{ 2208169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2209169240Sjfv s32 ret_val; 2210169240Sjfv u16 data; 2211169240Sjfv 2212169240Sjfv DEBUGFUNC("e1000_check_polarity_m88"); 2213169240Sjfv 2214177867Sjfv ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 2215169240Sjfv 2216169240Sjfv if (!ret_val) 2217256200Sjfv phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY) 2218256200Sjfv ? e1000_rev_polarity_reversed 2219256200Sjfv : e1000_rev_polarity_normal); 2220169240Sjfv 2221169240Sjfv return ret_val; 2222169240Sjfv} 2223169240Sjfv 2224169240Sjfv/** 2225169240Sjfv * e1000_check_polarity_igp - Checks the polarity. 2226169589Sjfv * @hw: pointer to the HW structure 2227169240Sjfv * 2228169240Sjfv * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2229169240Sjfv * 2230169240Sjfv * Polarity is determined based on the PHY port status register, and the 2231169240Sjfv * current speed (since there is no polarity at 100Mbps). 2232169240Sjfv **/ 2233173788Sjfvs32 e1000_check_polarity_igp(struct e1000_hw *hw) 2234169240Sjfv{ 2235169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2236169240Sjfv s32 ret_val; 2237169240Sjfv u16 data, offset, mask; 2238169240Sjfv 2239169240Sjfv DEBUGFUNC("e1000_check_polarity_igp"); 2240169240Sjfv 2241247064Sjfv /* Polarity is determined based on the speed of 2242173788Sjfv * our connection. 2243173788Sjfv */ 2244177867Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2245169240Sjfv if (ret_val) 2246238148Sjfv return ret_val; 2247169240Sjfv 2248169240Sjfv if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2249169240Sjfv IGP01E1000_PSSR_SPEED_1000MBPS) { 2250228386Sjfv offset = IGP01E1000_PHY_PCS_INIT_REG; 2251228386Sjfv mask = IGP01E1000_PHY_POLARITY_MASK; 2252169240Sjfv } else { 2253247064Sjfv /* This really only applies to 10Mbps since 2254169240Sjfv * there is no polarity for 100Mbps (always 0). 2255169240Sjfv */ 2256228386Sjfv offset = IGP01E1000_PHY_PORT_STATUS; 2257228386Sjfv mask = IGP01E1000_PSSR_POLARITY_REVERSED; 2258169240Sjfv } 2259169240Sjfv 2260177867Sjfv ret_val = phy->ops.read_reg(hw, offset, &data); 2261169240Sjfv 2262169240Sjfv if (!ret_val) 2263256200Sjfv phy->cable_polarity = ((data & mask) 2264256200Sjfv ? e1000_rev_polarity_reversed 2265256200Sjfv : e1000_rev_polarity_normal); 2266169240Sjfv 2267169240Sjfv return ret_val; 2268169240Sjfv} 2269169240Sjfv 2270169240Sjfv/** 2271194865Sjfv * e1000_check_polarity_ife - Check cable polarity for IFE PHY 2272194865Sjfv * @hw: pointer to the HW structure 2273194865Sjfv * 2274194865Sjfv * Polarity is determined on the polarity reversal feature being enabled. 2275194865Sjfv **/ 2276194865Sjfvs32 e1000_check_polarity_ife(struct e1000_hw *hw) 2277194865Sjfv{ 2278194865Sjfv struct e1000_phy_info *phy = &hw->phy; 2279194865Sjfv s32 ret_val; 2280194865Sjfv u16 phy_data, offset, mask; 2281194865Sjfv 2282194865Sjfv DEBUGFUNC("e1000_check_polarity_ife"); 2283194865Sjfv 2284247064Sjfv /* Polarity is determined based on the reversal feature being enabled. 2285194865Sjfv */ 2286194865Sjfv if (phy->polarity_correction) { 2287194865Sjfv offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 2288194865Sjfv mask = IFE_PESC_POLARITY_REVERSED; 2289194865Sjfv } else { 2290194865Sjfv offset = IFE_PHY_SPECIAL_CONTROL; 2291194865Sjfv mask = IFE_PSC_FORCE_POLARITY; 2292194865Sjfv } 2293194865Sjfv 2294194865Sjfv ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2295194865Sjfv 2296194865Sjfv if (!ret_val) 2297256200Sjfv phy->cable_polarity = ((phy_data & mask) 2298228386Sjfv ? e1000_rev_polarity_reversed 2299256200Sjfv : e1000_rev_polarity_normal); 2300194865Sjfv 2301194865Sjfv return ret_val; 2302194865Sjfv} 2303194865Sjfv 2304194865Sjfv/** 2305247064Sjfv * e1000_wait_autoneg - Wait for auto-neg completion 2306169589Sjfv * @hw: pointer to the HW structure 2307169240Sjfv * 2308169240Sjfv * Waits for auto-negotiation to complete or for the auto-negotiation time 2309169240Sjfv * limit to expire, which ever happens first. 2310169240Sjfv **/ 2311247064Sjfvstatic s32 e1000_wait_autoneg(struct e1000_hw *hw) 2312169240Sjfv{ 2313169240Sjfv s32 ret_val = E1000_SUCCESS; 2314169240Sjfv u16 i, phy_status; 2315169240Sjfv 2316247064Sjfv DEBUGFUNC("e1000_wait_autoneg"); 2317169240Sjfv 2318238148Sjfv if (!hw->phy.ops.read_reg) 2319177867Sjfv return E1000_SUCCESS; 2320177867Sjfv 2321169240Sjfv /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 2322169240Sjfv for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 2323177867Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2324169240Sjfv if (ret_val) 2325169240Sjfv break; 2326177867Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2327169240Sjfv if (ret_val) 2328169240Sjfv break; 2329169240Sjfv if (phy_status & MII_SR_AUTONEG_COMPLETE) 2330169240Sjfv break; 2331169240Sjfv msec_delay(100); 2332169240Sjfv } 2333169240Sjfv 2334247064Sjfv /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2335169240Sjfv * has completed. 2336169240Sjfv */ 2337169240Sjfv return ret_val; 2338169240Sjfv} 2339169240Sjfv 2340169240Sjfv/** 2341169240Sjfv * e1000_phy_has_link_generic - Polls PHY for link 2342169589Sjfv * @hw: pointer to the HW structure 2343169589Sjfv * @iterations: number of times to poll for link 2344169589Sjfv * @usec_interval: delay between polling attempts 2345169589Sjfv * @success: pointer to whether polling was successful or not 2346169240Sjfv * 2347169240Sjfv * Polls the PHY status register for link, 'iterations' number of times. 2348169240Sjfv **/ 2349173788Sjfvs32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2350228386Sjfv u32 usec_interval, bool *success) 2351169240Sjfv{ 2352169240Sjfv s32 ret_val = E1000_SUCCESS; 2353169240Sjfv u16 i, phy_status; 2354169240Sjfv 2355169240Sjfv DEBUGFUNC("e1000_phy_has_link_generic"); 2356169240Sjfv 2357238148Sjfv if (!hw->phy.ops.read_reg) 2358177867Sjfv return E1000_SUCCESS; 2359177867Sjfv 2360169240Sjfv for (i = 0; i < iterations; i++) { 2361247064Sjfv /* Some PHYs require the PHY_STATUS register to be read 2362169240Sjfv * twice due to the link bit being sticky. No harm doing 2363169240Sjfv * it across the board. 2364169240Sjfv */ 2365177867Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2366269196Sjfv if (ret_val) { 2367247064Sjfv /* If the first read fails, another entity may have 2368194865Sjfv * ownership of the resources, wait and try again to 2369194865Sjfv * see if they have relinquished the resources yet. 2370194865Sjfv */ 2371269196Sjfv if (usec_interval >= 1000) 2372269196Sjfv msec_delay(usec_interval/1000); 2373269196Sjfv else 2374269196Sjfv usec_delay(usec_interval); 2375269196Sjfv } 2376200243Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2377169240Sjfv if (ret_val) 2378169240Sjfv break; 2379169240Sjfv if (phy_status & MII_SR_LINK_STATUS) 2380169240Sjfv break; 2381169240Sjfv if (usec_interval >= 1000) 2382269196Sjfv msec_delay(usec_interval/1000); 2383169240Sjfv else 2384169240Sjfv usec_delay(usec_interval); 2385169240Sjfv } 2386169240Sjfv 2387238148Sjfv *success = (i < iterations); 2388169240Sjfv 2389169240Sjfv return ret_val; 2390169240Sjfv} 2391169240Sjfv 2392169240Sjfv/** 2393169240Sjfv * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2394169589Sjfv * @hw: pointer to the HW structure 2395169240Sjfv * 2396169240Sjfv * Reads the PHY specific status register to retrieve the cable length 2397169240Sjfv * information. The cable length is determined by averaging the minimum and 2398169240Sjfv * maximum values to get the "average" cable length. The m88 PHY has four 2399169240Sjfv * possible cable length values, which are: 2400169240Sjfv * Register Value Cable Length 2401169240Sjfv * 0 < 50 meters 2402169240Sjfv * 1 50 - 80 meters 2403169240Sjfv * 2 80 - 110 meters 2404169240Sjfv * 3 110 - 140 meters 2405169240Sjfv * 4 > 140 meters 2406169240Sjfv **/ 2407173788Sjfvs32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2408169240Sjfv{ 2409169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2410169240Sjfv s32 ret_val; 2411169240Sjfv u16 phy_data, index; 2412169240Sjfv 2413169240Sjfv DEBUGFUNC("e1000_get_cable_length_m88"); 2414169240Sjfv 2415177867Sjfv ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2416169240Sjfv if (ret_val) 2417238148Sjfv return ret_val; 2418169240Sjfv 2419256200Sjfv index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2420256200Sjfv M88E1000_PSSR_CABLE_LENGTH_SHIFT); 2421169240Sjfv 2422238148Sjfv if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2423238148Sjfv return -E1000_ERR_PHY; 2424238148Sjfv 2425190872Sjfv phy->min_cable_length = e1000_m88_cable_length_table[index]; 2426200243Sjfv phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2427190872Sjfv 2428190872Sjfv phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2429190872Sjfv 2430238148Sjfv return E1000_SUCCESS; 2431169240Sjfv} 2432169240Sjfv 2433218530Sjfvs32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) 2434218530Sjfv{ 2435218530Sjfv struct e1000_phy_info *phy = &hw->phy; 2436218530Sjfv s32 ret_val; 2437247064Sjfv u16 phy_data, phy_data2, is_cm; 2438247064Sjfv u16 index, default_page; 2439218530Sjfv 2440218530Sjfv DEBUGFUNC("e1000_get_cable_length_m88_gen2"); 2441218530Sjfv 2442218530Sjfv switch (hw->phy.id) { 2443238148Sjfv case I210_I_PHY_ID: 2444238148Sjfv /* Get cable length from PHY Cable Diagnostics Control Reg */ 2445238148Sjfv ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2446238148Sjfv (I347AT4_PCDL + phy->addr), 2447238148Sjfv &phy_data); 2448238148Sjfv if (ret_val) 2449238148Sjfv return ret_val; 2450238148Sjfv 2451238148Sjfv /* Check if the unit of cable length is meters or cm */ 2452238148Sjfv ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2453238148Sjfv I347AT4_PCDC, &phy_data2); 2454238148Sjfv if (ret_val) 2455238148Sjfv return ret_val; 2456238148Sjfv 2457238148Sjfv is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2458238148Sjfv 2459238148Sjfv /* Populate the phy structure with cable length in meters */ 2460238148Sjfv phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2461238148Sjfv phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2462238148Sjfv phy->cable_length = phy_data / (is_cm ? 100 : 1); 2463238148Sjfv break; 2464256200Sjfv case M88E1543_E_PHY_ID: 2465256200Sjfv case M88E1512_E_PHY_ID: 2466219753Sjfv case M88E1340M_E_PHY_ID: 2467218530Sjfv case I347AT4_E_PHY_ID: 2468218530Sjfv /* Remember the original page select and set it to 7 */ 2469218530Sjfv ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2470218530Sjfv &default_page); 2471218530Sjfv if (ret_val) 2472238148Sjfv return ret_val; 2473218530Sjfv 2474218530Sjfv ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 2475218530Sjfv if (ret_val) 2476238148Sjfv return ret_val; 2477218530Sjfv 2478218530Sjfv /* Get cable length from PHY Cable Diagnostics Control Reg */ 2479218530Sjfv ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 2480218530Sjfv &phy_data); 2481218530Sjfv if (ret_val) 2482238148Sjfv return ret_val; 2483218530Sjfv 2484218530Sjfv /* Check if the unit of cable length is meters or cm */ 2485218530Sjfv ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 2486218530Sjfv if (ret_val) 2487238148Sjfv return ret_val; 2488218530Sjfv 2489228386Sjfv is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2490218530Sjfv 2491218530Sjfv /* Populate the phy structure with cable length in meters */ 2492218530Sjfv phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2493218530Sjfv phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2494218530Sjfv phy->cable_length = phy_data / (is_cm ? 100 : 1); 2495218530Sjfv 2496228386Sjfv /* Reset the page select to its original value */ 2497218530Sjfv ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2498218530Sjfv default_page); 2499218530Sjfv if (ret_val) 2500238148Sjfv return ret_val; 2501218530Sjfv break; 2502238148Sjfv 2503218530Sjfv case M88E1112_E_PHY_ID: 2504218530Sjfv /* Remember the original page select and set it to 5 */ 2505218530Sjfv ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2506218530Sjfv &default_page); 2507218530Sjfv if (ret_val) 2508238148Sjfv return ret_val; 2509218530Sjfv 2510218530Sjfv ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 2511218530Sjfv if (ret_val) 2512238148Sjfv return ret_val; 2513218530Sjfv 2514218530Sjfv ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 2515218530Sjfv &phy_data); 2516218530Sjfv if (ret_val) 2517238148Sjfv return ret_val; 2518218530Sjfv 2519218530Sjfv index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2520218530Sjfv M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2521218530Sjfv 2522238148Sjfv if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2523238148Sjfv return -E1000_ERR_PHY; 2524238148Sjfv 2525218530Sjfv phy->min_cable_length = e1000_m88_cable_length_table[index]; 2526218530Sjfv phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2527218530Sjfv 2528218530Sjfv phy->cable_length = (phy->min_cable_length + 2529218530Sjfv phy->max_cable_length) / 2; 2530218530Sjfv 2531218530Sjfv /* Reset the page select to its original value */ 2532218530Sjfv ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2533218530Sjfv default_page); 2534218530Sjfv if (ret_val) 2535238148Sjfv return ret_val; 2536218530Sjfv 2537218530Sjfv break; 2538218530Sjfv default: 2539238148Sjfv return -E1000_ERR_PHY; 2540218530Sjfv } 2541218530Sjfv 2542218530Sjfv return ret_val; 2543218530Sjfv} 2544218530Sjfv 2545169240Sjfv/** 2546169240Sjfv * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2547169589Sjfv * @hw: pointer to the HW structure 2548169240Sjfv * 2549169240Sjfv * The automatic gain control (agc) normalizes the amplitude of the 2550169240Sjfv * received signal, adjusting for the attenuation produced by the 2551176667Sjfv * cable. By reading the AGC registers, which represent the 2552176667Sjfv * combination of coarse and fine gain value, the value can be put 2553169240Sjfv * into a lookup table to obtain the approximate cable length 2554169240Sjfv * for each channel. 2555169240Sjfv **/ 2556173788Sjfvs32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2557169240Sjfv{ 2558169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2559238148Sjfv s32 ret_val; 2560169240Sjfv u16 phy_data, i, agc_value = 0; 2561169240Sjfv u16 cur_agc_index, max_agc_index = 0; 2562169240Sjfv u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2563218530Sjfv static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 2564228386Sjfv IGP02E1000_PHY_AGC_A, 2565228386Sjfv IGP02E1000_PHY_AGC_B, 2566228386Sjfv IGP02E1000_PHY_AGC_C, 2567228386Sjfv IGP02E1000_PHY_AGC_D 2568218530Sjfv }; 2569169240Sjfv 2570169240Sjfv DEBUGFUNC("e1000_get_cable_length_igp_2"); 2571169240Sjfv 2572169240Sjfv /* Read the AGC registers for all channels */ 2573169240Sjfv for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2574177867Sjfv ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2575169240Sjfv if (ret_val) 2576238148Sjfv return ret_val; 2577169240Sjfv 2578247064Sjfv /* Getting bits 15:9, which represent the combination of 2579176667Sjfv * coarse and fine gain values. The result is a number 2580169240Sjfv * that can be put into the lookup table to obtain the 2581173788Sjfv * approximate cable length. 2582173788Sjfv */ 2583256200Sjfv cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2584256200Sjfv IGP02E1000_AGC_LENGTH_MASK); 2585169240Sjfv 2586169240Sjfv /* Array index bound check. */ 2587169240Sjfv if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2588238148Sjfv (cur_agc_index == 0)) 2589238148Sjfv return -E1000_ERR_PHY; 2590169240Sjfv 2591169240Sjfv /* Remove min & max AGC values from calculation. */ 2592169240Sjfv if (e1000_igp_2_cable_length_table[min_agc_index] > 2593169240Sjfv e1000_igp_2_cable_length_table[cur_agc_index]) 2594169240Sjfv min_agc_index = cur_agc_index; 2595169240Sjfv if (e1000_igp_2_cable_length_table[max_agc_index] < 2596169240Sjfv e1000_igp_2_cable_length_table[cur_agc_index]) 2597169240Sjfv max_agc_index = cur_agc_index; 2598169240Sjfv 2599169240Sjfv agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2600169240Sjfv } 2601169240Sjfv 2602169240Sjfv agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2603228386Sjfv e1000_igp_2_cable_length_table[max_agc_index]); 2604169240Sjfv agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2605169240Sjfv 2606169240Sjfv /* Calculate cable length with the error range of +/- 10 meters. */ 2607256200Sjfv phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2608256200Sjfv (agc_value - IGP02E1000_AGC_RANGE) : 0); 2609169240Sjfv phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2610169240Sjfv 2611169240Sjfv phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2612169240Sjfv 2613238148Sjfv return E1000_SUCCESS; 2614169240Sjfv} 2615169240Sjfv 2616169240Sjfv/** 2617169240Sjfv * e1000_get_phy_info_m88 - Retrieve PHY information 2618169589Sjfv * @hw: pointer to the HW structure 2619169240Sjfv * 2620169240Sjfv * Valid for only copper links. Read the PHY status register (sticky read) 2621169240Sjfv * to verify that link is up. Read the PHY special control register to 2622169240Sjfv * determine the polarity and 10base-T extended distance. Read the PHY 2623169240Sjfv * special status register to determine MDI/MDIx and current speed. If 2624169240Sjfv * speed is 1000, then determine cable length, local and remote receiver. 2625169240Sjfv **/ 2626173788Sjfvs32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2627169240Sjfv{ 2628169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2629169240Sjfv s32 ret_val; 2630169240Sjfv u16 phy_data; 2631173788Sjfv bool link; 2632169240Sjfv 2633169240Sjfv DEBUGFUNC("e1000_get_phy_info_m88"); 2634169240Sjfv 2635200243Sjfv if (phy->media_type != e1000_media_type_copper) { 2636169240Sjfv DEBUGOUT("Phy info is only valid for copper media\n"); 2637238148Sjfv return -E1000_ERR_CONFIG; 2638169240Sjfv } 2639169240Sjfv 2640169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2641169240Sjfv if (ret_val) 2642238148Sjfv return ret_val; 2643169240Sjfv 2644169240Sjfv if (!link) { 2645169240Sjfv DEBUGOUT("Phy info is only valid if link is up\n"); 2646238148Sjfv return -E1000_ERR_CONFIG; 2647169240Sjfv } 2648169240Sjfv 2649177867Sjfv ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2650169240Sjfv if (ret_val) 2651238148Sjfv return ret_val; 2652169240Sjfv 2653238148Sjfv phy->polarity_correction = !!(phy_data & 2654238148Sjfv M88E1000_PSCR_POLARITY_REVERSAL); 2655169240Sjfv 2656169240Sjfv ret_val = e1000_check_polarity_m88(hw); 2657169240Sjfv if (ret_val) 2658238148Sjfv return ret_val; 2659169240Sjfv 2660177867Sjfv ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2661169240Sjfv if (ret_val) 2662238148Sjfv return ret_val; 2663169240Sjfv 2664238148Sjfv phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); 2665169240Sjfv 2666169240Sjfv if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2667181027Sjfv ret_val = hw->phy.ops.get_cable_length(hw); 2668169240Sjfv if (ret_val) 2669238148Sjfv return ret_val; 2670169240Sjfv 2671177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2672169240Sjfv if (ret_val) 2673238148Sjfv return ret_val; 2674169240Sjfv 2675169240Sjfv phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2676228386Sjfv ? e1000_1000t_rx_status_ok 2677228386Sjfv : e1000_1000t_rx_status_not_ok; 2678169240Sjfv 2679169240Sjfv phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2680228386Sjfv ? e1000_1000t_rx_status_ok 2681228386Sjfv : e1000_1000t_rx_status_not_ok; 2682169240Sjfv } else { 2683169240Sjfv /* Set values to "undefined" */ 2684169240Sjfv phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2685169240Sjfv phy->local_rx = e1000_1000t_rx_status_undefined; 2686169240Sjfv phy->remote_rx = e1000_1000t_rx_status_undefined; 2687169240Sjfv } 2688169240Sjfv 2689169240Sjfv return ret_val; 2690169240Sjfv} 2691169240Sjfv 2692169240Sjfv/** 2693169240Sjfv * e1000_get_phy_info_igp - Retrieve igp PHY information 2694169589Sjfv * @hw: pointer to the HW structure 2695169240Sjfv * 2696169240Sjfv * Read PHY status to determine if link is up. If link is up, then 2697169240Sjfv * set/determine 10base-T extended distance and polarity correction. Read 2698169240Sjfv * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2699169240Sjfv * determine on the cable length, local and remote receiver. 2700169240Sjfv **/ 2701173788Sjfvs32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2702169240Sjfv{ 2703169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2704169240Sjfv s32 ret_val; 2705169240Sjfv u16 data; 2706173788Sjfv bool link; 2707169240Sjfv 2708169240Sjfv DEBUGFUNC("e1000_get_phy_info_igp"); 2709169240Sjfv 2710169240Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2711169240Sjfv if (ret_val) 2712238148Sjfv return ret_val; 2713169240Sjfv 2714169240Sjfv if (!link) { 2715169240Sjfv DEBUGOUT("Phy info is only valid if link is up\n"); 2716238148Sjfv return -E1000_ERR_CONFIG; 2717169240Sjfv } 2718169240Sjfv 2719169240Sjfv phy->polarity_correction = TRUE; 2720169240Sjfv 2721169240Sjfv ret_val = e1000_check_polarity_igp(hw); 2722169240Sjfv if (ret_val) 2723238148Sjfv return ret_val; 2724169240Sjfv 2725177867Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2726169240Sjfv if (ret_val) 2727238148Sjfv return ret_val; 2728169240Sjfv 2729238148Sjfv phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); 2730169240Sjfv 2731169240Sjfv if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2732169240Sjfv IGP01E1000_PSSR_SPEED_1000MBPS) { 2733200243Sjfv ret_val = phy->ops.get_cable_length(hw); 2734169240Sjfv if (ret_val) 2735238148Sjfv return ret_val; 2736169240Sjfv 2737177867Sjfv ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2738169240Sjfv if (ret_val) 2739238148Sjfv return ret_val; 2740169240Sjfv 2741169240Sjfv phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2742228386Sjfv ? e1000_1000t_rx_status_ok 2743228386Sjfv : e1000_1000t_rx_status_not_ok; 2744169240Sjfv 2745169240Sjfv phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2746228386Sjfv ? e1000_1000t_rx_status_ok 2747228386Sjfv : e1000_1000t_rx_status_not_ok; 2748169240Sjfv } else { 2749169240Sjfv phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2750169240Sjfv phy->local_rx = e1000_1000t_rx_status_undefined; 2751169240Sjfv phy->remote_rx = e1000_1000t_rx_status_undefined; 2752169240Sjfv } 2753169240Sjfv 2754169240Sjfv return ret_val; 2755169240Sjfv} 2756169240Sjfv 2757169240Sjfv/** 2758200243Sjfv * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2759200243Sjfv * @hw: pointer to the HW structure 2760200243Sjfv * 2761200243Sjfv * Populates "phy" structure with various feature states. 2762200243Sjfv **/ 2763200243Sjfvs32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2764200243Sjfv{ 2765200243Sjfv struct e1000_phy_info *phy = &hw->phy; 2766200243Sjfv s32 ret_val; 2767200243Sjfv u16 data; 2768200243Sjfv bool link; 2769200243Sjfv 2770200243Sjfv DEBUGFUNC("e1000_get_phy_info_ife"); 2771200243Sjfv 2772200243Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2773200243Sjfv if (ret_val) 2774238148Sjfv return ret_val; 2775200243Sjfv 2776200243Sjfv if (!link) { 2777200243Sjfv DEBUGOUT("Phy info is only valid if link is up\n"); 2778238148Sjfv return -E1000_ERR_CONFIG; 2779200243Sjfv } 2780200243Sjfv 2781200243Sjfv ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2782200243Sjfv if (ret_val) 2783238148Sjfv return ret_val; 2784238148Sjfv phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); 2785200243Sjfv 2786200243Sjfv if (phy->polarity_correction) { 2787200243Sjfv ret_val = e1000_check_polarity_ife(hw); 2788200243Sjfv if (ret_val) 2789238148Sjfv return ret_val; 2790200243Sjfv } else { 2791200243Sjfv /* Polarity is forced */ 2792256200Sjfv phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY) 2793256200Sjfv ? e1000_rev_polarity_reversed 2794256200Sjfv : e1000_rev_polarity_normal); 2795200243Sjfv } 2796200243Sjfv 2797200243Sjfv ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2798200243Sjfv if (ret_val) 2799238148Sjfv return ret_val; 2800200243Sjfv 2801238148Sjfv phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); 2802200243Sjfv 2803200243Sjfv /* The following parameters are undefined for 10/100 operation. */ 2804200243Sjfv phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2805200243Sjfv phy->local_rx = e1000_1000t_rx_status_undefined; 2806200243Sjfv phy->remote_rx = e1000_1000t_rx_status_undefined; 2807200243Sjfv 2808238148Sjfv return E1000_SUCCESS; 2809200243Sjfv} 2810200243Sjfv 2811200243Sjfv/** 2812169240Sjfv * e1000_phy_sw_reset_generic - PHY software reset 2813169589Sjfv * @hw: pointer to the HW structure 2814169240Sjfv * 2815169240Sjfv * Does a software reset of the PHY by reading the PHY control register and 2816169240Sjfv * setting/write the control register reset bit to the PHY. 2817169240Sjfv **/ 2818173788Sjfvs32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2819169240Sjfv{ 2820238148Sjfv s32 ret_val; 2821169240Sjfv u16 phy_ctrl; 2822169240Sjfv 2823169240Sjfv DEBUGFUNC("e1000_phy_sw_reset_generic"); 2824169240Sjfv 2825238148Sjfv if (!hw->phy.ops.read_reg) 2826238148Sjfv return E1000_SUCCESS; 2827177867Sjfv 2828177867Sjfv ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2829169240Sjfv if (ret_val) 2830238148Sjfv return ret_val; 2831169240Sjfv 2832169240Sjfv phy_ctrl |= MII_CR_RESET; 2833177867Sjfv ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2834169240Sjfv if (ret_val) 2835238148Sjfv return ret_val; 2836169240Sjfv 2837169240Sjfv usec_delay(1); 2838169240Sjfv 2839169240Sjfv return ret_val; 2840169240Sjfv} 2841169240Sjfv 2842169240Sjfv/** 2843169240Sjfv * e1000_phy_hw_reset_generic - PHY hardware reset 2844169589Sjfv * @hw: pointer to the HW structure 2845169240Sjfv * 2846169240Sjfv * Verify the reset block is not blocking us from resetting. Acquire 2847169240Sjfv * semaphore (if necessary) and read/set/write the device control reset 2848169240Sjfv * bit in the PHY. Wait the appropriate delay time for the device to 2849176667Sjfv * reset and release the semaphore (if necessary). 2850169240Sjfv **/ 2851173788Sjfvs32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2852169240Sjfv{ 2853169240Sjfv struct e1000_phy_info *phy = &hw->phy; 2854238148Sjfv s32 ret_val; 2855169240Sjfv u32 ctrl; 2856169240Sjfv 2857169240Sjfv DEBUGFUNC("e1000_phy_hw_reset_generic"); 2858169240Sjfv 2859238148Sjfv if (phy->ops.check_reset_block) { 2860238148Sjfv ret_val = phy->ops.check_reset_block(hw); 2861238148Sjfv if (ret_val) 2862238148Sjfv return E1000_SUCCESS; 2863169240Sjfv } 2864169240Sjfv 2865177867Sjfv ret_val = phy->ops.acquire(hw); 2866169240Sjfv if (ret_val) 2867238148Sjfv return ret_val; 2868169240Sjfv 2869169240Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2870169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2871169240Sjfv E1000_WRITE_FLUSH(hw); 2872169240Sjfv 2873169240Sjfv usec_delay(phy->reset_delay_us); 2874169240Sjfv 2875169240Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2876169240Sjfv E1000_WRITE_FLUSH(hw); 2877169240Sjfv 2878169240Sjfv usec_delay(150); 2879169240Sjfv 2880177867Sjfv phy->ops.release(hw); 2881169240Sjfv 2882238148Sjfv return phy->ops.get_cfg_done(hw); 2883169240Sjfv} 2884169240Sjfv 2885169240Sjfv/** 2886169240Sjfv * e1000_get_cfg_done_generic - Generic configuration done 2887169589Sjfv * @hw: pointer to the HW structure 2888169240Sjfv * 2889169240Sjfv * Generic function to wait 10 milli-seconds for configuration to complete 2890169240Sjfv * and return success. 2891169240Sjfv **/ 2892256200Sjfvs32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2893169240Sjfv{ 2894169240Sjfv DEBUGFUNC("e1000_get_cfg_done_generic"); 2895169240Sjfv 2896169240Sjfv msec_delay_irq(10); 2897169240Sjfv 2898169240Sjfv return E1000_SUCCESS; 2899169240Sjfv} 2900169240Sjfv 2901169240Sjfv/** 2902169240Sjfv * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2903169589Sjfv * @hw: pointer to the HW structure 2904169240Sjfv * 2905169240Sjfv * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2906169240Sjfv **/ 2907173788Sjfvs32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2908169240Sjfv{ 2909169240Sjfv DEBUGOUT("Running IGP 3 PHY init script\n"); 2910169240Sjfv 2911169240Sjfv /* PHY init IGP 3 */ 2912169240Sjfv /* Enable rise/fall, 10-mode work in class-A */ 2913177867Sjfv hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2914169240Sjfv /* Remove all caps from Replica path filter */ 2915177867Sjfv hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2916169240Sjfv /* Bias trimming for ADC, AFE and Driver (Default) */ 2917177867Sjfv hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2918169240Sjfv /* Increase Hybrid poly bias */ 2919177867Sjfv hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2920176667Sjfv /* Add 4% to Tx amplitude in Gig mode */ 2921177867Sjfv hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2922169240Sjfv /* Disable trimming (TTT) */ 2923177867Sjfv hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2924169240Sjfv /* Poly DC correction to 94.6% + 2% for all channels */ 2925177867Sjfv hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2926169240Sjfv /* ABS DC correction to 95.9% */ 2927177867Sjfv hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2928169240Sjfv /* BG temp curve trim */ 2929177867Sjfv hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2930169240Sjfv /* Increasing ADC OPAMP stage 1 currents to max */ 2931177867Sjfv hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2932169240Sjfv /* Force 1000 ( required for enabling PHY regs configuration) */ 2933177867Sjfv hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2934169240Sjfv /* Set upd_freq to 6 */ 2935177867Sjfv hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2936169240Sjfv /* Disable NPDFE */ 2937177867Sjfv hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2938169240Sjfv /* Disable adaptive fixed FFE (Default) */ 2939177867Sjfv hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2940169240Sjfv /* Enable FFE hysteresis */ 2941177867Sjfv hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2942169240Sjfv /* Fixed FFE for short cable lengths */ 2943177867Sjfv hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2944169240Sjfv /* Fixed FFE for medium cable lengths */ 2945177867Sjfv hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2946169240Sjfv /* Fixed FFE for long cable lengths */ 2947177867Sjfv hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2948169240Sjfv /* Enable Adaptive Clip Threshold */ 2949177867Sjfv hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2950169240Sjfv /* AHT reset limit to 1 */ 2951177867Sjfv hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2952169240Sjfv /* Set AHT master delay to 127 msec */ 2953177867Sjfv hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2954169240Sjfv /* Set scan bits for AHT */ 2955177867Sjfv hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2956169240Sjfv /* Set AHT Preset bits */ 2957177867Sjfv hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2958169240Sjfv /* Change integ_factor of channel A to 3 */ 2959177867Sjfv hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2960169240Sjfv /* Change prop_factor of channels BCD to 8 */ 2961177867Sjfv hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2962169240Sjfv /* Change cg_icount + enable integbp for channels BCD */ 2963177867Sjfv hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2964247064Sjfv /* Change cg_icount + enable integbp + change prop_factor_master 2965169240Sjfv * to 8 for channel A 2966169240Sjfv */ 2967177867Sjfv hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2968169240Sjfv /* Disable AHT in Slave mode on channel A */ 2969177867Sjfv hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2970247064Sjfv /* Enable LPLU and disable AN to 1000 in non-D0a states, 2971169240Sjfv * Enable SPD+B2B 2972169240Sjfv */ 2973177867Sjfv hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2974169240Sjfv /* Enable restart AN on an1000_dis change */ 2975177867Sjfv hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2976169240Sjfv /* Enable wh_fifo read clock in 10/100 modes */ 2977177867Sjfv hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2978169240Sjfv /* Restart AN, Speed selection is 1000 */ 2979177867Sjfv hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2980169240Sjfv 2981169240Sjfv return E1000_SUCCESS; 2982169240Sjfv} 2983169589Sjfv 2984169589Sjfv/** 2985169589Sjfv * e1000_get_phy_type_from_id - Get PHY type from id 2986169589Sjfv * @phy_id: phy_id read from the phy 2987169589Sjfv * 2988169589Sjfv * Returns the phy type from the id. 2989169589Sjfv **/ 2990181027Sjfvenum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2991169589Sjfv{ 2992181027Sjfv enum e1000_phy_type phy_type = e1000_phy_unknown; 2993169589Sjfv 2994200243Sjfv switch (phy_id) { 2995169589Sjfv case M88E1000_I_PHY_ID: 2996169589Sjfv case M88E1000_E_PHY_ID: 2997169589Sjfv case M88E1111_I_PHY_ID: 2998169589Sjfv case M88E1011_I_PHY_ID: 2999256200Sjfv case M88E1543_E_PHY_ID: 3000256200Sjfv case M88E1512_E_PHY_ID: 3001218530Sjfv case I347AT4_E_PHY_ID: 3002218530Sjfv case M88E1112_E_PHY_ID: 3003219753Sjfv case M88E1340M_E_PHY_ID: 3004169589Sjfv phy_type = e1000_phy_m88; 3005169589Sjfv break; 3006169589Sjfv case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 3007169589Sjfv phy_type = e1000_phy_igp_2; 3008169589Sjfv break; 3009169589Sjfv case GG82563_E_PHY_ID: 3010169589Sjfv phy_type = e1000_phy_gg82563; 3011169589Sjfv break; 3012169589Sjfv case IGP03E1000_E_PHY_ID: 3013169589Sjfv phy_type = e1000_phy_igp_3; 3014169589Sjfv break; 3015169589Sjfv case IFE_E_PHY_ID: 3016169589Sjfv case IFE_PLUS_E_PHY_ID: 3017169589Sjfv case IFE_C_E_PHY_ID: 3018169589Sjfv phy_type = e1000_phy_ife; 3019169589Sjfv break; 3020176667Sjfv case BME1000_E_PHY_ID: 3021176667Sjfv case BME1000_E_PHY_ID_R2: 3022176667Sjfv phy_type = e1000_phy_bm; 3023176667Sjfv break; 3024194865Sjfv case I82578_E_PHY_ID: 3025194865Sjfv phy_type = e1000_phy_82578; 3026194865Sjfv break; 3027194865Sjfv case I82577_E_PHY_ID: 3028194865Sjfv phy_type = e1000_phy_82577; 3029194865Sjfv break; 3030213234Sjfv case I82579_E_PHY_ID: 3031213234Sjfv phy_type = e1000_phy_82579; 3032213234Sjfv break; 3033247064Sjfv case I217_E_PHY_ID: 3034247064Sjfv phy_type = e1000_phy_i217; 3035247064Sjfv break; 3036200243Sjfv case I82580_I_PHY_ID: 3037200243Sjfv phy_type = e1000_phy_82580; 3038200243Sjfv break; 3039238148Sjfv case I210_I_PHY_ID: 3040238148Sjfv phy_type = e1000_phy_i210; 3041238148Sjfv break; 3042169589Sjfv default: 3043169589Sjfv phy_type = e1000_phy_unknown; 3044169589Sjfv break; 3045169589Sjfv } 3046169589Sjfv return phy_type; 3047169589Sjfv} 3048169589Sjfv 3049173788Sjfv/** 3050176667Sjfv * e1000_determine_phy_address - Determines PHY address. 3051176667Sjfv * @hw: pointer to the HW structure 3052176667Sjfv * 3053176667Sjfv * This uses a trial and error method to loop through possible PHY 3054176667Sjfv * addresses. It tests each by reading the PHY ID registers and 3055176667Sjfv * checking for a match. 3056176667Sjfv **/ 3057185353Sjfvs32 e1000_determine_phy_address(struct e1000_hw *hw) 3058176667Sjfv{ 3059185353Sjfv u32 phy_addr = 0; 3060177867Sjfv u32 i; 3061181027Sjfv enum e1000_phy_type phy_type = e1000_phy_unknown; 3062176667Sjfv 3063190872Sjfv hw->phy.id = phy_type; 3064190872Sjfv 3065177867Sjfv for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 3066177867Sjfv hw->phy.addr = phy_addr; 3067177867Sjfv i = 0; 3068177867Sjfv 3069177867Sjfv do { 3070176667Sjfv e1000_get_phy_id(hw); 3071176667Sjfv phy_type = e1000_get_phy_type_from_id(hw->phy.id); 3072176667Sjfv 3073247064Sjfv /* If phy_type is valid, break - we found our 3074185353Sjfv * PHY address 3075185353Sjfv */ 3076238148Sjfv if (phy_type != e1000_phy_unknown) 3077238148Sjfv return E1000_SUCCESS; 3078238148Sjfv 3079177867Sjfv msec_delay(1); 3080177867Sjfv i++; 3081177867Sjfv } while (i < 10); 3082177867Sjfv } 3083176667Sjfv 3084238148Sjfv return -E1000_ERR_PHY_TYPE; 3085176667Sjfv} 3086176667Sjfv 3087176667Sjfv/** 3088176667Sjfv * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 3089176667Sjfv * @page: page to access 3090176667Sjfv * 3091176667Sjfv * Returns the phy address for the page requested. 3092176667Sjfv **/ 3093176667Sjfvstatic u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 3094176667Sjfv{ 3095176667Sjfv u32 phy_addr = 2; 3096176667Sjfv 3097176667Sjfv if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 3098176667Sjfv phy_addr = 1; 3099176667Sjfv 3100176667Sjfv return phy_addr; 3101176667Sjfv} 3102176667Sjfv 3103176667Sjfv/** 3104176667Sjfv * e1000_write_phy_reg_bm - Write BM PHY register 3105176667Sjfv * @hw: pointer to the HW structure 3106176667Sjfv * @offset: register offset to write to 3107176667Sjfv * @data: data to write at register offset 3108176667Sjfv * 3109176667Sjfv * Acquires semaphore, if necessary, then writes the data to PHY register 3110176667Sjfv * at the offset. Release any acquired semaphores before exiting. 3111176667Sjfv **/ 3112176667Sjfvs32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 3113176667Sjfv{ 3114176667Sjfv s32 ret_val; 3115176667Sjfv u32 page = offset >> IGP_PAGE_SHIFT; 3116176667Sjfv 3117176667Sjfv DEBUGFUNC("e1000_write_phy_reg_bm"); 3118176667Sjfv 3119200243Sjfv ret_val = hw->phy.ops.acquire(hw); 3120200243Sjfv if (ret_val) 3121200243Sjfv return ret_val; 3122200243Sjfv 3123176667Sjfv /* Page 800 works differently than the rest so it has its own func */ 3124176667Sjfv if (page == BM_WUC_PAGE) { 3125185353Sjfv ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3126294958Smarius FALSE, false); 3127238148Sjfv goto release; 3128176667Sjfv } 3129176667Sjfv 3130176667Sjfv hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3131176667Sjfv 3132176667Sjfv if (offset > MAX_PHY_MULTI_PAGE_REG) { 3133218530Sjfv u32 page_shift, page_select; 3134218530Sjfv 3135247064Sjfv /* Page select is register 31 for phy address 1 and 22 for 3136176667Sjfv * phy address 2 and 3. Page select is shifted only for 3137176667Sjfv * phy address 1. 3138176667Sjfv */ 3139176667Sjfv if (hw->phy.addr == 1) { 3140176667Sjfv page_shift = IGP_PAGE_SHIFT; 3141176667Sjfv page_select = IGP01E1000_PHY_PAGE_SELECT; 3142176667Sjfv } else { 3143176667Sjfv page_shift = 0; 3144176667Sjfv page_select = BM_PHY_PAGE_SELECT; 3145176667Sjfv } 3146176667Sjfv 3147176667Sjfv /* Page is shifted left, PHY expects (page x 32) */ 3148176667Sjfv ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3149228386Sjfv (page << page_shift)); 3150200243Sjfv if (ret_val) 3151238148Sjfv goto release; 3152176667Sjfv } 3153176667Sjfv 3154185353Sjfv ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3155228386Sjfv data); 3156176667Sjfv 3157238148Sjfvrelease: 3158177867Sjfv hw->phy.ops.release(hw); 3159176667Sjfv return ret_val; 3160176667Sjfv} 3161176667Sjfv 3162176667Sjfv/** 3163176667Sjfv * e1000_read_phy_reg_bm - Read BM PHY register 3164176667Sjfv * @hw: pointer to the HW structure 3165176667Sjfv * @offset: register offset to be read 3166176667Sjfv * @data: pointer to the read data 3167176667Sjfv * 3168176667Sjfv * Acquires semaphore, if necessary, then reads the PHY register at offset 3169176667Sjfv * and storing the retrieved information in data. Release any acquired 3170176667Sjfv * semaphores before exiting. 3171176667Sjfv **/ 3172176667Sjfvs32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 3173176667Sjfv{ 3174176667Sjfv s32 ret_val; 3175176667Sjfv u32 page = offset >> IGP_PAGE_SHIFT; 3176176667Sjfv 3177177867Sjfv DEBUGFUNC("e1000_read_phy_reg_bm"); 3178176667Sjfv 3179200243Sjfv ret_val = hw->phy.ops.acquire(hw); 3180200243Sjfv if (ret_val) 3181200243Sjfv return ret_val; 3182200243Sjfv 3183176667Sjfv /* Page 800 works differently than the rest so it has its own func */ 3184176667Sjfv if (page == BM_WUC_PAGE) { 3185185353Sjfv ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3186228386Sjfv TRUE, FALSE); 3187238148Sjfv goto release; 3188176667Sjfv } 3189176667Sjfv 3190176667Sjfv hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3191176667Sjfv 3192176667Sjfv if (offset > MAX_PHY_MULTI_PAGE_REG) { 3193218530Sjfv u32 page_shift, page_select; 3194218530Sjfv 3195247064Sjfv /* Page select is register 31 for phy address 1 and 22 for 3196176667Sjfv * phy address 2 and 3. Page select is shifted only for 3197176667Sjfv * phy address 1. 3198176667Sjfv */ 3199176667Sjfv if (hw->phy.addr == 1) { 3200176667Sjfv page_shift = IGP_PAGE_SHIFT; 3201176667Sjfv page_select = IGP01E1000_PHY_PAGE_SELECT; 3202176667Sjfv } else { 3203176667Sjfv page_shift = 0; 3204176667Sjfv page_select = BM_PHY_PAGE_SELECT; 3205176667Sjfv } 3206176667Sjfv 3207176667Sjfv /* Page is shifted left, PHY expects (page x 32) */ 3208176667Sjfv ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3209228386Sjfv (page << page_shift)); 3210200243Sjfv if (ret_val) 3211238148Sjfv goto release; 3212176667Sjfv } 3213176667Sjfv 3214185353Sjfv ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3215228386Sjfv data); 3216238148Sjfvrelease: 3217177867Sjfv hw->phy.ops.release(hw); 3218176667Sjfv return ret_val; 3219176667Sjfv} 3220176667Sjfv 3221176667Sjfv/** 3222178523Sjfv * e1000_read_phy_reg_bm2 - Read BM PHY register 3223178523Sjfv * @hw: pointer to the HW structure 3224178523Sjfv * @offset: register offset to be read 3225178523Sjfv * @data: pointer to the read data 3226178523Sjfv * 3227178523Sjfv * Acquires semaphore, if necessary, then reads the PHY register at offset 3228178523Sjfv * and storing the retrieved information in data. Release any acquired 3229178523Sjfv * semaphores before exiting. 3230178523Sjfv **/ 3231178523Sjfvs32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 3232178523Sjfv{ 3233178523Sjfv s32 ret_val; 3234178523Sjfv u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3235178523Sjfv 3236228386Sjfv DEBUGFUNC("e1000_read_phy_reg_bm2"); 3237178523Sjfv 3238200243Sjfv ret_val = hw->phy.ops.acquire(hw); 3239200243Sjfv if (ret_val) 3240200243Sjfv return ret_val; 3241200243Sjfv 3242178523Sjfv /* Page 800 works differently than the rest so it has its own func */ 3243178523Sjfv if (page == BM_WUC_PAGE) { 3244178523Sjfv ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3245228386Sjfv TRUE, FALSE); 3246238148Sjfv goto release; 3247178523Sjfv } 3248178523Sjfv 3249178523Sjfv hw->phy.addr = 1; 3250178523Sjfv 3251178523Sjfv if (offset > MAX_PHY_MULTI_PAGE_REG) { 3252178523Sjfv /* Page is shifted left, PHY expects (page x 32) */ 3253178523Sjfv ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3254228386Sjfv page); 3255178523Sjfv 3256200243Sjfv if (ret_val) 3257238148Sjfv goto release; 3258178523Sjfv } 3259178523Sjfv 3260185353Sjfv ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3261228386Sjfv data); 3262238148Sjfvrelease: 3263178523Sjfv hw->phy.ops.release(hw); 3264178523Sjfv return ret_val; 3265178523Sjfv} 3266178523Sjfv 3267178523Sjfv/** 3268178523Sjfv * e1000_write_phy_reg_bm2 - Write BM PHY register 3269178523Sjfv * @hw: pointer to the HW structure 3270178523Sjfv * @offset: register offset to write to 3271178523Sjfv * @data: data to write at register offset 3272178523Sjfv * 3273178523Sjfv * Acquires semaphore, if necessary, then writes the data to PHY register 3274178523Sjfv * at the offset. Release any acquired semaphores before exiting. 3275178523Sjfv **/ 3276178523Sjfvs32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 3277178523Sjfv{ 3278178523Sjfv s32 ret_val; 3279178523Sjfv u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3280178523Sjfv 3281178523Sjfv DEBUGFUNC("e1000_write_phy_reg_bm2"); 3282178523Sjfv 3283200243Sjfv ret_val = hw->phy.ops.acquire(hw); 3284200243Sjfv if (ret_val) 3285200243Sjfv return ret_val; 3286200243Sjfv 3287178523Sjfv /* Page 800 works differently than the rest so it has its own func */ 3288178523Sjfv if (page == BM_WUC_PAGE) { 3289178523Sjfv ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3290294958Smarius FALSE, false); 3291238148Sjfv goto release; 3292178523Sjfv } 3293178523Sjfv 3294178523Sjfv hw->phy.addr = 1; 3295178523Sjfv 3296178523Sjfv if (offset > MAX_PHY_MULTI_PAGE_REG) { 3297178523Sjfv /* Page is shifted left, PHY expects (page x 32) */ 3298178523Sjfv ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3299228386Sjfv page); 3300178523Sjfv 3301200243Sjfv if (ret_val) 3302238148Sjfv goto release; 3303178523Sjfv } 3304178523Sjfv 3305178523Sjfv ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3306228386Sjfv data); 3307178523Sjfv 3308238148Sjfvrelease: 3309178523Sjfv hw->phy.ops.release(hw); 3310178523Sjfv return ret_val; 3311178523Sjfv} 3312178523Sjfv 3313178523Sjfv/** 3314228386Sjfv * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 3315176667Sjfv * @hw: pointer to the HW structure 3316228386Sjfv * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 3317228386Sjfv * 3318228386Sjfv * Assumes semaphore already acquired and phy_reg points to a valid memory 3319228386Sjfv * address to store contents of the BM_WUC_ENABLE_REG register. 3320228386Sjfv **/ 3321228386Sjfvs32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3322228386Sjfv{ 3323228386Sjfv s32 ret_val; 3324228386Sjfv u16 temp; 3325228386Sjfv 3326228386Sjfv DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm"); 3327228386Sjfv 3328238148Sjfv if (!phy_reg) 3329238148Sjfv return -E1000_ERR_PARAM; 3330228386Sjfv 3331228386Sjfv /* All page select, port ctrl and wakeup registers use phy address 1 */ 3332228386Sjfv hw->phy.addr = 1; 3333228386Sjfv 3334228386Sjfv /* Select Port Control Registers page */ 3335228386Sjfv ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3336228386Sjfv if (ret_val) { 3337228386Sjfv DEBUGOUT("Could not set Port Control page\n"); 3338238148Sjfv return ret_val; 3339228386Sjfv } 3340228386Sjfv 3341228386Sjfv ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3342228386Sjfv if (ret_val) { 3343228386Sjfv DEBUGOUT2("Could not read PHY register %d.%d\n", 3344228386Sjfv BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3345238148Sjfv return ret_val; 3346228386Sjfv } 3347228386Sjfv 3348247064Sjfv /* Enable both PHY wakeup mode and Wakeup register page writes. 3349228386Sjfv * Prevent a power state change by disabling ME and Host PHY wakeup. 3350228386Sjfv */ 3351228386Sjfv temp = *phy_reg; 3352228386Sjfv temp |= BM_WUC_ENABLE_BIT; 3353228386Sjfv temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 3354228386Sjfv 3355228386Sjfv ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 3356228386Sjfv if (ret_val) { 3357228386Sjfv DEBUGOUT2("Could not write PHY register %d.%d\n", 3358228386Sjfv BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3359238148Sjfv return ret_val; 3360228386Sjfv } 3361228386Sjfv 3362247064Sjfv /* Select Host Wakeup Registers page - caller now able to write 3363238148Sjfv * registers on the Wakeup registers page 3364238148Sjfv */ 3365238148Sjfv return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 3366228386Sjfv} 3367228386Sjfv 3368228386Sjfv/** 3369228386Sjfv * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 3370228386Sjfv * @hw: pointer to the HW structure 3371228386Sjfv * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 3372228386Sjfv * 3373228386Sjfv * Restore BM_WUC_ENABLE_REG to its original value. 3374228386Sjfv * 3375228386Sjfv * Assumes semaphore already acquired and *phy_reg is the contents of the 3376228386Sjfv * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 3377228386Sjfv * caller. 3378228386Sjfv **/ 3379228386Sjfvs32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3380228386Sjfv{ 3381247064Sjfv s32 ret_val; 3382228386Sjfv 3383228386Sjfv DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm"); 3384228386Sjfv 3385228386Sjfv if (!phy_reg) 3386228386Sjfv return -E1000_ERR_PARAM; 3387228386Sjfv 3388228386Sjfv /* Select Port Control Registers page */ 3389228386Sjfv ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3390228386Sjfv if (ret_val) { 3391228386Sjfv DEBUGOUT("Could not set Port Control page\n"); 3392238148Sjfv return ret_val; 3393228386Sjfv } 3394228386Sjfv 3395228386Sjfv /* Restore 769.17 to its original value */ 3396228386Sjfv ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 3397228386Sjfv if (ret_val) 3398228386Sjfv DEBUGOUT2("Could not restore PHY register %d.%d\n", 3399228386Sjfv BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3400238148Sjfv 3401228386Sjfv return ret_val; 3402228386Sjfv} 3403228386Sjfv 3404228386Sjfv/** 3405228386Sjfv * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 3406228386Sjfv * @hw: pointer to the HW structure 3407176667Sjfv * @offset: register offset to be read or written 3408176667Sjfv * @data: pointer to the data to read or write 3409176667Sjfv * @read: determines if operation is read or write 3410228386Sjfv * @page_set: BM_WUC_PAGE already set and access enabled 3411176667Sjfv * 3412228386Sjfv * Read the PHY register at offset and store the retrieved information in 3413228386Sjfv * data, or write data to PHY register at offset. Note the procedure to 3414228386Sjfv * access the PHY wakeup registers is different than reading the other PHY 3415228386Sjfv * registers. It works as such: 3416228386Sjfv * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 3417176667Sjfv * 2) Set page to 800 for host (801 if we were manageability) 3418176667Sjfv * 3) Write the address using the address opcode (0x11) 3419176667Sjfv * 4) Read or write the data using the data opcode (0x12) 3420228386Sjfv * 5) Restore 769.17.2 to its original value 3421200243Sjfv * 3422228386Sjfv * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 3423228386Sjfv * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 3424228386Sjfv * 3425228386Sjfv * Assumes semaphore is already acquired. When page_set==TRUE, assumes 3426228386Sjfv * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 3427228386Sjfv * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 3428176667Sjfv **/ 3429185353Sjfvstatic s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 3430228386Sjfv u16 *data, bool read, bool page_set) 3431176667Sjfv{ 3432176667Sjfv s32 ret_val; 3433296055Serj u16 reg = BM_PHY_REG_NUM(offset); 3434296055Serj u16 page = BM_PHY_REG_PAGE(offset); 3435176667Sjfv u16 phy_reg = 0; 3436176667Sjfv 3437190872Sjfv DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 3438294958Smarius 3439228386Sjfv /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 3440194865Sjfv if ((hw->mac.type == e1000_pchlan) && 3441194865Sjfv (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 3442228386Sjfv DEBUGOUT1("Attempting to access page %d while gig enabled.\n", 3443228386Sjfv page); 3444194865Sjfv 3445228386Sjfv if (!page_set) { 3446228386Sjfv /* Enable access to PHY wakeup registers */ 3447228386Sjfv ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3448228386Sjfv if (ret_val) { 3449228386Sjfv DEBUGOUT("Could not enable PHY wakeup reg access\n"); 3450238148Sjfv return ret_val; 3451228386Sjfv } 3452176667Sjfv } 3453176667Sjfv 3454228386Sjfv DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg); 3455176667Sjfv 3456228386Sjfv /* Write the Wakeup register page offset value using opcode 0x11 */ 3457176667Sjfv ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 3458176667Sjfv if (ret_val) { 3459228386Sjfv DEBUGOUT1("Could not write address opcode to page %d\n", page); 3460238148Sjfv return ret_val; 3461176667Sjfv } 3462176667Sjfv 3463176667Sjfv if (read) { 3464228386Sjfv /* Read the Wakeup register page value using opcode 0x12 */ 3465176667Sjfv ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3466228386Sjfv data); 3467176667Sjfv } else { 3468228386Sjfv /* Write the Wakeup register page value using opcode 0x12 */ 3469176667Sjfv ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3470228386Sjfv *data); 3471176667Sjfv } 3472176667Sjfv 3473176667Sjfv if (ret_val) { 3474228386Sjfv DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg); 3475238148Sjfv return ret_val; 3476176667Sjfv } 3477176667Sjfv 3478228386Sjfv if (!page_set) 3479228386Sjfv ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3480176667Sjfv 3481176667Sjfv return ret_val; 3482176667Sjfv} 3483176667Sjfv 3484176667Sjfv/** 3485173788Sjfv * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 3486173788Sjfv * @hw: pointer to the HW structure 3487173788Sjfv * 3488173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 3489173788Sjfv * driver unload, or wake on lan is not enabled, restore the link to previous 3490173788Sjfv * settings. 3491173788Sjfv **/ 3492173788Sjfvvoid e1000_power_up_phy_copper(struct e1000_hw *hw) 3493173788Sjfv{ 3494173788Sjfv u16 mii_reg = 0; 3495169589Sjfv 3496173788Sjfv /* The PHY will retain its settings across a power down/up cycle */ 3497177867Sjfv hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3498173788Sjfv mii_reg &= ~MII_CR_POWER_DOWN; 3499177867Sjfv hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3500173788Sjfv} 3501173788Sjfv 3502173788Sjfv/** 3503173788Sjfv * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 3504173788Sjfv * @hw: pointer to the HW structure 3505173788Sjfv * 3506173788Sjfv * In the case of a PHY power down to save power, or to turn off link during a 3507173788Sjfv * driver unload, or wake on lan is not enabled, restore the link to previous 3508173788Sjfv * settings. 3509173788Sjfv **/ 3510173788Sjfvvoid e1000_power_down_phy_copper(struct e1000_hw *hw) 3511173788Sjfv{ 3512173788Sjfv u16 mii_reg = 0; 3513173788Sjfv 3514173788Sjfv /* The PHY will retain its settings across a power down/up cycle */ 3515177867Sjfv hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3516173788Sjfv mii_reg |= MII_CR_POWER_DOWN; 3517177867Sjfv hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3518173788Sjfv msec_delay(1); 3519173788Sjfv} 3520194865Sjfv 3521200243Sjfv/** 3522200243Sjfv * __e1000_read_phy_reg_hv - Read HV PHY register 3523194865Sjfv * @hw: pointer to the HW structure 3524194865Sjfv * @offset: register offset to be read 3525194865Sjfv * @data: pointer to the read data 3526200243Sjfv * @locked: semaphore has already been acquired or not 3527194865Sjfv * 3528194865Sjfv * Acquires semaphore, if necessary, then reads the PHY register at offset 3529200243Sjfv * and stores the retrieved information in data. Release any acquired 3530194865Sjfv * semaphore before exiting. 3531194865Sjfv **/ 3532200243Sjfvstatic s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 3533228386Sjfv bool locked, bool page_set) 3534194865Sjfv{ 3535194865Sjfv s32 ret_val; 3536194865Sjfv u16 page = BM_PHY_REG_PAGE(offset); 3537194865Sjfv u16 reg = BM_PHY_REG_NUM(offset); 3538228386Sjfv u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3539194865Sjfv 3540203049Sjfv DEBUGFUNC("__e1000_read_phy_reg_hv"); 3541194865Sjfv 3542200243Sjfv if (!locked) { 3543200243Sjfv ret_val = hw->phy.ops.acquire(hw); 3544200243Sjfv if (ret_val) 3545200243Sjfv return ret_val; 3546200243Sjfv } 3547194865Sjfv /* Page 800 works differently than the rest so it has its own func */ 3548194865Sjfv if (page == BM_WUC_PAGE) { 3549228386Sjfv ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3550228386Sjfv TRUE, page_set); 3551194865Sjfv goto out; 3552194865Sjfv } 3553194865Sjfv 3554194865Sjfv if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3555194865Sjfv ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3556228386Sjfv data, TRUE); 3557194865Sjfv goto out; 3558194865Sjfv } 3559194865Sjfv 3560228386Sjfv if (!page_set) { 3561228386Sjfv if (page == HV_INTC_FC_PAGE_START) 3562228386Sjfv page = 0; 3563194865Sjfv 3564228386Sjfv if (reg > MAX_PHY_MULTI_PAGE_REG) { 3565228386Sjfv /* Page is shifted left, PHY expects (page x 32) */ 3566228386Sjfv ret_val = e1000_set_page_igp(hw, 3567228386Sjfv (page << IGP_PAGE_SHIFT)); 3568194865Sjfv 3569228386Sjfv hw->phy.addr = phy_addr; 3570194865Sjfv 3571228386Sjfv if (ret_val) 3572228386Sjfv goto out; 3573228386Sjfv } 3574228386Sjfv } 3575194865Sjfv 3576228386Sjfv DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3577228386Sjfv page << IGP_PAGE_SHIFT, reg); 3578200243Sjfv 3579194865Sjfv ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3580228386Sjfv data); 3581194865Sjfvout: 3582200243Sjfv if (!locked) 3583200243Sjfv hw->phy.ops.release(hw); 3584200243Sjfv 3585194865Sjfv return ret_val; 3586194865Sjfv} 3587194865Sjfv 3588194865Sjfv/** 3589200243Sjfv * e1000_read_phy_reg_hv - Read HV PHY register 3590194865Sjfv * @hw: pointer to the HW structure 3591200243Sjfv * @offset: register offset to be read 3592200243Sjfv * @data: pointer to the read data 3593200243Sjfv * 3594200243Sjfv * Acquires semaphore then reads the PHY register at offset and stores 3595200243Sjfv * the retrieved information in data. Release the acquired semaphore 3596200243Sjfv * before exiting. 3597200243Sjfv **/ 3598200243Sjfvs32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3599200243Sjfv{ 3600294958Smarius return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, false); 3601200243Sjfv} 3602200243Sjfv 3603200243Sjfv/** 3604200243Sjfv * e1000_read_phy_reg_hv_locked - Read HV PHY register 3605200243Sjfv * @hw: pointer to the HW structure 3606200243Sjfv * @offset: register offset to be read 3607200243Sjfv * @data: pointer to the read data 3608200243Sjfv * 3609200243Sjfv * Reads the PHY register at offset and stores the retrieved information 3610200243Sjfv * in data. Assumes semaphore already acquired. 3611200243Sjfv **/ 3612200243Sjfvs32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3613200243Sjfv{ 3614228386Sjfv return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3615200243Sjfv} 3616200243Sjfv 3617200243Sjfv/** 3618228386Sjfv * e1000_read_phy_reg_page_hv - Read HV PHY register 3619228386Sjfv * @hw: pointer to the HW structure 3620228386Sjfv * @offset: register offset to write to 3621228386Sjfv * @data: data to write at register offset 3622228386Sjfv * 3623228386Sjfv * Reads the PHY register at offset and stores the retrieved information 3624228386Sjfv * in data. Assumes semaphore already acquired and page already set. 3625228386Sjfv **/ 3626228386Sjfvs32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3627228386Sjfv{ 3628228386Sjfv return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true); 3629228386Sjfv} 3630228386Sjfv 3631228386Sjfv/** 3632200243Sjfv * __e1000_write_phy_reg_hv - Write HV PHY register 3633200243Sjfv * @hw: pointer to the HW structure 3634194865Sjfv * @offset: register offset to write to 3635194865Sjfv * @data: data to write at register offset 3636200243Sjfv * @locked: semaphore has already been acquired or not 3637194865Sjfv * 3638194865Sjfv * Acquires semaphore, if necessary, then writes the data to PHY register 3639194865Sjfv * at the offset. Release any acquired semaphores before exiting. 3640194865Sjfv **/ 3641200243Sjfvstatic s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3642228386Sjfv bool locked, bool page_set) 3643194865Sjfv{ 3644194865Sjfv s32 ret_val; 3645194865Sjfv u16 page = BM_PHY_REG_PAGE(offset); 3646194865Sjfv u16 reg = BM_PHY_REG_NUM(offset); 3647228386Sjfv u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3648194865Sjfv 3649203049Sjfv DEBUGFUNC("__e1000_write_phy_reg_hv"); 3650194865Sjfv 3651200243Sjfv if (!locked) { 3652200243Sjfv ret_val = hw->phy.ops.acquire(hw); 3653200243Sjfv if (ret_val) 3654200243Sjfv return ret_val; 3655200243Sjfv } 3656194865Sjfv /* Page 800 works differently than the rest so it has its own func */ 3657194865Sjfv if (page == BM_WUC_PAGE) { 3658228386Sjfv ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3659228386Sjfv FALSE, page_set); 3660194865Sjfv goto out; 3661194865Sjfv } 3662194865Sjfv 3663194865Sjfv if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3664194865Sjfv ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3665228386Sjfv &data, FALSE); 3666194865Sjfv goto out; 3667194865Sjfv } 3668194865Sjfv 3669228386Sjfv if (!page_set) { 3670228386Sjfv if (page == HV_INTC_FC_PAGE_START) 3671228386Sjfv page = 0; 3672194865Sjfv 3673247064Sjfv /* Workaround MDIO accesses being disabled after entering IEEE 3674228386Sjfv * Power Down (when bit 11 of the PHY Control register is set) 3675228386Sjfv */ 3676228386Sjfv if ((hw->phy.type == e1000_phy_82578) && 3677228386Sjfv (hw->phy.revision >= 1) && 3678228386Sjfv (hw->phy.addr == 2) && 3679238148Sjfv !(MAX_PHY_REG_ADDRESS & reg) && 3680228386Sjfv (data & (1 << 11))) { 3681228386Sjfv u16 data2 = 0x7EFF; 3682228386Sjfv ret_val = e1000_access_phy_debug_regs_hv(hw, 3683228386Sjfv (1 << 6) | 0x3, 3684228386Sjfv &data2, FALSE); 3685228386Sjfv if (ret_val) 3686228386Sjfv goto out; 3687228386Sjfv } 3688194865Sjfv 3689228386Sjfv if (reg > MAX_PHY_MULTI_PAGE_REG) { 3690228386Sjfv /* Page is shifted left, PHY expects (page x 32) */ 3691228386Sjfv ret_val = e1000_set_page_igp(hw, 3692228386Sjfv (page << IGP_PAGE_SHIFT)); 3693194865Sjfv 3694228386Sjfv hw->phy.addr = phy_addr; 3695194865Sjfv 3696228386Sjfv if (ret_val) 3697228386Sjfv goto out; 3698228386Sjfv } 3699228386Sjfv } 3700194865Sjfv 3701228386Sjfv DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3702228386Sjfv page << IGP_PAGE_SHIFT, reg); 3703200243Sjfv 3704194865Sjfv ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3705228386Sjfv data); 3706194865Sjfv 3707194865Sjfvout: 3708200243Sjfv if (!locked) 3709200243Sjfv hw->phy.ops.release(hw); 3710200243Sjfv 3711194865Sjfv return ret_val; 3712194865Sjfv} 3713194865Sjfv 3714194865Sjfv/** 3715200243Sjfv * e1000_write_phy_reg_hv - Write HV PHY register 3716200243Sjfv * @hw: pointer to the HW structure 3717200243Sjfv * @offset: register offset to write to 3718200243Sjfv * @data: data to write at register offset 3719200243Sjfv * 3720200243Sjfv * Acquires semaphore then writes the data to PHY register at the offset. 3721200243Sjfv * Release the acquired semaphores before exiting. 3722200243Sjfv **/ 3723200243Sjfvs32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3724200243Sjfv{ 3725294958Smarius return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, false); 3726200243Sjfv} 3727200243Sjfv 3728200243Sjfv/** 3729200243Sjfv * e1000_write_phy_reg_hv_locked - Write HV PHY register 3730200243Sjfv * @hw: pointer to the HW structure 3731200243Sjfv * @offset: register offset to write to 3732200243Sjfv * @data: data to write at register offset 3733200243Sjfv * 3734200243Sjfv * Writes the data to PHY register at the offset. Assumes semaphore 3735200243Sjfv * already acquired. 3736200243Sjfv **/ 3737200243Sjfvs32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3738200243Sjfv{ 3739228386Sjfv return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3740200243Sjfv} 3741200243Sjfv 3742200243Sjfv/** 3743228386Sjfv * e1000_write_phy_reg_page_hv - Write HV PHY register 3744228386Sjfv * @hw: pointer to the HW structure 3745228386Sjfv * @offset: register offset to write to 3746228386Sjfv * @data: data to write at register offset 3747228386Sjfv * 3748228386Sjfv * Writes the data to PHY register at the offset. Assumes semaphore 3749228386Sjfv * already acquired and page already set. 3750228386Sjfv **/ 3751228386Sjfvs32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 3752228386Sjfv{ 3753228386Sjfv return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true); 3754228386Sjfv} 3755228386Sjfv 3756228386Sjfv/** 3757194865Sjfv * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3758194865Sjfv * @page: page to be accessed 3759194865Sjfv **/ 3760194865Sjfvstatic u32 e1000_get_phy_addr_for_hv_page(u32 page) 3761194865Sjfv{ 3762194865Sjfv u32 phy_addr = 2; 3763194865Sjfv 3764194865Sjfv if (page >= HV_INTC_FC_PAGE_START) 3765194865Sjfv phy_addr = 1; 3766194865Sjfv 3767194865Sjfv return phy_addr; 3768194865Sjfv} 3769194865Sjfv 3770194865Sjfv/** 3771194865Sjfv * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3772194865Sjfv * @hw: pointer to the HW structure 3773194865Sjfv * @offset: register offset to be read or written 3774194865Sjfv * @data: pointer to the data to be read or written 3775228386Sjfv * @read: determines if operation is read or write 3776194865Sjfv * 3777200243Sjfv * Reads the PHY register at offset and stores the retreived information 3778200243Sjfv * in data. Assumes semaphore already acquired. Note that the procedure 3779228386Sjfv * to access these regs uses the address port and data port to read/write. 3780228386Sjfv * These accesses done with PHY address 2 and without using pages. 3781194865Sjfv **/ 3782194865Sjfvstatic s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3783228386Sjfv u16 *data, bool read) 3784194865Sjfv{ 3785194865Sjfv s32 ret_val; 3786247064Sjfv u32 addr_reg; 3787247064Sjfv u32 data_reg; 3788194865Sjfv 3789194865Sjfv DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3790194865Sjfv 3791194865Sjfv /* This takes care of the difference with desktop vs mobile phy */ 3792256200Sjfv addr_reg = ((hw->phy.type == e1000_phy_82578) ? 3793256200Sjfv I82578_ADDR_REG : I82577_ADDR_REG); 3794194865Sjfv data_reg = addr_reg + 1; 3795194865Sjfv 3796194865Sjfv /* All operations in this function are phy address 2 */ 3797194865Sjfv hw->phy.addr = 2; 3798194865Sjfv 3799194865Sjfv /* masking with 0x3F to remove the page from offset */ 3800194865Sjfv ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3801194865Sjfv if (ret_val) { 3802228386Sjfv DEBUGOUT("Could not write the Address Offset port register\n"); 3803238148Sjfv return ret_val; 3804194865Sjfv } 3805194865Sjfv 3806194865Sjfv /* Read or write the data value next */ 3807194865Sjfv if (read) 3808194865Sjfv ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3809194865Sjfv else 3810194865Sjfv ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3811194865Sjfv 3812238148Sjfv if (ret_val) 3813228386Sjfv DEBUGOUT("Could not access the Data port register\n"); 3814194865Sjfv 3815194865Sjfv return ret_val; 3816194865Sjfv} 3817194865Sjfv 3818194865Sjfv/** 3819194865Sjfv * e1000_link_stall_workaround_hv - Si workaround 3820194865Sjfv * @hw: pointer to the HW structure 3821194865Sjfv * 3822194865Sjfv * This function works around a Si bug where the link partner can get 3823194865Sjfv * a link up indication before the PHY does. If small packets are sent 3824194865Sjfv * by the link partner they can be placed in the packet buffer without 3825194865Sjfv * being properly accounted for by the PHY and will stall preventing 3826194865Sjfv * further packets from being received. The workaround is to clear the 3827194865Sjfv * packet buffer after the PHY detects link up. 3828194865Sjfv **/ 3829194865Sjfvs32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3830194865Sjfv{ 3831194865Sjfv s32 ret_val = E1000_SUCCESS; 3832194865Sjfv u16 data; 3833194865Sjfv 3834194865Sjfv DEBUGFUNC("e1000_link_stall_workaround_hv"); 3835194865Sjfv 3836194865Sjfv if (hw->phy.type != e1000_phy_82578) 3837238148Sjfv return E1000_SUCCESS; 3838194865Sjfv 3839194865Sjfv /* Do not apply workaround if in PHY loopback bit 14 set */ 3840194865Sjfv hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3841194865Sjfv if (data & PHY_CONTROL_LB) 3842238148Sjfv return E1000_SUCCESS; 3843200243Sjfv 3844194865Sjfv /* check if link is up and at 1Gbps */ 3845194865Sjfv ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3846194865Sjfv if (ret_val) 3847238148Sjfv return ret_val; 3848194865Sjfv 3849256200Sjfv data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3850256200Sjfv BM_CS_STATUS_SPEED_MASK); 3851194865Sjfv 3852228386Sjfv if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3853228386Sjfv BM_CS_STATUS_SPEED_1000)) 3854238148Sjfv return E1000_SUCCESS; 3855194865Sjfv 3856194865Sjfv msec_delay(200); 3857194865Sjfv 3858194865Sjfv /* flush the packets in the fifo buffer */ 3859194865Sjfv ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3860247064Sjfv (HV_MUX_DATA_CTRL_GEN_TO_MAC | 3861247064Sjfv HV_MUX_DATA_CTRL_FORCE_SPEED)); 3862194865Sjfv if (ret_val) 3863238148Sjfv return ret_val; 3864194865Sjfv 3865238148Sjfv return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3866238148Sjfv HV_MUX_DATA_CTRL_GEN_TO_MAC); 3867194865Sjfv} 3868194865Sjfv 3869194865Sjfv/** 3870194865Sjfv * e1000_check_polarity_82577 - Checks the polarity. 3871194865Sjfv * @hw: pointer to the HW structure 3872194865Sjfv * 3873194865Sjfv * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3874194865Sjfv * 3875194865Sjfv * Polarity is determined based on the PHY specific status register. 3876194865Sjfv **/ 3877194865Sjfvs32 e1000_check_polarity_82577(struct e1000_hw *hw) 3878194865Sjfv{ 3879194865Sjfv struct e1000_phy_info *phy = &hw->phy; 3880194865Sjfv s32 ret_val; 3881194865Sjfv u16 data; 3882194865Sjfv 3883194865Sjfv DEBUGFUNC("e1000_check_polarity_82577"); 3884194865Sjfv 3885194865Sjfv ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3886194865Sjfv 3887194865Sjfv if (!ret_val) 3888256200Sjfv phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY) 3889256200Sjfv ? e1000_rev_polarity_reversed 3890256200Sjfv : e1000_rev_polarity_normal); 3891194865Sjfv 3892194865Sjfv return ret_val; 3893194865Sjfv} 3894194865Sjfv 3895194865Sjfv/** 3896194865Sjfv * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3897194865Sjfv * @hw: pointer to the HW structure 3898194865Sjfv * 3899205869Sjfv * Calls the PHY setup function to force speed and duplex. 3900194865Sjfv **/ 3901194865Sjfvs32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3902194865Sjfv{ 3903194865Sjfv struct e1000_phy_info *phy = &hw->phy; 3904194865Sjfv s32 ret_val; 3905194865Sjfv u16 phy_data; 3906194865Sjfv bool link; 3907194865Sjfv 3908194865Sjfv DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3909194865Sjfv 3910194865Sjfv ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3911194865Sjfv if (ret_val) 3912238148Sjfv return ret_val; 3913194865Sjfv 3914194865Sjfv e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3915194865Sjfv 3916194865Sjfv ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3917194865Sjfv if (ret_val) 3918238148Sjfv return ret_val; 3919194865Sjfv 3920194865Sjfv usec_delay(1); 3921194865Sjfv 3922194865Sjfv if (phy->autoneg_wait_to_complete) { 3923194865Sjfv DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3924194865Sjfv 3925228386Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3926228386Sjfv 100000, &link); 3927194865Sjfv if (ret_val) 3928238148Sjfv return ret_val; 3929194865Sjfv 3930194865Sjfv if (!link) 3931194865Sjfv DEBUGOUT("Link taking longer than expected.\n"); 3932194865Sjfv 3933194865Sjfv /* Try once more */ 3934228386Sjfv ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3935228386Sjfv 100000, &link); 3936194865Sjfv } 3937194865Sjfv 3938194865Sjfv return ret_val; 3939194865Sjfv} 3940194865Sjfv 3941194865Sjfv/** 3942194865Sjfv * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3943194865Sjfv * @hw: pointer to the HW structure 3944194865Sjfv * 3945194865Sjfv * Read PHY status to determine if link is up. If link is up, then 3946194865Sjfv * set/determine 10base-T extended distance and polarity correction. Read 3947194865Sjfv * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3948194865Sjfv * determine on the cable length, local and remote receiver. 3949194865Sjfv **/ 3950194865Sjfvs32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3951194865Sjfv{ 3952194865Sjfv struct e1000_phy_info *phy = &hw->phy; 3953194865Sjfv s32 ret_val; 3954194865Sjfv u16 data; 3955194865Sjfv bool link; 3956194865Sjfv 3957194865Sjfv DEBUGFUNC("e1000_get_phy_info_82577"); 3958194865Sjfv 3959194865Sjfv ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3960194865Sjfv if (ret_val) 3961238148Sjfv return ret_val; 3962194865Sjfv 3963194865Sjfv if (!link) { 3964194865Sjfv DEBUGOUT("Phy info is only valid if link is up\n"); 3965238148Sjfv return -E1000_ERR_CONFIG; 3966194865Sjfv } 3967194865Sjfv 3968194865Sjfv phy->polarity_correction = TRUE; 3969194865Sjfv 3970194865Sjfv ret_val = e1000_check_polarity_82577(hw); 3971194865Sjfv if (ret_val) 3972238148Sjfv return ret_val; 3973194865Sjfv 3974194865Sjfv ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3975194865Sjfv if (ret_val) 3976238148Sjfv return ret_val; 3977194865Sjfv 3978238148Sjfv phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); 3979194865Sjfv 3980194865Sjfv if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3981194865Sjfv I82577_PHY_STATUS2_SPEED_1000MBPS) { 3982194865Sjfv ret_val = hw->phy.ops.get_cable_length(hw); 3983194865Sjfv if (ret_val) 3984238148Sjfv return ret_val; 3985194865Sjfv 3986194865Sjfv ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3987194865Sjfv if (ret_val) 3988238148Sjfv return ret_val; 3989194865Sjfv 3990194865Sjfv phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3991228386Sjfv ? e1000_1000t_rx_status_ok 3992228386Sjfv : e1000_1000t_rx_status_not_ok; 3993194865Sjfv 3994194865Sjfv phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3995228386Sjfv ? e1000_1000t_rx_status_ok 3996228386Sjfv : e1000_1000t_rx_status_not_ok; 3997194865Sjfv } else { 3998194865Sjfv phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3999194865Sjfv phy->local_rx = e1000_1000t_rx_status_undefined; 4000194865Sjfv phy->remote_rx = e1000_1000t_rx_status_undefined; 4001194865Sjfv } 4002194865Sjfv 4003238148Sjfv return E1000_SUCCESS; 4004194865Sjfv} 4005194865Sjfv 4006194865Sjfv/** 4007194865Sjfv * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 4008194865Sjfv * @hw: pointer to the HW structure 4009194865Sjfv * 4010194865Sjfv * Reads the diagnostic status register and verifies result is valid before 4011194865Sjfv * placing it in the phy_cable_length field. 4012194865Sjfv **/ 4013194865Sjfvs32 e1000_get_cable_length_82577(struct e1000_hw *hw) 4014194865Sjfv{ 4015194865Sjfv struct e1000_phy_info *phy = &hw->phy; 4016194865Sjfv s32 ret_val; 4017194865Sjfv u16 phy_data, length; 4018194865Sjfv 4019194865Sjfv DEBUGFUNC("e1000_get_cable_length_82577"); 4020194865Sjfv 4021194865Sjfv ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 4022194865Sjfv if (ret_val) 4023238148Sjfv return ret_val; 4024194865Sjfv 4025256200Sjfv length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 4026256200Sjfv I82577_DSTATUS_CABLE_LENGTH_SHIFT); 4027194865Sjfv 4028194865Sjfv if (length == E1000_CABLE_LENGTH_UNDEFINED) 4029247064Sjfv return -E1000_ERR_PHY; 4030194865Sjfv 4031194865Sjfv phy->cable_length = length; 4032194865Sjfv 4033238148Sjfv return E1000_SUCCESS; 4034238148Sjfv} 4035238148Sjfv 4036238148Sjfv/** 4037238148Sjfv * e1000_write_phy_reg_gs40g - Write GS40G PHY register 4038238148Sjfv * @hw: pointer to the HW structure 4039238148Sjfv * @offset: register offset to write to 4040238148Sjfv * @data: data to write at register offset 4041238148Sjfv * 4042238148Sjfv * Acquires semaphore, if necessary, then writes the data to PHY register 4043238148Sjfv * at the offset. Release any acquired semaphores before exiting. 4044238148Sjfv **/ 4045238148Sjfvs32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 4046238148Sjfv{ 4047238148Sjfv s32 ret_val; 4048238148Sjfv u16 page = offset >> GS40G_PAGE_SHIFT; 4049238148Sjfv 4050238148Sjfv DEBUGFUNC("e1000_write_phy_reg_gs40g"); 4051238148Sjfv 4052238148Sjfv offset = offset & GS40G_OFFSET_MASK; 4053238148Sjfv ret_val = hw->phy.ops.acquire(hw); 4054238148Sjfv if (ret_val) 4055238148Sjfv return ret_val; 4056238148Sjfv 4057238148Sjfv ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4058238148Sjfv if (ret_val) 4059238148Sjfv goto release; 4060238148Sjfv ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 4061238148Sjfv 4062238148Sjfvrelease: 4063238148Sjfv hw->phy.ops.release(hw); 4064194865Sjfv return ret_val; 4065194865Sjfv} 4066238148Sjfv 4067238148Sjfv/** 4068238148Sjfv * e1000_read_phy_reg_gs40g - Read GS40G PHY register 4069238148Sjfv * @hw: pointer to the HW structure 4070238148Sjfv * @offset: lower half is register offset to read to 4071238148Sjfv * upper half is page to use. 4072238148Sjfv * @data: data to read at register offset 4073238148Sjfv * 4074238148Sjfv * Acquires semaphore, if necessary, then reads the data in the PHY register 4075238148Sjfv * at the offset. Release any acquired semaphores before exiting. 4076238148Sjfv **/ 4077238148Sjfvs32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 4078238148Sjfv{ 4079238148Sjfv s32 ret_val; 4080238148Sjfv u16 page = offset >> GS40G_PAGE_SHIFT; 4081238148Sjfv 4082238148Sjfv DEBUGFUNC("e1000_read_phy_reg_gs40g"); 4083238148Sjfv 4084238148Sjfv offset = offset & GS40G_OFFSET_MASK; 4085238148Sjfv ret_val = hw->phy.ops.acquire(hw); 4086238148Sjfv if (ret_val) 4087238148Sjfv return ret_val; 4088238148Sjfv 4089238148Sjfv ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4090238148Sjfv if (ret_val) 4091238148Sjfv goto release; 4092238148Sjfv ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 4093238148Sjfv 4094238148Sjfvrelease: 4095238148Sjfv hw->phy.ops.release(hw); 4096238148Sjfv return ret_val; 4097238148Sjfv} 4098247064Sjfv 4099256200Sjfv/** 4100256200Sjfv * e1000_read_phy_reg_mphy - Read mPHY control register 4101256200Sjfv * @hw: pointer to the HW structure 4102256200Sjfv * @address: address to be read 4103256200Sjfv * @data: pointer to the read data 4104256200Sjfv * 4105256200Sjfv * Reads the mPHY control register in the PHY at offset and stores the 4106256200Sjfv * information read to data. 4107256200Sjfv **/ 4108256200Sjfvs32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data) 4109256200Sjfv{ 4110256200Sjfv u32 mphy_ctrl = 0; 4111256200Sjfv bool locked = FALSE; 4112269196Sjfv bool ready; 4113256200Sjfv 4114256200Sjfv DEBUGFUNC("e1000_read_phy_reg_mphy"); 4115256200Sjfv 4116256200Sjfv /* Check if mPHY is ready to read/write operations */ 4117256200Sjfv ready = e1000_is_mphy_ready(hw); 4118256200Sjfv if (!ready) 4119256200Sjfv return -E1000_ERR_PHY; 4120256200Sjfv 4121256200Sjfv /* Check if mPHY access is disabled and enable it if so */ 4122256200Sjfv mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4123256200Sjfv if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) { 4124256200Sjfv locked = TRUE; 4125256200Sjfv ready = e1000_is_mphy_ready(hw); 4126256200Sjfv if (!ready) 4127256200Sjfv return -E1000_ERR_PHY; 4128256200Sjfv mphy_ctrl |= E1000_MPHY_ENA_ACCESS; 4129256200Sjfv E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4130256200Sjfv } 4131256200Sjfv 4132256200Sjfv /* Set the address that we want to read */ 4133256200Sjfv ready = e1000_is_mphy_ready(hw); 4134256200Sjfv if (!ready) 4135256200Sjfv return -E1000_ERR_PHY; 4136256200Sjfv 4137256200Sjfv /* We mask address, because we want to use only current lane */ 4138256200Sjfv mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK & 4139256200Sjfv ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) | 4140256200Sjfv (address & E1000_MPHY_ADDRESS_MASK); 4141256200Sjfv E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4142256200Sjfv 4143256200Sjfv /* Read data from the address */ 4144256200Sjfv ready = e1000_is_mphy_ready(hw); 4145256200Sjfv if (!ready) 4146256200Sjfv return -E1000_ERR_PHY; 4147256200Sjfv *data = E1000_READ_REG(hw, E1000_MPHY_DATA); 4148256200Sjfv 4149256200Sjfv /* Disable access to mPHY if it was originally disabled */ 4150256200Sjfv if (locked) 4151256200Sjfv ready = e1000_is_mphy_ready(hw); 4152304338Ssbruno if (!ready) 4153304338Ssbruno return -E1000_ERR_PHY; 4154304338Ssbruno E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, 4155304338Ssbruno E1000_MPHY_DIS_ACCESS); 4156256200Sjfv 4157256200Sjfv return E1000_SUCCESS; 4158256200Sjfv} 4159256200Sjfv 4160256200Sjfv/** 4161256200Sjfv * e1000_write_phy_reg_mphy - Write mPHY control register 4162256200Sjfv * @hw: pointer to the HW structure 4163256200Sjfv * @address: address to write to 4164256200Sjfv * @data: data to write to register at offset 4165256200Sjfv * @line_override: used when we want to use different line than default one 4166256200Sjfv * 4167256200Sjfv * Writes data to mPHY control register. 4168256200Sjfv **/ 4169256200Sjfvs32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data, 4170256200Sjfv bool line_override) 4171256200Sjfv{ 4172256200Sjfv u32 mphy_ctrl = 0; 4173256200Sjfv bool locked = FALSE; 4174269196Sjfv bool ready; 4175256200Sjfv 4176256200Sjfv DEBUGFUNC("e1000_write_phy_reg_mphy"); 4177256200Sjfv 4178256200Sjfv /* Check if mPHY is ready to read/write operations */ 4179256200Sjfv ready = e1000_is_mphy_ready(hw); 4180256200Sjfv if (!ready) 4181256200Sjfv return -E1000_ERR_PHY; 4182256200Sjfv 4183256200Sjfv /* Check if mPHY access is disabled and enable it if so */ 4184256200Sjfv mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4185256200Sjfv if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) { 4186256200Sjfv locked = TRUE; 4187256200Sjfv ready = e1000_is_mphy_ready(hw); 4188256200Sjfv if (!ready) 4189256200Sjfv return -E1000_ERR_PHY; 4190256200Sjfv mphy_ctrl |= E1000_MPHY_ENA_ACCESS; 4191256200Sjfv E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4192256200Sjfv } 4193256200Sjfv 4194256200Sjfv /* Set the address that we want to read */ 4195256200Sjfv ready = e1000_is_mphy_ready(hw); 4196256200Sjfv if (!ready) 4197256200Sjfv return -E1000_ERR_PHY; 4198256200Sjfv 4199256200Sjfv /* We mask address, because we want to use only current lane */ 4200256200Sjfv if (line_override) 4201256200Sjfv mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE; 4202256200Sjfv else 4203256200Sjfv mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE; 4204256200Sjfv mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) | 4205256200Sjfv (address & E1000_MPHY_ADDRESS_MASK); 4206256200Sjfv E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4207256200Sjfv 4208256200Sjfv /* Read data from the address */ 4209256200Sjfv ready = e1000_is_mphy_ready(hw); 4210256200Sjfv if (!ready) 4211256200Sjfv return -E1000_ERR_PHY; 4212256200Sjfv E1000_WRITE_REG(hw, E1000_MPHY_DATA, data); 4213256200Sjfv 4214256200Sjfv /* Disable access to mPHY if it was originally disabled */ 4215256200Sjfv if (locked) 4216256200Sjfv ready = e1000_is_mphy_ready(hw); 4217304338Ssbruno if (!ready) 4218304338Ssbruno return -E1000_ERR_PHY; 4219304338Ssbruno E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, 4220304338Ssbruno E1000_MPHY_DIS_ACCESS); 4221256200Sjfv 4222256200Sjfv return E1000_SUCCESS; 4223256200Sjfv} 4224256200Sjfv 4225256200Sjfv/** 4226256200Sjfv * e1000_is_mphy_ready - Check if mPHY control register is not busy 4227256200Sjfv * @hw: pointer to the HW structure 4228256200Sjfv * 4229256200Sjfv * Returns mPHY control register status. 4230256200Sjfv **/ 4231256200Sjfvbool e1000_is_mphy_ready(struct e1000_hw *hw) 4232256200Sjfv{ 4233256200Sjfv u16 retry_count = 0; 4234256200Sjfv u32 mphy_ctrl = 0; 4235256200Sjfv bool ready = FALSE; 4236256200Sjfv 4237256200Sjfv while (retry_count < 2) { 4238256200Sjfv mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4239256200Sjfv if (mphy_ctrl & E1000_MPHY_BUSY) { 4240256200Sjfv usec_delay(20); 4241256200Sjfv retry_count++; 4242256200Sjfv continue; 4243256200Sjfv } 4244256200Sjfv ready = TRUE; 4245256200Sjfv break; 4246256200Sjfv } 4247256200Sjfv 4248256200Sjfv if (!ready) 4249256200Sjfv DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n"); 4250256200Sjfv 4251256200Sjfv return ready; 4252256200Sjfv} 4253