e1000_hw.h revision 304338
1177867Sjfv/****************************************************************************** 2169240Sjfv 3294958Smarius Copyright (c) 2001-2015, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: stable/10/sys/dev/e1000/e1000_hw.h 304338 2016-08-18 07:32:02Z sbruno $*/ 34169240Sjfv 35169240Sjfv#ifndef _E1000_HW_H_ 36169240Sjfv#define _E1000_HW_H_ 37169240Sjfv 38169240Sjfv#include "e1000_osdep.h" 39169240Sjfv#include "e1000_regs.h" 40169240Sjfv#include "e1000_defines.h" 41169240Sjfv 42169240Sjfvstruct e1000_hw; 43169240Sjfv 44228386Sjfv#define E1000_DEV_ID_82542 0x1000 45228386Sjfv#define E1000_DEV_ID_82543GC_FIBER 0x1001 46228386Sjfv#define E1000_DEV_ID_82543GC_COPPER 0x1004 47228386Sjfv#define E1000_DEV_ID_82544EI_COPPER 0x1008 48228386Sjfv#define E1000_DEV_ID_82544EI_FIBER 0x1009 49228386Sjfv#define E1000_DEV_ID_82544GC_COPPER 0x100C 50228386Sjfv#define E1000_DEV_ID_82544GC_LOM 0x100D 51228386Sjfv#define E1000_DEV_ID_82540EM 0x100E 52228386Sjfv#define E1000_DEV_ID_82540EM_LOM 0x1015 53228386Sjfv#define E1000_DEV_ID_82540EP_LOM 0x1016 54228386Sjfv#define E1000_DEV_ID_82540EP 0x1017 55228386Sjfv#define E1000_DEV_ID_82540EP_LP 0x101E 56228386Sjfv#define E1000_DEV_ID_82545EM_COPPER 0x100F 57228386Sjfv#define E1000_DEV_ID_82545EM_FIBER 0x1011 58228386Sjfv#define E1000_DEV_ID_82545GM_COPPER 0x1026 59228386Sjfv#define E1000_DEV_ID_82545GM_FIBER 0x1027 60228386Sjfv#define E1000_DEV_ID_82545GM_SERDES 0x1028 61228386Sjfv#define E1000_DEV_ID_82546EB_COPPER 0x1010 62228386Sjfv#define E1000_DEV_ID_82546EB_FIBER 0x1012 63228386Sjfv#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64228386Sjfv#define E1000_DEV_ID_82546GB_COPPER 0x1079 65228386Sjfv#define E1000_DEV_ID_82546GB_FIBER 0x107A 66228386Sjfv#define E1000_DEV_ID_82546GB_SERDES 0x107B 67228386Sjfv#define E1000_DEV_ID_82546GB_PCIE 0x108A 68228386Sjfv#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69228386Sjfv#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70228386Sjfv#define E1000_DEV_ID_82541EI 0x1013 71228386Sjfv#define E1000_DEV_ID_82541EI_MOBILE 0x1018 72228386Sjfv#define E1000_DEV_ID_82541ER_LOM 0x1014 73228386Sjfv#define E1000_DEV_ID_82541ER 0x1078 74228386Sjfv#define E1000_DEV_ID_82541GI 0x1076 75228386Sjfv#define E1000_DEV_ID_82541GI_LF 0x107C 76228386Sjfv#define E1000_DEV_ID_82541GI_MOBILE 0x1077 77228386Sjfv#define E1000_DEV_ID_82547EI 0x1019 78228386Sjfv#define E1000_DEV_ID_82547EI_MOBILE 0x101A 79228386Sjfv#define E1000_DEV_ID_82547GI 0x1075 80228386Sjfv#define E1000_DEV_ID_82571EB_COPPER 0x105E 81228386Sjfv#define E1000_DEV_ID_82571EB_FIBER 0x105F 82228386Sjfv#define E1000_DEV_ID_82571EB_SERDES 0x1060 83228386Sjfv#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84228386Sjfv#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85228386Sjfv#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86228386Sjfv#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87228386Sjfv#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88228386Sjfv#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89228386Sjfv#define E1000_DEV_ID_82572EI_COPPER 0x107D 90228386Sjfv#define E1000_DEV_ID_82572EI_FIBER 0x107E 91228386Sjfv#define E1000_DEV_ID_82572EI_SERDES 0x107F 92228386Sjfv#define E1000_DEV_ID_82572EI 0x10B9 93228386Sjfv#define E1000_DEV_ID_82573E 0x108B 94228386Sjfv#define E1000_DEV_ID_82573E_IAMT 0x108C 95228386Sjfv#define E1000_DEV_ID_82573L 0x109A 96228386Sjfv#define E1000_DEV_ID_82574L 0x10D3 97228386Sjfv#define E1000_DEV_ID_82574LA 0x10F6 98228386Sjfv#define E1000_DEV_ID_82583V 0x150C 99228386Sjfv#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100228386Sjfv#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101228386Sjfv#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102228386Sjfv#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103228386Sjfv#define E1000_DEV_ID_ICH8_82567V_3 0x1501 104228386Sjfv#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 105228386Sjfv#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 106228386Sjfv#define E1000_DEV_ID_ICH8_IGP_C 0x104B 107228386Sjfv#define E1000_DEV_ID_ICH8_IFE 0x104C 108228386Sjfv#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 109228386Sjfv#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 110228386Sjfv#define E1000_DEV_ID_ICH8_IGP_M 0x104D 111228386Sjfv#define E1000_DEV_ID_ICH9_IGP_M 0x10BF 112228386Sjfv#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 113228386Sjfv#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 114228386Sjfv#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 115228386Sjfv#define E1000_DEV_ID_ICH9_BM 0x10E5 116228386Sjfv#define E1000_DEV_ID_ICH9_IGP_C 0x294C 117228386Sjfv#define E1000_DEV_ID_ICH9_IFE 0x10C0 118228386Sjfv#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 119228386Sjfv#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 120228386Sjfv#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 121228386Sjfv#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 122228386Sjfv#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 123228386Sjfv#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 124228386Sjfv#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 125228386Sjfv#define E1000_DEV_ID_ICH10_D_BM_V 0x1525 126228386Sjfv#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 127228386Sjfv#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 128228386Sjfv#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 129228386Sjfv#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 130228386Sjfv#define E1000_DEV_ID_PCH2_LV_LM 0x1502 131228386Sjfv#define E1000_DEV_ID_PCH2_LV_V 0x1503 132247064Sjfv#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 133247064Sjfv#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 134247064Sjfv#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 135247064Sjfv#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 136269196Sjfv#define E1000_DEV_ID_PCH_I218_LM2 0x15A0 137269196Sjfv#define E1000_DEV_ID_PCH_I218_V2 0x15A1 138269196Sjfv#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 139269196Sjfv#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 140296055Serj#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 141296055Serj#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 142296055Serj#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 143296055Serj#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 144296055Serj#define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 145304338Ssbruno#define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 146304338Ssbruno#define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 147304338Ssbruno#define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 148304338Ssbruno#define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 149228386Sjfv#define E1000_DEV_ID_82576 0x10C9 150228386Sjfv#define E1000_DEV_ID_82576_FIBER 0x10E6 151228386Sjfv#define E1000_DEV_ID_82576_SERDES 0x10E7 152228386Sjfv#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 153228386Sjfv#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 154228386Sjfv#define E1000_DEV_ID_82576_NS 0x150A 155228386Sjfv#define E1000_DEV_ID_82576_NS_SERDES 0x1518 156228386Sjfv#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 157228386Sjfv#define E1000_DEV_ID_82576_VF 0x10CA 158247064Sjfv#define E1000_DEV_ID_82576_VF_HV 0x152D 159228386Sjfv#define E1000_DEV_ID_I350_VF 0x1520 160247064Sjfv#define E1000_DEV_ID_I350_VF_HV 0x152F 161228386Sjfv#define E1000_DEV_ID_82575EB_COPPER 0x10A7 162228386Sjfv#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 163228386Sjfv#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 164228386Sjfv#define E1000_DEV_ID_82580_COPPER 0x150E 165228386Sjfv#define E1000_DEV_ID_82580_FIBER 0x150F 166228386Sjfv#define E1000_DEV_ID_82580_SERDES 0x1510 167228386Sjfv#define E1000_DEV_ID_82580_SGMII 0x1511 168228386Sjfv#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 169228386Sjfv#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 170228386Sjfv#define E1000_DEV_ID_I350_COPPER 0x1521 171228386Sjfv#define E1000_DEV_ID_I350_FIBER 0x1522 172228386Sjfv#define E1000_DEV_ID_I350_SERDES 0x1523 173228386Sjfv#define E1000_DEV_ID_I350_SGMII 0x1524 174228386Sjfv#define E1000_DEV_ID_I350_DA4 0x1546 175238148Sjfv#define E1000_DEV_ID_I210_COPPER 0x1533 176238148Sjfv#define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 177238148Sjfv#define E1000_DEV_ID_I210_COPPER_IT 0x1535 178238148Sjfv#define E1000_DEV_ID_I210_FIBER 0x1536 179238148Sjfv#define E1000_DEV_ID_I210_SERDES 0x1537 180238148Sjfv#define E1000_DEV_ID_I210_SGMII 0x1538 181256200Sjfv#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 182256200Sjfv#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 183238148Sjfv#define E1000_DEV_ID_I211_COPPER 0x1539 184256200Sjfv#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 185256200Sjfv#define E1000_DEV_ID_I354_SGMII 0x1F41 186256200Sjfv#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 187228386Sjfv#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 188228386Sjfv#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 189228386Sjfv#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 190228386Sjfv#define E1000_DEV_ID_DH89XXCC_SFP 0x0440 191247064Sjfv 192228386Sjfv#define E1000_REVISION_0 0 193228386Sjfv#define E1000_REVISION_1 1 194228386Sjfv#define E1000_REVISION_2 2 195228386Sjfv#define E1000_REVISION_3 3 196228386Sjfv#define E1000_REVISION_4 4 197169240Sjfv 198228386Sjfv#define E1000_FUNC_0 0 199228386Sjfv#define E1000_FUNC_1 1 200228386Sjfv#define E1000_FUNC_2 2 201228386Sjfv#define E1000_FUNC_3 3 202169240Sjfv 203228386Sjfv#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 204228386Sjfv#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 205228386Sjfv#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 206228386Sjfv#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 207190872Sjfv 208181027Sjfvenum e1000_mac_type { 209169240Sjfv e1000_undefined = 0, 210169240Sjfv e1000_82542, 211169240Sjfv e1000_82543, 212169240Sjfv e1000_82544, 213169240Sjfv e1000_82540, 214169240Sjfv e1000_82545, 215169240Sjfv e1000_82545_rev_3, 216169240Sjfv e1000_82546, 217169240Sjfv e1000_82546_rev_3, 218169240Sjfv e1000_82541, 219169240Sjfv e1000_82541_rev_2, 220169240Sjfv e1000_82547, 221169240Sjfv e1000_82547_rev_2, 222169240Sjfv e1000_82571, 223169240Sjfv e1000_82572, 224169240Sjfv e1000_82573, 225178523Sjfv e1000_82574, 226194865Sjfv e1000_82583, 227169240Sjfv e1000_80003es2lan, 228169240Sjfv e1000_ich8lan, 229169240Sjfv e1000_ich9lan, 230178523Sjfv e1000_ich10lan, 231194865Sjfv e1000_pchlan, 232213234Sjfv e1000_pch2lan, 233247064Sjfv e1000_pch_lpt, 234296055Serj e1000_pch_spt, 235177867Sjfv e1000_82575, 236181027Sjfv e1000_82576, 237200243Sjfv e1000_82580, 238218530Sjfv e1000_i350, 239256200Sjfv e1000_i354, 240238148Sjfv e1000_i210, 241238148Sjfv e1000_i211, 242209616Sjfv e1000_vfadapt, 243218530Sjfv e1000_vfadapt_i350, 244177867Sjfv e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 245181027Sjfv}; 246169240Sjfv 247181027Sjfvenum e1000_media_type { 248169240Sjfv e1000_media_type_unknown = 0, 249169240Sjfv e1000_media_type_copper = 1, 250169240Sjfv e1000_media_type_fiber = 2, 251169240Sjfv e1000_media_type_internal_serdes = 3, 252169240Sjfv e1000_num_media_types 253181027Sjfv}; 254169240Sjfv 255181027Sjfvenum e1000_nvm_type { 256169240Sjfv e1000_nvm_unknown = 0, 257169240Sjfv e1000_nvm_none, 258169240Sjfv e1000_nvm_eeprom_spi, 259169240Sjfv e1000_nvm_eeprom_microwire, 260169240Sjfv e1000_nvm_flash_hw, 261256200Sjfv e1000_nvm_invm, 262169240Sjfv e1000_nvm_flash_sw 263181027Sjfv}; 264169240Sjfv 265181027Sjfvenum e1000_nvm_override { 266169240Sjfv e1000_nvm_override_none = 0, 267169240Sjfv e1000_nvm_override_spi_small, 268169240Sjfv e1000_nvm_override_spi_large, 269169240Sjfv e1000_nvm_override_microwire_small, 270169240Sjfv e1000_nvm_override_microwire_large 271181027Sjfv}; 272169240Sjfv 273181027Sjfvenum e1000_phy_type { 274169240Sjfv e1000_phy_unknown = 0, 275169240Sjfv e1000_phy_none, 276169240Sjfv e1000_phy_m88, 277169240Sjfv e1000_phy_igp, 278169240Sjfv e1000_phy_igp_2, 279169240Sjfv e1000_phy_gg82563, 280169240Sjfv e1000_phy_igp_3, 281169240Sjfv e1000_phy_ife, 282176667Sjfv e1000_phy_bm, 283194865Sjfv e1000_phy_82578, 284194865Sjfv e1000_phy_82577, 285213234Sjfv e1000_phy_82579, 286247064Sjfv e1000_phy_i217, 287200243Sjfv e1000_phy_82580, 288181027Sjfv e1000_phy_vf, 289238148Sjfv e1000_phy_i210, 290181027Sjfv}; 291169240Sjfv 292181027Sjfvenum e1000_bus_type { 293169240Sjfv e1000_bus_type_unknown = 0, 294169240Sjfv e1000_bus_type_pci, 295169240Sjfv e1000_bus_type_pcix, 296169240Sjfv e1000_bus_type_pci_express, 297169240Sjfv e1000_bus_type_reserved 298181027Sjfv}; 299169240Sjfv 300181027Sjfvenum e1000_bus_speed { 301169240Sjfv e1000_bus_speed_unknown = 0, 302169240Sjfv e1000_bus_speed_33, 303169240Sjfv e1000_bus_speed_66, 304169240Sjfv e1000_bus_speed_100, 305169240Sjfv e1000_bus_speed_120, 306169240Sjfv e1000_bus_speed_133, 307169240Sjfv e1000_bus_speed_2500, 308173788Sjfv e1000_bus_speed_5000, 309169240Sjfv e1000_bus_speed_reserved 310181027Sjfv}; 311169240Sjfv 312181027Sjfvenum e1000_bus_width { 313169240Sjfv e1000_bus_width_unknown = 0, 314169240Sjfv e1000_bus_width_pcie_x1, 315169240Sjfv e1000_bus_width_pcie_x2, 316169240Sjfv e1000_bus_width_pcie_x4 = 4, 317173788Sjfv e1000_bus_width_pcie_x8 = 8, 318169240Sjfv e1000_bus_width_32, 319169240Sjfv e1000_bus_width_64, 320169240Sjfv e1000_bus_width_reserved 321181027Sjfv}; 322169240Sjfv 323181027Sjfvenum e1000_1000t_rx_status { 324169240Sjfv e1000_1000t_rx_status_not_ok = 0, 325169240Sjfv e1000_1000t_rx_status_ok, 326169240Sjfv e1000_1000t_rx_status_undefined = 0xFF 327181027Sjfv}; 328169240Sjfv 329181027Sjfvenum e1000_rev_polarity { 330169240Sjfv e1000_rev_polarity_normal = 0, 331169240Sjfv e1000_rev_polarity_reversed, 332169240Sjfv e1000_rev_polarity_undefined = 0xFF 333181027Sjfv}; 334169240Sjfv 335185353Sjfvenum e1000_fc_mode { 336169240Sjfv e1000_fc_none = 0, 337169240Sjfv e1000_fc_rx_pause, 338169240Sjfv e1000_fc_tx_pause, 339169240Sjfv e1000_fc_full, 340169240Sjfv e1000_fc_default = 0xFF 341181027Sjfv}; 342169240Sjfv 343181027Sjfvenum e1000_ffe_config { 344169240Sjfv e1000_ffe_config_enabled = 0, 345169240Sjfv e1000_ffe_config_active, 346169240Sjfv e1000_ffe_config_blocked 347181027Sjfv}; 348169240Sjfv 349181027Sjfvenum e1000_dsp_config { 350169240Sjfv e1000_dsp_config_disabled = 0, 351169240Sjfv e1000_dsp_config_enabled, 352169240Sjfv e1000_dsp_config_activated, 353169240Sjfv e1000_dsp_config_undefined = 0xFF 354181027Sjfv}; 355169240Sjfv 356185353Sjfvenum e1000_ms_type { 357185353Sjfv e1000_ms_hw_default = 0, 358185353Sjfv e1000_ms_force_master, 359185353Sjfv e1000_ms_force_slave, 360185353Sjfv e1000_ms_auto 361185353Sjfv}; 362185353Sjfv 363185353Sjfvenum e1000_smart_speed { 364185353Sjfv e1000_smart_speed_default = 0, 365185353Sjfv e1000_smart_speed_on, 366185353Sjfv e1000_smart_speed_off 367185353Sjfv}; 368185353Sjfv 369190872Sjfvenum e1000_serdes_link_state { 370190872Sjfv e1000_serdes_link_down = 0, 371190872Sjfv e1000_serdes_link_autoneg_progress, 372190872Sjfv e1000_serdes_link_autoneg_complete, 373190872Sjfv e1000_serdes_link_forced_up 374190872Sjfv}; 375190872Sjfv 376213234Sjfv#define __le16 u16 377213234Sjfv#define __le32 u32 378213234Sjfv#define __le64 u64 379169240Sjfv/* Receive Descriptor */ 380169240Sjfvstruct e1000_rx_desc { 381185353Sjfv __le64 buffer_addr; /* Address of the descriptor's data buffer */ 382185353Sjfv __le16 length; /* Length of data DMAed into data buffer */ 383228386Sjfv __le16 csum; /* Packet checksum */ 384228386Sjfv u8 status; /* Descriptor status */ 385228386Sjfv u8 errors; /* Descriptor Errors */ 386185353Sjfv __le16 special; 387169240Sjfv}; 388169240Sjfv 389169240Sjfv/* Receive Descriptor - Extended */ 390169240Sjfvunion e1000_rx_desc_extended { 391169240Sjfv struct { 392185353Sjfv __le64 buffer_addr; 393185353Sjfv __le64 reserved; 394169240Sjfv } read; 395169240Sjfv struct { 396169240Sjfv struct { 397228386Sjfv __le32 mrq; /* Multiple Rx Queues */ 398169240Sjfv union { 399228386Sjfv __le32 rss; /* RSS Hash */ 400169240Sjfv struct { 401185353Sjfv __le16 ip_id; /* IP id */ 402185353Sjfv __le16 csum; /* Packet Checksum */ 403169240Sjfv } csum_ip; 404169240Sjfv } hi_dword; 405169240Sjfv } lower; 406169240Sjfv struct { 407185353Sjfv __le32 status_error; /* ext status/error */ 408185353Sjfv __le16 length; 409228386Sjfv __le16 vlan; /* VLAN tag */ 410169240Sjfv } upper; 411169240Sjfv } wb; /* writeback */ 412169240Sjfv}; 413169240Sjfv 414169240Sjfv#define MAX_PS_BUFFERS 4 415256200Sjfv 416256200Sjfv/* Number of packet split data buffers (not including the header buffer) */ 417256200Sjfv#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 418256200Sjfv 419169240Sjfv/* Receive Descriptor - Packet Split */ 420169240Sjfvunion e1000_rx_desc_packet_split { 421169240Sjfv struct { 422169240Sjfv /* one buffer for protocol header(s), three data buffers */ 423185353Sjfv __le64 buffer_addr[MAX_PS_BUFFERS]; 424169240Sjfv } read; 425169240Sjfv struct { 426169240Sjfv struct { 427228386Sjfv __le32 mrq; /* Multiple Rx Queues */ 428169240Sjfv union { 429228386Sjfv __le32 rss; /* RSS Hash */ 430169240Sjfv struct { 431185353Sjfv __le16 ip_id; /* IP id */ 432185353Sjfv __le16 csum; /* Packet Checksum */ 433169240Sjfv } csum_ip; 434169240Sjfv } hi_dword; 435169240Sjfv } lower; 436169240Sjfv struct { 437185353Sjfv __le32 status_error; /* ext status/error */ 438228386Sjfv __le16 length0; /* length of buffer 0 */ 439228386Sjfv __le16 vlan; /* VLAN tag */ 440169240Sjfv } middle; 441169240Sjfv struct { 442185353Sjfv __le16 header_status; 443256200Sjfv /* length of buffers 1-3 */ 444256200Sjfv __le16 length[PS_PAGE_BUFFERS]; 445169240Sjfv } upper; 446185353Sjfv __le64 reserved; 447169240Sjfv } wb; /* writeback */ 448169240Sjfv}; 449169240Sjfv 450169240Sjfv/* Transmit Descriptor */ 451169240Sjfvstruct e1000_tx_desc { 452185353Sjfv __le64 buffer_addr; /* Address of the descriptor's data buffer */ 453169240Sjfv union { 454185353Sjfv __le32 data; 455169240Sjfv struct { 456228386Sjfv __le16 length; /* Data buffer length */ 457228386Sjfv u8 cso; /* Checksum offset */ 458228386Sjfv u8 cmd; /* Descriptor control */ 459169240Sjfv } flags; 460169240Sjfv } lower; 461169240Sjfv union { 462185353Sjfv __le32 data; 463169240Sjfv struct { 464228386Sjfv u8 status; /* Descriptor status */ 465228386Sjfv u8 css; /* Checksum start */ 466185353Sjfv __le16 special; 467169240Sjfv } fields; 468169240Sjfv } upper; 469169240Sjfv}; 470169240Sjfv 471169240Sjfv/* Offload Context Descriptor */ 472169240Sjfvstruct e1000_context_desc { 473169240Sjfv union { 474185353Sjfv __le32 ip_config; 475169240Sjfv struct { 476228386Sjfv u8 ipcss; /* IP checksum start */ 477228386Sjfv u8 ipcso; /* IP checksum offset */ 478228386Sjfv __le16 ipcse; /* IP checksum end */ 479169240Sjfv } ip_fields; 480169240Sjfv } lower_setup; 481169240Sjfv union { 482185353Sjfv __le32 tcp_config; 483169240Sjfv struct { 484228386Sjfv u8 tucss; /* TCP checksum start */ 485228386Sjfv u8 tucso; /* TCP checksum offset */ 486228386Sjfv __le16 tucse; /* TCP checksum end */ 487169240Sjfv } tcp_fields; 488169240Sjfv } upper_setup; 489185353Sjfv __le32 cmd_and_length; 490169240Sjfv union { 491185353Sjfv __le32 data; 492169240Sjfv struct { 493228386Sjfv u8 status; /* Descriptor status */ 494228386Sjfv u8 hdr_len; /* Header length */ 495228386Sjfv __le16 mss; /* Maximum segment size */ 496169240Sjfv } fields; 497169240Sjfv } tcp_seg_setup; 498169240Sjfv}; 499169240Sjfv 500169240Sjfv/* Offload data descriptor */ 501169240Sjfvstruct e1000_data_desc { 502228386Sjfv __le64 buffer_addr; /* Address of the descriptor's buffer address */ 503169240Sjfv union { 504185353Sjfv __le32 data; 505169240Sjfv struct { 506228386Sjfv __le16 length; /* Data buffer length */ 507169240Sjfv u8 typ_len_ext; 508169240Sjfv u8 cmd; 509169240Sjfv } flags; 510169240Sjfv } lower; 511169240Sjfv union { 512185353Sjfv __le32 data; 513169240Sjfv struct { 514228386Sjfv u8 status; /* Descriptor status */ 515228386Sjfv u8 popts; /* Packet Options */ 516185353Sjfv __le16 special; 517169240Sjfv } fields; 518169240Sjfv } upper; 519169240Sjfv}; 520169240Sjfv 521169240Sjfv/* Statistics counters collected by the MAC */ 522169240Sjfvstruct e1000_hw_stats { 523169240Sjfv u64 crcerrs; 524169240Sjfv u64 algnerrc; 525169240Sjfv u64 symerrs; 526169240Sjfv u64 rxerrc; 527169240Sjfv u64 mpc; 528169240Sjfv u64 scc; 529169240Sjfv u64 ecol; 530169240Sjfv u64 mcc; 531169240Sjfv u64 latecol; 532169240Sjfv u64 colc; 533169240Sjfv u64 dc; 534169240Sjfv u64 tncrs; 535169240Sjfv u64 sec; 536169240Sjfv u64 cexterr; 537169240Sjfv u64 rlec; 538169240Sjfv u64 xonrxc; 539169240Sjfv u64 xontxc; 540169240Sjfv u64 xoffrxc; 541169240Sjfv u64 xofftxc; 542169240Sjfv u64 fcruc; 543169240Sjfv u64 prc64; 544169240Sjfv u64 prc127; 545169240Sjfv u64 prc255; 546169240Sjfv u64 prc511; 547169240Sjfv u64 prc1023; 548169240Sjfv u64 prc1522; 549169240Sjfv u64 gprc; 550169240Sjfv u64 bprc; 551169240Sjfv u64 mprc; 552169240Sjfv u64 gptc; 553173788Sjfv u64 gorc; 554173788Sjfv u64 gotc; 555169240Sjfv u64 rnbc; 556169240Sjfv u64 ruc; 557169240Sjfv u64 rfc; 558169240Sjfv u64 roc; 559169240Sjfv u64 rjc; 560169240Sjfv u64 mgprc; 561169240Sjfv u64 mgpdc; 562169240Sjfv u64 mgptc; 563173788Sjfv u64 tor; 564173788Sjfv u64 tot; 565169240Sjfv u64 tpr; 566169240Sjfv u64 tpt; 567169240Sjfv u64 ptc64; 568169240Sjfv u64 ptc127; 569169240Sjfv u64 ptc255; 570169240Sjfv u64 ptc511; 571169240Sjfv u64 ptc1023; 572169240Sjfv u64 ptc1522; 573169240Sjfv u64 mptc; 574169240Sjfv u64 bptc; 575169240Sjfv u64 tsctc; 576169240Sjfv u64 tsctfc; 577169240Sjfv u64 iac; 578169240Sjfv u64 icrxptc; 579169240Sjfv u64 icrxatc; 580169240Sjfv u64 ictxptc; 581169240Sjfv u64 ictxatc; 582169240Sjfv u64 ictxqec; 583169240Sjfv u64 ictxqmtc; 584169240Sjfv u64 icrxdmtc; 585169240Sjfv u64 icrxoc; 586169240Sjfv u64 cbtmpc; 587169240Sjfv u64 htdpmc; 588169240Sjfv u64 cbrdpc; 589169240Sjfv u64 cbrmpc; 590169240Sjfv u64 rpthc; 591169240Sjfv u64 hgptc; 592169240Sjfv u64 htcbdpc; 593173788Sjfv u64 hgorc; 594173788Sjfv u64 hgotc; 595169240Sjfv u64 lenerrs; 596169240Sjfv u64 scvpc; 597169240Sjfv u64 hrmpc; 598185353Sjfv u64 doosync; 599228386Sjfv u64 o2bgptc; 600228386Sjfv u64 o2bspc; 601228386Sjfv u64 b2ospc; 602228386Sjfv u64 b2ogprc; 603169240Sjfv}; 604169240Sjfv 605209616Sjfvstruct e1000_vf_stats { 606209616Sjfv u64 base_gprc; 607209616Sjfv u64 base_gptc; 608209616Sjfv u64 base_gorc; 609209616Sjfv u64 base_gotc; 610209616Sjfv u64 base_mprc; 611209616Sjfv u64 base_gotlbc; 612209616Sjfv u64 base_gptlbc; 613209616Sjfv u64 base_gorlbc; 614209616Sjfv u64 base_gprlbc; 615185353Sjfv 616209616Sjfv u32 last_gprc; 617209616Sjfv u32 last_gptc; 618209616Sjfv u32 last_gorc; 619209616Sjfv u32 last_gotc; 620209616Sjfv u32 last_mprc; 621209616Sjfv u32 last_gotlbc; 622209616Sjfv u32 last_gptlbc; 623209616Sjfv u32 last_gorlbc; 624209616Sjfv u32 last_gprlbc; 625209616Sjfv 626209616Sjfv u64 gprc; 627209616Sjfv u64 gptc; 628209616Sjfv u64 gorc; 629209616Sjfv u64 gotc; 630209616Sjfv u64 mprc; 631209616Sjfv u64 gotlbc; 632209616Sjfv u64 gptlbc; 633209616Sjfv u64 gorlbc; 634209616Sjfv u64 gprlbc; 635209616Sjfv}; 636209616Sjfv 637169240Sjfvstruct e1000_phy_stats { 638169240Sjfv u32 idle_errors; 639169240Sjfv u32 receive_errors; 640169240Sjfv}; 641169240Sjfv 642169240Sjfvstruct e1000_host_mng_dhcp_cookie { 643169240Sjfv u32 signature; 644169240Sjfv u8 status; 645169240Sjfv u8 reserved0; 646169240Sjfv u16 vlan_id; 647169240Sjfv u32 reserved1; 648169240Sjfv u16 reserved2; 649169240Sjfv u8 reserved3; 650169240Sjfv u8 checksum; 651169240Sjfv}; 652169240Sjfv 653169240Sjfv/* Host Interface "Rev 1" */ 654169240Sjfvstruct e1000_host_command_header { 655169240Sjfv u8 command_id; 656169240Sjfv u8 command_length; 657169240Sjfv u8 command_options; 658169240Sjfv u8 checksum; 659169240Sjfv}; 660169240Sjfv 661228386Sjfv#define E1000_HI_MAX_DATA_LENGTH 252 662169240Sjfvstruct e1000_host_command_info { 663169240Sjfv struct e1000_host_command_header command_header; 664169240Sjfv u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 665169240Sjfv}; 666169240Sjfv 667169240Sjfv/* Host Interface "Rev 2" */ 668169240Sjfvstruct e1000_host_mng_command_header { 669169240Sjfv u8 command_id; 670169240Sjfv u8 checksum; 671169240Sjfv u16 reserved1; 672169240Sjfv u16 reserved2; 673169240Sjfv u16 command_length; 674169240Sjfv}; 675169240Sjfv 676228386Sjfv#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 677169240Sjfvstruct e1000_host_mng_command_info { 678169240Sjfv struct e1000_host_mng_command_header command_header; 679169240Sjfv u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 680169240Sjfv}; 681169240Sjfv 682169240Sjfv#include "e1000_mac.h" 683169240Sjfv#include "e1000_phy.h" 684169240Sjfv#include "e1000_nvm.h" 685169240Sjfv#include "e1000_manage.h" 686209616Sjfv#include "e1000_mbx.h" 687169240Sjfv 688247064Sjfv/* Function pointers for the MAC. */ 689177867Sjfvstruct e1000_mac_operations { 690177867Sjfv s32 (*init_params)(struct e1000_hw *); 691190872Sjfv s32 (*id_led_init)(struct e1000_hw *); 692173788Sjfv s32 (*blink_led)(struct e1000_hw *); 693247064Sjfv bool (*check_mng_mode)(struct e1000_hw *); 694173788Sjfv s32 (*check_for_link)(struct e1000_hw *); 695173788Sjfv s32 (*cleanup_led)(struct e1000_hw *); 696173788Sjfv void (*clear_hw_cntrs)(struct e1000_hw *); 697173788Sjfv void (*clear_vfta)(struct e1000_hw *); 698173788Sjfv s32 (*get_bus_info)(struct e1000_hw *); 699185353Sjfv void (*set_lan_id)(struct e1000_hw *); 700173788Sjfv s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 701173788Sjfv s32 (*led_on)(struct e1000_hw *); 702173788Sjfv s32 (*led_off)(struct e1000_hw *); 703190872Sjfv void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 704173788Sjfv s32 (*reset_hw)(struct e1000_hw *); 705173788Sjfv s32 (*init_hw)(struct e1000_hw *); 706181027Sjfv void (*shutdown_serdes)(struct e1000_hw *); 707203049Sjfv void (*power_up_serdes)(struct e1000_hw *); 708173788Sjfv s32 (*setup_link)(struct e1000_hw *); 709173788Sjfv s32 (*setup_physical_interface)(struct e1000_hw *); 710173788Sjfv s32 (*setup_led)(struct e1000_hw *); 711173788Sjfv void (*write_vfta)(struct e1000_hw *, u32, u32); 712185353Sjfv void (*config_collision_dist)(struct e1000_hw *); 713269196Sjfv int (*rar_set)(struct e1000_hw *, u8*, u32); 714185353Sjfv s32 (*read_mac_addr)(struct e1000_hw *); 715185353Sjfv s32 (*validate_mdi_setting)(struct e1000_hw *); 716247064Sjfv s32 (*set_obff_timer)(struct e1000_hw *, u32); 717238148Sjfv s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 718238148Sjfv void (*release_swfw_sync)(struct e1000_hw *, u16); 719177867Sjfv}; 720169240Sjfv 721247064Sjfv/* When to use various PHY register access functions: 722228386Sjfv * 723228386Sjfv * Func Caller 724228386Sjfv * Function Does Does When to use 725228386Sjfv * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 726228386Sjfv * X_reg L,P,A n/a for simple PHY reg accesses 727228386Sjfv * X_reg_locked P,A L for multiple accesses of different regs 728228386Sjfv * on different pages 729228386Sjfv * X_reg_page A L,P for multiple accesses of different regs 730228386Sjfv * on the same page 731228386Sjfv * 732228386Sjfv * Where X=[read|write], L=locking, P=sets page, A=register access 733228386Sjfv * 734228386Sjfv */ 735177867Sjfvstruct e1000_phy_operations { 736177867Sjfv s32 (*init_params)(struct e1000_hw *); 737177867Sjfv s32 (*acquire)(struct e1000_hw *); 738185353Sjfv s32 (*cfg_on_link_up)(struct e1000_hw *); 739173788Sjfv s32 (*check_polarity)(struct e1000_hw *); 740173788Sjfv s32 (*check_reset_block)(struct e1000_hw *); 741177867Sjfv s32 (*commit)(struct e1000_hw *); 742173788Sjfv s32 (*force_speed_duplex)(struct e1000_hw *); 743173788Sjfv s32 (*get_cfg_done)(struct e1000_hw *hw); 744173788Sjfv s32 (*get_cable_length)(struct e1000_hw *); 745177867Sjfv s32 (*get_info)(struct e1000_hw *); 746228386Sjfv s32 (*set_page)(struct e1000_hw *, u16); 747177867Sjfv s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 748200243Sjfv s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 749228386Sjfv s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 750177867Sjfv void (*release)(struct e1000_hw *); 751177867Sjfv s32 (*reset)(struct e1000_hw *); 752173788Sjfv s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 753173788Sjfv s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 754177867Sjfv s32 (*write_reg)(struct e1000_hw *, u32, u16); 755200243Sjfv s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 756228386Sjfv s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 757177867Sjfv void (*power_up)(struct e1000_hw *); 758177867Sjfv void (*power_down)(struct e1000_hw *); 759228386Sjfv s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 760228386Sjfv s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 761177867Sjfv}; 762169240Sjfv 763247064Sjfv/* Function pointers for the NVM. */ 764177867Sjfvstruct e1000_nvm_operations { 765177867Sjfv s32 (*init_params)(struct e1000_hw *); 766177867Sjfv s32 (*acquire)(struct e1000_hw *); 767177867Sjfv s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 768177867Sjfv void (*release)(struct e1000_hw *); 769177867Sjfv void (*reload)(struct e1000_hw *); 770177867Sjfv s32 (*update)(struct e1000_hw *); 771173788Sjfv s32 (*valid_led_default)(struct e1000_hw *, u16 *); 772177867Sjfv s32 (*validate)(struct e1000_hw *); 773177867Sjfv s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 774169240Sjfv}; 775169240Sjfv 776169240Sjfvstruct e1000_mac_info { 777177867Sjfv struct e1000_mac_operations ops; 778218530Sjfv u8 addr[ETH_ADDR_LEN]; 779218530Sjfv u8 perm_addr[ETH_ADDR_LEN]; 780169240Sjfv 781181027Sjfv enum e1000_mac_type type; 782169240Sjfv 783169240Sjfv u32 collision_delta; 784169240Sjfv u32 ledctl_default; 785169240Sjfv u32 ledctl_mode1; 786169240Sjfv u32 ledctl_mode2; 787169240Sjfv u32 mc_filter_type; 788169240Sjfv u32 tx_packet_delta; 789169240Sjfv u32 txcw; 790169240Sjfv 791169240Sjfv u16 current_ifs_val; 792169240Sjfv u16 ifs_max_val; 793169240Sjfv u16 ifs_min_val; 794169240Sjfv u16 ifs_ratio; 795169240Sjfv u16 ifs_step_size; 796169240Sjfv u16 mta_reg_count; 797200243Sjfv u16 uta_reg_count; 798194865Sjfv 799194865Sjfv /* Maximum size of the MTA register table in all supported adapters */ 800294958Smarius#define MAX_MTA_REG 128 801190872Sjfv u32 mta_shadow[MAX_MTA_REG]; 802169240Sjfv u16 rar_entry_count; 803169240Sjfv 804169240Sjfv u8 forced_speed_duplex; 805169240Sjfv 806173788Sjfv bool adaptive_ifs; 807205869Sjfv bool has_fwsm; 808173788Sjfv bool arc_subsystem_valid; 809173788Sjfv bool asf_firmware_present; 810173788Sjfv bool autoneg; 811173788Sjfv bool autoneg_failed; 812173788Sjfv bool get_link_status; 813173788Sjfv bool in_ifs_mode; 814173788Sjfv bool report_tx_early; 815190872Sjfv enum e1000_serdes_link_state serdes_link_state; 816173788Sjfv bool serdes_has_link; 817173788Sjfv bool tx_pkt_filtering; 818296055Serj u32 max_frame_size; 819169240Sjfv}; 820169240Sjfv 821169240Sjfvstruct e1000_phy_info { 822177867Sjfv struct e1000_phy_operations ops; 823181027Sjfv enum e1000_phy_type type; 824169240Sjfv 825181027Sjfv enum e1000_1000t_rx_status local_rx; 826181027Sjfv enum e1000_1000t_rx_status remote_rx; 827181027Sjfv enum e1000_ms_type ms_type; 828181027Sjfv enum e1000_ms_type original_ms_type; 829181027Sjfv enum e1000_rev_polarity cable_polarity; 830181027Sjfv enum e1000_smart_speed smart_speed; 831169240Sjfv 832169240Sjfv u32 addr; 833169240Sjfv u32 id; 834169240Sjfv u32 reset_delay_us; /* in usec */ 835169240Sjfv u32 revision; 836169240Sjfv 837181027Sjfv enum e1000_media_type media_type; 838173788Sjfv 839169240Sjfv u16 autoneg_advertised; 840169240Sjfv u16 autoneg_mask; 841169240Sjfv u16 cable_length; 842169240Sjfv u16 max_cable_length; 843169240Sjfv u16 min_cable_length; 844169240Sjfv 845169240Sjfv u8 mdix; 846169240Sjfv 847173788Sjfv bool disable_polarity_correction; 848173788Sjfv bool is_mdix; 849173788Sjfv bool polarity_correction; 850173788Sjfv bool speed_downgraded; 851173788Sjfv bool autoneg_wait_to_complete; 852169240Sjfv}; 853169240Sjfv 854169240Sjfvstruct e1000_nvm_info { 855177867Sjfv struct e1000_nvm_operations ops; 856181027Sjfv enum e1000_nvm_type type; 857181027Sjfv enum e1000_nvm_override override; 858169240Sjfv 859169240Sjfv u32 flash_bank_size; 860169240Sjfv u32 flash_base_addr; 861169240Sjfv 862169240Sjfv u16 word_size; 863169240Sjfv u16 delay_usec; 864169240Sjfv u16 address_bits; 865169240Sjfv u16 opcode_bits; 866169240Sjfv u16 page_size; 867169240Sjfv}; 868169240Sjfv 869169240Sjfvstruct e1000_bus_info { 870181027Sjfv enum e1000_bus_type type; 871181027Sjfv enum e1000_bus_speed speed; 872181027Sjfv enum e1000_bus_width width; 873169240Sjfv 874169240Sjfv u16 func; 875169240Sjfv u16 pci_cmd_word; 876169240Sjfv}; 877169240Sjfv 878173788Sjfvstruct e1000_fc_info { 879228386Sjfv u32 high_water; /* Flow control high-water mark */ 880228386Sjfv u32 low_water; /* Flow control low-water mark */ 881228386Sjfv u16 pause_time; /* Flow control pause timer */ 882228386Sjfv u16 refresh_time; /* Flow control refresh timer */ 883228386Sjfv bool send_xon; /* Flow control send XON */ 884228386Sjfv bool strict_ieee; /* Strict IEEE mode */ 885228386Sjfv enum e1000_fc_mode current_mode; /* FC mode in effect */ 886228386Sjfv enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 887173788Sjfv}; 888173788Sjfv 889213234Sjfvstruct e1000_mbx_operations { 890213234Sjfv s32 (*init_params)(struct e1000_hw *hw); 891213234Sjfv s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 892213234Sjfv s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 893213234Sjfv s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 894213234Sjfv s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 895213234Sjfv s32 (*check_for_msg)(struct e1000_hw *, u16); 896213234Sjfv s32 (*check_for_ack)(struct e1000_hw *, u16); 897213234Sjfv s32 (*check_for_rst)(struct e1000_hw *, u16); 898213234Sjfv}; 899213234Sjfv 900213234Sjfvstruct e1000_mbx_stats { 901213234Sjfv u32 msgs_tx; 902213234Sjfv u32 msgs_rx; 903213234Sjfv 904213234Sjfv u32 acks; 905213234Sjfv u32 reqs; 906213234Sjfv u32 rsts; 907213234Sjfv}; 908213234Sjfv 909213234Sjfvstruct e1000_mbx_info { 910213234Sjfv struct e1000_mbx_operations ops; 911213234Sjfv struct e1000_mbx_stats stats; 912213234Sjfv u32 timeout; 913213234Sjfv u32 usec_delay; 914213234Sjfv u16 size; 915213234Sjfv}; 916213234Sjfv 917185353Sjfvstruct e1000_dev_spec_82541 { 918185353Sjfv enum e1000_dsp_config dsp_config; 919185353Sjfv enum e1000_ffe_config ffe_config; 920185353Sjfv u16 spd_default; 921185353Sjfv bool phy_init_script; 922185353Sjfv}; 923185353Sjfv 924185353Sjfvstruct e1000_dev_spec_82542 { 925185353Sjfv bool dma_fairness; 926185353Sjfv}; 927185353Sjfv 928185353Sjfvstruct e1000_dev_spec_82543 { 929185353Sjfv u32 tbi_compatibility; 930185353Sjfv bool dma_fairness; 931185353Sjfv bool init_phy_disabled; 932185353Sjfv}; 933185353Sjfv 934185353Sjfvstruct e1000_dev_spec_82571 { 935185353Sjfv bool laa_is_present; 936194865Sjfv u32 smb_counter; 937213234Sjfv E1000_MUTEX swflag_mutex; 938185353Sjfv}; 939185353Sjfv 940200243Sjfvstruct e1000_dev_spec_80003es2lan { 941200243Sjfv bool mdic_wa_enable; 942200243Sjfv}; 943200243Sjfv 944185353Sjfvstruct e1000_shadow_ram { 945185353Sjfv u16 value; 946185353Sjfv bool modified; 947185353Sjfv}; 948185353Sjfv 949247064Sjfv#define E1000_SHADOW_RAM_WORDS 2048 950185353Sjfv 951269196Sjfv/* I218 PHY Ultra Low Power (ULP) states */ 952269196Sjfvenum e1000_ulp_state { 953269196Sjfv e1000_ulp_state_unknown, 954269196Sjfv e1000_ulp_state_off, 955269196Sjfv e1000_ulp_state_on, 956269196Sjfv}; 957269196Sjfv 958185353Sjfvstruct e1000_dev_spec_ich8lan { 959185353Sjfv bool kmrn_lock_loss_workaround_enabled; 960185353Sjfv struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 961200243Sjfv E1000_MUTEX nvm_mutex; 962200243Sjfv E1000_MUTEX swflag_mutex; 963200243Sjfv bool nvm_k1_enabled; 964304338Ssbruno bool disable_k1_off; 965238148Sjfv bool eee_disable; 966247064Sjfv u16 eee_lp_ability; 967269196Sjfv enum e1000_ulp_state ulp_state; 968304338Ssbruno bool ulp_capability_disabled; 969304338Ssbruno bool during_suspend_flow; 970304338Ssbruno bool during_dpg_exit; 971185353Sjfv}; 972185353Sjfv 973185353Sjfvstruct e1000_dev_spec_82575 { 974185353Sjfv bool sgmii_active; 975190872Sjfv bool global_device_reset; 976238148Sjfv bool eee_disable; 977228386Sjfv bool module_plugged; 978247064Sjfv bool clear_semaphore_once; 979228386Sjfv u32 mtu; 980247064Sjfv struct sfp_e1000_flags eth_flags; 981256200Sjfv u8 media_port; 982256200Sjfv bool media_changed; 983185353Sjfv}; 984185353Sjfv 985185353Sjfvstruct e1000_dev_spec_vf { 986218530Sjfv u32 vf_number; 987218530Sjfv u32 v2p_mailbox; 988185353Sjfv}; 989185353Sjfv 990169240Sjfvstruct e1000_hw { 991169240Sjfv void *back; 992169240Sjfv 993169240Sjfv u8 *hw_addr; 994169240Sjfv u8 *flash_address; 995169240Sjfv unsigned long io_base; 996169240Sjfv 997169240Sjfv struct e1000_mac_info mac; 998173788Sjfv struct e1000_fc_info fc; 999169240Sjfv struct e1000_phy_info phy; 1000169240Sjfv struct e1000_nvm_info nvm; 1001169240Sjfv struct e1000_bus_info bus; 1002209616Sjfv struct e1000_mbx_info mbx; 1003169240Sjfv struct e1000_host_mng_dhcp_cookie mng_cookie; 1004169240Sjfv 1005185353Sjfv union { 1006218530Sjfv struct e1000_dev_spec_82541 _82541; 1007218530Sjfv struct e1000_dev_spec_82542 _82542; 1008218530Sjfv struct e1000_dev_spec_82543 _82543; 1009218530Sjfv struct e1000_dev_spec_82571 _82571; 1010200243Sjfv struct e1000_dev_spec_80003es2lan _80003es2lan; 1011218530Sjfv struct e1000_dev_spec_ich8lan ich8lan; 1012218530Sjfv struct e1000_dev_spec_82575 _82575; 1013218530Sjfv struct e1000_dev_spec_vf vf; 1014185353Sjfv } dev_spec; 1015169240Sjfv 1016169240Sjfv u16 device_id; 1017169240Sjfv u16 subsystem_vendor_id; 1018169240Sjfv u16 subsystem_device_id; 1019169240Sjfv u16 vendor_id; 1020169240Sjfv 1021169240Sjfv u8 revision_id; 1022169240Sjfv}; 1023169240Sjfv 1024181027Sjfv#include "e1000_82541.h" 1025181027Sjfv#include "e1000_82543.h" 1026181027Sjfv#include "e1000_82571.h" 1027181027Sjfv#include "e1000_80003es2lan.h" 1028181027Sjfv#include "e1000_ich8lan.h" 1029181027Sjfv#include "e1000_82575.h" 1030238148Sjfv#include "e1000_i210.h" 1031181027Sjfv 1032169240Sjfv/* These functions must be implemented by drivers */ 1033169240Sjfvvoid e1000_pci_clear_mwi(struct e1000_hw *hw); 1034169240Sjfvvoid e1000_pci_set_mwi(struct e1000_hw *hw); 1035169240Sjfvs32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1036194865Sjfvs32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1037169240Sjfvvoid e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1038169240Sjfvvoid e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1039169240Sjfv 1040169240Sjfv#endif 1041