e1000_hw.h revision 178523
1/****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/em/e1000_hw.h 178523 2008-04-25 21:19:41Z jfv $*/ 34 35#ifndef _E1000_HW_H_ 36#define _E1000_HW_H_ 37 38#include "e1000_osdep.h" 39#include "e1000_regs.h" 40#include "e1000_defines.h" 41 42struct e1000_hw; 43 44#ifndef NO_82542_SUPPORT 45#define E1000_DEV_ID_82542 0x1000 46#endif 47#define E1000_DEV_ID_82543GC_FIBER 0x1001 48#define E1000_DEV_ID_82543GC_COPPER 0x1004 49#define E1000_DEV_ID_82544EI_COPPER 0x1008 50#define E1000_DEV_ID_82544EI_FIBER 0x1009 51#define E1000_DEV_ID_82544GC_COPPER 0x100C 52#define E1000_DEV_ID_82544GC_LOM 0x100D 53#define E1000_DEV_ID_82540EM 0x100E 54#define E1000_DEV_ID_82540EM_LOM 0x1015 55#define E1000_DEV_ID_82540EP_LOM 0x1016 56#define E1000_DEV_ID_82540EP 0x1017 57#define E1000_DEV_ID_82540EP_LP 0x101E 58#define E1000_DEV_ID_82545EM_COPPER 0x100F 59#define E1000_DEV_ID_82545EM_FIBER 0x1011 60#define E1000_DEV_ID_82545GM_COPPER 0x1026 61#define E1000_DEV_ID_82545GM_FIBER 0x1027 62#define E1000_DEV_ID_82545GM_SERDES 0x1028 63#define E1000_DEV_ID_82546EB_COPPER 0x1010 64#define E1000_DEV_ID_82546EB_FIBER 0x1012 65#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 66#define E1000_DEV_ID_82546GB_COPPER 0x1079 67#define E1000_DEV_ID_82546GB_FIBER 0x107A 68#define E1000_DEV_ID_82546GB_SERDES 0x107B 69#define E1000_DEV_ID_82546GB_PCIE 0x108A 70#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 71#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 72#define E1000_DEV_ID_82541EI 0x1013 73#define E1000_DEV_ID_82541EI_MOBILE 0x1018 74#define E1000_DEV_ID_82541ER_LOM 0x1014 75#define E1000_DEV_ID_82541ER 0x1078 76#define E1000_DEV_ID_82541GI 0x1076 77#define E1000_DEV_ID_82541GI_LF 0x107C 78#define E1000_DEV_ID_82541GI_MOBILE 0x1077 79#define E1000_DEV_ID_82547EI 0x1019 80#define E1000_DEV_ID_82547EI_MOBILE 0x101A 81#define E1000_DEV_ID_82547GI 0x1075 82#define E1000_DEV_ID_82571EB_COPPER 0x105E 83#define E1000_DEV_ID_82571EB_FIBER 0x105F 84#define E1000_DEV_ID_82571EB_SERDES 0x1060 85#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 86#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 87#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 88#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 89#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 90#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 91#define E1000_DEV_ID_82572EI_COPPER 0x107D 92#define E1000_DEV_ID_82572EI_FIBER 0x107E 93#define E1000_DEV_ID_82572EI_SERDES 0x107F 94#define E1000_DEV_ID_82572EI 0x10B9 95#define E1000_DEV_ID_82573E 0x108B 96#define E1000_DEV_ID_82573E_IAMT 0x108C 97#define E1000_DEV_ID_82573L 0x109A 98#define E1000_DEV_ID_82574L 0x10D3 99#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 104#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 105#define E1000_DEV_ID_ICH8_IGP_C 0x104B 106#define E1000_DEV_ID_ICH8_IFE 0x104C 107#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 108#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 109#define E1000_DEV_ID_ICH8_IGP_M 0x104D 110#define E1000_DEV_ID_ICH9_IGP_M 0x10BF 111#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 112#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 113#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 114#define E1000_DEV_ID_ICH9_BM 0x10E5 115#define E1000_DEV_ID_ICH9_IGP_C 0x294C 116#define E1000_DEV_ID_ICH9_IFE 0x10C0 117#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 118#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 119#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 120#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 121#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 122#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 123#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 124#define E1000_DEV_ID_82575EB_COPPER 0x10A7 125#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 126#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 127 128#define E1000_REVISION_0 0 129#define E1000_REVISION_1 1 130#define E1000_REVISION_2 2 131#define E1000_REVISION_3 3 132#define E1000_REVISION_4 4 133 134#define E1000_FUNC_0 0 135#define E1000_FUNC_1 1 136 137typedef enum { 138 e1000_undefined = 0, 139#ifndef NO_82542_SUPPORT 140 e1000_82542, 141#endif 142 e1000_82543, 143 e1000_82544, 144 e1000_82540, 145 e1000_82545, 146 e1000_82545_rev_3, 147 e1000_82546, 148 e1000_82546_rev_3, 149 e1000_82541, 150 e1000_82541_rev_2, 151 e1000_82547, 152 e1000_82547_rev_2, 153 e1000_82571, 154 e1000_82572, 155 e1000_82573, 156 e1000_82574, 157 e1000_80003es2lan, 158 e1000_ich8lan, 159 e1000_ich9lan, 160 e1000_ich10lan, 161 e1000_82575, 162 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 163} e1000_mac_type; 164 165typedef enum { 166 e1000_media_type_unknown = 0, 167 e1000_media_type_copper = 1, 168 e1000_media_type_fiber = 2, 169 e1000_media_type_internal_serdes = 3, 170 e1000_num_media_types 171} e1000_media_type; 172 173typedef enum { 174 e1000_nvm_unknown = 0, 175 e1000_nvm_none, 176 e1000_nvm_eeprom_spi, 177 e1000_nvm_eeprom_microwire, 178 e1000_nvm_flash_hw, 179 e1000_nvm_flash_sw 180} e1000_nvm_type; 181 182typedef enum { 183 e1000_nvm_override_none = 0, 184 e1000_nvm_override_spi_small, 185 e1000_nvm_override_spi_large, 186 e1000_nvm_override_microwire_small, 187 e1000_nvm_override_microwire_large 188} e1000_nvm_override; 189 190typedef enum { 191 e1000_phy_unknown = 0, 192 e1000_phy_none, 193 e1000_phy_m88, 194 e1000_phy_igp, 195 e1000_phy_igp_2, 196 e1000_phy_gg82563, 197 e1000_phy_igp_3, 198 e1000_phy_ife, 199 e1000_phy_bm, 200} e1000_phy_type; 201 202typedef enum { 203 e1000_bus_type_unknown = 0, 204 e1000_bus_type_pci, 205 e1000_bus_type_pcix, 206 e1000_bus_type_pci_express, 207 e1000_bus_type_reserved 208} e1000_bus_type; 209 210typedef enum { 211 e1000_bus_speed_unknown = 0, 212 e1000_bus_speed_33, 213 e1000_bus_speed_66, 214 e1000_bus_speed_100, 215 e1000_bus_speed_120, 216 e1000_bus_speed_133, 217 e1000_bus_speed_2500, 218 e1000_bus_speed_5000, 219 e1000_bus_speed_reserved 220} e1000_bus_speed; 221 222typedef enum { 223 e1000_bus_width_unknown = 0, 224 e1000_bus_width_pcie_x1, 225 e1000_bus_width_pcie_x2, 226 e1000_bus_width_pcie_x4 = 4, 227 e1000_bus_width_pcie_x8 = 8, 228 e1000_bus_width_32, 229 e1000_bus_width_64, 230 e1000_bus_width_reserved 231} e1000_bus_width; 232 233typedef enum { 234 e1000_1000t_rx_status_not_ok = 0, 235 e1000_1000t_rx_status_ok, 236 e1000_1000t_rx_status_undefined = 0xFF 237} e1000_1000t_rx_status; 238 239typedef enum { 240 e1000_rev_polarity_normal = 0, 241 e1000_rev_polarity_reversed, 242 e1000_rev_polarity_undefined = 0xFF 243} e1000_rev_polarity; 244 245typedef enum { 246 e1000_fc_none = 0, 247 e1000_fc_rx_pause, 248 e1000_fc_tx_pause, 249 e1000_fc_full, 250 e1000_fc_default = 0xFF 251} e1000_fc_type; 252 253typedef enum { 254 e1000_ffe_config_enabled = 0, 255 e1000_ffe_config_active, 256 e1000_ffe_config_blocked 257} e1000_ffe_config; 258 259typedef enum { 260 e1000_dsp_config_disabled = 0, 261 e1000_dsp_config_enabled, 262 e1000_dsp_config_activated, 263 e1000_dsp_config_undefined = 0xFF 264} e1000_dsp_config; 265 266/* Receive Descriptor */ 267struct e1000_rx_desc { 268 u64 buffer_addr; /* Address of the descriptor's data buffer */ 269 u16 length; /* Length of data DMAed into data buffer */ 270 u16 csum; /* Packet checksum */ 271 u8 status; /* Descriptor status */ 272 u8 errors; /* Descriptor Errors */ 273 u16 special; 274}; 275 276/* Receive Descriptor - Extended */ 277union e1000_rx_desc_extended { 278 struct { 279 u64 buffer_addr; 280 u64 reserved; 281 } read; 282 struct { 283 struct { 284 u32 mrq; /* Multiple Rx Queues */ 285 union { 286 u32 rss; /* RSS Hash */ 287 struct { 288 u16 ip_id; /* IP id */ 289 u16 csum; /* Packet Checksum */ 290 } csum_ip; 291 } hi_dword; 292 } lower; 293 struct { 294 u32 status_error; /* ext status/error */ 295 u16 length; 296 u16 vlan; /* VLAN tag */ 297 } upper; 298 } wb; /* writeback */ 299}; 300 301#define MAX_PS_BUFFERS 4 302/* Receive Descriptor - Packet Split */ 303union e1000_rx_desc_packet_split { 304 struct { 305 /* one buffer for protocol header(s), three data buffers */ 306 u64 buffer_addr[MAX_PS_BUFFERS]; 307 } read; 308 struct { 309 struct { 310 u32 mrq; /* Multiple Rx Queues */ 311 union { 312 u32 rss; /* RSS Hash */ 313 struct { 314 u16 ip_id; /* IP id */ 315 u16 csum; /* Packet Checksum */ 316 } csum_ip; 317 } hi_dword; 318 } lower; 319 struct { 320 u32 status_error; /* ext status/error */ 321 u16 length0; /* length of buffer 0 */ 322 u16 vlan; /* VLAN tag */ 323 } middle; 324 struct { 325 u16 header_status; 326 u16 length[3]; /* length of buffers 1-3 */ 327 } upper; 328 u64 reserved; 329 } wb; /* writeback */ 330}; 331 332/* Transmit Descriptor */ 333struct e1000_tx_desc { 334 u64 buffer_addr; /* Address of the descriptor's data buffer */ 335 union { 336 u32 data; 337 struct { 338 u16 length; /* Data buffer length */ 339 u8 cso; /* Checksum offset */ 340 u8 cmd; /* Descriptor control */ 341 } flags; 342 } lower; 343 union { 344 u32 data; 345 struct { 346 u8 status; /* Descriptor status */ 347 u8 css; /* Checksum start */ 348 u16 special; 349 } fields; 350 } upper; 351}; 352 353/* Offload Context Descriptor */ 354struct e1000_context_desc { 355 union { 356 u32 ip_config; 357 struct { 358 u8 ipcss; /* IP checksum start */ 359 u8 ipcso; /* IP checksum offset */ 360 u16 ipcse; /* IP checksum end */ 361 } ip_fields; 362 } lower_setup; 363 union { 364 u32 tcp_config; 365 struct { 366 u8 tucss; /* TCP checksum start */ 367 u8 tucso; /* TCP checksum offset */ 368 u16 tucse; /* TCP checksum end */ 369 } tcp_fields; 370 } upper_setup; 371 u32 cmd_and_length; 372 union { 373 u32 data; 374 struct { 375 u8 status; /* Descriptor status */ 376 u8 hdr_len; /* Header length */ 377 u16 mss; /* Maximum segment size */ 378 } fields; 379 } tcp_seg_setup; 380}; 381 382/* Offload data descriptor */ 383struct e1000_data_desc { 384 u64 buffer_addr; /* Address of the descriptor's buffer address */ 385 union { 386 u32 data; 387 struct { 388 u16 length; /* Data buffer length */ 389 u8 typ_len_ext; 390 u8 cmd; 391 } flags; 392 } lower; 393 union { 394 u32 data; 395 struct { 396 u8 status; /* Descriptor status */ 397 u8 popts; /* Packet Options */ 398 u16 special; 399 } fields; 400 } upper; 401}; 402 403/* Statistics counters collected by the MAC */ 404struct e1000_hw_stats { 405 u64 crcerrs; 406 u64 algnerrc; 407 u64 symerrs; 408 u64 rxerrc; 409 u64 mpc; 410 u64 scc; 411 u64 ecol; 412 u64 mcc; 413 u64 latecol; 414 u64 colc; 415 u64 dc; 416 u64 tncrs; 417 u64 sec; 418 u64 cexterr; 419 u64 rlec; 420 u64 xonrxc; 421 u64 xontxc; 422 u64 xoffrxc; 423 u64 xofftxc; 424 u64 fcruc; 425 u64 prc64; 426 u64 prc127; 427 u64 prc255; 428 u64 prc511; 429 u64 prc1023; 430 u64 prc1522; 431 u64 gprc; 432 u64 bprc; 433 u64 mprc; 434 u64 gptc; 435 u64 gorc; 436 u64 gotc; 437 u64 rnbc; 438 u64 ruc; 439 u64 rfc; 440 u64 roc; 441 u64 rjc; 442 u64 mgprc; 443 u64 mgpdc; 444 u64 mgptc; 445 u64 tor; 446 u64 tot; 447 u64 tpr; 448 u64 tpt; 449 u64 ptc64; 450 u64 ptc127; 451 u64 ptc255; 452 u64 ptc511; 453 u64 ptc1023; 454 u64 ptc1522; 455 u64 mptc; 456 u64 bptc; 457 u64 tsctc; 458 u64 tsctfc; 459 u64 iac; 460 u64 icrxptc; 461 u64 icrxatc; 462 u64 ictxptc; 463 u64 ictxatc; 464 u64 ictxqec; 465 u64 ictxqmtc; 466 u64 icrxdmtc; 467 u64 icrxoc; 468 u64 cbtmpc; 469 u64 htdpmc; 470 u64 cbrdpc; 471 u64 cbrmpc; 472 u64 rpthc; 473 u64 hgptc; 474 u64 htcbdpc; 475 u64 hgorc; 476 u64 hgotc; 477 u64 lenerrs; 478 u64 scvpc; 479 u64 hrmpc; 480}; 481 482struct e1000_phy_stats { 483 u32 idle_errors; 484 u32 receive_errors; 485}; 486 487struct e1000_host_mng_dhcp_cookie { 488 u32 signature; 489 u8 status; 490 u8 reserved0; 491 u16 vlan_id; 492 u32 reserved1; 493 u16 reserved2; 494 u8 reserved3; 495 u8 checksum; 496}; 497 498/* Host Interface "Rev 1" */ 499struct e1000_host_command_header { 500 u8 command_id; 501 u8 command_length; 502 u8 command_options; 503 u8 checksum; 504}; 505 506#define E1000_HI_MAX_DATA_LENGTH 252 507struct e1000_host_command_info { 508 struct e1000_host_command_header command_header; 509 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 510}; 511 512/* Host Interface "Rev 2" */ 513struct e1000_host_mng_command_header { 514 u8 command_id; 515 u8 checksum; 516 u16 reserved1; 517 u16 reserved2; 518 u16 command_length; 519}; 520 521#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 522struct e1000_host_mng_command_info { 523 struct e1000_host_mng_command_header command_header; 524 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 525}; 526 527#include "e1000_mac.h" 528#include "e1000_phy.h" 529#include "e1000_nvm.h" 530#include "e1000_manage.h" 531 532struct e1000_mac_operations { 533 /* Function pointers for the MAC. */ 534 s32 (*init_params)(struct e1000_hw *); 535 s32 (*blink_led)(struct e1000_hw *); 536 s32 (*check_for_link)(struct e1000_hw *); 537 bool (*check_mng_mode)(struct e1000_hw *hw); 538 s32 (*cleanup_led)(struct e1000_hw *); 539 void (*clear_hw_cntrs)(struct e1000_hw *); 540 void (*clear_vfta)(struct e1000_hw *); 541 s32 (*get_bus_info)(struct e1000_hw *); 542 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 543 s32 (*led_on)(struct e1000_hw *); 544 s32 (*led_off)(struct e1000_hw *); 545 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, 546 u32); 547 void (*remove_device)(struct e1000_hw *); 548 s32 (*reset_hw)(struct e1000_hw *); 549 s32 (*init_hw)(struct e1000_hw *); 550 s32 (*setup_link)(struct e1000_hw *); 551 s32 (*setup_physical_interface)(struct e1000_hw *); 552 s32 (*setup_led)(struct e1000_hw *); 553 void (*write_vfta)(struct e1000_hw *, u32, u32); 554 void (*mta_set)(struct e1000_hw *, u32); 555 void (*config_collision_dist)(struct e1000_hw*); 556 void (*rar_set)(struct e1000_hw*, u8*, u32); 557 s32 (*read_mac_addr)(struct e1000_hw*); 558 s32 (*validate_mdi_setting)(struct e1000_hw*); 559 s32 (*mng_host_if_write)(struct e1000_hw*, u8*, u16, u16, u8*); 560 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 561 struct e1000_host_mng_command_header*); 562 s32 (*mng_enable_host_if)(struct e1000_hw*); 563 s32 (*wait_autoneg)(struct e1000_hw*); 564}; 565 566struct e1000_phy_operations { 567 s32 (*init_params)(struct e1000_hw *); 568 s32 (*acquire)(struct e1000_hw *); 569 s32 (*check_polarity)(struct e1000_hw *); 570 s32 (*check_reset_block)(struct e1000_hw *); 571 s32 (*commit)(struct e1000_hw *); 572 s32 (*force_speed_duplex)(struct e1000_hw *); 573 s32 (*get_cfg_done)(struct e1000_hw *hw); 574 s32 (*get_cable_length)(struct e1000_hw *); 575 s32 (*get_info)(struct e1000_hw *); 576 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 577 void (*release)(struct e1000_hw *); 578 s32 (*reset)(struct e1000_hw *); 579 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 580 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 581 s32 (*write_reg)(struct e1000_hw *, u32, u16); 582 void (*power_up)(struct e1000_hw *); 583 void (*power_down)(struct e1000_hw *); 584}; 585 586struct e1000_nvm_operations { 587 s32 (*init_params)(struct e1000_hw *); 588 s32 (*acquire)(struct e1000_hw *); 589 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 590 void (*release)(struct e1000_hw *); 591 void (*reload)(struct e1000_hw *); 592 s32 (*update)(struct e1000_hw *); 593 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 594 s32 (*validate)(struct e1000_hw *); 595 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 596}; 597 598struct e1000_mac_info { 599 struct e1000_mac_operations ops; 600 u8 addr[6]; 601 u8 perm_addr[6]; 602 603 e1000_mac_type type; 604 605 u32 collision_delta; 606 u32 ledctl_default; 607 u32 ledctl_mode1; 608 u32 ledctl_mode2; 609 u32 mc_filter_type; 610 u32 tx_packet_delta; 611 u32 txcw; 612 613 u16 current_ifs_val; 614 u16 ifs_max_val; 615 u16 ifs_min_val; 616 u16 ifs_ratio; 617 u16 ifs_step_size; 618 u16 mta_reg_count; 619 u16 rar_entry_count; 620 621 u8 forced_speed_duplex; 622 623 bool adaptive_ifs; 624 bool arc_subsystem_valid; 625 bool asf_firmware_present; 626 bool autoneg; 627 bool autoneg_failed; 628 bool disable_av; 629 bool disable_hw_init_bits; 630 bool get_link_status; 631 bool ifs_params_forced; 632 bool in_ifs_mode; 633 bool report_tx_early; 634 bool serdes_has_link; 635 bool tx_pkt_filtering; 636}; 637 638struct e1000_phy_info { 639 struct e1000_phy_operations ops; 640 e1000_phy_type type; 641 642 e1000_1000t_rx_status local_rx; 643 e1000_1000t_rx_status remote_rx; 644 e1000_ms_type ms_type; 645 e1000_ms_type original_ms_type; 646 e1000_rev_polarity cable_polarity; 647 e1000_smart_speed smart_speed; 648 649 u32 addr; 650 u32 id; 651 u32 reset_delay_us; /* in usec */ 652 u32 revision; 653 654 e1000_media_type media_type; 655 656 u16 autoneg_advertised; 657 u16 autoneg_mask; 658 u16 cable_length; 659 u16 max_cable_length; 660 u16 min_cable_length; 661 662 u8 mdix; 663 664 bool disable_polarity_correction; 665 bool is_mdix; 666 bool polarity_correction; 667 bool reset_disable; 668 bool speed_downgraded; 669 bool autoneg_wait_to_complete; 670}; 671 672struct e1000_nvm_info { 673 struct e1000_nvm_operations ops; 674 e1000_nvm_type type; 675 e1000_nvm_override override; 676 677 u32 flash_bank_size; 678 u32 flash_base_addr; 679 680 u16 word_size; 681 u16 delay_usec; 682 u16 address_bits; 683 u16 opcode_bits; 684 u16 page_size; 685}; 686 687struct e1000_bus_info { 688 e1000_bus_type type; 689 e1000_bus_speed speed; 690 e1000_bus_width width; 691 692 u32 snoop; 693 694 u16 func; 695 u16 pci_cmd_word; 696}; 697 698struct e1000_fc_info { 699 u32 high_water; /* Flow control high-water mark */ 700 u32 low_water; /* Flow control low-water mark */ 701 u16 pause_time; /* Flow control pause timer */ 702 bool send_xon; /* Flow control send XON */ 703 bool strict_ieee; /* Strict IEEE mode */ 704 e1000_fc_type type; /* Type of flow control */ 705 e1000_fc_type original_type; 706}; 707 708struct e1000_hw { 709 void *back; 710 void *dev_spec; 711 712 u8 *hw_addr; 713 u8 *flash_address; 714 unsigned long io_base; 715 716 struct e1000_mac_info mac; 717 struct e1000_fc_info fc; 718 struct e1000_phy_info phy; 719 struct e1000_nvm_info nvm; 720 struct e1000_bus_info bus; 721 struct e1000_host_mng_dhcp_cookie mng_cookie; 722 723 u32 dev_spec_size; 724 725 u16 device_id; 726 u16 subsystem_vendor_id; 727 u16 subsystem_device_id; 728 u16 vendor_id; 729 730 u8 revision_id; 731}; 732 733/* These functions must be implemented by drivers */ 734void e1000_pci_clear_mwi(struct e1000_hw *hw); 735void e1000_pci_set_mwi(struct e1000_hw *hw); 736s32 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size); 737s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 738void e1000_free_dev_spec_struct(struct e1000_hw *hw); 739void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 740void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 741 742#endif 743