1177867Sjfv/****************************************************************************** 2169240Sjfv 3294958Smarius Copyright (c) 2001-2015, Intel Corporation 4169240Sjfv All rights reserved. 5169240Sjfv 6169240Sjfv Redistribution and use in source and binary forms, with or without 7169240Sjfv modification, are permitted provided that the following conditions are met: 8169240Sjfv 9169240Sjfv 1. Redistributions of source code must retain the above copyright notice, 10169240Sjfv this list of conditions and the following disclaimer. 11169240Sjfv 12169240Sjfv 2. Redistributions in binary form must reproduce the above copyright 13169240Sjfv notice, this list of conditions and the following disclaimer in the 14169240Sjfv documentation and/or other materials provided with the distribution. 15169240Sjfv 16169240Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17169240Sjfv contributors may be used to endorse or promote products derived from 18169240Sjfv this software without specific prior written permission. 19169240Sjfv 20169240Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21169240Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22169240Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23169240Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24169240Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25169240Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26169240Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27169240Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28169240Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29169240Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30169240Sjfv POSSIBILITY OF SUCH DAMAGE. 31169240Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: stable/10/sys/dev/e1000/e1000_hw.h 333214 2018-05-03 15:41:04Z marius $*/ 34169240Sjfv 35169240Sjfv#ifndef _E1000_HW_H_ 36169240Sjfv#define _E1000_HW_H_ 37169240Sjfv 38169240Sjfv#include "e1000_osdep.h" 39169240Sjfv#include "e1000_regs.h" 40169240Sjfv#include "e1000_defines.h" 41169240Sjfv 42169240Sjfvstruct e1000_hw; 43169240Sjfv 44228386Sjfv#define E1000_DEV_ID_82542 0x1000 45228386Sjfv#define E1000_DEV_ID_82543GC_FIBER 0x1001 46228386Sjfv#define E1000_DEV_ID_82543GC_COPPER 0x1004 47228386Sjfv#define E1000_DEV_ID_82544EI_COPPER 0x1008 48228386Sjfv#define E1000_DEV_ID_82544EI_FIBER 0x1009 49228386Sjfv#define E1000_DEV_ID_82544GC_COPPER 0x100C 50228386Sjfv#define E1000_DEV_ID_82544GC_LOM 0x100D 51228386Sjfv#define E1000_DEV_ID_82540EM 0x100E 52228386Sjfv#define E1000_DEV_ID_82540EM_LOM 0x1015 53228386Sjfv#define E1000_DEV_ID_82540EP_LOM 0x1016 54228386Sjfv#define E1000_DEV_ID_82540EP 0x1017 55228386Sjfv#define E1000_DEV_ID_82540EP_LP 0x101E 56228386Sjfv#define E1000_DEV_ID_82545EM_COPPER 0x100F 57228386Sjfv#define E1000_DEV_ID_82545EM_FIBER 0x1011 58228386Sjfv#define E1000_DEV_ID_82545GM_COPPER 0x1026 59228386Sjfv#define E1000_DEV_ID_82545GM_FIBER 0x1027 60228386Sjfv#define E1000_DEV_ID_82545GM_SERDES 0x1028 61228386Sjfv#define E1000_DEV_ID_82546EB_COPPER 0x1010 62228386Sjfv#define E1000_DEV_ID_82546EB_FIBER 0x1012 63228386Sjfv#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64228386Sjfv#define E1000_DEV_ID_82546GB_COPPER 0x1079 65228386Sjfv#define E1000_DEV_ID_82546GB_FIBER 0x107A 66228386Sjfv#define E1000_DEV_ID_82546GB_SERDES 0x107B 67228386Sjfv#define E1000_DEV_ID_82546GB_PCIE 0x108A 68228386Sjfv#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69228386Sjfv#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70228386Sjfv#define E1000_DEV_ID_82541EI 0x1013 71228386Sjfv#define E1000_DEV_ID_82541EI_MOBILE 0x1018 72228386Sjfv#define E1000_DEV_ID_82541ER_LOM 0x1014 73228386Sjfv#define E1000_DEV_ID_82541ER 0x1078 74228386Sjfv#define E1000_DEV_ID_82541GI 0x1076 75228386Sjfv#define E1000_DEV_ID_82541GI_LF 0x107C 76228386Sjfv#define E1000_DEV_ID_82541GI_MOBILE 0x1077 77228386Sjfv#define E1000_DEV_ID_82547EI 0x1019 78228386Sjfv#define E1000_DEV_ID_82547EI_MOBILE 0x101A 79228386Sjfv#define E1000_DEV_ID_82547GI 0x1075 80228386Sjfv#define E1000_DEV_ID_82571EB_COPPER 0x105E 81228386Sjfv#define E1000_DEV_ID_82571EB_FIBER 0x105F 82228386Sjfv#define E1000_DEV_ID_82571EB_SERDES 0x1060 83228386Sjfv#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84228386Sjfv#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85228386Sjfv#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86228386Sjfv#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87228386Sjfv#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88228386Sjfv#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89228386Sjfv#define E1000_DEV_ID_82572EI_COPPER 0x107D 90228386Sjfv#define E1000_DEV_ID_82572EI_FIBER 0x107E 91228386Sjfv#define E1000_DEV_ID_82572EI_SERDES 0x107F 92228386Sjfv#define E1000_DEV_ID_82572EI 0x10B9 93228386Sjfv#define E1000_DEV_ID_82573E 0x108B 94228386Sjfv#define E1000_DEV_ID_82573E_IAMT 0x108C 95228386Sjfv#define E1000_DEV_ID_82573L 0x109A 96228386Sjfv#define E1000_DEV_ID_82574L 0x10D3 97228386Sjfv#define E1000_DEV_ID_82574LA 0x10F6 98228386Sjfv#define E1000_DEV_ID_82583V 0x150C 99228386Sjfv#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100228386Sjfv#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101228386Sjfv#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102228386Sjfv#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103228386Sjfv#define E1000_DEV_ID_ICH8_82567V_3 0x1501 104228386Sjfv#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 105228386Sjfv#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 106228386Sjfv#define E1000_DEV_ID_ICH8_IGP_C 0x104B 107228386Sjfv#define E1000_DEV_ID_ICH8_IFE 0x104C 108228386Sjfv#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 109228386Sjfv#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 110228386Sjfv#define E1000_DEV_ID_ICH8_IGP_M 0x104D 111228386Sjfv#define E1000_DEV_ID_ICH9_IGP_M 0x10BF 112228386Sjfv#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 113228386Sjfv#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 114228386Sjfv#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 115228386Sjfv#define E1000_DEV_ID_ICH9_BM 0x10E5 116228386Sjfv#define E1000_DEV_ID_ICH9_IGP_C 0x294C 117228386Sjfv#define E1000_DEV_ID_ICH9_IFE 0x10C0 118228386Sjfv#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 119228386Sjfv#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 120228386Sjfv#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 121228386Sjfv#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 122228386Sjfv#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 123228386Sjfv#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 124228386Sjfv#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 125228386Sjfv#define E1000_DEV_ID_ICH10_D_BM_V 0x1525 126228386Sjfv#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 127228386Sjfv#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 128228386Sjfv#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 129228386Sjfv#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 130228386Sjfv#define E1000_DEV_ID_PCH2_LV_LM 0x1502 131228386Sjfv#define E1000_DEV_ID_PCH2_LV_V 0x1503 132247064Sjfv#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 133247064Sjfv#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 134247064Sjfv#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 135247064Sjfv#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 136269196Sjfv#define E1000_DEV_ID_PCH_I218_LM2 0x15A0 137269196Sjfv#define E1000_DEV_ID_PCH_I218_V2 0x15A1 138269196Sjfv#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */ 139269196Sjfv#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */ 140296055Serj#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */ 141296055Serj#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */ 142296055Serj#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */ 143296055Serj#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */ 144296055Serj#define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */ 145304338Ssbruno#define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 146304338Ssbruno#define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 147304338Ssbruno#define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 148304338Ssbruno#define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 149333214Smarius#define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 150333214Smarius#define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 151333214Smarius#define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 152333214Smarius#define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 153333214Smarius#define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 154333214Smarius#define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 155333214Smarius#define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 156333214Smarius#define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 157228386Sjfv#define E1000_DEV_ID_82576 0x10C9 158228386Sjfv#define E1000_DEV_ID_82576_FIBER 0x10E6 159228386Sjfv#define E1000_DEV_ID_82576_SERDES 0x10E7 160228386Sjfv#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 161228386Sjfv#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 162228386Sjfv#define E1000_DEV_ID_82576_NS 0x150A 163228386Sjfv#define E1000_DEV_ID_82576_NS_SERDES 0x1518 164228386Sjfv#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 165228386Sjfv#define E1000_DEV_ID_82576_VF 0x10CA 166247064Sjfv#define E1000_DEV_ID_82576_VF_HV 0x152D 167228386Sjfv#define E1000_DEV_ID_I350_VF 0x1520 168247064Sjfv#define E1000_DEV_ID_I350_VF_HV 0x152F 169228386Sjfv#define E1000_DEV_ID_82575EB_COPPER 0x10A7 170228386Sjfv#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 171228386Sjfv#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 172228386Sjfv#define E1000_DEV_ID_82580_COPPER 0x150E 173228386Sjfv#define E1000_DEV_ID_82580_FIBER 0x150F 174228386Sjfv#define E1000_DEV_ID_82580_SERDES 0x1510 175228386Sjfv#define E1000_DEV_ID_82580_SGMII 0x1511 176228386Sjfv#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 177228386Sjfv#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 178228386Sjfv#define E1000_DEV_ID_I350_COPPER 0x1521 179228386Sjfv#define E1000_DEV_ID_I350_FIBER 0x1522 180228386Sjfv#define E1000_DEV_ID_I350_SERDES 0x1523 181228386Sjfv#define E1000_DEV_ID_I350_SGMII 0x1524 182228386Sjfv#define E1000_DEV_ID_I350_DA4 0x1546 183238148Sjfv#define E1000_DEV_ID_I210_COPPER 0x1533 184238148Sjfv#define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 185238148Sjfv#define E1000_DEV_ID_I210_COPPER_IT 0x1535 186238148Sjfv#define E1000_DEV_ID_I210_FIBER 0x1536 187238148Sjfv#define E1000_DEV_ID_I210_SERDES 0x1537 188238148Sjfv#define E1000_DEV_ID_I210_SGMII 0x1538 189256200Sjfv#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 190256200Sjfv#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 191238148Sjfv#define E1000_DEV_ID_I211_COPPER 0x1539 192256200Sjfv#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 193256200Sjfv#define E1000_DEV_ID_I354_SGMII 0x1F41 194256200Sjfv#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 195228386Sjfv#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 196228386Sjfv#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 197228386Sjfv#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 198228386Sjfv#define E1000_DEV_ID_DH89XXCC_SFP 0x0440 199247064Sjfv 200228386Sjfv#define E1000_REVISION_0 0 201228386Sjfv#define E1000_REVISION_1 1 202228386Sjfv#define E1000_REVISION_2 2 203228386Sjfv#define E1000_REVISION_3 3 204228386Sjfv#define E1000_REVISION_4 4 205169240Sjfv 206228386Sjfv#define E1000_FUNC_0 0 207228386Sjfv#define E1000_FUNC_1 1 208228386Sjfv#define E1000_FUNC_2 2 209228386Sjfv#define E1000_FUNC_3 3 210169240Sjfv 211228386Sjfv#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 212228386Sjfv#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 213228386Sjfv#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 214228386Sjfv#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 215190872Sjfv 216181027Sjfvenum e1000_mac_type { 217169240Sjfv e1000_undefined = 0, 218169240Sjfv e1000_82542, 219169240Sjfv e1000_82543, 220169240Sjfv e1000_82544, 221169240Sjfv e1000_82540, 222169240Sjfv e1000_82545, 223169240Sjfv e1000_82545_rev_3, 224169240Sjfv e1000_82546, 225169240Sjfv e1000_82546_rev_3, 226169240Sjfv e1000_82541, 227169240Sjfv e1000_82541_rev_2, 228169240Sjfv e1000_82547, 229169240Sjfv e1000_82547_rev_2, 230169240Sjfv e1000_82571, 231169240Sjfv e1000_82572, 232169240Sjfv e1000_82573, 233178523Sjfv e1000_82574, 234194865Sjfv e1000_82583, 235169240Sjfv e1000_80003es2lan, 236169240Sjfv e1000_ich8lan, 237169240Sjfv e1000_ich9lan, 238178523Sjfv e1000_ich10lan, 239194865Sjfv e1000_pchlan, 240213234Sjfv e1000_pch2lan, 241247064Sjfv e1000_pch_lpt, 242296055Serj e1000_pch_spt, 243333214Smarius e1000_pch_cnp, 244177867Sjfv e1000_82575, 245181027Sjfv e1000_82576, 246200243Sjfv e1000_82580, 247218530Sjfv e1000_i350, 248256200Sjfv e1000_i354, 249238148Sjfv e1000_i210, 250238148Sjfv e1000_i211, 251209616Sjfv e1000_vfadapt, 252218530Sjfv e1000_vfadapt_i350, 253177867Sjfv e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 254181027Sjfv}; 255169240Sjfv 256181027Sjfvenum e1000_media_type { 257169240Sjfv e1000_media_type_unknown = 0, 258169240Sjfv e1000_media_type_copper = 1, 259169240Sjfv e1000_media_type_fiber = 2, 260169240Sjfv e1000_media_type_internal_serdes = 3, 261169240Sjfv e1000_num_media_types 262181027Sjfv}; 263169240Sjfv 264181027Sjfvenum e1000_nvm_type { 265169240Sjfv e1000_nvm_unknown = 0, 266169240Sjfv e1000_nvm_none, 267169240Sjfv e1000_nvm_eeprom_spi, 268169240Sjfv e1000_nvm_eeprom_microwire, 269169240Sjfv e1000_nvm_flash_hw, 270256200Sjfv e1000_nvm_invm, 271169240Sjfv e1000_nvm_flash_sw 272181027Sjfv}; 273169240Sjfv 274181027Sjfvenum e1000_nvm_override { 275169240Sjfv e1000_nvm_override_none = 0, 276169240Sjfv e1000_nvm_override_spi_small, 277169240Sjfv e1000_nvm_override_spi_large, 278169240Sjfv e1000_nvm_override_microwire_small, 279169240Sjfv e1000_nvm_override_microwire_large 280181027Sjfv}; 281169240Sjfv 282181027Sjfvenum e1000_phy_type { 283169240Sjfv e1000_phy_unknown = 0, 284169240Sjfv e1000_phy_none, 285169240Sjfv e1000_phy_m88, 286169240Sjfv e1000_phy_igp, 287169240Sjfv e1000_phy_igp_2, 288169240Sjfv e1000_phy_gg82563, 289169240Sjfv e1000_phy_igp_3, 290169240Sjfv e1000_phy_ife, 291176667Sjfv e1000_phy_bm, 292194865Sjfv e1000_phy_82578, 293194865Sjfv e1000_phy_82577, 294213234Sjfv e1000_phy_82579, 295247064Sjfv e1000_phy_i217, 296200243Sjfv e1000_phy_82580, 297181027Sjfv e1000_phy_vf, 298238148Sjfv e1000_phy_i210, 299181027Sjfv}; 300169240Sjfv 301181027Sjfvenum e1000_bus_type { 302169240Sjfv e1000_bus_type_unknown = 0, 303169240Sjfv e1000_bus_type_pci, 304169240Sjfv e1000_bus_type_pcix, 305169240Sjfv e1000_bus_type_pci_express, 306169240Sjfv e1000_bus_type_reserved 307181027Sjfv}; 308169240Sjfv 309181027Sjfvenum e1000_bus_speed { 310169240Sjfv e1000_bus_speed_unknown = 0, 311169240Sjfv e1000_bus_speed_33, 312169240Sjfv e1000_bus_speed_66, 313169240Sjfv e1000_bus_speed_100, 314169240Sjfv e1000_bus_speed_120, 315169240Sjfv e1000_bus_speed_133, 316169240Sjfv e1000_bus_speed_2500, 317173788Sjfv e1000_bus_speed_5000, 318169240Sjfv e1000_bus_speed_reserved 319181027Sjfv}; 320169240Sjfv 321181027Sjfvenum e1000_bus_width { 322169240Sjfv e1000_bus_width_unknown = 0, 323169240Sjfv e1000_bus_width_pcie_x1, 324169240Sjfv e1000_bus_width_pcie_x2, 325169240Sjfv e1000_bus_width_pcie_x4 = 4, 326173788Sjfv e1000_bus_width_pcie_x8 = 8, 327169240Sjfv e1000_bus_width_32, 328169240Sjfv e1000_bus_width_64, 329169240Sjfv e1000_bus_width_reserved 330181027Sjfv}; 331169240Sjfv 332181027Sjfvenum e1000_1000t_rx_status { 333169240Sjfv e1000_1000t_rx_status_not_ok = 0, 334169240Sjfv e1000_1000t_rx_status_ok, 335169240Sjfv e1000_1000t_rx_status_undefined = 0xFF 336181027Sjfv}; 337169240Sjfv 338181027Sjfvenum e1000_rev_polarity { 339169240Sjfv e1000_rev_polarity_normal = 0, 340169240Sjfv e1000_rev_polarity_reversed, 341169240Sjfv e1000_rev_polarity_undefined = 0xFF 342181027Sjfv}; 343169240Sjfv 344185353Sjfvenum e1000_fc_mode { 345169240Sjfv e1000_fc_none = 0, 346169240Sjfv e1000_fc_rx_pause, 347169240Sjfv e1000_fc_tx_pause, 348169240Sjfv e1000_fc_full, 349169240Sjfv e1000_fc_default = 0xFF 350181027Sjfv}; 351169240Sjfv 352181027Sjfvenum e1000_ffe_config { 353169240Sjfv e1000_ffe_config_enabled = 0, 354169240Sjfv e1000_ffe_config_active, 355169240Sjfv e1000_ffe_config_blocked 356181027Sjfv}; 357169240Sjfv 358181027Sjfvenum e1000_dsp_config { 359169240Sjfv e1000_dsp_config_disabled = 0, 360169240Sjfv e1000_dsp_config_enabled, 361169240Sjfv e1000_dsp_config_activated, 362169240Sjfv e1000_dsp_config_undefined = 0xFF 363181027Sjfv}; 364169240Sjfv 365185353Sjfvenum e1000_ms_type { 366185353Sjfv e1000_ms_hw_default = 0, 367185353Sjfv e1000_ms_force_master, 368185353Sjfv e1000_ms_force_slave, 369185353Sjfv e1000_ms_auto 370185353Sjfv}; 371185353Sjfv 372185353Sjfvenum e1000_smart_speed { 373185353Sjfv e1000_smart_speed_default = 0, 374185353Sjfv e1000_smart_speed_on, 375185353Sjfv e1000_smart_speed_off 376185353Sjfv}; 377185353Sjfv 378190872Sjfvenum e1000_serdes_link_state { 379190872Sjfv e1000_serdes_link_down = 0, 380190872Sjfv e1000_serdes_link_autoneg_progress, 381190872Sjfv e1000_serdes_link_autoneg_complete, 382190872Sjfv e1000_serdes_link_forced_up 383190872Sjfv}; 384190872Sjfv 385213234Sjfv#define __le16 u16 386213234Sjfv#define __le32 u32 387213234Sjfv#define __le64 u64 388169240Sjfv/* Receive Descriptor */ 389169240Sjfvstruct e1000_rx_desc { 390185353Sjfv __le64 buffer_addr; /* Address of the descriptor's data buffer */ 391185353Sjfv __le16 length; /* Length of data DMAed into data buffer */ 392228386Sjfv __le16 csum; /* Packet checksum */ 393228386Sjfv u8 status; /* Descriptor status */ 394228386Sjfv u8 errors; /* Descriptor Errors */ 395185353Sjfv __le16 special; 396169240Sjfv}; 397169240Sjfv 398169240Sjfv/* Receive Descriptor - Extended */ 399169240Sjfvunion e1000_rx_desc_extended { 400169240Sjfv struct { 401185353Sjfv __le64 buffer_addr; 402185353Sjfv __le64 reserved; 403169240Sjfv } read; 404169240Sjfv struct { 405169240Sjfv struct { 406228386Sjfv __le32 mrq; /* Multiple Rx Queues */ 407169240Sjfv union { 408228386Sjfv __le32 rss; /* RSS Hash */ 409169240Sjfv struct { 410185353Sjfv __le16 ip_id; /* IP id */ 411185353Sjfv __le16 csum; /* Packet Checksum */ 412169240Sjfv } csum_ip; 413169240Sjfv } hi_dword; 414169240Sjfv } lower; 415169240Sjfv struct { 416185353Sjfv __le32 status_error; /* ext status/error */ 417185353Sjfv __le16 length; 418228386Sjfv __le16 vlan; /* VLAN tag */ 419169240Sjfv } upper; 420169240Sjfv } wb; /* writeback */ 421169240Sjfv}; 422169240Sjfv 423169240Sjfv#define MAX_PS_BUFFERS 4 424256200Sjfv 425256200Sjfv/* Number of packet split data buffers (not including the header buffer) */ 426256200Sjfv#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 427256200Sjfv 428169240Sjfv/* Receive Descriptor - Packet Split */ 429169240Sjfvunion e1000_rx_desc_packet_split { 430169240Sjfv struct { 431169240Sjfv /* one buffer for protocol header(s), three data buffers */ 432185353Sjfv __le64 buffer_addr[MAX_PS_BUFFERS]; 433169240Sjfv } read; 434169240Sjfv struct { 435169240Sjfv struct { 436228386Sjfv __le32 mrq; /* Multiple Rx Queues */ 437169240Sjfv union { 438228386Sjfv __le32 rss; /* RSS Hash */ 439169240Sjfv struct { 440185353Sjfv __le16 ip_id; /* IP id */ 441185353Sjfv __le16 csum; /* Packet Checksum */ 442169240Sjfv } csum_ip; 443169240Sjfv } hi_dword; 444169240Sjfv } lower; 445169240Sjfv struct { 446185353Sjfv __le32 status_error; /* ext status/error */ 447228386Sjfv __le16 length0; /* length of buffer 0 */ 448228386Sjfv __le16 vlan; /* VLAN tag */ 449169240Sjfv } middle; 450169240Sjfv struct { 451185353Sjfv __le16 header_status; 452256200Sjfv /* length of buffers 1-3 */ 453256200Sjfv __le16 length[PS_PAGE_BUFFERS]; 454169240Sjfv } upper; 455185353Sjfv __le64 reserved; 456169240Sjfv } wb; /* writeback */ 457169240Sjfv}; 458169240Sjfv 459169240Sjfv/* Transmit Descriptor */ 460169240Sjfvstruct e1000_tx_desc { 461185353Sjfv __le64 buffer_addr; /* Address of the descriptor's data buffer */ 462169240Sjfv union { 463185353Sjfv __le32 data; 464169240Sjfv struct { 465228386Sjfv __le16 length; /* Data buffer length */ 466228386Sjfv u8 cso; /* Checksum offset */ 467228386Sjfv u8 cmd; /* Descriptor control */ 468169240Sjfv } flags; 469169240Sjfv } lower; 470169240Sjfv union { 471185353Sjfv __le32 data; 472169240Sjfv struct { 473228386Sjfv u8 status; /* Descriptor status */ 474228386Sjfv u8 css; /* Checksum start */ 475185353Sjfv __le16 special; 476169240Sjfv } fields; 477169240Sjfv } upper; 478169240Sjfv}; 479169240Sjfv 480169240Sjfv/* Offload Context Descriptor */ 481169240Sjfvstruct e1000_context_desc { 482169240Sjfv union { 483185353Sjfv __le32 ip_config; 484169240Sjfv struct { 485228386Sjfv u8 ipcss; /* IP checksum start */ 486228386Sjfv u8 ipcso; /* IP checksum offset */ 487228386Sjfv __le16 ipcse; /* IP checksum end */ 488169240Sjfv } ip_fields; 489169240Sjfv } lower_setup; 490169240Sjfv union { 491185353Sjfv __le32 tcp_config; 492169240Sjfv struct { 493228386Sjfv u8 tucss; /* TCP checksum start */ 494228386Sjfv u8 tucso; /* TCP checksum offset */ 495228386Sjfv __le16 tucse; /* TCP checksum end */ 496169240Sjfv } tcp_fields; 497169240Sjfv } upper_setup; 498185353Sjfv __le32 cmd_and_length; 499169240Sjfv union { 500185353Sjfv __le32 data; 501169240Sjfv struct { 502228386Sjfv u8 status; /* Descriptor status */ 503228386Sjfv u8 hdr_len; /* Header length */ 504228386Sjfv __le16 mss; /* Maximum segment size */ 505169240Sjfv } fields; 506169240Sjfv } tcp_seg_setup; 507169240Sjfv}; 508169240Sjfv 509169240Sjfv/* Offload data descriptor */ 510169240Sjfvstruct e1000_data_desc { 511228386Sjfv __le64 buffer_addr; /* Address of the descriptor's buffer address */ 512169240Sjfv union { 513185353Sjfv __le32 data; 514169240Sjfv struct { 515228386Sjfv __le16 length; /* Data buffer length */ 516169240Sjfv u8 typ_len_ext; 517169240Sjfv u8 cmd; 518169240Sjfv } flags; 519169240Sjfv } lower; 520169240Sjfv union { 521185353Sjfv __le32 data; 522169240Sjfv struct { 523228386Sjfv u8 status; /* Descriptor status */ 524228386Sjfv u8 popts; /* Packet Options */ 525185353Sjfv __le16 special; 526169240Sjfv } fields; 527169240Sjfv } upper; 528169240Sjfv}; 529169240Sjfv 530169240Sjfv/* Statistics counters collected by the MAC */ 531169240Sjfvstruct e1000_hw_stats { 532169240Sjfv u64 crcerrs; 533169240Sjfv u64 algnerrc; 534169240Sjfv u64 symerrs; 535169240Sjfv u64 rxerrc; 536169240Sjfv u64 mpc; 537169240Sjfv u64 scc; 538169240Sjfv u64 ecol; 539169240Sjfv u64 mcc; 540169240Sjfv u64 latecol; 541169240Sjfv u64 colc; 542169240Sjfv u64 dc; 543169240Sjfv u64 tncrs; 544169240Sjfv u64 sec; 545169240Sjfv u64 cexterr; 546169240Sjfv u64 rlec; 547169240Sjfv u64 xonrxc; 548169240Sjfv u64 xontxc; 549169240Sjfv u64 xoffrxc; 550169240Sjfv u64 xofftxc; 551169240Sjfv u64 fcruc; 552169240Sjfv u64 prc64; 553169240Sjfv u64 prc127; 554169240Sjfv u64 prc255; 555169240Sjfv u64 prc511; 556169240Sjfv u64 prc1023; 557169240Sjfv u64 prc1522; 558169240Sjfv u64 gprc; 559169240Sjfv u64 bprc; 560169240Sjfv u64 mprc; 561169240Sjfv u64 gptc; 562173788Sjfv u64 gorc; 563173788Sjfv u64 gotc; 564169240Sjfv u64 rnbc; 565169240Sjfv u64 ruc; 566169240Sjfv u64 rfc; 567169240Sjfv u64 roc; 568169240Sjfv u64 rjc; 569169240Sjfv u64 mgprc; 570169240Sjfv u64 mgpdc; 571169240Sjfv u64 mgptc; 572173788Sjfv u64 tor; 573173788Sjfv u64 tot; 574169240Sjfv u64 tpr; 575169240Sjfv u64 tpt; 576169240Sjfv u64 ptc64; 577169240Sjfv u64 ptc127; 578169240Sjfv u64 ptc255; 579169240Sjfv u64 ptc511; 580169240Sjfv u64 ptc1023; 581169240Sjfv u64 ptc1522; 582169240Sjfv u64 mptc; 583169240Sjfv u64 bptc; 584169240Sjfv u64 tsctc; 585169240Sjfv u64 tsctfc; 586169240Sjfv u64 iac; 587169240Sjfv u64 icrxptc; 588169240Sjfv u64 icrxatc; 589169240Sjfv u64 ictxptc; 590169240Sjfv u64 ictxatc; 591169240Sjfv u64 ictxqec; 592169240Sjfv u64 ictxqmtc; 593169240Sjfv u64 icrxdmtc; 594169240Sjfv u64 icrxoc; 595169240Sjfv u64 cbtmpc; 596169240Sjfv u64 htdpmc; 597169240Sjfv u64 cbrdpc; 598169240Sjfv u64 cbrmpc; 599169240Sjfv u64 rpthc; 600169240Sjfv u64 hgptc; 601169240Sjfv u64 htcbdpc; 602173788Sjfv u64 hgorc; 603173788Sjfv u64 hgotc; 604169240Sjfv u64 lenerrs; 605169240Sjfv u64 scvpc; 606169240Sjfv u64 hrmpc; 607185353Sjfv u64 doosync; 608228386Sjfv u64 o2bgptc; 609228386Sjfv u64 o2bspc; 610228386Sjfv u64 b2ospc; 611228386Sjfv u64 b2ogprc; 612169240Sjfv}; 613169240Sjfv 614209616Sjfvstruct e1000_vf_stats { 615209616Sjfv u64 base_gprc; 616209616Sjfv u64 base_gptc; 617209616Sjfv u64 base_gorc; 618209616Sjfv u64 base_gotc; 619209616Sjfv u64 base_mprc; 620209616Sjfv u64 base_gotlbc; 621209616Sjfv u64 base_gptlbc; 622209616Sjfv u64 base_gorlbc; 623209616Sjfv u64 base_gprlbc; 624185353Sjfv 625209616Sjfv u32 last_gprc; 626209616Sjfv u32 last_gptc; 627209616Sjfv u32 last_gorc; 628209616Sjfv u32 last_gotc; 629209616Sjfv u32 last_mprc; 630209616Sjfv u32 last_gotlbc; 631209616Sjfv u32 last_gptlbc; 632209616Sjfv u32 last_gorlbc; 633209616Sjfv u32 last_gprlbc; 634209616Sjfv 635209616Sjfv u64 gprc; 636209616Sjfv u64 gptc; 637209616Sjfv u64 gorc; 638209616Sjfv u64 gotc; 639209616Sjfv u64 mprc; 640209616Sjfv u64 gotlbc; 641209616Sjfv u64 gptlbc; 642209616Sjfv u64 gorlbc; 643209616Sjfv u64 gprlbc; 644209616Sjfv}; 645209616Sjfv 646169240Sjfvstruct e1000_phy_stats { 647169240Sjfv u32 idle_errors; 648169240Sjfv u32 receive_errors; 649169240Sjfv}; 650169240Sjfv 651169240Sjfvstruct e1000_host_mng_dhcp_cookie { 652169240Sjfv u32 signature; 653169240Sjfv u8 status; 654169240Sjfv u8 reserved0; 655169240Sjfv u16 vlan_id; 656169240Sjfv u32 reserved1; 657169240Sjfv u16 reserved2; 658169240Sjfv u8 reserved3; 659169240Sjfv u8 checksum; 660169240Sjfv}; 661169240Sjfv 662169240Sjfv/* Host Interface "Rev 1" */ 663169240Sjfvstruct e1000_host_command_header { 664169240Sjfv u8 command_id; 665169240Sjfv u8 command_length; 666169240Sjfv u8 command_options; 667169240Sjfv u8 checksum; 668169240Sjfv}; 669169240Sjfv 670228386Sjfv#define E1000_HI_MAX_DATA_LENGTH 252 671169240Sjfvstruct e1000_host_command_info { 672169240Sjfv struct e1000_host_command_header command_header; 673169240Sjfv u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 674169240Sjfv}; 675169240Sjfv 676169240Sjfv/* Host Interface "Rev 2" */ 677169240Sjfvstruct e1000_host_mng_command_header { 678169240Sjfv u8 command_id; 679169240Sjfv u8 checksum; 680169240Sjfv u16 reserved1; 681169240Sjfv u16 reserved2; 682169240Sjfv u16 command_length; 683169240Sjfv}; 684169240Sjfv 685228386Sjfv#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 686169240Sjfvstruct e1000_host_mng_command_info { 687169240Sjfv struct e1000_host_mng_command_header command_header; 688169240Sjfv u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 689169240Sjfv}; 690169240Sjfv 691169240Sjfv#include "e1000_mac.h" 692169240Sjfv#include "e1000_phy.h" 693169240Sjfv#include "e1000_nvm.h" 694169240Sjfv#include "e1000_manage.h" 695209616Sjfv#include "e1000_mbx.h" 696169240Sjfv 697247064Sjfv/* Function pointers for the MAC. */ 698177867Sjfvstruct e1000_mac_operations { 699177867Sjfv s32 (*init_params)(struct e1000_hw *); 700190872Sjfv s32 (*id_led_init)(struct e1000_hw *); 701173788Sjfv s32 (*blink_led)(struct e1000_hw *); 702247064Sjfv bool (*check_mng_mode)(struct e1000_hw *); 703173788Sjfv s32 (*check_for_link)(struct e1000_hw *); 704173788Sjfv s32 (*cleanup_led)(struct e1000_hw *); 705173788Sjfv void (*clear_hw_cntrs)(struct e1000_hw *); 706173788Sjfv void (*clear_vfta)(struct e1000_hw *); 707173788Sjfv s32 (*get_bus_info)(struct e1000_hw *); 708185353Sjfv void (*set_lan_id)(struct e1000_hw *); 709173788Sjfv s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 710173788Sjfv s32 (*led_on)(struct e1000_hw *); 711173788Sjfv s32 (*led_off)(struct e1000_hw *); 712190872Sjfv void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 713173788Sjfv s32 (*reset_hw)(struct e1000_hw *); 714173788Sjfv s32 (*init_hw)(struct e1000_hw *); 715181027Sjfv void (*shutdown_serdes)(struct e1000_hw *); 716203049Sjfv void (*power_up_serdes)(struct e1000_hw *); 717173788Sjfv s32 (*setup_link)(struct e1000_hw *); 718173788Sjfv s32 (*setup_physical_interface)(struct e1000_hw *); 719173788Sjfv s32 (*setup_led)(struct e1000_hw *); 720173788Sjfv void (*write_vfta)(struct e1000_hw *, u32, u32); 721185353Sjfv void (*config_collision_dist)(struct e1000_hw *); 722269196Sjfv int (*rar_set)(struct e1000_hw *, u8*, u32); 723185353Sjfv s32 (*read_mac_addr)(struct e1000_hw *); 724185353Sjfv s32 (*validate_mdi_setting)(struct e1000_hw *); 725247064Sjfv s32 (*set_obff_timer)(struct e1000_hw *, u32); 726238148Sjfv s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 727238148Sjfv void (*release_swfw_sync)(struct e1000_hw *, u16); 728177867Sjfv}; 729169240Sjfv 730247064Sjfv/* When to use various PHY register access functions: 731228386Sjfv * 732228386Sjfv * Func Caller 733228386Sjfv * Function Does Does When to use 734228386Sjfv * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 735228386Sjfv * X_reg L,P,A n/a for simple PHY reg accesses 736228386Sjfv * X_reg_locked P,A L for multiple accesses of different regs 737228386Sjfv * on different pages 738228386Sjfv * X_reg_page A L,P for multiple accesses of different regs 739228386Sjfv * on the same page 740228386Sjfv * 741228386Sjfv * Where X=[read|write], L=locking, P=sets page, A=register access 742228386Sjfv * 743228386Sjfv */ 744177867Sjfvstruct e1000_phy_operations { 745177867Sjfv s32 (*init_params)(struct e1000_hw *); 746177867Sjfv s32 (*acquire)(struct e1000_hw *); 747185353Sjfv s32 (*cfg_on_link_up)(struct e1000_hw *); 748173788Sjfv s32 (*check_polarity)(struct e1000_hw *); 749173788Sjfv s32 (*check_reset_block)(struct e1000_hw *); 750177867Sjfv s32 (*commit)(struct e1000_hw *); 751173788Sjfv s32 (*force_speed_duplex)(struct e1000_hw *); 752173788Sjfv s32 (*get_cfg_done)(struct e1000_hw *hw); 753173788Sjfv s32 (*get_cable_length)(struct e1000_hw *); 754177867Sjfv s32 (*get_info)(struct e1000_hw *); 755228386Sjfv s32 (*set_page)(struct e1000_hw *, u16); 756177867Sjfv s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 757200243Sjfv s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 758228386Sjfv s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 759177867Sjfv void (*release)(struct e1000_hw *); 760177867Sjfv s32 (*reset)(struct e1000_hw *); 761173788Sjfv s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 762173788Sjfv s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 763177867Sjfv s32 (*write_reg)(struct e1000_hw *, u32, u16); 764200243Sjfv s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 765228386Sjfv s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 766177867Sjfv void (*power_up)(struct e1000_hw *); 767177867Sjfv void (*power_down)(struct e1000_hw *); 768228386Sjfv s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 769228386Sjfv s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 770177867Sjfv}; 771169240Sjfv 772247064Sjfv/* Function pointers for the NVM. */ 773177867Sjfvstruct e1000_nvm_operations { 774177867Sjfv s32 (*init_params)(struct e1000_hw *); 775177867Sjfv s32 (*acquire)(struct e1000_hw *); 776177867Sjfv s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 777177867Sjfv void (*release)(struct e1000_hw *); 778177867Sjfv void (*reload)(struct e1000_hw *); 779177867Sjfv s32 (*update)(struct e1000_hw *); 780173788Sjfv s32 (*valid_led_default)(struct e1000_hw *, u16 *); 781177867Sjfv s32 (*validate)(struct e1000_hw *); 782177867Sjfv s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 783169240Sjfv}; 784169240Sjfv 785169240Sjfvstruct e1000_mac_info { 786177867Sjfv struct e1000_mac_operations ops; 787218530Sjfv u8 addr[ETH_ADDR_LEN]; 788218530Sjfv u8 perm_addr[ETH_ADDR_LEN]; 789169240Sjfv 790181027Sjfv enum e1000_mac_type type; 791169240Sjfv 792169240Sjfv u32 collision_delta; 793169240Sjfv u32 ledctl_default; 794169240Sjfv u32 ledctl_mode1; 795169240Sjfv u32 ledctl_mode2; 796169240Sjfv u32 mc_filter_type; 797169240Sjfv u32 tx_packet_delta; 798169240Sjfv u32 txcw; 799169240Sjfv 800169240Sjfv u16 current_ifs_val; 801169240Sjfv u16 ifs_max_val; 802169240Sjfv u16 ifs_min_val; 803169240Sjfv u16 ifs_ratio; 804169240Sjfv u16 ifs_step_size; 805169240Sjfv u16 mta_reg_count; 806200243Sjfv u16 uta_reg_count; 807194865Sjfv 808194865Sjfv /* Maximum size of the MTA register table in all supported adapters */ 809294958Smarius#define MAX_MTA_REG 128 810190872Sjfv u32 mta_shadow[MAX_MTA_REG]; 811169240Sjfv u16 rar_entry_count; 812169240Sjfv 813169240Sjfv u8 forced_speed_duplex; 814169240Sjfv 815173788Sjfv bool adaptive_ifs; 816205869Sjfv bool has_fwsm; 817173788Sjfv bool arc_subsystem_valid; 818173788Sjfv bool asf_firmware_present; 819173788Sjfv bool autoneg; 820173788Sjfv bool autoneg_failed; 821173788Sjfv bool get_link_status; 822173788Sjfv bool in_ifs_mode; 823173788Sjfv bool report_tx_early; 824190872Sjfv enum e1000_serdes_link_state serdes_link_state; 825173788Sjfv bool serdes_has_link; 826173788Sjfv bool tx_pkt_filtering; 827296055Serj u32 max_frame_size; 828169240Sjfv}; 829169240Sjfv 830169240Sjfvstruct e1000_phy_info { 831177867Sjfv struct e1000_phy_operations ops; 832181027Sjfv enum e1000_phy_type type; 833169240Sjfv 834181027Sjfv enum e1000_1000t_rx_status local_rx; 835181027Sjfv enum e1000_1000t_rx_status remote_rx; 836181027Sjfv enum e1000_ms_type ms_type; 837181027Sjfv enum e1000_ms_type original_ms_type; 838181027Sjfv enum e1000_rev_polarity cable_polarity; 839181027Sjfv enum e1000_smart_speed smart_speed; 840169240Sjfv 841169240Sjfv u32 addr; 842169240Sjfv u32 id; 843169240Sjfv u32 reset_delay_us; /* in usec */ 844169240Sjfv u32 revision; 845169240Sjfv 846181027Sjfv enum e1000_media_type media_type; 847173788Sjfv 848169240Sjfv u16 autoneg_advertised; 849169240Sjfv u16 autoneg_mask; 850169240Sjfv u16 cable_length; 851169240Sjfv u16 max_cable_length; 852169240Sjfv u16 min_cable_length; 853169240Sjfv 854169240Sjfv u8 mdix; 855169240Sjfv 856173788Sjfv bool disable_polarity_correction; 857173788Sjfv bool is_mdix; 858173788Sjfv bool polarity_correction; 859173788Sjfv bool speed_downgraded; 860173788Sjfv bool autoneg_wait_to_complete; 861169240Sjfv}; 862169240Sjfv 863169240Sjfvstruct e1000_nvm_info { 864177867Sjfv struct e1000_nvm_operations ops; 865181027Sjfv enum e1000_nvm_type type; 866181027Sjfv enum e1000_nvm_override override; 867169240Sjfv 868169240Sjfv u32 flash_bank_size; 869169240Sjfv u32 flash_base_addr; 870169240Sjfv 871169240Sjfv u16 word_size; 872169240Sjfv u16 delay_usec; 873169240Sjfv u16 address_bits; 874169240Sjfv u16 opcode_bits; 875169240Sjfv u16 page_size; 876169240Sjfv}; 877169240Sjfv 878169240Sjfvstruct e1000_bus_info { 879181027Sjfv enum e1000_bus_type type; 880181027Sjfv enum e1000_bus_speed speed; 881181027Sjfv enum e1000_bus_width width; 882169240Sjfv 883169240Sjfv u16 func; 884169240Sjfv u16 pci_cmd_word; 885169240Sjfv}; 886169240Sjfv 887173788Sjfvstruct e1000_fc_info { 888228386Sjfv u32 high_water; /* Flow control high-water mark */ 889228386Sjfv u32 low_water; /* Flow control low-water mark */ 890228386Sjfv u16 pause_time; /* Flow control pause timer */ 891228386Sjfv u16 refresh_time; /* Flow control refresh timer */ 892228386Sjfv bool send_xon; /* Flow control send XON */ 893228386Sjfv bool strict_ieee; /* Strict IEEE mode */ 894228386Sjfv enum e1000_fc_mode current_mode; /* FC mode in effect */ 895228386Sjfv enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 896173788Sjfv}; 897173788Sjfv 898213234Sjfvstruct e1000_mbx_operations { 899213234Sjfv s32 (*init_params)(struct e1000_hw *hw); 900213234Sjfv s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 901213234Sjfv s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 902213234Sjfv s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 903213234Sjfv s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 904213234Sjfv s32 (*check_for_msg)(struct e1000_hw *, u16); 905213234Sjfv s32 (*check_for_ack)(struct e1000_hw *, u16); 906213234Sjfv s32 (*check_for_rst)(struct e1000_hw *, u16); 907213234Sjfv}; 908213234Sjfv 909213234Sjfvstruct e1000_mbx_stats { 910213234Sjfv u32 msgs_tx; 911213234Sjfv u32 msgs_rx; 912213234Sjfv 913213234Sjfv u32 acks; 914213234Sjfv u32 reqs; 915213234Sjfv u32 rsts; 916213234Sjfv}; 917213234Sjfv 918213234Sjfvstruct e1000_mbx_info { 919213234Sjfv struct e1000_mbx_operations ops; 920213234Sjfv struct e1000_mbx_stats stats; 921213234Sjfv u32 timeout; 922213234Sjfv u32 usec_delay; 923213234Sjfv u16 size; 924213234Sjfv}; 925213234Sjfv 926185353Sjfvstruct e1000_dev_spec_82541 { 927185353Sjfv enum e1000_dsp_config dsp_config; 928185353Sjfv enum e1000_ffe_config ffe_config; 929185353Sjfv u16 spd_default; 930185353Sjfv bool phy_init_script; 931185353Sjfv}; 932185353Sjfv 933185353Sjfvstruct e1000_dev_spec_82542 { 934185353Sjfv bool dma_fairness; 935185353Sjfv}; 936185353Sjfv 937185353Sjfvstruct e1000_dev_spec_82543 { 938185353Sjfv u32 tbi_compatibility; 939185353Sjfv bool dma_fairness; 940185353Sjfv bool init_phy_disabled; 941185353Sjfv}; 942185353Sjfv 943185353Sjfvstruct e1000_dev_spec_82571 { 944185353Sjfv bool laa_is_present; 945194865Sjfv u32 smb_counter; 946213234Sjfv E1000_MUTEX swflag_mutex; 947185353Sjfv}; 948185353Sjfv 949200243Sjfvstruct e1000_dev_spec_80003es2lan { 950200243Sjfv bool mdic_wa_enable; 951200243Sjfv}; 952200243Sjfv 953185353Sjfvstruct e1000_shadow_ram { 954185353Sjfv u16 value; 955185353Sjfv bool modified; 956185353Sjfv}; 957185353Sjfv 958247064Sjfv#define E1000_SHADOW_RAM_WORDS 2048 959185353Sjfv 960269196Sjfv/* I218 PHY Ultra Low Power (ULP) states */ 961269196Sjfvenum e1000_ulp_state { 962269196Sjfv e1000_ulp_state_unknown, 963269196Sjfv e1000_ulp_state_off, 964269196Sjfv e1000_ulp_state_on, 965269196Sjfv}; 966269196Sjfv 967185353Sjfvstruct e1000_dev_spec_ich8lan { 968185353Sjfv bool kmrn_lock_loss_workaround_enabled; 969185353Sjfv struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 970200243Sjfv E1000_MUTEX nvm_mutex; 971200243Sjfv E1000_MUTEX swflag_mutex; 972200243Sjfv bool nvm_k1_enabled; 973304338Ssbruno bool disable_k1_off; 974238148Sjfv bool eee_disable; 975247064Sjfv u16 eee_lp_ability; 976269196Sjfv enum e1000_ulp_state ulp_state; 977304338Ssbruno bool ulp_capability_disabled; 978304338Ssbruno bool during_suspend_flow; 979304338Ssbruno bool during_dpg_exit; 980185353Sjfv}; 981185353Sjfv 982185353Sjfvstruct e1000_dev_spec_82575 { 983185353Sjfv bool sgmii_active; 984190872Sjfv bool global_device_reset; 985238148Sjfv bool eee_disable; 986228386Sjfv bool module_plugged; 987247064Sjfv bool clear_semaphore_once; 988228386Sjfv u32 mtu; 989247064Sjfv struct sfp_e1000_flags eth_flags; 990256200Sjfv u8 media_port; 991256200Sjfv bool media_changed; 992185353Sjfv}; 993185353Sjfv 994185353Sjfvstruct e1000_dev_spec_vf { 995218530Sjfv u32 vf_number; 996218530Sjfv u32 v2p_mailbox; 997185353Sjfv}; 998185353Sjfv 999169240Sjfvstruct e1000_hw { 1000169240Sjfv void *back; 1001169240Sjfv 1002169240Sjfv u8 *hw_addr; 1003169240Sjfv u8 *flash_address; 1004169240Sjfv unsigned long io_base; 1005169240Sjfv 1006169240Sjfv struct e1000_mac_info mac; 1007173788Sjfv struct e1000_fc_info fc; 1008169240Sjfv struct e1000_phy_info phy; 1009169240Sjfv struct e1000_nvm_info nvm; 1010169240Sjfv struct e1000_bus_info bus; 1011209616Sjfv struct e1000_mbx_info mbx; 1012169240Sjfv struct e1000_host_mng_dhcp_cookie mng_cookie; 1013169240Sjfv 1014185353Sjfv union { 1015218530Sjfv struct e1000_dev_spec_82541 _82541; 1016218530Sjfv struct e1000_dev_spec_82542 _82542; 1017218530Sjfv struct e1000_dev_spec_82543 _82543; 1018218530Sjfv struct e1000_dev_spec_82571 _82571; 1019200243Sjfv struct e1000_dev_spec_80003es2lan _80003es2lan; 1020218530Sjfv struct e1000_dev_spec_ich8lan ich8lan; 1021218530Sjfv struct e1000_dev_spec_82575 _82575; 1022218530Sjfv struct e1000_dev_spec_vf vf; 1023185353Sjfv } dev_spec; 1024169240Sjfv 1025169240Sjfv u16 device_id; 1026169240Sjfv u16 subsystem_vendor_id; 1027169240Sjfv u16 subsystem_device_id; 1028169240Sjfv u16 vendor_id; 1029169240Sjfv 1030169240Sjfv u8 revision_id; 1031169240Sjfv}; 1032169240Sjfv 1033181027Sjfv#include "e1000_82541.h" 1034181027Sjfv#include "e1000_82543.h" 1035181027Sjfv#include "e1000_82571.h" 1036181027Sjfv#include "e1000_80003es2lan.h" 1037181027Sjfv#include "e1000_ich8lan.h" 1038181027Sjfv#include "e1000_82575.h" 1039238148Sjfv#include "e1000_i210.h" 1040181027Sjfv 1041169240Sjfv/* These functions must be implemented by drivers */ 1042169240Sjfvvoid e1000_pci_clear_mwi(struct e1000_hw *hw); 1043169240Sjfvvoid e1000_pci_set_mwi(struct e1000_hw *hw); 1044169240Sjfvs32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1045194865Sjfvs32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1046169240Sjfvvoid e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1047169240Sjfvvoid e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1048169240Sjfv 1049169240Sjfv#endif 1050