1254885Sdumbbell/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 2254885Sdumbbell * 3254885Sdumbbell * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4254885Sdumbbell * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5254885Sdumbbell * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6254885Sdumbbell * All rights reserved. 7254885Sdumbbell * 8254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 9254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 10254885Sdumbbell * to deal in the Software without restriction, including without limitation 11254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 13254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 14254885Sdumbbell * 15254885Sdumbbell * The above copyright notice and this permission notice (including the next 16254885Sdumbbell * paragraph) shall be included in all copies or substantial portions of the 17254885Sdumbbell * Software. 18254885Sdumbbell * 19254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22254885Sdumbbell * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25254885Sdumbbell * DEALINGS IN THE SOFTWARE. 26254885Sdumbbell * 27254885Sdumbbell * Authors: 28254885Sdumbbell * Kevin E. Martin <martin@valinux.com> 29254885Sdumbbell * Gareth Hughes <gareth@valinux.com> 30254885Sdumbbell * Keith Whitwell <keith@tungstengraphics.com> 31254885Sdumbbell */ 32254885Sdumbbell 33254885Sdumbbell#include <sys/cdefs.h> 34254885Sdumbbell__FBSDID("$FreeBSD$"); 35254885Sdumbbell 36254885Sdumbbell#ifndef __RADEON_DRM_H__ 37254885Sdumbbell#define __RADEON_DRM_H__ 38254885Sdumbbell 39254885Sdumbbell#include <dev/drm2/drm.h> 40254885Sdumbbell 41254885Sdumbbell/* WARNING: If you change any of these defines, make sure to change the 42254885Sdumbbell * defines in the X server file (radeon_sarea.h) 43254885Sdumbbell */ 44254885Sdumbbell#ifndef __RADEON_SAREA_DEFINES__ 45254885Sdumbbell#define __RADEON_SAREA_DEFINES__ 46254885Sdumbbell 47254885Sdumbbell/* Old style state flags, required for sarea interface (1.1 and 1.2 48254885Sdumbbell * clears) and 1.2 drm_vertex2 ioctl. 49254885Sdumbbell */ 50254885Sdumbbell#define RADEON_UPLOAD_CONTEXT 0x00000001 51254885Sdumbbell#define RADEON_UPLOAD_VERTFMT 0x00000002 52254885Sdumbbell#define RADEON_UPLOAD_LINE 0x00000004 53254885Sdumbbell#define RADEON_UPLOAD_BUMPMAP 0x00000008 54254885Sdumbbell#define RADEON_UPLOAD_MASKS 0x00000010 55254885Sdumbbell#define RADEON_UPLOAD_VIEWPORT 0x00000020 56254885Sdumbbell#define RADEON_UPLOAD_SETUP 0x00000040 57254885Sdumbbell#define RADEON_UPLOAD_TCL 0x00000080 58254885Sdumbbell#define RADEON_UPLOAD_MISC 0x00000100 59254885Sdumbbell#define RADEON_UPLOAD_TEX0 0x00000200 60254885Sdumbbell#define RADEON_UPLOAD_TEX1 0x00000400 61254885Sdumbbell#define RADEON_UPLOAD_TEX2 0x00000800 62254885Sdumbbell#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 63254885Sdumbbell#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 64254885Sdumbbell#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 65254885Sdumbbell#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ 66254885Sdumbbell#define RADEON_REQUIRE_QUIESCENCE 0x00010000 67254885Sdumbbell#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ 68254885Sdumbbell#define RADEON_UPLOAD_ALL 0x003effff 69254885Sdumbbell#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 70254885Sdumbbell 71254885Sdumbbell/* New style per-packet identifiers for use in cmd_buffer ioctl with 72254885Sdumbbell * the RADEON_EMIT_PACKET command. Comments relate new packets to old 73254885Sdumbbell * state bits and the packet size: 74254885Sdumbbell */ 75254885Sdumbbell#define RADEON_EMIT_PP_MISC 0 /* context/7 */ 76254885Sdumbbell#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ 77254885Sdumbbell#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ 78254885Sdumbbell#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ 79254885Sdumbbell#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ 80254885Sdumbbell#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ 81254885Sdumbbell#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ 82254885Sdumbbell#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ 83254885Sdumbbell#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ 84254885Sdumbbell#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ 85254885Sdumbbell#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ 86254885Sdumbbell#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ 87254885Sdumbbell#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ 88254885Sdumbbell#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ 89254885Sdumbbell#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ 90254885Sdumbbell#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ 91254885Sdumbbell#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ 92254885Sdumbbell#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ 93254885Sdumbbell#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ 94254885Sdumbbell#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ 95254885Sdumbbell#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ 96254885Sdumbbell#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ 97254885Sdumbbell#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ 98254885Sdumbbell#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ 99254885Sdumbbell#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ 100254885Sdumbbell#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ 101254885Sdumbbell#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ 102254885Sdumbbell#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ 103254885Sdumbbell#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ 104254885Sdumbbell#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ 105254885Sdumbbell#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ 106254885Sdumbbell#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ 107254885Sdumbbell#define R200_EMIT_VAP_CTL 32 /* vap/1 */ 108254885Sdumbbell#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ 109254885Sdumbbell#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ 110254885Sdumbbell#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ 111254885Sdumbbell#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ 112254885Sdumbbell#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ 113254885Sdumbbell#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ 114254885Sdumbbell#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ 115254885Sdumbbell#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ 116254885Sdumbbell#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ 117254885Sdumbbell#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ 118254885Sdumbbell#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ 119254885Sdumbbell#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ 120254885Sdumbbell#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ 121254885Sdumbbell#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ 122254885Sdumbbell#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ 123254885Sdumbbell#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ 124254885Sdumbbell#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ 125254885Sdumbbell#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ 126254885Sdumbbell#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ 127254885Sdumbbell#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ 128254885Sdumbbell#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ 129254885Sdumbbell#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ 130254885Sdumbbell#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ 131254885Sdumbbell#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ 132254885Sdumbbell#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ 133254885Sdumbbell#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ 134254885Sdumbbell#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ 135254885Sdumbbell#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ 136254885Sdumbbell#define R200_EMIT_PP_CUBIC_FACES_0 61 137254885Sdumbbell#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 138254885Sdumbbell#define R200_EMIT_PP_CUBIC_FACES_1 63 139254885Sdumbbell#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 140254885Sdumbbell#define R200_EMIT_PP_CUBIC_FACES_2 65 141254885Sdumbbell#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 142254885Sdumbbell#define R200_EMIT_PP_CUBIC_FACES_3 67 143254885Sdumbbell#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 144254885Sdumbbell#define R200_EMIT_PP_CUBIC_FACES_4 69 145254885Sdumbbell#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 146254885Sdumbbell#define R200_EMIT_PP_CUBIC_FACES_5 71 147254885Sdumbbell#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 148254885Sdumbbell#define RADEON_EMIT_PP_TEX_SIZE_0 73 149254885Sdumbbell#define RADEON_EMIT_PP_TEX_SIZE_1 74 150254885Sdumbbell#define RADEON_EMIT_PP_TEX_SIZE_2 75 151254885Sdumbbell#define R200_EMIT_RB3D_BLENDCOLOR 76 152254885Sdumbbell#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 153254885Sdumbbell#define RADEON_EMIT_PP_CUBIC_FACES_0 78 154254885Sdumbbell#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 155254885Sdumbbell#define RADEON_EMIT_PP_CUBIC_FACES_1 80 156254885Sdumbbell#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 157254885Sdumbbell#define RADEON_EMIT_PP_CUBIC_FACES_2 82 158254885Sdumbbell#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 159254885Sdumbbell#define R200_EMIT_PP_TRI_PERF_CNTL 84 160254885Sdumbbell#define R200_EMIT_PP_AFS_0 85 161254885Sdumbbell#define R200_EMIT_PP_AFS_1 86 162254885Sdumbbell#define R200_EMIT_ATF_TFACTOR 87 163254885Sdumbbell#define R200_EMIT_PP_TXCTLALL_0 88 164254885Sdumbbell#define R200_EMIT_PP_TXCTLALL_1 89 165254885Sdumbbell#define R200_EMIT_PP_TXCTLALL_2 90 166254885Sdumbbell#define R200_EMIT_PP_TXCTLALL_3 91 167254885Sdumbbell#define R200_EMIT_PP_TXCTLALL_4 92 168254885Sdumbbell#define R200_EMIT_PP_TXCTLALL_5 93 169254885Sdumbbell#define R200_EMIT_VAP_PVS_CNTL 94 170254885Sdumbbell#define RADEON_MAX_STATE_PACKETS 95 171254885Sdumbbell 172254885Sdumbbell/* Commands understood by cmd_buffer ioctl. More can be added but 173254885Sdumbbell * obviously these can't be removed or changed: 174254885Sdumbbell */ 175254885Sdumbbell#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 176254885Sdumbbell#define RADEON_CMD_SCALARS 2 /* emit scalar data */ 177254885Sdumbbell#define RADEON_CMD_VECTORS 3 /* emit vector data */ 178254885Sdumbbell#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ 179254885Sdumbbell#define RADEON_CMD_PACKET3 5 /* emit hw packet */ 180254885Sdumbbell#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ 181254885Sdumbbell#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ 182254885Sdumbbell#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: 183254885Sdumbbell * doesn't make the cpu wait, just 184254885Sdumbbell * the graphics hardware */ 185254885Sdumbbell#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ 186254885Sdumbbell 187254885Sdumbbelltypedef union { 188254885Sdumbbell int i; 189254885Sdumbbell struct { 190254885Sdumbbell unsigned char cmd_type, pad0, pad1, pad2; 191254885Sdumbbell } header; 192254885Sdumbbell struct { 193254885Sdumbbell unsigned char cmd_type, packet_id, pad0, pad1; 194254885Sdumbbell } packet; 195254885Sdumbbell struct { 196254885Sdumbbell unsigned char cmd_type, offset, stride, count; 197254885Sdumbbell } scalars; 198254885Sdumbbell struct { 199254885Sdumbbell unsigned char cmd_type, offset, stride, count; 200254885Sdumbbell } vectors; 201254885Sdumbbell struct { 202254885Sdumbbell unsigned char cmd_type, addr_lo, addr_hi, count; 203254885Sdumbbell } veclinear; 204254885Sdumbbell struct { 205254885Sdumbbell unsigned char cmd_type, buf_idx, pad0, pad1; 206254885Sdumbbell } dma; 207254885Sdumbbell struct { 208254885Sdumbbell unsigned char cmd_type, flags, pad0, pad1; 209254885Sdumbbell } wait; 210254885Sdumbbell} drm_radeon_cmd_header_t; 211254885Sdumbbell 212254885Sdumbbell#define RADEON_WAIT_2D 0x1 213254885Sdumbbell#define RADEON_WAIT_3D 0x2 214254885Sdumbbell 215254885Sdumbbell/* Allowed parameters for R300_CMD_PACKET3 216254885Sdumbbell */ 217254885Sdumbbell#define R300_CMD_PACKET3_CLEAR 0 218254885Sdumbbell#define R300_CMD_PACKET3_RAW 1 219254885Sdumbbell 220254885Sdumbbell/* Commands understood by cmd_buffer ioctl for R300. 221254885Sdumbbell * The interface has not been stabilized, so some of these may be removed 222254885Sdumbbell * and eventually reordered before stabilization. 223254885Sdumbbell */ 224254885Sdumbbell#define R300_CMD_PACKET0 1 225254885Sdumbbell#define R300_CMD_VPU 2 /* emit vertex program upload */ 226254885Sdumbbell#define R300_CMD_PACKET3 3 /* emit a packet3 */ 227254885Sdumbbell#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ 228254885Sdumbbell#define R300_CMD_CP_DELAY 5 229254885Sdumbbell#define R300_CMD_DMA_DISCARD 6 230254885Sdumbbell#define R300_CMD_WAIT 7 231254885Sdumbbell# define R300_WAIT_2D 0x1 232254885Sdumbbell# define R300_WAIT_3D 0x2 233254885Sdumbbell/* these two defines are DOING IT WRONG - however 234254885Sdumbbell * we have userspace which relies on using these. 235254885Sdumbbell * The wait interface is backwards compat new 236254885Sdumbbell * code should use the NEW_WAIT defines below 237254885Sdumbbell * THESE ARE NOT BIT FIELDS 238254885Sdumbbell */ 239254885Sdumbbell# define R300_WAIT_2D_CLEAN 0x3 240254885Sdumbbell# define R300_WAIT_3D_CLEAN 0x4 241254885Sdumbbell 242254885Sdumbbell# define R300_NEW_WAIT_2D_3D 0x3 243254885Sdumbbell# define R300_NEW_WAIT_2D_2D_CLEAN 0x4 244254885Sdumbbell# define R300_NEW_WAIT_3D_3D_CLEAN 0x6 245254885Sdumbbell# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 246254885Sdumbbell 247254885Sdumbbell#define R300_CMD_SCRATCH 8 248254885Sdumbbell#define R300_CMD_R500FP 9 249254885Sdumbbell 250254885Sdumbbelltypedef union { 251254885Sdumbbell unsigned int u; 252254885Sdumbbell struct { 253254885Sdumbbell unsigned char cmd_type, pad0, pad1, pad2; 254254885Sdumbbell } header; 255254885Sdumbbell struct { 256254885Sdumbbell unsigned char cmd_type, count, reglo, reghi; 257254885Sdumbbell } packet0; 258254885Sdumbbell struct { 259254885Sdumbbell unsigned char cmd_type, count, adrlo, adrhi; 260254885Sdumbbell } vpu; 261254885Sdumbbell struct { 262254885Sdumbbell unsigned char cmd_type, packet, pad0, pad1; 263254885Sdumbbell } packet3; 264254885Sdumbbell struct { 265254885Sdumbbell unsigned char cmd_type, packet; 266254885Sdumbbell unsigned short count; /* amount of packet2 to emit */ 267254885Sdumbbell } delay; 268254885Sdumbbell struct { 269254885Sdumbbell unsigned char cmd_type, buf_idx, pad0, pad1; 270254885Sdumbbell } dma; 271254885Sdumbbell struct { 272254885Sdumbbell unsigned char cmd_type, flags, pad0, pad1; 273254885Sdumbbell } wait; 274254885Sdumbbell struct { 275254885Sdumbbell unsigned char cmd_type, reg, n_bufs, flags; 276254885Sdumbbell } scratch; 277254885Sdumbbell struct { 278254885Sdumbbell unsigned char cmd_type, count, adrlo, adrhi_flags; 279254885Sdumbbell } r500fp; 280254885Sdumbbell} drm_r300_cmd_header_t; 281254885Sdumbbell 282254885Sdumbbell#define RADEON_FRONT 0x1 283254885Sdumbbell#define RADEON_BACK 0x2 284254885Sdumbbell#define RADEON_DEPTH 0x4 285254885Sdumbbell#define RADEON_STENCIL 0x8 286254885Sdumbbell#define RADEON_CLEAR_FASTZ 0x80000000 287254885Sdumbbell#define RADEON_USE_HIERZ 0x40000000 288254885Sdumbbell#define RADEON_USE_COMP_ZBUF 0x20000000 289254885Sdumbbell 290254885Sdumbbell#define R500FP_CONSTANT_TYPE (1 << 1) 291254885Sdumbbell#define R500FP_CONSTANT_CLAMP (1 << 2) 292254885Sdumbbell 293254885Sdumbbell/* Primitive types 294254885Sdumbbell */ 295254885Sdumbbell#define RADEON_POINTS 0x1 296254885Sdumbbell#define RADEON_LINES 0x2 297254885Sdumbbell#define RADEON_LINE_STRIP 0x3 298254885Sdumbbell#define RADEON_TRIANGLES 0x4 299254885Sdumbbell#define RADEON_TRIANGLE_FAN 0x5 300254885Sdumbbell#define RADEON_TRIANGLE_STRIP 0x6 301254885Sdumbbell 302254885Sdumbbell/* Vertex/indirect buffer size 303254885Sdumbbell */ 304254885Sdumbbell#define RADEON_BUFFER_SIZE 65536 305254885Sdumbbell 306254885Sdumbbell/* Byte offsets for indirect buffer data 307254885Sdumbbell */ 308254885Sdumbbell#define RADEON_INDEX_PRIM_OFFSET 20 309254885Sdumbbell 310254885Sdumbbell#define RADEON_SCRATCH_REG_OFFSET 32 311254885Sdumbbell 312254885Sdumbbell#define R600_SCRATCH_REG_OFFSET 256 313254885Sdumbbell 314254885Sdumbbell#define RADEON_NR_SAREA_CLIPRECTS 12 315254885Sdumbbell 316254885Sdumbbell/* There are 2 heaps (local/GART). Each region within a heap is a 317254885Sdumbbell * minimum of 64k, and there are at most 64 of them per heap. 318254885Sdumbbell */ 319254885Sdumbbell#define RADEON_LOCAL_TEX_HEAP 0 320254885Sdumbbell#define RADEON_GART_TEX_HEAP 1 321254885Sdumbbell#define RADEON_NR_TEX_HEAPS 2 322254885Sdumbbell#define RADEON_NR_TEX_REGIONS 64 323254885Sdumbbell#define RADEON_LOG_TEX_GRANULARITY 16 324254885Sdumbbell 325254885Sdumbbell#define RADEON_MAX_TEXTURE_LEVELS 12 326254885Sdumbbell#define RADEON_MAX_TEXTURE_UNITS 3 327254885Sdumbbell 328254885Sdumbbell#define RADEON_MAX_SURFACES 8 329254885Sdumbbell 330254885Sdumbbell/* Blits have strict offset rules. All blit offset must be aligned on 331254885Sdumbbell * a 1K-byte boundary. 332254885Sdumbbell */ 333254885Sdumbbell#define RADEON_OFFSET_SHIFT 10 334254885Sdumbbell#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 335254885Sdumbbell#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 336254885Sdumbbell 337254885Sdumbbell#endif /* __RADEON_SAREA_DEFINES__ */ 338254885Sdumbbell 339254885Sdumbbelltypedef struct { 340254885Sdumbbell unsigned int red; 341254885Sdumbbell unsigned int green; 342254885Sdumbbell unsigned int blue; 343254885Sdumbbell unsigned int alpha; 344254885Sdumbbell} radeon_color_regs_t; 345254885Sdumbbell 346254885Sdumbbelltypedef struct { 347254885Sdumbbell /* Context state */ 348254885Sdumbbell unsigned int pp_misc; /* 0x1c14 */ 349254885Sdumbbell unsigned int pp_fog_color; 350254885Sdumbbell unsigned int re_solid_color; 351254885Sdumbbell unsigned int rb3d_blendcntl; 352254885Sdumbbell unsigned int rb3d_depthoffset; 353254885Sdumbbell unsigned int rb3d_depthpitch; 354254885Sdumbbell unsigned int rb3d_zstencilcntl; 355254885Sdumbbell 356254885Sdumbbell unsigned int pp_cntl; /* 0x1c38 */ 357254885Sdumbbell unsigned int rb3d_cntl; 358254885Sdumbbell unsigned int rb3d_coloroffset; 359254885Sdumbbell unsigned int re_width_height; 360254885Sdumbbell unsigned int rb3d_colorpitch; 361254885Sdumbbell unsigned int se_cntl; 362254885Sdumbbell 363254885Sdumbbell /* Vertex format state */ 364254885Sdumbbell unsigned int se_coord_fmt; /* 0x1c50 */ 365254885Sdumbbell 366254885Sdumbbell /* Line state */ 367254885Sdumbbell unsigned int re_line_pattern; /* 0x1cd0 */ 368254885Sdumbbell unsigned int re_line_state; 369254885Sdumbbell 370254885Sdumbbell unsigned int se_line_width; /* 0x1db8 */ 371254885Sdumbbell 372254885Sdumbbell /* Bumpmap state */ 373254885Sdumbbell unsigned int pp_lum_matrix; /* 0x1d00 */ 374254885Sdumbbell 375254885Sdumbbell unsigned int pp_rot_matrix_0; /* 0x1d58 */ 376254885Sdumbbell unsigned int pp_rot_matrix_1; 377254885Sdumbbell 378254885Sdumbbell /* Mask state */ 379254885Sdumbbell unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 380254885Sdumbbell unsigned int rb3d_ropcntl; 381254885Sdumbbell unsigned int rb3d_planemask; 382254885Sdumbbell 383254885Sdumbbell /* Viewport state */ 384254885Sdumbbell unsigned int se_vport_xscale; /* 0x1d98 */ 385254885Sdumbbell unsigned int se_vport_xoffset; 386254885Sdumbbell unsigned int se_vport_yscale; 387254885Sdumbbell unsigned int se_vport_yoffset; 388254885Sdumbbell unsigned int se_vport_zscale; 389254885Sdumbbell unsigned int se_vport_zoffset; 390254885Sdumbbell 391254885Sdumbbell /* Setup state */ 392254885Sdumbbell unsigned int se_cntl_status; /* 0x2140 */ 393254885Sdumbbell 394254885Sdumbbell /* Misc state */ 395254885Sdumbbell unsigned int re_top_left; /* 0x26c0 */ 396254885Sdumbbell unsigned int re_misc; 397254885Sdumbbell} drm_radeon_context_regs_t; 398254885Sdumbbell 399254885Sdumbbelltypedef struct { 400254885Sdumbbell /* Zbias state */ 401254885Sdumbbell unsigned int se_zbias_factor; /* 0x1dac */ 402254885Sdumbbell unsigned int se_zbias_constant; 403254885Sdumbbell} drm_radeon_context2_regs_t; 404254885Sdumbbell 405254885Sdumbbell/* Setup registers for each texture unit 406254885Sdumbbell */ 407254885Sdumbbelltypedef struct { 408254885Sdumbbell unsigned int pp_txfilter; 409254885Sdumbbell unsigned int pp_txformat; 410254885Sdumbbell unsigned int pp_txoffset; 411254885Sdumbbell unsigned int pp_txcblend; 412254885Sdumbbell unsigned int pp_txablend; 413254885Sdumbbell unsigned int pp_tfactor; 414254885Sdumbbell unsigned int pp_border_color; 415254885Sdumbbell} drm_radeon_texture_regs_t; 416254885Sdumbbell 417254885Sdumbbelltypedef struct { 418254885Sdumbbell unsigned int start; 419254885Sdumbbell unsigned int finish; 420254885Sdumbbell unsigned int prim:8; 421254885Sdumbbell unsigned int stateidx:8; 422254885Sdumbbell unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ 423254885Sdumbbell unsigned int vc_format; /* vertex format */ 424254885Sdumbbell} drm_radeon_prim_t; 425254885Sdumbbell 426254885Sdumbbelltypedef struct { 427254885Sdumbbell drm_radeon_context_regs_t context; 428254885Sdumbbell drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 429254885Sdumbbell drm_radeon_context2_regs_t context2; 430254885Sdumbbell unsigned int dirty; 431254885Sdumbbell} drm_radeon_state_t; 432254885Sdumbbell 433254885Sdumbbelltypedef struct { 434254885Sdumbbell /* The channel for communication of state information to the 435254885Sdumbbell * kernel on firing a vertex buffer with either of the 436254885Sdumbbell * obsoleted vertex/index ioctls. 437254885Sdumbbell */ 438254885Sdumbbell drm_radeon_context_regs_t context_state; 439254885Sdumbbell drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 440254885Sdumbbell unsigned int dirty; 441254885Sdumbbell unsigned int vertsize; 442254885Sdumbbell unsigned int vc_format; 443254885Sdumbbell 444254885Sdumbbell /* The current cliprects, or a subset thereof. 445254885Sdumbbell */ 446254885Sdumbbell struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 447254885Sdumbbell unsigned int nbox; 448254885Sdumbbell 449254885Sdumbbell /* Counters for client-side throttling of rendering clients. 450254885Sdumbbell */ 451254885Sdumbbell unsigned int last_frame; 452254885Sdumbbell unsigned int last_dispatch; 453254885Sdumbbell unsigned int last_clear; 454254885Sdumbbell 455254885Sdumbbell struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 456254885Sdumbbell 1]; 457254885Sdumbbell unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 458254885Sdumbbell int ctx_owner; 459254885Sdumbbell int pfState; /* number of 3d windows (0,1,2ormore) */ 460254885Sdumbbell int pfCurrentPage; /* which buffer is being displayed? */ 461254885Sdumbbell int crtc2_base; /* CRTC2 frame offset */ 462254885Sdumbbell int tiling_enabled; /* set by drm, read by 2d + 3d clients */ 463254885Sdumbbell} drm_radeon_sarea_t; 464254885Sdumbbell 465254885Sdumbbell/* WARNING: If you change any of these defines, make sure to change the 466254885Sdumbbell * defines in the Xserver file (xf86drmRadeon.h) 467254885Sdumbbell * 468254885Sdumbbell * KW: actually it's illegal to change any of this (backwards compatibility). 469254885Sdumbbell */ 470254885Sdumbbell 471254885Sdumbbell/* Radeon specific ioctls 472254885Sdumbbell * The device specific ioctl range is 0x40 to 0x79. 473254885Sdumbbell */ 474254885Sdumbbell#define DRM_RADEON_CP_INIT 0x00 475254885Sdumbbell#define DRM_RADEON_CP_START 0x01 476254885Sdumbbell#define DRM_RADEON_CP_STOP 0x02 477254885Sdumbbell#define DRM_RADEON_CP_RESET 0x03 478254885Sdumbbell#define DRM_RADEON_CP_IDLE 0x04 479254885Sdumbbell#define DRM_RADEON_RESET 0x05 480254885Sdumbbell#define DRM_RADEON_FULLSCREEN 0x06 481254885Sdumbbell#define DRM_RADEON_SWAP 0x07 482254885Sdumbbell#define DRM_RADEON_CLEAR 0x08 483254885Sdumbbell#define DRM_RADEON_VERTEX 0x09 484254885Sdumbbell#define DRM_RADEON_INDICES 0x0A 485254885Sdumbbell#define DRM_RADEON_NOT_USED 486254885Sdumbbell#define DRM_RADEON_STIPPLE 0x0C 487254885Sdumbbell#define DRM_RADEON_INDIRECT 0x0D 488254885Sdumbbell#define DRM_RADEON_TEXTURE 0x0E 489254885Sdumbbell#define DRM_RADEON_VERTEX2 0x0F 490254885Sdumbbell#define DRM_RADEON_CMDBUF 0x10 491254885Sdumbbell#define DRM_RADEON_GETPARAM 0x11 492254885Sdumbbell#define DRM_RADEON_FLIP 0x12 493254885Sdumbbell#define DRM_RADEON_ALLOC 0x13 494254885Sdumbbell#define DRM_RADEON_FREE 0x14 495254885Sdumbbell#define DRM_RADEON_INIT_HEAP 0x15 496254885Sdumbbell#define DRM_RADEON_IRQ_EMIT 0x16 497254885Sdumbbell#define DRM_RADEON_IRQ_WAIT 0x17 498254885Sdumbbell#define DRM_RADEON_CP_RESUME 0x18 499254885Sdumbbell#define DRM_RADEON_SETPARAM 0x19 500254885Sdumbbell#define DRM_RADEON_SURF_ALLOC 0x1a 501254885Sdumbbell#define DRM_RADEON_SURF_FREE 0x1b 502254885Sdumbbell/* KMS ioctl */ 503254885Sdumbbell#define DRM_RADEON_GEM_INFO 0x1c 504254885Sdumbbell#define DRM_RADEON_GEM_CREATE 0x1d 505254885Sdumbbell#define DRM_RADEON_GEM_MMAP 0x1e 506254885Sdumbbell#define DRM_RADEON_GEM_PREAD 0x21 507254885Sdumbbell#define DRM_RADEON_GEM_PWRITE 0x22 508254885Sdumbbell#define DRM_RADEON_GEM_SET_DOMAIN 0x23 509254885Sdumbbell#define DRM_RADEON_GEM_WAIT_IDLE 0x24 510254885Sdumbbell#define DRM_RADEON_CS 0x26 511254885Sdumbbell#define DRM_RADEON_INFO 0x27 512254885Sdumbbell#define DRM_RADEON_GEM_SET_TILING 0x28 513254885Sdumbbell#define DRM_RADEON_GEM_GET_TILING 0x29 514254885Sdumbbell#define DRM_RADEON_GEM_BUSY 0x2a 515254885Sdumbbell#define DRM_RADEON_GEM_VA 0x2b 516254885Sdumbbell 517254885Sdumbbell#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 518254885Sdumbbell#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 519254885Sdumbbell#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 520254885Sdumbbell#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 521254885Sdumbbell#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 522254885Sdumbbell#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) 523254885Sdumbbell#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 524254885Sdumbbell#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) 525254885Sdumbbell#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 526254885Sdumbbell#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 527254885Sdumbbell#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 528254885Sdumbbell#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 529254885Sdumbbell#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 530254885Sdumbbell#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 531254885Sdumbbell#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 532254885Sdumbbell#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 533254885Sdumbbell#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 534254885Sdumbbell#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) 535254885Sdumbbell#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 536254885Sdumbbell#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 537254885Sdumbbell#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 538254885Sdumbbell#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 539254885Sdumbbell#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 540254885Sdumbbell#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 541254885Sdumbbell#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 542254885Sdumbbell#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 543254885Sdumbbell#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 544254885Sdumbbell/* KMS */ 545254885Sdumbbell#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 546254885Sdumbbell#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 547254885Sdumbbell#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 548254885Sdumbbell#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 549254885Sdumbbell#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 550254885Sdumbbell#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 551254885Sdumbbell#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 552254885Sdumbbell#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 553254885Sdumbbell#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 554254885Sdumbbell#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 555254885Sdumbbell#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 556254885Sdumbbell#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 557254885Sdumbbell#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) 558254885Sdumbbell 559254885Sdumbbelltypedef struct drm_radeon_init { 560254885Sdumbbell enum { 561254885Sdumbbell RADEON_INIT_CP = 0x01, 562254885Sdumbbell RADEON_CLEANUP_CP = 0x02, 563254885Sdumbbell RADEON_INIT_R200_CP = 0x03, 564254885Sdumbbell RADEON_INIT_R300_CP = 0x04, 565254885Sdumbbell RADEON_INIT_R600_CP = 0x05 566254885Sdumbbell } func; 567254885Sdumbbell unsigned long sarea_priv_offset; 568254885Sdumbbell int is_pci; 569254885Sdumbbell int cp_mode; 570254885Sdumbbell int gart_size; 571254885Sdumbbell int ring_size; 572254885Sdumbbell int usec_timeout; 573254885Sdumbbell 574254885Sdumbbell unsigned int fb_bpp; 575254885Sdumbbell unsigned int front_offset, front_pitch; 576254885Sdumbbell unsigned int back_offset, back_pitch; 577254885Sdumbbell unsigned int depth_bpp; 578254885Sdumbbell unsigned int depth_offset, depth_pitch; 579254885Sdumbbell 580254885Sdumbbell unsigned long fb_offset; 581254885Sdumbbell unsigned long mmio_offset; 582254885Sdumbbell unsigned long ring_offset; 583254885Sdumbbell unsigned long ring_rptr_offset; 584254885Sdumbbell unsigned long buffers_offset; 585254885Sdumbbell unsigned long gart_textures_offset; 586254885Sdumbbell} drm_radeon_init_t; 587254885Sdumbbell 588254885Sdumbbelltypedef struct drm_radeon_cp_stop { 589254885Sdumbbell int flush; 590254885Sdumbbell int idle; 591254885Sdumbbell} drm_radeon_cp_stop_t; 592254885Sdumbbell 593254885Sdumbbelltypedef struct drm_radeon_fullscreen { 594254885Sdumbbell enum { 595254885Sdumbbell RADEON_INIT_FULLSCREEN = 0x01, 596254885Sdumbbell RADEON_CLEANUP_FULLSCREEN = 0x02 597254885Sdumbbell } func; 598254885Sdumbbell} drm_radeon_fullscreen_t; 599254885Sdumbbell 600254885Sdumbbell#define CLEAR_X1 0 601254885Sdumbbell#define CLEAR_Y1 1 602254885Sdumbbell#define CLEAR_X2 2 603254885Sdumbbell#define CLEAR_Y2 3 604254885Sdumbbell#define CLEAR_DEPTH 4 605254885Sdumbbell 606254885Sdumbbelltypedef union drm_radeon_clear_rect { 607254885Sdumbbell float f[5]; 608254885Sdumbbell unsigned int ui[5]; 609254885Sdumbbell} drm_radeon_clear_rect_t; 610254885Sdumbbell 611254885Sdumbbelltypedef struct drm_radeon_clear { 612254885Sdumbbell unsigned int flags; 613254885Sdumbbell unsigned int clear_color; 614254885Sdumbbell unsigned int clear_depth; 615254885Sdumbbell unsigned int color_mask; 616254885Sdumbbell unsigned int depth_mask; /* misnamed field: should be stencil */ 617254885Sdumbbell drm_radeon_clear_rect_t __user *depth_boxes; 618254885Sdumbbell} drm_radeon_clear_t; 619254885Sdumbbell 620254885Sdumbbelltypedef struct drm_radeon_vertex { 621254885Sdumbbell int prim; 622254885Sdumbbell int idx; /* Index of vertex buffer */ 623254885Sdumbbell int count; /* Number of vertices in buffer */ 624254885Sdumbbell int discard; /* Client finished with buffer? */ 625254885Sdumbbell} drm_radeon_vertex_t; 626254885Sdumbbell 627254885Sdumbbelltypedef struct drm_radeon_indices { 628254885Sdumbbell int prim; 629254885Sdumbbell int idx; 630254885Sdumbbell int start; 631254885Sdumbbell int end; 632254885Sdumbbell int discard; /* Client finished with buffer? */ 633254885Sdumbbell} drm_radeon_indices_t; 634254885Sdumbbell 635254885Sdumbbell/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices 636254885Sdumbbell * - allows multiple primitives and state changes in a single ioctl 637254885Sdumbbell * - supports driver change to emit native primitives 638254885Sdumbbell */ 639254885Sdumbbelltypedef struct drm_radeon_vertex2 { 640254885Sdumbbell int idx; /* Index of vertex buffer */ 641254885Sdumbbell int discard; /* Client finished with buffer? */ 642254885Sdumbbell int nr_states; 643254885Sdumbbell drm_radeon_state_t __user *state; 644254885Sdumbbell int nr_prims; 645254885Sdumbbell drm_radeon_prim_t __user *prim; 646254885Sdumbbell} drm_radeon_vertex2_t; 647254885Sdumbbell 648254885Sdumbbell/* v1.3 - obsoletes drm_radeon_vertex2 649254885Sdumbbell * - allows arbitrarily large cliprect list 650254885Sdumbbell * - allows updating of tcl packet, vector and scalar state 651254885Sdumbbell * - allows memory-efficient description of state updates 652254885Sdumbbell * - allows state to be emitted without a primitive 653254885Sdumbbell * (for clears, ctx switches) 654254885Sdumbbell * - allows more than one dma buffer to be referenced per ioctl 655254885Sdumbbell * - supports tcl driver 656254885Sdumbbell * - may be extended in future versions with new cmd types, packets 657254885Sdumbbell */ 658254885Sdumbbelltypedef struct drm_radeon_cmd_buffer { 659254885Sdumbbell int bufsz; 660254885Sdumbbell char __user *buf; 661254885Sdumbbell int nbox; 662254885Sdumbbell struct drm_clip_rect __user *boxes; 663254885Sdumbbell} drm_radeon_cmd_buffer_t; 664254885Sdumbbell 665254885Sdumbbelltypedef struct drm_radeon_tex_image { 666254885Sdumbbell unsigned int x, y; /* Blit coordinates */ 667254885Sdumbbell unsigned int width, height; 668254885Sdumbbell const void __user *data; 669254885Sdumbbell} drm_radeon_tex_image_t; 670254885Sdumbbell 671254885Sdumbbelltypedef struct drm_radeon_texture { 672254885Sdumbbell unsigned int offset; 673254885Sdumbbell int pitch; 674254885Sdumbbell int format; 675254885Sdumbbell int width; /* Texture image coordinates */ 676254885Sdumbbell int height; 677254885Sdumbbell drm_radeon_tex_image_t __user *image; 678254885Sdumbbell} drm_radeon_texture_t; 679254885Sdumbbell 680254885Sdumbbelltypedef struct drm_radeon_stipple { 681254885Sdumbbell unsigned int __user *mask; 682254885Sdumbbell} drm_radeon_stipple_t; 683254885Sdumbbell 684254885Sdumbbelltypedef struct drm_radeon_indirect { 685254885Sdumbbell int idx; 686254885Sdumbbell int start; 687254885Sdumbbell int end; 688254885Sdumbbell int discard; 689254885Sdumbbell} drm_radeon_indirect_t; 690254885Sdumbbell 691254885Sdumbbell/* enum for card type parameters */ 692254885Sdumbbell#define RADEON_CARD_PCI 0 693254885Sdumbbell#define RADEON_CARD_AGP 1 694254885Sdumbbell#define RADEON_CARD_PCIE 2 695254885Sdumbbell 696254885Sdumbbell/* 1.3: An ioctl to get parameters that aren't available to the 3d 697254885Sdumbbell * client any other way. 698254885Sdumbbell */ 699254885Sdumbbell#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ 700254885Sdumbbell#define RADEON_PARAM_LAST_FRAME 2 701254885Sdumbbell#define RADEON_PARAM_LAST_DISPATCH 3 702254885Sdumbbell#define RADEON_PARAM_LAST_CLEAR 4 703254885Sdumbbell/* Added with DRM version 1.6. */ 704254885Sdumbbell#define RADEON_PARAM_IRQ_NR 5 705254885Sdumbbell#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ 706254885Sdumbbell/* Added with DRM version 1.8. */ 707254885Sdumbbell#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 708254885Sdumbbell#define RADEON_PARAM_STATUS_HANDLE 8 709254885Sdumbbell#define RADEON_PARAM_SAREA_HANDLE 9 710254885Sdumbbell#define RADEON_PARAM_GART_TEX_HANDLE 10 711254885Sdumbbell#define RADEON_PARAM_SCRATCH_OFFSET 11 712254885Sdumbbell#define RADEON_PARAM_CARD_TYPE 12 713254885Sdumbbell#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 714254885Sdumbbell#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 715254885Sdumbbell#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ 716254885Sdumbbell#define RADEON_PARAM_DEVICE_ID 16 717254885Sdumbbell#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ 718254885Sdumbbell 719254885Sdumbbelltypedef struct drm_radeon_getparam { 720254885Sdumbbell int param; 721254885Sdumbbell void __user *value; 722254885Sdumbbell} drm_radeon_getparam_t; 723254885Sdumbbell 724254885Sdumbbell/* 1.6: Set up a memory manager for regions of shared memory: 725254885Sdumbbell */ 726254885Sdumbbell#define RADEON_MEM_REGION_GART 1 727254885Sdumbbell#define RADEON_MEM_REGION_FB 2 728254885Sdumbbell 729254885Sdumbbelltypedef struct drm_radeon_mem_alloc { 730254885Sdumbbell int region; 731254885Sdumbbell int alignment; 732254885Sdumbbell int size; 733254885Sdumbbell int __user *region_offset; /* offset from start of fb or GART */ 734254885Sdumbbell} drm_radeon_mem_alloc_t; 735254885Sdumbbell 736254885Sdumbbelltypedef struct drm_radeon_mem_free { 737254885Sdumbbell int region; 738254885Sdumbbell int region_offset; 739254885Sdumbbell} drm_radeon_mem_free_t; 740254885Sdumbbell 741254885Sdumbbelltypedef struct drm_radeon_mem_init_heap { 742254885Sdumbbell int region; 743254885Sdumbbell int size; 744254885Sdumbbell int start; 745254885Sdumbbell} drm_radeon_mem_init_heap_t; 746254885Sdumbbell 747254885Sdumbbell/* 1.6: Userspace can request & wait on irq's: 748254885Sdumbbell */ 749254885Sdumbbelltypedef struct drm_radeon_irq_emit { 750254885Sdumbbell int __user *irq_seq; 751254885Sdumbbell} drm_radeon_irq_emit_t; 752254885Sdumbbell 753254885Sdumbbelltypedef struct drm_radeon_irq_wait { 754254885Sdumbbell int irq_seq; 755254885Sdumbbell} drm_radeon_irq_wait_t; 756254885Sdumbbell 757254885Sdumbbell/* 1.10: Clients tell the DRM where they think the framebuffer is located in 758254885Sdumbbell * the card's address space, via a new generic ioctl to set parameters 759254885Sdumbbell */ 760254885Sdumbbell 761254885Sdumbbelltypedef struct drm_radeon_setparam { 762254885Sdumbbell unsigned int param; 763282199Sdumbbell __s64 value; 764254885Sdumbbell} drm_radeon_setparam_t; 765254885Sdumbbell 766254885Sdumbbell#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ 767254885Sdumbbell#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ 768254885Sdumbbell#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ 769254885Sdumbbell#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ 770254885Sdumbbell#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ 771254885Sdumbbell#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ 772254885Sdumbbell/* 1.14: Clients can allocate/free a surface 773254885Sdumbbell */ 774254885Sdumbbelltypedef struct drm_radeon_surface_alloc { 775254885Sdumbbell unsigned int address; 776254885Sdumbbell unsigned int size; 777254885Sdumbbell unsigned int flags; 778254885Sdumbbell} drm_radeon_surface_alloc_t; 779254885Sdumbbell 780254885Sdumbbelltypedef struct drm_radeon_surface_free { 781254885Sdumbbell unsigned int address; 782254885Sdumbbell} drm_radeon_surface_free_t; 783254885Sdumbbell 784254885Sdumbbell#define DRM_RADEON_VBLANK_CRTC1 1 785254885Sdumbbell#define DRM_RADEON_VBLANK_CRTC2 2 786254885Sdumbbell 787254885Sdumbbell/* 788254885Sdumbbell * Kernel modesetting world below. 789254885Sdumbbell */ 790254885Sdumbbell#define RADEON_GEM_DOMAIN_CPU 0x1 791254885Sdumbbell#define RADEON_GEM_DOMAIN_GTT 0x2 792254885Sdumbbell#define RADEON_GEM_DOMAIN_VRAM 0x4 793254885Sdumbbell 794254885Sdumbbellstruct drm_radeon_gem_info { 795254885Sdumbbell uint64_t gart_size; 796254885Sdumbbell uint64_t vram_size; 797254885Sdumbbell uint64_t vram_visible; 798254885Sdumbbell}; 799254885Sdumbbell 800254885Sdumbbell#define RADEON_GEM_NO_BACKING_STORE 1 801254885Sdumbbell 802254885Sdumbbellstruct drm_radeon_gem_create { 803254885Sdumbbell uint64_t size; 804254885Sdumbbell uint64_t alignment; 805254885Sdumbbell uint32_t handle; 806254885Sdumbbell uint32_t initial_domain; 807254885Sdumbbell uint32_t flags; 808254885Sdumbbell}; 809254885Sdumbbell 810254885Sdumbbell#define RADEON_TILING_MACRO 0x1 811254885Sdumbbell#define RADEON_TILING_MICRO 0x2 812254885Sdumbbell#define RADEON_TILING_SWAP_16BIT 0x4 813254885Sdumbbell#define RADEON_TILING_SWAP_32BIT 0x8 814254885Sdumbbell/* this object requires a surface when mapped - i.e. front buffer */ 815254885Sdumbbell#define RADEON_TILING_SURFACE 0x10 816254885Sdumbbell#define RADEON_TILING_MICRO_SQUARE 0x20 817254885Sdumbbell#define RADEON_TILING_EG_BANKW_SHIFT 8 818254885Sdumbbell#define RADEON_TILING_EG_BANKW_MASK 0xf 819254885Sdumbbell#define RADEON_TILING_EG_BANKH_SHIFT 12 820254885Sdumbbell#define RADEON_TILING_EG_BANKH_MASK 0xf 821254885Sdumbbell#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 822254885Sdumbbell#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf 823254885Sdumbbell#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 824254885Sdumbbell#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf 825254885Sdumbbell#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 826254885Sdumbbell#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 827254885Sdumbbell 828254885Sdumbbellstruct drm_radeon_gem_set_tiling { 829254885Sdumbbell uint32_t handle; 830254885Sdumbbell uint32_t tiling_flags; 831254885Sdumbbell uint32_t pitch; 832254885Sdumbbell}; 833254885Sdumbbell 834254885Sdumbbellstruct drm_radeon_gem_get_tiling { 835254885Sdumbbell uint32_t handle; 836254885Sdumbbell uint32_t tiling_flags; 837254885Sdumbbell uint32_t pitch; 838254885Sdumbbell}; 839254885Sdumbbell 840254885Sdumbbellstruct drm_radeon_gem_mmap { 841254885Sdumbbell uint32_t handle; 842254885Sdumbbell uint32_t pad; 843254885Sdumbbell uint64_t offset; 844254885Sdumbbell uint64_t size; 845254885Sdumbbell uint64_t addr_ptr; 846254885Sdumbbell}; 847254885Sdumbbell 848254885Sdumbbellstruct drm_radeon_gem_set_domain { 849254885Sdumbbell uint32_t handle; 850254885Sdumbbell uint32_t read_domains; 851254885Sdumbbell uint32_t write_domain; 852254885Sdumbbell}; 853254885Sdumbbell 854254885Sdumbbellstruct drm_radeon_gem_wait_idle { 855254885Sdumbbell uint32_t handle; 856254885Sdumbbell uint32_t pad; 857254885Sdumbbell}; 858254885Sdumbbell 859254885Sdumbbellstruct drm_radeon_gem_busy { 860254885Sdumbbell uint32_t handle; 861254885Sdumbbell uint32_t domain; 862254885Sdumbbell}; 863254885Sdumbbell 864254885Sdumbbellstruct drm_radeon_gem_pread { 865254885Sdumbbell /** Handle for the object being read. */ 866254885Sdumbbell uint32_t handle; 867254885Sdumbbell uint32_t pad; 868254885Sdumbbell /** Offset into the object to read from */ 869254885Sdumbbell uint64_t offset; 870254885Sdumbbell /** Length of data to read */ 871254885Sdumbbell uint64_t size; 872254885Sdumbbell /** Pointer to write the data into. */ 873254885Sdumbbell /* void *, but pointers are not 32/64 compatible */ 874254885Sdumbbell uint64_t data_ptr; 875254885Sdumbbell}; 876254885Sdumbbell 877254885Sdumbbellstruct drm_radeon_gem_pwrite { 878254885Sdumbbell /** Handle for the object being written to. */ 879254885Sdumbbell uint32_t handle; 880254885Sdumbbell uint32_t pad; 881254885Sdumbbell /** Offset into the object to write to */ 882254885Sdumbbell uint64_t offset; 883254885Sdumbbell /** Length of data to write */ 884254885Sdumbbell uint64_t size; 885254885Sdumbbell /** Pointer to read the data from. */ 886254885Sdumbbell /* void *, but pointers are not 32/64 compatible */ 887254885Sdumbbell uint64_t data_ptr; 888254885Sdumbbell}; 889254885Sdumbbell 890254885Sdumbbell#define RADEON_VA_MAP 1 891254885Sdumbbell#define RADEON_VA_UNMAP 2 892254885Sdumbbell 893254885Sdumbbell#define RADEON_VA_RESULT_OK 0 894254885Sdumbbell#define RADEON_VA_RESULT_ERROR 1 895254885Sdumbbell#define RADEON_VA_RESULT_VA_EXIST 2 896254885Sdumbbell 897254885Sdumbbell#define RADEON_VM_PAGE_VALID (1 << 0) 898254885Sdumbbell#define RADEON_VM_PAGE_READABLE (1 << 1) 899254885Sdumbbell#define RADEON_VM_PAGE_WRITEABLE (1 << 2) 900254885Sdumbbell#define RADEON_VM_PAGE_SYSTEM (1 << 3) 901254885Sdumbbell#define RADEON_VM_PAGE_SNOOPED (1 << 4) 902254885Sdumbbell 903254885Sdumbbellstruct drm_radeon_gem_va { 904254885Sdumbbell uint32_t handle; 905254885Sdumbbell uint32_t operation; 906254885Sdumbbell uint32_t vm_id; 907254885Sdumbbell uint32_t flags; 908254885Sdumbbell uint64_t offset; 909254885Sdumbbell}; 910254885Sdumbbell 911254885Sdumbbell#define RADEON_CHUNK_ID_RELOCS 0x01 912254885Sdumbbell#define RADEON_CHUNK_ID_IB 0x02 913254885Sdumbbell#define RADEON_CHUNK_ID_FLAGS 0x03 914254885Sdumbbell#define RADEON_CHUNK_ID_CONST_IB 0x04 915254885Sdumbbell 916254885Sdumbbell/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ 917254885Sdumbbell#define RADEON_CS_KEEP_TILING_FLAGS 0x01 918254885Sdumbbell#define RADEON_CS_USE_VM 0x02 919254885Sdumbbell#define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS is the last one */ 920254885Sdumbbell/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */ 921254885Sdumbbell#define RADEON_CS_RING_GFX 0 922254885Sdumbbell#define RADEON_CS_RING_COMPUTE 1 923254885Sdumbbell#define RADEON_CS_RING_DMA 2 924254885Sdumbbell/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */ 925254885Sdumbbell/* 0 = normal, + = higher priority, - = lower priority */ 926254885Sdumbbell 927254885Sdumbbellstruct drm_radeon_cs_chunk { 928254885Sdumbbell uint32_t chunk_id; 929254885Sdumbbell uint32_t length_dw; 930254885Sdumbbell uint64_t chunk_data; 931254885Sdumbbell}; 932254885Sdumbbell 933254885Sdumbbell/* drm_radeon_cs_reloc.flags */ 934254885Sdumbbell 935254885Sdumbbellstruct drm_radeon_cs_reloc { 936254885Sdumbbell uint32_t handle; 937254885Sdumbbell uint32_t read_domains; 938254885Sdumbbell uint32_t write_domain; 939254885Sdumbbell uint32_t flags; 940254885Sdumbbell}; 941254885Sdumbbell 942254885Sdumbbellstruct drm_radeon_cs { 943254885Sdumbbell uint32_t num_chunks; 944254885Sdumbbell uint32_t cs_id; 945254885Sdumbbell /* this points to uint64_t * which point to cs chunks */ 946254885Sdumbbell uint64_t chunks; 947254885Sdumbbell /* updates to the limits after this CS ioctl */ 948254885Sdumbbell uint64_t gart_limit; 949254885Sdumbbell uint64_t vram_limit; 950254885Sdumbbell}; 951254885Sdumbbell 952254885Sdumbbell#define RADEON_INFO_DEVICE_ID 0x00 953254885Sdumbbell#define RADEON_INFO_NUM_GB_PIPES 0x01 954254885Sdumbbell#define RADEON_INFO_NUM_Z_PIPES 0x02 955254885Sdumbbell#define RADEON_INFO_ACCEL_WORKING 0x03 956254885Sdumbbell#define RADEON_INFO_CRTC_FROM_ID 0x04 957254885Sdumbbell#define RADEON_INFO_ACCEL_WORKING2 0x05 958254885Sdumbbell#define RADEON_INFO_TILING_CONFIG 0x06 959254885Sdumbbell#define RADEON_INFO_WANT_HYPERZ 0x07 960254885Sdumbbell#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ 961254885Sdumbbell#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ 962254885Sdumbbell#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ 963254885Sdumbbell#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ 964254885Sdumbbell#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ 965254885Sdumbbell#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ 966254885Sdumbbell/* virtual address start, va < start are reserved by the kernel */ 967254885Sdumbbell#define RADEON_INFO_VA_START 0x0e 968254885Sdumbbell/* maximum size of ib using the virtual memory cs */ 969254885Sdumbbell#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f 970254885Sdumbbell/* max pipes - needed for compute shaders */ 971254885Sdumbbell#define RADEON_INFO_MAX_PIPES 0x10 972254885Sdumbbell/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */ 973254885Sdumbbell#define RADEON_INFO_TIMESTAMP 0x11 974254885Sdumbbell/* max shader engines (SE) - needed for geometry shaders, etc. */ 975254885Sdumbbell#define RADEON_INFO_MAX_SE 0x12 976254885Sdumbbell/* max SH per SE */ 977254885Sdumbbell#define RADEON_INFO_MAX_SH_PER_SE 0x13 978254885Sdumbbell 979254885Sdumbbellstruct drm_radeon_info { 980254885Sdumbbell uint32_t request; 981254885Sdumbbell uint32_t pad; 982254885Sdumbbell uint64_t value; 983254885Sdumbbell}; 984254885Sdumbbell 985254885Sdumbbell#endif 986