1/* 2 * Copyright �� 2011-2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * 26 */ 27 28/* 29 * This file implements HW context support. On gen5+ a HW context consists of an 30 * opaque GPU object which is referenced at times of context saves and restores. 31 * With RC6 enabled, the context is also referenced as the GPU enters and exists 32 * from RC6 (GPU has it's own internal power context, except on gen5). Though 33 * something like a context does exist for the media ring, the code only 34 * supports contexts for the render ring. 35 * 36 * In software, there is a distinction between contexts created by the user, 37 * and the default HW context. The default HW context is used by GPU clients 38 * that do not request setup of their own hardware context. The default 39 * context's state is never restored to help prevent programming errors. This 40 * would happen if a client ran and piggy-backed off another clients GPU state. 41 * The default context only exists to give the GPU some offset to load as the 42 * current to invoke a save of the context we actually care about. In fact, the 43 * code could likely be constructed, albeit in a more complicated fashion, to 44 * never use the default context, though that limits the driver's ability to 45 * swap out, and/or destroy other contexts. 46 * 47 * All other contexts are created as a request by the GPU client. These contexts 48 * store GPU state, and thus allow GPU clients to not re-emit state (and 49 * potentially query certain state) at any time. The kernel driver makes 50 * certain that the appropriate commands are inserted. 51 * 52 * The context life cycle is semi-complicated in that context BOs may live 53 * longer than the context itself because of the way the hardware, and object 54 * tracking works. Below is a very crude representation of the state machine 55 * describing the context life. 56 * refcount pincount active 57 * S0: initial state 0 0 0 58 * S1: context created 1 0 0 59 * S2: context is currently running 2 1 X 60 * S3: GPU referenced, but not current 2 0 1 61 * S4: context is current, but destroyed 1 1 0 62 * S5: like S3, but destroyed 1 0 1 63 * 64 * The most common (but not all) transitions: 65 * S0->S1: client creates a context 66 * S1->S2: client submits execbuf with context 67 * S2->S3: other clients submits execbuf with context 68 * S3->S1: context object was retired 69 * S3->S2: clients submits another execbuf 70 * S2->S4: context destroy called with current context 71 * S3->S5->S0: destroy path 72 * S4->S5->S0: destroy path on current context 73 * 74 * There are two confusing terms used above: 75 * The "current context" means the context which is currently running on the 76 * GPU. The GPU has loaded it's state already and has stored away the gtt 77 * offset of the BO. The GPU is not actively referencing the data at this 78 * offset, but it will on the next context switch. The only way to avoid this 79 * is to do a GPU reset. 80 * 81 * An "active context' is one which was previously the "current context" and is 82 * on the active list waiting for the next context switch to occur. Until this 83 * happens, the object must remain at the same gtt offset. It is therefore 84 * possible to destroy a context, but it is still active. 85 * 86 */ 87 88#include <sys/cdefs.h> 89__FBSDID("$FreeBSD$"); 90 91#include <dev/drm2/drmP.h> 92#include <dev/drm2/i915/i915_drm.h> 93#include "i915_drv.h" 94 95/* This is a HW constraint. The value below is the largest known requirement 96 * I've seen in a spec to date, and that was a workaround for a non-shipping 97 * part. It should be safe to decrease this, but it's more future proof as is. 98 */ 99#define CONTEXT_ALIGN (64<<10) 100 101static struct i915_hw_context * 102i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); 103static int do_switch(struct i915_hw_context *to); 104 105static int get_context_size(struct drm_device *dev) 106{ 107 struct drm_i915_private *dev_priv = dev->dev_private; 108 int ret; 109 u32 reg; 110 111 switch (INTEL_INFO(dev)->gen) { 112 case 6: 113 reg = I915_READ(CXT_SIZE); 114 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; 115 break; 116 case 7: 117 reg = I915_READ(GEN7_CXT_SIZE); 118#ifdef FREEBSD_WIP 119 if (IS_HASWELL(dev)) 120 ret = HSW_CXT_TOTAL_SIZE(reg) * 64; 121 else 122#endif 123 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; 124 break; 125 default: 126 panic("i915_gem_context: Unsupported Intel GPU generation %d", 127 INTEL_INFO(dev)->gen); 128 } 129 130 return ret; 131} 132 133static void do_destroy(struct i915_hw_context *ctx) 134{ 135#if defined(INVARIANTS) 136 struct drm_device *dev = ctx->obj->base.dev; 137 struct drm_i915_private *dev_priv = dev->dev_private; 138#endif 139 140 if (ctx->file_priv) 141 drm_gem_names_remove(&ctx->file_priv->context_idr, ctx->id); 142 else 143 KASSERT(ctx == dev_priv->rings[RCS].default_context, 144 ("i915_gem_context: ctx != default_context")); 145 146 drm_gem_object_unreference(&ctx->obj->base); 147 free(ctx, DRM_I915_GEM); 148} 149 150static int 151create_hw_context(struct drm_device *dev, 152 struct drm_i915_file_private *file_priv, 153 struct i915_hw_context **ret_ctx) 154{ 155 struct drm_i915_private *dev_priv = dev->dev_private; 156 struct i915_hw_context *ctx; 157 int ret, id; 158 159 ctx = malloc(sizeof(*ctx), DRM_I915_GEM, M_NOWAIT | M_ZERO); 160 if (ctx == NULL) 161 return (-ENOMEM); 162 163 ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size); 164 if (ctx->obj == NULL) { 165 free(ctx, DRM_I915_GEM); 166 DRM_DEBUG_DRIVER("Context object allocated failed\n"); 167 return (-ENOMEM); 168 } 169 170 if (INTEL_INFO(dev)->gen >= 7) { 171 ret = i915_gem_object_set_cache_level(ctx->obj, 172 I915_CACHE_LLC_MLC); 173 if (ret) 174 goto err_out; 175 } 176 177 /* The ring associated with the context object is handled by the normal 178 * object tracking code. We give an initial ring value simple to pass an 179 * assertion in the context switch code. 180 */ 181 ctx->ring = &dev_priv->rings[RCS]; 182 183 /* Default context will never have a file_priv */ 184 if (file_priv == NULL) { 185 *ret_ctx = ctx; 186 return (0); 187 } 188 189 ctx->file_priv = file_priv; 190 191again: 192 id = 0; 193 ret = drm_gem_name_create(&file_priv->context_idr, ctx, &id); 194 if (ret == 0) 195 ctx->id = id; 196 197 if (ret == -EAGAIN) 198 goto again; 199 else if (ret) 200 goto err_out; 201 202 *ret_ctx = ctx; 203 return (0); 204 205err_out: 206 do_destroy(ctx); 207 return (ret); 208} 209 210static inline bool is_default_context(struct i915_hw_context *ctx) 211{ 212 return (ctx == ctx->ring->default_context); 213} 214 215/** 216 * The default context needs to exist per ring that uses contexts. It stores the 217 * context state of the GPU for applications that don't utilize HW contexts, as 218 * well as an idle case. 219 */ 220static int create_default_context(struct drm_i915_private *dev_priv) 221{ 222 struct i915_hw_context *ctx; 223 int ret; 224 225 DRM_LOCK_ASSERT(dev_priv->dev); 226 227 ret = create_hw_context(dev_priv->dev, NULL, &ctx); 228 if (ret != 0) 229 return (ret); 230 231 /* We may need to do things with the shrinker which require us to 232 * immediately switch back to the default context. This can cause a 233 * problem as pinning the default context also requires GTT space which 234 * may not be available. To avoid this we always pin the 235 * default context. 236 */ 237 dev_priv->rings[RCS].default_context = ctx; 238 ret = i915_gem_object_pin(ctx->obj, CONTEXT_ALIGN, false); 239 if (ret) 240 goto err_destroy; 241 242 ret = do_switch(ctx); 243 if (ret) 244 goto err_unpin; 245 246 DRM_DEBUG_DRIVER("Default HW context loaded\n"); 247 return 0; 248 249err_unpin: 250 i915_gem_object_unpin(ctx->obj); 251err_destroy: 252 do_destroy(ctx); 253 return ret; 254} 255 256void i915_gem_context_init(struct drm_device *dev) 257{ 258 struct drm_i915_private *dev_priv = dev->dev_private; 259 uint32_t ctx_size; 260 261 if (!HAS_HW_CONTEXTS(dev)) { 262 dev_priv->hw_contexts_disabled = true; 263 return; 264 } 265 266 /* If called from reset, or thaw... we've been here already */ 267 if (dev_priv->hw_contexts_disabled || 268 dev_priv->rings[RCS].default_context) 269 return; 270 271 ctx_size = get_context_size(dev); 272 dev_priv->hw_context_size = get_context_size(dev); 273 dev_priv->hw_context_size = roundup(dev_priv->hw_context_size, 4096); 274 275 if (ctx_size <= 0 || ctx_size > (1<<20)) { 276 dev_priv->hw_contexts_disabled = true; 277 return; 278 } 279 280 if (create_default_context(dev_priv)) { 281 dev_priv->hw_contexts_disabled = true; 282 return; 283 } 284 285 DRM_DEBUG_DRIVER("HW context support initialized\n"); 286} 287 288void i915_gem_context_fini(struct drm_device *dev) 289{ 290 struct drm_i915_private *dev_priv = dev->dev_private; 291 292 if (dev_priv->hw_contexts_disabled) 293 return; 294 295 /* The only known way to stop the gpu from accessing the hw context is 296 * to reset it. Do this as the very last operation to avoid confusing 297 * other code, leading to spurious errors. */ 298 intel_gpu_reset(dev); 299 300 i915_gem_object_unpin(dev_priv->rings[RCS].default_context->obj); 301 302 do_destroy(dev_priv->rings[RCS].default_context); 303} 304 305static int context_idr_cleanup(uint32_t id, void *p, void *data) 306{ 307 struct i915_hw_context *ctx = p; 308 309 KASSERT(id != DEFAULT_CONTEXT_ID, ("i915_gem_context: id == DEFAULT_CONTEXT_ID in cleanup")); 310 311 do_destroy(ctx); 312 313 return 0; 314} 315 316void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) 317{ 318 struct drm_i915_file_private *file_priv = file->driver_priv; 319 320 DRM_LOCK(dev); 321 drm_gem_names_foreach(&file_priv->context_idr, context_idr_cleanup, NULL); 322 drm_gem_names_fini(&file_priv->context_idr); 323 DRM_UNLOCK(dev); 324} 325 326static struct i915_hw_context * 327i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id) 328{ 329 return (struct i915_hw_context *)drm_gem_find_ptr(&file_priv->context_idr, id); 330} 331 332static inline int 333mi_set_context(struct intel_ring_buffer *ring, 334 struct i915_hw_context *new_context, 335 u32 hw_flags) 336{ 337 int ret; 338 339 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB 340 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value 341 * explicitly, so we rely on the value at ring init, stored in 342 * itlb_before_ctx_switch. 343 */ 344 if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) { 345 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); 346 if (ret) 347 return ret; 348 } 349 350 ret = intel_ring_begin(ring, 6); 351 if (ret) 352 return ret; 353 354 if (IS_GEN7(ring->dev)) 355 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); 356 else 357 intel_ring_emit(ring, MI_NOOP); 358 359 intel_ring_emit(ring, MI_NOOP); 360 intel_ring_emit(ring, MI_SET_CONTEXT); 361 intel_ring_emit(ring, new_context->obj->gtt_offset | 362 MI_MM_SPACE_GTT | 363 MI_SAVE_EXT_STATE_EN | 364 MI_RESTORE_EXT_STATE_EN | 365 hw_flags); 366 /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */ 367 intel_ring_emit(ring, MI_NOOP); 368 369 if (IS_GEN7(ring->dev)) 370 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); 371 else 372 intel_ring_emit(ring, MI_NOOP); 373 374 intel_ring_advance(ring); 375 376 return ret; 377} 378 379static int do_switch(struct i915_hw_context *to) 380{ 381 struct intel_ring_buffer *ring = to->ring; 382 struct drm_i915_gem_object *from_obj = ring->last_context_obj; 383 u32 hw_flags = 0; 384 int ret; 385 386 KASSERT(!(from_obj != NULL && from_obj->pin_count == 0), 387 ("i915_gem_context: invalid \"from\" context")); 388 389 if (from_obj == to->obj) 390 return 0; 391 392 ret = i915_gem_object_pin(to->obj, CONTEXT_ALIGN, false); 393 if (ret) 394 return ret; 395 396 /* Clear this page out of any CPU caches for coherent swap-in/out. Note 397 * that thanks to write = false in this call and us not setting any gpu 398 * write domains when putting a context object onto the active list 399 * (when switching away from it), this won't block. 400 * XXX: We need a real interface to do this instead of trickery. */ 401 ret = i915_gem_object_set_to_gtt_domain(to->obj, false); 402 if (ret) { 403 i915_gem_object_unpin(to->obj); 404 return ret; 405 } 406 407 if (!to->obj->has_global_gtt_mapping) 408 i915_gem_gtt_bind_object(to->obj, to->obj->cache_level); 409 410 if (!to->is_initialized || is_default_context(to)) 411 hw_flags |= MI_RESTORE_INHIBIT; 412 else if (from_obj == to->obj) /* not yet expected */ 413 hw_flags |= MI_FORCE_RESTORE; 414 415 ret = mi_set_context(ring, to, hw_flags); 416 if (ret) { 417 i915_gem_object_unpin(to->obj); 418 return ret; 419 } 420 421 /* The backing object for the context is done after switching to the 422 * *next* context. Therefore we cannot retire the previous context until 423 * the next context has already started running. In fact, the below code 424 * is a bit suboptimal because the retiring can occur simply after the 425 * MI_SET_CONTEXT instead of when the next seqno has completed. 426 */ 427 if (from_obj != NULL) { 428 from_obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION; 429 i915_gem_object_move_to_active(from_obj, ring, 430 i915_gem_next_request_seqno(ring)); 431 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the 432 * whole damn pipeline, we don't need to explicitly mark the 433 * object dirty. The only exception is that the context must be 434 * correct in case the object gets swapped out. Ideally we'd be 435 * able to defer doing this until we know the object would be 436 * swapped, but there is no way to do that yet. 437 */ 438 from_obj->dirty = 1; 439 KASSERT(from_obj->ring == ring, ("i915_gem_context: from_ring != ring")); 440 i915_gem_object_unpin(from_obj); 441 442 drm_gem_object_unreference(&from_obj->base); 443 } 444 445 drm_gem_object_reference(&to->obj->base); 446 ring->last_context_obj = to->obj; 447 to->is_initialized = true; 448 449 return 0; 450} 451 452/** 453 * i915_switch_context() - perform a GPU context switch. 454 * @ring: ring for which we'll execute the context switch 455 * @file_priv: file_priv associated with the context, may be NULL 456 * @id: context id number 457 * @seqno: sequence number by which the new context will be switched to 458 * @flags: 459 * 460 * The context life cycle is simple. The context refcount is incremented and 461 * decremented by 1 and create and destroy. If the context is in use by the GPU, 462 * it will have a refoucnt > 1. This allows us to destroy the context abstract 463 * object while letting the normal object tracking destroy the backing BO. 464 */ 465int i915_switch_context(struct intel_ring_buffer *ring, 466 struct drm_file *file, 467 int to_id) 468{ 469 struct drm_i915_private *dev_priv = ring->dev->dev_private; 470 struct i915_hw_context *to; 471 472 if (dev_priv->hw_contexts_disabled) 473 return 0; 474 475 if (ring != &dev_priv->rings[RCS]) 476 return 0; 477 478 if (to_id == DEFAULT_CONTEXT_ID) { 479 to = ring->default_context; 480 } else { 481 if (file == NULL) 482 return -EINVAL; 483 484 to = i915_gem_context_get(file->driver_priv, to_id); 485 if (to == NULL) 486 return -ENOENT; 487 } 488 489 return do_switch(to); 490} 491 492int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 493 struct drm_file *file) 494{ 495 struct drm_i915_private *dev_priv = dev->dev_private; 496 struct drm_i915_gem_context_create *args = data; 497 struct drm_i915_file_private *file_priv = file->driver_priv; 498 struct i915_hw_context *ctx; 499 int ret; 500 501 if (!(dev->driver->driver_features & DRIVER_GEM)) 502 return -ENODEV; 503 504 if (dev_priv->hw_contexts_disabled) 505 return -ENODEV; 506 507 ret = i915_mutex_lock_interruptible(dev); 508 if (ret) 509 return ret; 510 511 ret = create_hw_context(dev, file_priv, &ctx); 512 DRM_UNLOCK(dev); 513 if (ret != 0) 514 return (ret); 515 516 args->ctx_id = ctx->id; 517 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id); 518 519 return 0; 520} 521 522int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 523 struct drm_file *file) 524{ 525 struct drm_i915_gem_context_destroy *args = data; 526 struct drm_i915_file_private *file_priv = file->driver_priv; 527 struct i915_hw_context *ctx; 528 int ret; 529 530 if (!(dev->driver->driver_features & DRIVER_GEM)) 531 return -ENODEV; 532 533 ret = i915_mutex_lock_interruptible(dev); 534 if (ret) 535 return ret; 536 537 ctx = i915_gem_context_get(file_priv, args->ctx_id); 538 if (!ctx) { 539 DRM_UNLOCK(dev); 540 return -ENOENT; 541 } 542 543 do_destroy(ctx); 544 545 DRM_UNLOCK(dev); 546 547 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id); 548 return 0; 549} 550