1152909Sanholt/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2152909Sanholt * 395584Sanholt * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 495584Sanholt * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 595584Sanholt * All rights reserved. 695584Sanholt * 795584Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 895584Sanholt * copy of this software and associated documentation files (the "Software"), 995584Sanholt * to deal in the Software without restriction, including without limitation 1095584Sanholt * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1195584Sanholt * and/or sell copies of the Software, and to permit persons to whom the 1295584Sanholt * Software is furnished to do so, subject to the following conditions: 1395584Sanholt * 1495584Sanholt * The above copyright notice and this permission notice (including the next 1595584Sanholt * paragraph) shall be included in all copies or substantial portions of the 1695584Sanholt * Software. 1795584Sanholt * 1895584Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1995584Sanholt * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2095584Sanholt * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2195584Sanholt * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2295584Sanholt * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2395584Sanholt * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2495584Sanholt * DEALINGS IN THE SOFTWARE. 2595584Sanholt * 2695584Sanholt * Authors: 2795584Sanholt * Kevin E. Martin <martin@valinux.com> 2895584Sanholt * Gareth Hughes <gareth@valinux.com> 2995584Sanholt */ 3095584Sanholt 31152909Sanholt#include <sys/cdefs.h> 32152909Sanholt__FBSDID("$FreeBSD$"); 33152909Sanholt 3495584Sanholt#ifndef __RADEON_DRV_H__ 3595584Sanholt#define __RADEON_DRV_H__ 3695584Sanholt 37145132Sanholt/* General customization: 38145132Sanholt */ 39145132Sanholt 40145132Sanholt#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41145132Sanholt 42145132Sanholt#define DRIVER_NAME "radeon" 43145132Sanholt#define DRIVER_DESC "ATI Radeon" 44196470Srnoland#define DRIVER_DATE "20080613" 45145132Sanholt 46145132Sanholt/* Interface history: 47145132Sanholt * 48145132Sanholt * 1.1 - ?? 49145132Sanholt * 1.2 - Add vertex2 ioctl (keith) 50145132Sanholt * - Add stencil capability to clear ioctl (gareth, keith) 51145132Sanholt * - Increase MAX_TEXTURE_LEVELS (brian) 52145132Sanholt * 1.3 - Add cmdbuf ioctl (keith) 53145132Sanholt * - Add support for new radeon packets (keith) 54145132Sanholt * - Add getparam ioctl (keith) 55145132Sanholt * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 56145132Sanholt * 1.4 - Add scratch registers to get_param ioctl. 57145132Sanholt * 1.5 - Add r200 packets to cmdbuf ioctl 58145132Sanholt * - Add r200 function to init ioctl 59145132Sanholt * - Add 'scalar2' instruction to cmdbuf 60145132Sanholt * 1.6 - Add static GART memory manager 61145132Sanholt * Add irq handler (won't be turned on unless X server knows to) 62145132Sanholt * Add irq ioctls and irq_active getparam. 63145132Sanholt * Add wait command for cmdbuf ioctl 64145132Sanholt * Add GART offset query for getparam 65145132Sanholt * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 66145132Sanholt * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 67145132Sanholt * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 68145132Sanholt * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 69145132Sanholt * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 70145132Sanholt * Add 'GET' queries for starting additional clients on different VT's. 71145132Sanholt * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 72145132Sanholt * Add texture rectangle support for r100. 73145132Sanholt * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 74145132Sanholt * clients use to tell the DRM where they think the framebuffer is 75145132Sanholt * located in the card's address space 76145132Sanholt * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 77145132Sanholt * and GL_EXT_blend_[func|equation]_separate on r200 78145132Sanholt * 1.12- Add R300 CP microcode support - this just loads the CP on r300 79145132Sanholt * (No 3D support yet - just microcode loading). 80145132Sanholt * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 81145132Sanholt * - Add hyperz support, add hyperz flags to clear ioctl. 82145132Sanholt * 1.14- Add support for color tiling 83145132Sanholt * - Add R100/R200 surface allocation/free support 84145132Sanholt * 1.15- Add support for texture micro tiling 85145132Sanholt * - Add support for r100 cube maps 86145132Sanholt * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87145132Sanholt * texture filtering on r200 88152909Sanholt * 1.17- Add initial support for R300 (3D). 89157617Sanholt * 1.18- Add support for GL_ATI_fragment_shader, new packets 90157617Sanholt * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 91157617Sanholt * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 92157617Sanholt * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 93152909Sanholt * 1.19- Add support for gart table in FB memory and PCIE r300 94157617Sanholt * 1.20- Add support for r300 texrect 95157617Sanholt * 1.21- Add support for card type getparam 96157617Sanholt * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 97157617Sanholt * 1.23- Add new radeon memory map work from benh 98157617Sanholt * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 99162132Sanholt * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 100162132Sanholt * new packet type) 101182080Srnoland * 1.26- Add support for variable size PCI(E) gart aperture 102182080Srnoland * 1.27- Add support for IGP GART 103182080Srnoland * 1.28- Add support for VBL on CRTC2 104182080Srnoland * 1.29- R500 3D cmd buffer support 105196471Srnoland * 1.30- Add support for occlusion queries 106196471Srnoland * 1.31- Add support for num Z pipes from GET_PARAM 107145132Sanholt */ 108145132Sanholt#define DRIVER_MAJOR 1 109196471Srnoland#define DRIVER_MINOR 31 110145132Sanholt#define DRIVER_PATCHLEVEL 0 111145132Sanholt 112157617Sanholt/* 113157617Sanholt * Radeon chip families 114157617Sanholt */ 115145132Sanholtenum radeon_family { 116145132Sanholt CHIP_R100, 117157617Sanholt CHIP_RV100, 118145132Sanholt CHIP_RS100, 119152909Sanholt CHIP_RV200, 120157617Sanholt CHIP_RS200, 121145132Sanholt CHIP_R200, 122145132Sanholt CHIP_RV250, 123157617Sanholt CHIP_RS300, 124145132Sanholt CHIP_RV280, 125145132Sanholt CHIP_R300, 126148211Sanholt CHIP_R350, 127145132Sanholt CHIP_RV350, 128157617Sanholt CHIP_RV380, 129148211Sanholt CHIP_R420, 130183830Srnoland CHIP_R423, 131157617Sanholt CHIP_RV410, 132157617Sanholt CHIP_RS400, 133182080Srnoland CHIP_RS480, 134189499Srnoland CHIP_RS600, 135182080Srnoland CHIP_RS690, 136183828Srnoland CHIP_RS740, 137182080Srnoland CHIP_RV515, 138182080Srnoland CHIP_R520, 139182080Srnoland CHIP_RV530, 140182080Srnoland CHIP_RV560, 141182080Srnoland CHIP_RV570, 142182080Srnoland CHIP_R580, 143189499Srnoland CHIP_R600, 144189499Srnoland CHIP_RV610, 145189499Srnoland CHIP_RV630, 146197605Srnoland CHIP_RV670, 147189499Srnoland CHIP_RV620, 148189499Srnoland CHIP_RV635, 149189499Srnoland CHIP_RS780, 150196142Srnoland CHIP_RS880, 151189499Srnoland CHIP_RV770, 152189499Srnoland CHIP_RV730, 153189499Srnoland CHIP_RV710, 154197605Srnoland CHIP_RV740, 155145132Sanholt CHIP_LAST, 156145132Sanholt}; 157145132Sanholt 158189499Srnolandenum radeon_cp_microcode_version { 159189499Srnoland UCODE_R100, 160189499Srnoland UCODE_R200, 161189499Srnoland UCODE_R300, 162189499Srnoland}; 163189499Srnoland 164145132Sanholt/* 165145132Sanholt * Chip flags 166145132Sanholt */ 167145132Sanholtenum radeon_chip_flags { 168182080Srnoland RADEON_FAMILY_MASK = 0x0000ffffUL, 169182080Srnoland RADEON_FLAGS_MASK = 0xffff0000UL, 170182080Srnoland RADEON_IS_MOBILITY = 0x00010000UL, 171182080Srnoland RADEON_IS_IGP = 0x00020000UL, 172182080Srnoland RADEON_SINGLE_CRTC = 0x00040000UL, 173182080Srnoland RADEON_IS_AGP = 0x00080000UL, 174182080Srnoland RADEON_HAS_HIERZ = 0x00100000UL, 175182080Srnoland RADEON_IS_PCIE = 0x00200000UL, 176182080Srnoland RADEON_NEW_MEMMAP = 0x00400000UL, 177182080Srnoland RADEON_IS_PCI = 0x00800000UL, 178182080Srnoland RADEON_IS_IGPGART = 0x01000000UL, 179145132Sanholt}; 180145132Sanholt 18195584Sanholttypedef struct drm_radeon_freelist { 182145132Sanholt unsigned int age; 183182080Srnoland struct drm_buf *buf; 184145132Sanholt struct drm_radeon_freelist *next; 185145132Sanholt struct drm_radeon_freelist *prev; 18695584Sanholt} drm_radeon_freelist_t; 18795584Sanholt 18895584Sanholttypedef struct drm_radeon_ring_buffer { 18995584Sanholt u32 *start; 19095584Sanholt u32 *end; 191189499Srnoland int size; 192189499Srnoland int size_l2qw; 19395584Sanholt 194182080Srnoland int rptr_update; /* Double Words */ 195182080Srnoland int rptr_update_l2qw; /* log2 Quad Words */ 196182080Srnoland 197182080Srnoland int fetch_size; /* Double Words */ 198182080Srnoland int fetch_size_l2ow; /* log2 Oct Words */ 199182080Srnoland 20095584Sanholt u32 tail; 20195584Sanholt u32 tail_mask; 20295584Sanholt int space; 20395584Sanholt 20495584Sanholt int high_mark; 20595584Sanholt} drm_radeon_ring_buffer_t; 20695584Sanholt 20795584Sanholttypedef struct drm_radeon_depth_clear_t { 20895584Sanholt u32 rb3d_cntl; 20995584Sanholt u32 rb3d_zstencilcntl; 21095584Sanholt u32 se_cntl; 21195584Sanholt} drm_radeon_depth_clear_t; 21295584Sanholt 213145132Sanholtstruct drm_radeon_driver_file_fields { 214145132Sanholt int64_t radeon_fb_delta; 215145132Sanholt}; 216112015Sanholt 217112015Sanholtstruct mem_block { 218112015Sanholt struct mem_block *next; 219112015Sanholt struct mem_block *prev; 220112015Sanholt int start; 221112015Sanholt int size; 222182080Srnoland struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 223112015Sanholt}; 224112015Sanholt 225145132Sanholtstruct radeon_surface { 226145132Sanholt int refcount; 227145132Sanholt u32 lower; 228145132Sanholt u32 upper; 229145132Sanholt u32 flags; 230145132Sanholt}; 231145132Sanholt 232145132Sanholtstruct radeon_virt_surface { 233145132Sanholt int surface_index; 234145132Sanholt u32 lower; 235145132Sanholt u32 upper; 236145132Sanholt u32 flags; 237182080Srnoland struct drm_file *file_priv; 238189499Srnoland#define PCIGART_FILE_PRIV ((void *) -1L) 239145132Sanholt}; 240145132Sanholt 241196470Srnolandstruct drm_radeon_kernel_chunk { 242196470Srnoland uint32_t chunk_id; 243196470Srnoland uint32_t length_dw; 244196470Srnoland uint32_t __user *chunk_data; 245196470Srnoland uint32_t *kdata; 246196470Srnoland}; 247196470Srnoland 248196470Srnolandstruct drm_radeon_cs_parser { 249196470Srnoland struct drm_device *dev; 250196470Srnoland struct drm_file *file_priv; 251196470Srnoland uint32_t num_chunks; 252196470Srnoland struct drm_radeon_kernel_chunk *chunks; 253196470Srnoland int ib_index; 254196470Srnoland int reloc_index; 255196470Srnoland uint32_t card_offset; 256196470Srnoland void *ib; 257196470Srnoland}; 258196470Srnoland 259196470Srnoland/* command submission struct */ 260196470Srnolandstruct drm_radeon_cs_priv { 261196470Srnoland struct mtx cs_mutex; 262196470Srnoland uint32_t id_wcnt; 263196470Srnoland uint32_t id_scnt; 264196470Srnoland uint32_t id_last_wcnt; 265196470Srnoland uint32_t id_last_scnt; 266196470Srnoland 267196470Srnoland int (*parse)(struct drm_radeon_cs_parser *parser); 268196470Srnoland void (*id_emit)(struct drm_radeon_cs_parser *parser, uint32_t *id); 269196470Srnoland uint32_t (*id_last_get)(struct drm_device *dev); 270196470Srnoland /* this ib handling callback are for hidding memory manager drm 271196470Srnoland * from memory manager less drm, free have to emit ib discard 272196470Srnoland * sequence into the ring */ 273196470Srnoland int (*ib_get)(struct drm_radeon_cs_parser *parser); 274196470Srnoland uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib); 275196470Srnoland void (*ib_free)(struct drm_radeon_cs_parser *parser, int error); 276196470Srnoland /* do a relocation either MM or non-MM */ 277196470Srnoland int (*relocate)(struct drm_radeon_cs_parser *parser, 278196470Srnoland uint32_t *reloc, uint64_t *offset); 279196470Srnoland}; 280196470Srnoland 281189499Srnoland#define RADEON_FLUSH_EMITED (1 << 0) 282189499Srnoland#define RADEON_PURGE_EMITED (1 << 1) 283182080Srnoland 28495584Sanholttypedef struct drm_radeon_private { 28595584Sanholt drm_radeon_ring_buffer_t ring; 28695584Sanholt drm_radeon_sarea_t *sarea_priv; 28795584Sanholt 288122580Sanholt u32 fb_location; 289157617Sanholt u32 fb_size; 290157617Sanholt int new_memmap; 291122580Sanholt 292119895Sanholt int gart_size; 293119895Sanholt u32 gart_vm_start; 294119895Sanholt unsigned long gart_buffers_offset; 29595584Sanholt 29695584Sanholt int cp_mode; 29795584Sanholt int cp_running; 29895584Sanholt 299145132Sanholt drm_radeon_freelist_t *head; 300145132Sanholt drm_radeon_freelist_t *tail; 30195584Sanholt int last_buf; 302112015Sanholt int writeback_works; 30395584Sanholt 30495584Sanholt int usec_timeout; 305112015Sanholt 306189499Srnoland int microcode_version; 307189499Srnoland 308112015Sanholt struct { 309112015Sanholt u32 boxes; 310112015Sanholt int freelist_timeouts; 311112015Sanholt int freelist_loops; 312112015Sanholt int requested_bufs; 313112015Sanholt int last_frame_reads; 314112015Sanholt int last_clear_reads; 315112015Sanholt int clears; 316112015Sanholt int texture_uploads; 317112015Sanholt } stats; 31895584Sanholt 319112015Sanholt int do_boxes; 32095584Sanholt int page_flipping; 32195584Sanholt 32295584Sanholt u32 color_fmt; 32395584Sanholt unsigned int front_offset; 32495584Sanholt unsigned int front_pitch; 32595584Sanholt unsigned int back_offset; 32695584Sanholt unsigned int back_pitch; 32795584Sanholt 32895584Sanholt u32 depth_fmt; 32995584Sanholt unsigned int depth_offset; 33095584Sanholt unsigned int depth_pitch; 33195584Sanholt 33295584Sanholt u32 front_pitch_offset; 33395584Sanholt u32 back_pitch_offset; 33495584Sanholt u32 depth_pitch_offset; 33595584Sanholt 33695584Sanholt drm_radeon_depth_clear_t depth_clear; 337145132Sanholt 338113995Sanholt unsigned long ring_offset; 339113995Sanholt unsigned long ring_rptr_offset; 340113995Sanholt unsigned long buffers_offset; 341119895Sanholt unsigned long gart_textures_offset; 34295584Sanholt 343112015Sanholt drm_local_map_t *sarea; 344112015Sanholt drm_local_map_t *cp_ring; 345112015Sanholt drm_local_map_t *ring_rptr; 346119895Sanholt drm_local_map_t *gart_textures; 347112015Sanholt 348119895Sanholt struct mem_block *gart_heap; 349112015Sanholt struct mem_block *fb_heap; 350112015Sanholt 351112015Sanholt /* SW interrupt */ 352145132Sanholt wait_queue_head_t swi_queue; 353145132Sanholt atomic_t swi_emitted; 354182080Srnoland int vblank_crtc; 355182080Srnoland uint32_t irq_enable_reg; 356182080Srnoland int irq_enabled; 357182080Srnoland uint32_t r500_disp_irq_reg; 358112015Sanholt 359145132Sanholt struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 360182080Srnoland struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 361152909Sanholt 362152909Sanholt unsigned long pcigart_offset; 363182080Srnoland unsigned int pcigart_offset_set; 364182080Srnoland struct drm_ati_pcigart_info gart_info; 365157617Sanholt 366157617Sanholt u32 scratch_ages[5]; 367157617Sanholt 368145132Sanholt /* starting from here on, data is preserved accross an open */ 369145132Sanholt uint32_t flags; /* see radeon_chip_flags */ 370182080Srnoland unsigned long fb_aper_offset; 371145132Sanholt 372182080Srnoland int num_gb_pipes; 373196471Srnoland int num_z_pipes; 374182080Srnoland int track_flush; 375189499Srnoland drm_local_map_t *mmio; 376189499Srnoland 377189499Srnoland /* r6xx/r7xx pipe/shader config */ 378189499Srnoland int r600_max_pipes; 379189499Srnoland int r600_max_tile_pipes; 380189499Srnoland int r600_max_simds; 381189499Srnoland int r600_max_backends; 382189499Srnoland int r600_max_gprs; 383189499Srnoland int r600_max_threads; 384189499Srnoland int r600_max_stack_entries; 385189499Srnoland int r600_max_hw_contexts; 386189499Srnoland int r600_max_gs_threads; 387189499Srnoland int r600_sx_max_export_size; 388189499Srnoland int r600_sx_max_export_pos_size; 389189499Srnoland int r600_sx_max_export_smx_size; 390189499Srnoland int r600_sq_num_cf_insts; 391189499Srnoland int r700_sx_num_of_sets; 392189499Srnoland int r700_sc_prim_fifo_size; 393189499Srnoland int r700_sc_hiz_tile_fifo_size; 394189499Srnoland int r700_sc_earlyz_tile_fifo_fize; 395196470Srnoland /* r6xx/r7xx drm blit vertex buffer */ 396196470Srnoland struct drm_buf *blit_vb; 397189499Srnoland 398196470Srnoland /* CS */ 399196470Srnoland struct drm_radeon_cs_priv cs; 400196470Srnoland struct drm_buf *cs_buf; 401196470Srnoland 40295584Sanholt} drm_radeon_private_t; 40395584Sanholt 40495584Sanholttypedef struct drm_radeon_buf_priv { 40595584Sanholt u32 age; 40695584Sanholt} drm_radeon_buf_priv_t; 40795584Sanholt 408157617Sanholttypedef struct drm_radeon_kcmd_buffer { 409157617Sanholt int bufsz; 410157617Sanholt char *buf; 411157617Sanholt int nbox; 412182080Srnoland struct drm_clip_rect __user *boxes; 413157617Sanholt} drm_radeon_kcmd_buffer_t; 414157617Sanholt 415152909Sanholtextern int radeon_no_wb; 416182080Srnolandextern struct drm_ioctl_desc radeon_ioctls[]; 417152909Sanholtextern int radeon_max_ioctl; 418152909Sanholt 419189499Srnolandextern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv); 420189499Srnolandextern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val); 421189499Srnoland 422189499Srnoland#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv) 423189499Srnoland#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val) 424189499Srnoland 425182080Srnoland/* Check whether the given hardware address is inside the framebuffer or the 426182080Srnoland * GART area. 427182080Srnoland */ 428182080Srnolandstatic __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 429182080Srnoland u64 off) 430182080Srnoland{ 431196470Srnoland u64 fb_start = dev_priv->fb_location; 432196470Srnoland u64 fb_end = fb_start + dev_priv->fb_size - 1; 433196470Srnoland u64 gart_start = dev_priv->gart_vm_start; 434196470Srnoland u64 gart_end = gart_start + dev_priv->gart_size - 1; 435182080Srnoland 436182080Srnoland return ((off >= fb_start && off <= fb_end) || 437182080Srnoland (off >= gart_start && off <= gart_end)); 438182080Srnoland} 439182080Srnoland 44095584Sanholt /* radeon_cp.c */ 441182080Srnolandextern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 442182080Srnolandextern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 443182080Srnolandextern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 444182080Srnolandextern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 445182080Srnolandextern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 446182080Srnolandextern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 447182080Srnolandextern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 448182080Srnolandextern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 449182080Srnolandextern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 450182080Srnolandextern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 451189499Srnolandextern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc); 452189499Srnolandextern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base); 453189499Srnolandextern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr); 45495584Sanholt 455182080Srnolandextern void radeon_freelist_reset(struct drm_device * dev); 456182080Srnolandextern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 45795584Sanholt 458145132Sanholtextern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 45995584Sanholt 460145132Sanholtextern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 46195584Sanholt 462189499Srnolandextern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); 463189499Srnolandextern int radeon_presetup(struct drm_device *dev); 464189499Srnolandextern int radeon_driver_postcleanup(struct drm_device *dev); 465189499Srnoland 466182080Srnolandextern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 467182080Srnolandextern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 468182080Srnolandextern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 469145132Sanholtextern void radeon_mem_takedown(struct mem_block **heap); 470182080Srnolandextern void radeon_mem_release(struct drm_file *file_priv, 471182080Srnoland struct mem_block *heap); 47295584Sanholt 473189499Srnolandextern void radeon_enable_bm(struct drm_radeon_private *dev_priv); 474189499Srnolandextern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off); 475189499Srnolandextern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val); 476189499Srnoland 477112015Sanholt /* radeon_irq.c */ 478182080Srnolandextern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 479182080Srnolandextern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 480182080Srnolandextern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 481112015Sanholt 482182080Srnolandextern void radeon_do_release(struct drm_device * dev); 483182080Srnolandextern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 484182080Srnolandextern int radeon_enable_vblank(struct drm_device *dev, int crtc); 485182080Srnolandextern void radeon_disable_vblank(struct drm_device *dev, int crtc); 486145132Sanholtextern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 487182080Srnolandextern void radeon_driver_irq_preinstall(struct drm_device * dev); 488189499Srnolandextern int radeon_driver_irq_postinstall(struct drm_device *dev); 489182080Srnolandextern void radeon_driver_irq_uninstall(struct drm_device * dev); 490189499Srnolandextern void radeon_enable_interrupt(struct drm_device *dev); 491182080Srnolandextern int radeon_vblank_crtc_get(struct drm_device *dev); 492182080Srnolandextern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 493112015Sanholt 494152909Sanholtextern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 495152909Sanholtextern int radeon_driver_unload(struct drm_device *dev); 496152909Sanholtextern int radeon_driver_firstopen(struct drm_device *dev); 497189499Srnolandextern void radeon_driver_preclose(struct drm_device *dev, 498182080Srnoland struct drm_file *file_priv); 499189499Srnolandextern void radeon_driver_postclose(struct drm_device *dev, 500182080Srnoland struct drm_file *file_priv); 501182080Srnolandextern void radeon_driver_lastclose(struct drm_device * dev); 502189499Srnolandextern int radeon_driver_open(struct drm_device *dev, 503189499Srnoland struct drm_file *file_priv); 504152909Sanholtextern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 505189499Srnoland unsigned long arg); 506152909Sanholt 507148211Sanholt/* r300_cmdbuf.c */ 508182080Srnolandextern void r300_init_reg_flags(struct drm_device *dev); 509148211Sanholt 510182080Srnolandextern int r300_do_cp_cmdbuf(struct drm_device *dev, 511182080Srnoland struct drm_file *file_priv, 512182080Srnoland drm_radeon_kcmd_buffer_t *cmdbuf); 513148211Sanholt 514189499Srnoland/* r600_cp.c */ 515189499Srnolandextern int r600_do_engine_reset(struct drm_device *dev); 516189499Srnolandextern int r600_do_cleanup_cp(struct drm_device *dev); 517189499Srnolandextern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 518189499Srnoland struct drm_file *file_priv); 519189499Srnolandextern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv); 520189499Srnolandextern int r600_do_cp_idle(drm_radeon_private_t *dev_priv); 521189499Srnolandextern void r600_do_cp_start(drm_radeon_private_t *dev_priv); 522189499Srnolandextern void r600_do_cp_reset(drm_radeon_private_t *dev_priv); 523189499Srnolandextern void r600_do_cp_stop(drm_radeon_private_t *dev_priv); 524189499Srnolandextern int r600_cp_dispatch_indirect(struct drm_device *dev, 525189499Srnoland struct drm_buf *buf, int start, int end); 526189499Srnolandextern int r600_page_table_init(struct drm_device *dev); 527189499Srnolandextern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); 528196470Srnolandextern void r600_cp_dispatch_swap(struct drm_device * dev); 529196470Srnolandextern int r600_cp_dispatch_texture(struct drm_device * dev, 530196470Srnoland struct drm_file *file_priv, 531196470Srnoland drm_radeon_texture_t * tex, 532196470Srnoland drm_radeon_tex_image_t * image); 533189499Srnoland 534196470Srnoland/* r600_blit.c */ 535196470Srnolandextern int 536196470Srnolandr600_prepare_blit_copy(struct drm_device *dev); 537196470Srnolandextern void 538196470Srnolandr600_done_blit_copy(struct drm_device *dev); 539196470Srnolandextern void 540196470Srnolandr600_blit_copy(struct drm_device *dev, 541196470Srnoland uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 542196470Srnoland int size_bytes); 543196470Srnolandextern void 544196470Srnolandr600_blit_swap(struct drm_device *dev, 545196470Srnoland uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 546196470Srnoland int sx, int sy, int dx, int dy, 547196470Srnoland int w, int h, int src_pitch, int dst_pitch, int cpp); 548196470Srnoland 549196470Srnoland/* radeon_state.c */ 550196470Srnolandextern void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf); 551196470Srnoland 552196470Srnoland/* radeon_cs.c */ 553196470Srnolandextern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); 554196470Srnolandextern int r600_cs_init(struct drm_device *dev); 555196470Srnoland 556112015Sanholt/* Flags for stats.boxes 557112015Sanholt */ 558112015Sanholt#define RADEON_BOX_DMA_IDLE 0x1 559112015Sanholt#define RADEON_BOX_RING_FULL 0x2 560112015Sanholt#define RADEON_BOX_FLIP 0x4 561112015Sanholt#define RADEON_BOX_WAIT_IDLE 0x8 562112015Sanholt#define RADEON_BOX_TEXTURE_LOAD 0x10 563112015Sanholt 56495584Sanholt/* Register definitions, register access macros and drmAddMap constants 56595584Sanholt * for Radeon kernel driver. 56695584Sanholt */ 567189499Srnoland#define RADEON_MM_INDEX 0x0000 568189499Srnoland#define RADEON_MM_DATA 0x0004 569189499Srnoland 570145132Sanholt#define RADEON_AGP_COMMAND 0x0f60 571189499Srnoland#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 572189499Srnoland# define RADEON_AGP_ENABLE (1<<8) 57395584Sanholt#define RADEON_AUX_SCISSOR_CNTL 0x26f0 57495584Sanholt# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 57595584Sanholt# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 57695584Sanholt# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 57795584Sanholt# define RADEON_SCISSOR_0_ENABLE (1 << 28) 57895584Sanholt# define RADEON_SCISSOR_1_ENABLE (1 << 29) 57995584Sanholt# define RADEON_SCISSOR_2_ENABLE (1 << 30) 58095584Sanholt 581183830Srnoland/* 582183830Srnoland * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) 583183830Srnoland * don't have an explicit bus mastering disable bit. It's handled 584183830Srnoland * by the PCI D-states. PMI_BM_DIS disables D-state bus master 585183830Srnoland * handling, not bus mastering itself. 586183830Srnoland */ 58795584Sanholt#define RADEON_BUS_CNTL 0x0030 588184374Srnoland/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 58995584Sanholt# define RADEON_BUS_MASTER_DIS (1 << 6) 590184374Srnoland/* rs600/rs690/rs740 */ 591184374Srnoland# define RS600_BUS_MASTER_DIS (1 << 14) 592184374Srnoland# define RS600_MSI_REARM (1 << 20) 593189499Srnoland/* see RS400_MSI_REARM in AIC_CNTL for rs480 */ 59495584Sanholt 595183830Srnoland#define RADEON_BUS_CNTL1 0x0034 596183830Srnoland# define RADEON_PMI_BM_DIS (1 << 2) 597183830Srnoland# define RADEON_PMI_INT_DIS (1 << 3) 598183830Srnoland 599183830Srnoland#define RV370_BUS_CNTL 0x004c 600183830Srnoland# define RV370_PMI_BM_DIS (1 << 5) 601183830Srnoland# define RV370_PMI_INT_DIS (1 << 6) 602183830Srnoland 603183830Srnoland#define RADEON_MSI_REARM_EN 0x0160 604183830Srnoland/* rv370/rv380, rv410, r423/r430/r480, r5xx */ 605183830Srnoland# define RV370_MSI_REARM_EN (1 << 0) 606183830Srnoland 60795584Sanholt#define RADEON_CLOCK_CNTL_DATA 0x000c 60895584Sanholt# define RADEON_PLL_WR_EN (1 << 7) 60995584Sanholt#define RADEON_CLOCK_CNTL_INDEX 0x0008 61095584Sanholt#define RADEON_CONFIG_APER_SIZE 0x0108 611189499Srnoland#define RADEON_CONFIG_MEMSIZE 0x00f8 61295584Sanholt#define RADEON_CRTC_OFFSET 0x0224 61395584Sanholt#define RADEON_CRTC_OFFSET_CNTL 0x0228 61495584Sanholt# define RADEON_CRTC_TILE_EN (1 << 15) 61595584Sanholt# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 616112015Sanholt#define RADEON_CRTC2_OFFSET 0x0324 617112015Sanholt#define RADEON_CRTC2_OFFSET_CNTL 0x0328 61895584Sanholt 619148211Sanholt#define RADEON_PCIE_INDEX 0x0030 620148211Sanholt#define RADEON_PCIE_DATA 0x0034 621148211Sanholt#define RADEON_PCIE_TX_GART_CNTL 0x10 622182080Srnoland# define RADEON_PCIE_TX_GART_EN (1 << 0) 623182080Srnoland# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 624182080Srnoland# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 625182080Srnoland# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 626182080Srnoland# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 627182080Srnoland# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 628182080Srnoland# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 629182080Srnoland# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 630148211Sanholt#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 631148211Sanholt#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 632182080Srnoland#define RADEON_PCIE_TX_GART_BASE 0x13 633148211Sanholt#define RADEON_PCIE_TX_GART_START_LO 0x14 634148211Sanholt#define RADEON_PCIE_TX_GART_START_HI 0x15 635148211Sanholt#define RADEON_PCIE_TX_GART_END_LO 0x16 636148211Sanholt#define RADEON_PCIE_TX_GART_END_HI 0x17 637148211Sanholt 638182080Srnoland#define RS480_NB_MC_INDEX 0x168 639182080Srnoland# define RS480_NB_MC_IND_WR_EN (1 << 8) 640182080Srnoland#define RS480_NB_MC_DATA 0x16c 641182080Srnoland 642182080Srnoland#define RS690_MC_INDEX 0x78 643182080Srnoland# define RS690_MC_INDEX_MASK 0x1ff 644182080Srnoland# define RS690_MC_INDEX_WR_EN (1 << 9) 645182080Srnoland# define RS690_MC_INDEX_WR_ACK 0x7f 646182080Srnoland#define RS690_MC_DATA 0x7c 647182080Srnoland 648182080Srnoland/* MC indirect registers */ 649182080Srnoland#define RS480_MC_MISC_CNTL 0x18 650182080Srnoland# define RS480_DISABLE_GTW (1 << 1) 651182080Srnoland/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 652182080Srnoland# define RS480_GART_INDEX_REG_EN (1 << 12) 653182080Srnoland# define RS690_BLOCK_GFX_D3_EN (1 << 14) 654182080Srnoland#define RS480_K8_FB_LOCATION 0x1e 655182080Srnoland#define RS480_GART_FEATURE_ID 0x2b 656182080Srnoland# define RS480_HANG_EN (1 << 11) 657182080Srnoland# define RS480_TLB_ENABLE (1 << 18) 658182080Srnoland# define RS480_P2P_ENABLE (1 << 19) 659182080Srnoland# define RS480_GTW_LAC_EN (1 << 25) 660182080Srnoland# define RS480_2LEVEL_GART (0 << 30) 661182080Srnoland# define RS480_1LEVEL_GART (1 << 30) 662261455Seadler# define RS480_PDC_EN (1U << 31) 663182080Srnoland#define RS480_GART_BASE 0x2c 664182080Srnoland#define RS480_GART_CACHE_CNTRL 0x2e 665182080Srnoland# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 666182080Srnoland#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 667182080Srnoland# define RS480_GART_EN (1 << 0) 668182080Srnoland# define RS480_VA_SIZE_32MB (0 << 1) 669182080Srnoland# define RS480_VA_SIZE_64MB (1 << 1) 670182080Srnoland# define RS480_VA_SIZE_128MB (2 << 1) 671182080Srnoland# define RS480_VA_SIZE_256MB (3 << 1) 672182080Srnoland# define RS480_VA_SIZE_512MB (4 << 1) 673182080Srnoland# define RS480_VA_SIZE_1GB (5 << 1) 674182080Srnoland# define RS480_VA_SIZE_2GB (6 << 1) 675182080Srnoland#define RS480_AGP_MODE_CNTL 0x39 676182080Srnoland# define RS480_POST_GART_Q_SIZE (1 << 18) 677182080Srnoland# define RS480_NONGART_SNOOP (1 << 19) 678182080Srnoland# define RS480_AGP_RD_BUF_SIZE (1 << 20) 679182080Srnoland# define RS480_REQ_TYPE_SNOOP_SHIFT 22 680182080Srnoland# define RS480_REQ_TYPE_SNOOP_MASK 0x3 681182080Srnoland# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 682182080Srnoland#define RS480_MC_MISC_UMA_CNTL 0x5f 683182080Srnoland#define RS480_MC_MCLK_CNTL 0x7a 684182080Srnoland#define RS480_MC_UMA_DUALCH_CNTL 0x86 685182080Srnoland 686182080Srnoland#define RS690_MC_FB_LOCATION 0x100 687182080Srnoland#define RS690_MC_AGP_LOCATION 0x101 688182080Srnoland#define RS690_MC_AGP_BASE 0x102 689182080Srnoland#define RS690_MC_AGP_BASE_2 0x103 690182080Srnoland 691189499Srnoland#define RS600_MC_INDEX 0x70 692189499Srnoland# define RS600_MC_ADDR_MASK 0xffff 693189499Srnoland# define RS600_MC_IND_SEQ_RBS_0 (1 << 16) 694189499Srnoland# define RS600_MC_IND_SEQ_RBS_1 (1 << 17) 695189499Srnoland# define RS600_MC_IND_SEQ_RBS_2 (1 << 18) 696189499Srnoland# define RS600_MC_IND_SEQ_RBS_3 (1 << 19) 697189499Srnoland# define RS600_MC_IND_AIC_RBS (1 << 20) 698189499Srnoland# define RS600_MC_IND_CITF_ARB0 (1 << 21) 699189499Srnoland# define RS600_MC_IND_CITF_ARB1 (1 << 22) 700189499Srnoland# define RS600_MC_IND_WR_EN (1 << 23) 701189499Srnoland#define RS600_MC_DATA 0x74 702189499Srnoland 703189499Srnoland#define RS600_MC_STATUS 0x0 704189499Srnoland# define RS600_MC_IDLE (1 << 1) 705189499Srnoland#define RS600_MC_FB_LOCATION 0x4 706189499Srnoland#define RS600_MC_AGP_LOCATION 0x5 707189499Srnoland#define RS600_AGP_BASE 0x6 708189499Srnoland#define RS600_AGP_BASE_2 0x7 709189499Srnoland#define RS600_MC_CNTL1 0x9 710189499Srnoland# define RS600_ENABLE_PAGE_TABLES (1 << 26) 711189499Srnoland#define RS600_MC_PT0_CNTL 0x100 712189499Srnoland# define RS600_ENABLE_PT (1 << 0) 713189499Srnoland# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) 714189499Srnoland# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) 715189499Srnoland# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) 716189499Srnoland# define RS600_INVALIDATE_L2_CACHE (1 << 29) 717189499Srnoland#define RS600_MC_PT0_CONTEXT0_CNTL 0x102 718189499Srnoland# define RS600_ENABLE_PAGE_TABLE (1 << 0) 719189499Srnoland# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) 720189499Srnoland#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 721189499Srnoland#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 722189499Srnoland#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c 723189499Srnoland#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c 724189499Srnoland#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c 725189499Srnoland#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c 726189499Srnoland#define RS600_MC_PT0_CLIENT0_CNTL 0x16c 727189499Srnoland# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) 728189499Srnoland# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) 729189499Srnoland# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) 730189499Srnoland# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) 731189499Srnoland# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) 732189499Srnoland# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) 733189499Srnoland# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) 734189499Srnoland# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) 735189499Srnoland# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) 736189499Srnoland# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) 737189499Srnoland# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) 738189499Srnoland# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 739189499Srnoland# define RS600_INVALIDATE_L1_TLB (1 << 20) 740189499Srnoland 741182080Srnoland#define R520_MC_IND_INDEX 0x70 742182080Srnoland#define R520_MC_IND_WR_EN (1 << 24) 743182080Srnoland#define R520_MC_IND_DATA 0x74 744182080Srnoland 745182080Srnoland#define RV515_MC_FB_LOCATION 0x01 746182080Srnoland#define RV515_MC_AGP_LOCATION 0x02 747182080Srnoland#define RV515_MC_AGP_BASE 0x03 748182080Srnoland#define RV515_MC_AGP_BASE_2 0x04 749182080Srnoland 750182080Srnoland#define R520_MC_FB_LOCATION 0x04 751182080Srnoland#define R520_MC_AGP_LOCATION 0x05 752182080Srnoland#define R520_MC_AGP_BASE 0x06 753182080Srnoland#define R520_MC_AGP_BASE_2 0x07 754182080Srnoland 755145132Sanholt#define RADEON_MPP_TB_CONFIG 0x01c0 756145132Sanholt#define RADEON_MEM_CNTL 0x0140 757145132Sanholt#define RADEON_MEM_SDRAM_MODE_REG 0x0158 758182080Srnoland#define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 759182080Srnoland#define RS480_AGP_BASE_2 0x0164 760145132Sanholt#define RADEON_AGP_BASE 0x0170 761145132Sanholt 762182080Srnoland/* pipe config regs */ 763182080Srnoland#define R400_GB_PIPE_SELECT 0x402c 764196471Srnoland#define RV530_GB_PIPE_SELECT2 0x4124 765182080Srnoland#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 766182080Srnoland#define R300_GB_TILE_CONFIG 0x4018 767182080Srnoland# define R300_ENABLE_TILING (1 << 0) 768182080Srnoland# define R300_PIPE_COUNT_RV350 (0 << 1) 769182080Srnoland# define R300_PIPE_COUNT_R300 (3 << 1) 770182080Srnoland# define R300_PIPE_COUNT_R420_3P (6 << 1) 771182080Srnoland# define R300_PIPE_COUNT_R420 (7 << 1) 772182080Srnoland# define R300_TILE_SIZE_8 (0 << 4) 773182080Srnoland# define R300_TILE_SIZE_16 (1 << 4) 774182080Srnoland# define R300_TILE_SIZE_32 (2 << 4) 775182080Srnoland# define R300_SUBPIXEL_1_12 (0 << 16) 776182080Srnoland# define R300_SUBPIXEL_1_16 (1 << 16) 777182080Srnoland#define R300_DST_PIPE_CONFIG 0x170c 778261455Seadler# define R300_PIPE_AUTO_CONFIG (1U << 31) 779182080Srnoland#define R300_RB2D_DSTCACHE_MODE 0x3428 780182080Srnoland# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 781182080Srnoland# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 782182080Srnoland 783122580Sanholt#define RADEON_RB3D_COLOROFFSET 0x1c40 78495584Sanholt#define RADEON_RB3D_COLORPITCH 0x1c48 78595584Sanholt 786182080Srnoland#define RADEON_SRC_X_Y 0x1590 787182080Srnoland 78895584Sanholt#define RADEON_DP_GUI_MASTER_CNTL 0x146c 78995584Sanholt# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 79095584Sanholt# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 79195584Sanholt# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 79295584Sanholt# define RADEON_GMC_BRUSH_NONE (15 << 4) 79395584Sanholt# define RADEON_GMC_DST_16BPP (4 << 8) 79495584Sanholt# define RADEON_GMC_DST_24BPP (5 << 8) 79595584Sanholt# define RADEON_GMC_DST_32BPP (6 << 8) 79695584Sanholt# define RADEON_GMC_DST_DATATYPE_SHIFT 8 79795584Sanholt# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 79895584Sanholt# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 79995584Sanholt# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 80095584Sanholt# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 80195584Sanholt# define RADEON_GMC_WR_MSK_DIS (1 << 30) 80295584Sanholt# define RADEON_ROP3_S 0x00cc0000 80395584Sanholt# define RADEON_ROP3_P 0x00f00000 80495584Sanholt#define RADEON_DP_WRITE_MASK 0x16cc 805182080Srnoland#define RADEON_SRC_PITCH_OFFSET 0x1428 80695584Sanholt#define RADEON_DST_PITCH_OFFSET 0x142c 80795584Sanholt#define RADEON_DST_PITCH_OFFSET_C 0x1c80 80895584Sanholt# define RADEON_DST_TILE_LINEAR (0 << 30) 80995584Sanholt# define RADEON_DST_TILE_MACRO (1 << 30) 810261455Seadler# define RADEON_DST_TILE_MICRO (2U << 30) 811261455Seadler# define RADEON_DST_TILE_BOTH (3U << 30) 81295584Sanholt 81395584Sanholt#define RADEON_SCRATCH_REG0 0x15e0 81495584Sanholt#define RADEON_SCRATCH_REG1 0x15e4 81595584Sanholt#define RADEON_SCRATCH_REG2 0x15e8 81695584Sanholt#define RADEON_SCRATCH_REG3 0x15ec 81795584Sanholt#define RADEON_SCRATCH_REG4 0x15f0 81895584Sanholt#define RADEON_SCRATCH_REG5 0x15f4 81995584Sanholt#define RADEON_SCRATCH_UMSK 0x0770 82095584Sanholt#define RADEON_SCRATCH_ADDR 0x0774 82195584Sanholt 822112015Sanholt#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 823112015Sanholt 824189499Srnolandextern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); 825112015Sanholt 826189499Srnoland#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x) 827182080Srnoland 828189499Srnoland#define R600_SCRATCH_REG0 0x8500 829189499Srnoland#define R600_SCRATCH_REG1 0x8504 830189499Srnoland#define R600_SCRATCH_REG2 0x8508 831189499Srnoland#define R600_SCRATCH_REG3 0x850c 832189499Srnoland#define R600_SCRATCH_REG4 0x8510 833189499Srnoland#define R600_SCRATCH_REG5 0x8514 834189499Srnoland#define R600_SCRATCH_REG6 0x8518 835189499Srnoland#define R600_SCRATCH_REG7 0x851c 836189499Srnoland#define R600_SCRATCH_UMSK 0x8540 837189499Srnoland#define R600_SCRATCH_ADDR 0x8544 838182080Srnoland 839189499Srnoland#define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x)) 840189499Srnoland 841112015Sanholt#define RADEON_GEN_INT_CNTL 0x0040 842112015Sanholt# define RADEON_CRTC_VBLANK_MASK (1 << 0) 843182080Srnoland# define RADEON_CRTC2_VBLANK_MASK (1 << 9) 844112015Sanholt# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 845112015Sanholt# define RADEON_SW_INT_ENABLE (1 << 25) 846112015Sanholt 847112015Sanholt#define RADEON_GEN_INT_STATUS 0x0044 848112015Sanholt# define RADEON_CRTC_VBLANK_STAT (1 << 0) 849182080Srnoland# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 850182080Srnoland# define RADEON_CRTC2_VBLANK_STAT (1 << 9) 851182080Srnoland# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 852112015Sanholt# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 853112015Sanholt# define RADEON_SW_INT_TEST (1 << 25) 854182080Srnoland# define RADEON_SW_INT_TEST_ACK (1 << 25) 855112015Sanholt# define RADEON_SW_INT_FIRE (1 << 26) 856182080Srnoland# define R500_DISPLAY_INT_STATUS (1 << 0) 857112015Sanholt 85895584Sanholt#define RADEON_HOST_PATH_CNTL 0x0130 85995584Sanholt# define RADEON_HDP_SOFT_RESET (1 << 26) 86095584Sanholt# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 86195584Sanholt# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 86295584Sanholt 86395584Sanholt#define RADEON_ISYNC_CNTL 0x1724 86495584Sanholt# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 86595584Sanholt# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 86695584Sanholt# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 86795584Sanholt# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 86895584Sanholt# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 86995584Sanholt# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 87095584Sanholt 871112015Sanholt#define RADEON_RBBM_GUICNTL 0x172c 872112015Sanholt# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 873112015Sanholt# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 874112015Sanholt# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 875112015Sanholt# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 876112015Sanholt 87795584Sanholt#define RADEON_MC_AGP_LOCATION 0x014c 87895584Sanholt#define RADEON_MC_FB_LOCATION 0x0148 87995584Sanholt#define RADEON_MCLK_CNTL 0x0012 88095584Sanholt# define RADEON_FORCEON_MCLKA (1 << 16) 88195584Sanholt# define RADEON_FORCEON_MCLKB (1 << 17) 88295584Sanholt# define RADEON_FORCEON_YCLKA (1 << 18) 88395584Sanholt# define RADEON_FORCEON_YCLKB (1 << 19) 88495584Sanholt# define RADEON_FORCEON_MC (1 << 20) 88595584Sanholt# define RADEON_FORCEON_AIC (1 << 21) 88695584Sanholt 88795584Sanholt#define RADEON_PP_BORDER_COLOR_0 0x1d40 88895584Sanholt#define RADEON_PP_BORDER_COLOR_1 0x1d44 88995584Sanholt#define RADEON_PP_BORDER_COLOR_2 0x1d48 89095584Sanholt#define RADEON_PP_CNTL 0x1c38 89195584Sanholt# define RADEON_SCISSOR_ENABLE (1 << 1) 89295584Sanholt#define RADEON_PP_LUM_MATRIX 0x1d00 89395584Sanholt#define RADEON_PP_MISC 0x1c14 89495584Sanholt#define RADEON_PP_ROT_MATRIX_0 0x1d58 89595584Sanholt#define RADEON_PP_TXFILTER_0 0x1c54 896122580Sanholt#define RADEON_PP_TXOFFSET_0 0x1c5c 89795584Sanholt#define RADEON_PP_TXFILTER_1 0x1c6c 89895584Sanholt#define RADEON_PP_TXFILTER_2 0x1c84 89995584Sanholt 900182080Srnoland#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 901182080Srnoland#define R300_DSTCACHE_CTLSTAT 0x1714 902182080Srnoland# define R300_RB2D_DC_FLUSH (3 << 0) 903182080Srnoland# define R300_RB2D_DC_FREE (3 << 2) 904182080Srnoland# define R300_RB2D_DC_FLUSH_ALL 0xf 905261455Seadler# define R300_RB2D_DC_BUSY (1U << 31) 90695584Sanholt#define RADEON_RB3D_CNTL 0x1c3c 90795584Sanholt# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 90895584Sanholt# define RADEON_PLANE_MASK_ENABLE (1 << 1) 90995584Sanholt# define RADEON_DITHER_ENABLE (1 << 2) 91095584Sanholt# define RADEON_ROUND_ENABLE (1 << 3) 91195584Sanholt# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 91295584Sanholt# define RADEON_DITHER_INIT (1 << 5) 91395584Sanholt# define RADEON_ROP_ENABLE (1 << 6) 91495584Sanholt# define RADEON_STENCIL_ENABLE (1 << 7) 91595584Sanholt# define RADEON_Z_ENABLE (1 << 8) 916145132Sanholt# define RADEON_ZBLOCK16 (1 << 15) 91795584Sanholt#define RADEON_RB3D_DEPTHOFFSET 0x1c24 918145132Sanholt#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 919112015Sanholt#define RADEON_RB3D_DEPTHPITCH 0x1c28 92095584Sanholt#define RADEON_RB3D_PLANEMASK 0x1d84 92195584Sanholt#define RADEON_RB3D_STENCILREFMASK 0x1d7c 92295584Sanholt#define RADEON_RB3D_ZCACHE_MODE 0x3250 92395584Sanholt#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 92495584Sanholt# define RADEON_RB3D_ZC_FLUSH (1 << 0) 92595584Sanholt# define RADEON_RB3D_ZC_FREE (1 << 2) 92695584Sanholt# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 927261455Seadler# define RADEON_RB3D_ZC_BUSY (1U << 31) 928182080Srnoland#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 929182080Srnoland# define R300_ZC_FLUSH (1 << 0) 930182080Srnoland# define R300_ZC_FREE (1 << 1) 931261455Seadler# define R300_ZC_BUSY (1U << 31) 932189499Srnoland#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 933162132Sanholt# define RADEON_RB3D_DC_FLUSH (3 << 0) 934162132Sanholt# define RADEON_RB3D_DC_FREE (3 << 2) 935162132Sanholt# define RADEON_RB3D_DC_FLUSH_ALL 0xf 936261455Seadler# define RADEON_RB3D_DC_BUSY (1U << 31) 937182080Srnoland#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 938182080Srnoland# define R300_RB3D_DC_FLUSH (2 << 0) 939182080Srnoland# define R300_RB3D_DC_FREE (2 << 2) 940182080Srnoland# define R300_RB3D_DC_FINISH (1 << 4) 94195584Sanholt#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 94295584Sanholt# define RADEON_Z_TEST_MASK (7 << 4) 94395584Sanholt# define RADEON_Z_TEST_ALWAYS (7 << 4) 944189499Srnoland# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 94595584Sanholt# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 946112015Sanholt# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 947112015Sanholt# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 948112015Sanholt# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 949189499Srnoland# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 950189499Srnoland# define RADEON_FORCE_Z_DIRTY (1 << 29) 95195584Sanholt# define RADEON_Z_WRITE_ENABLE (1 << 30) 952261455Seadler# define RADEON_Z_DECOMPRESSION_ENABLE (1U << 31) 95395584Sanholt#define RADEON_RBBM_SOFT_RESET 0x00f0 95495584Sanholt# define RADEON_SOFT_RESET_CP (1 << 0) 95595584Sanholt# define RADEON_SOFT_RESET_HI (1 << 1) 95695584Sanholt# define RADEON_SOFT_RESET_SE (1 << 2) 95795584Sanholt# define RADEON_SOFT_RESET_RE (1 << 3) 95895584Sanholt# define RADEON_SOFT_RESET_PP (1 << 4) 95995584Sanholt# define RADEON_SOFT_RESET_E2 (1 << 5) 96095584Sanholt# define RADEON_SOFT_RESET_RB (1 << 6) 96195584Sanholt# define RADEON_SOFT_RESET_HDP (1 << 7) 962182080Srnoland/* 963182080Srnoland * 6:0 Available slots in the FIFO 964182080Srnoland * 8 Host Interface active 965182080Srnoland * 9 CP request active 966182080Srnoland * 10 FIFO request active 967182080Srnoland * 11 Host Interface retry active 968182080Srnoland * 12 CP retry active 969182080Srnoland * 13 FIFO retry active 970182080Srnoland * 14 FIFO pipeline busy 971182080Srnoland * 15 Event engine busy 972182080Srnoland * 16 CP command stream busy 973182080Srnoland * 17 2D engine busy 974182080Srnoland * 18 2D portion of render backend busy 975182080Srnoland * 20 3D setup engine busy 976182080Srnoland * 26 GA engine busy 977182080Srnoland * 27 CBA 2D engine busy 978182080Srnoland * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 979182080Srnoland * command stream queue not empty or Ring Buffer not empty 980182080Srnoland */ 98195584Sanholt#define RADEON_RBBM_STATUS 0x0e40 982182080Srnoland/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 983182080Srnoland/* #define RADEON_RBBM_STATUS 0x1740 */ 984182080Srnoland/* bits 6:0 are dword slots available in the cmd fifo */ 98595584Sanholt# define RADEON_RBBM_FIFOCNT_MASK 0x007f 986182080Srnoland# define RADEON_HIRQ_ON_RBB (1 << 8) 987182080Srnoland# define RADEON_CPRQ_ON_RBB (1 << 9) 988182080Srnoland# define RADEON_CFRQ_ON_RBB (1 << 10) 989182080Srnoland# define RADEON_HIRQ_IN_RTBUF (1 << 11) 990182080Srnoland# define RADEON_CPRQ_IN_RTBUF (1 << 12) 991182080Srnoland# define RADEON_CFRQ_IN_RTBUF (1 << 13) 992182080Srnoland# define RADEON_PIPE_BUSY (1 << 14) 993182080Srnoland# define RADEON_ENG_EV_BUSY (1 << 15) 994182080Srnoland# define RADEON_CP_CMDSTRM_BUSY (1 << 16) 995182080Srnoland# define RADEON_E2_BUSY (1 << 17) 996182080Srnoland# define RADEON_RB2D_BUSY (1 << 18) 997182080Srnoland# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 998182080Srnoland# define RADEON_VAP_BUSY (1 << 20) 999182080Srnoland# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 1000182080Srnoland# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 1001182080Srnoland# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 1002182080Srnoland# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 1003182080Srnoland# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 1004182080Srnoland# define RADEON_GA_BUSY (1 << 26) 1005182080Srnoland# define RADEON_CBA2D_BUSY (1 << 27) 1006261455Seadler# define RADEON_RBBM_ACTIVE (1U << 31) 100795584Sanholt#define RADEON_RE_LINE_PATTERN 0x1cd0 100895584Sanholt#define RADEON_RE_MISC 0x26c4 100995584Sanholt#define RADEON_RE_TOP_LEFT 0x26c0 101095584Sanholt#define RADEON_RE_WIDTH_HEIGHT 0x1c44 101195584Sanholt#define RADEON_RE_STIPPLE_ADDR 0x1cc8 101295584Sanholt#define RADEON_RE_STIPPLE_DATA 0x1ccc 101395584Sanholt 101495584Sanholt#define RADEON_SCISSOR_TL_0 0x1cd8 101595584Sanholt#define RADEON_SCISSOR_BR_0 0x1cdc 101695584Sanholt#define RADEON_SCISSOR_TL_1 0x1ce0 101795584Sanholt#define RADEON_SCISSOR_BR_1 0x1ce4 101895584Sanholt#define RADEON_SCISSOR_TL_2 0x1ce8 101995584Sanholt#define RADEON_SCISSOR_BR_2 0x1cec 102095584Sanholt#define RADEON_SE_COORD_FMT 0x1c50 102195584Sanholt#define RADEON_SE_CNTL 0x1c4c 102295584Sanholt# define RADEON_FFACE_CULL_CW (0 << 0) 102395584Sanholt# define RADEON_BFACE_SOLID (3 << 1) 102495584Sanholt# define RADEON_FFACE_SOLID (3 << 3) 102595584Sanholt# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 102695584Sanholt# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 102795584Sanholt# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 102895584Sanholt# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 102995584Sanholt# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 103095584Sanholt# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 103195584Sanholt# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 103295584Sanholt# define RADEON_FOG_SHADE_FLAT (1 << 14) 103395584Sanholt# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 103495584Sanholt# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 103595584Sanholt# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 103695584Sanholt# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 103795584Sanholt# define RADEON_ROUND_MODE_TRUNC (0 << 28) 103895584Sanholt# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 103995584Sanholt#define RADEON_SE_CNTL_STATUS 0x2140 104095584Sanholt#define RADEON_SE_LINE_WIDTH 0x1db8 104195584Sanholt#define RADEON_SE_VPORT_XSCALE 0x1d98 1042112015Sanholt#define RADEON_SE_ZBIAS_FACTOR 0x1db0 1043112015Sanholt#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 1044112015Sanholt#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 1045112015Sanholt#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 1046112015Sanholt# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 1047112015Sanholt# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 1048112015Sanholt#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 1049112015Sanholt#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 1050112015Sanholt# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 1051112015Sanholt#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 105295584Sanholt#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 105395584Sanholt#define RADEON_SURFACE_ACCESS_CLR 0x0bfc 105495584Sanholt#define RADEON_SURFACE_CNTL 0x0b00 105595584Sanholt# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 105695584Sanholt# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 105795584Sanholt# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 105895584Sanholt# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 105995584Sanholt# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 106095584Sanholt# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 106195584Sanholt# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 106295584Sanholt# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 106395584Sanholt# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 106495584Sanholt#define RADEON_SURFACE0_INFO 0x0b0c 106595584Sanholt# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 106695584Sanholt# define RADEON_SURF_TILE_MODE_MASK (3 << 16) 106795584Sanholt# define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 106895584Sanholt# define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 106995584Sanholt# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 107095584Sanholt# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 107195584Sanholt#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 107295584Sanholt#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 1073145132Sanholt# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 107495584Sanholt#define RADEON_SURFACE1_INFO 0x0b1c 107595584Sanholt#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 107695584Sanholt#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 107795584Sanholt#define RADEON_SURFACE2_INFO 0x0b2c 107895584Sanholt#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 107995584Sanholt#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 108095584Sanholt#define RADEON_SURFACE3_INFO 0x0b3c 108195584Sanholt#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 108295584Sanholt#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 108395584Sanholt#define RADEON_SURFACE4_INFO 0x0b4c 108495584Sanholt#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 108595584Sanholt#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 108695584Sanholt#define RADEON_SURFACE5_INFO 0x0b5c 108795584Sanholt#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 108895584Sanholt#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 108995584Sanholt#define RADEON_SURFACE6_INFO 0x0b6c 109095584Sanholt#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 109195584Sanholt#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 109295584Sanholt#define RADEON_SURFACE7_INFO 0x0b7c 109395584Sanholt#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 109495584Sanholt#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 109595584Sanholt#define RADEON_SW_SEMAPHORE 0x013c 109695584Sanholt 109795584Sanholt#define RADEON_WAIT_UNTIL 0x1720 109895584Sanholt# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 1099148211Sanholt# define RADEON_WAIT_2D_IDLE (1 << 14) 1100148211Sanholt# define RADEON_WAIT_3D_IDLE (1 << 15) 110195584Sanholt# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 110295584Sanholt# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 110395584Sanholt# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 110495584Sanholt 1105145132Sanholt#define RADEON_RB3D_ZMASKOFFSET 0x3234 110695584Sanholt#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 110795584Sanholt# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 110895584Sanholt# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 110995584Sanholt 111095584Sanholt/* CP registers */ 111195584Sanholt#define RADEON_CP_ME_RAM_ADDR 0x07d4 111295584Sanholt#define RADEON_CP_ME_RAM_RADDR 0x07d8 111395584Sanholt#define RADEON_CP_ME_RAM_DATAH 0x07dc 111495584Sanholt#define RADEON_CP_ME_RAM_DATAL 0x07e0 111595584Sanholt 111695584Sanholt#define RADEON_CP_RB_BASE 0x0700 111795584Sanholt#define RADEON_CP_RB_CNTL 0x0704 1118112015Sanholt# define RADEON_BUF_SWAP_32BIT (2 << 16) 1119162132Sanholt# define RADEON_RB_NO_UPDATE (1 << 27) 1120261455Seadler# define RADEON_RB_RPTR_WR_ENA (1U << 31) 112195584Sanholt#define RADEON_CP_RB_RPTR_ADDR 0x070c 112295584Sanholt#define RADEON_CP_RB_RPTR 0x0710 112395584Sanholt#define RADEON_CP_RB_WPTR 0x0714 112495584Sanholt 112595584Sanholt#define RADEON_CP_RB_WPTR_DELAY 0x0718 112695584Sanholt# define RADEON_PRE_WRITE_TIMER_SHIFT 0 112795584Sanholt# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 112895584Sanholt 112995584Sanholt#define RADEON_CP_IB_BASE 0x0738 113095584Sanholt 113195584Sanholt#define RADEON_CP_CSQ_CNTL 0x0740 113295584Sanholt# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 113395584Sanholt# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 113495584Sanholt# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 113595584Sanholt# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 113695584Sanholt# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 113795584Sanholt# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 113895584Sanholt# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 113995584Sanholt 114095584Sanholt#define RADEON_AIC_CNTL 0x01d0 114195584Sanholt# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 1142184374Srnoland# define RS400_MSI_REARM (1 << 3) 114395584Sanholt#define RADEON_AIC_STAT 0x01d4 114495584Sanholt#define RADEON_AIC_PT_BASE 0x01d8 114595584Sanholt#define RADEON_AIC_LO_ADDR 0x01dc 114695584Sanholt#define RADEON_AIC_HI_ADDR 0x01e0 114795584Sanholt#define RADEON_AIC_TLB_ADDR 0x01e4 114895584Sanholt#define RADEON_AIC_TLB_DATA 0x01e8 114995584Sanholt 115095584Sanholt/* CP command packets */ 115195584Sanholt#define RADEON_CP_PACKET0 0x00000000 115295584Sanholt# define RADEON_ONE_REG_WR (1 << 15) 115395584Sanholt#define RADEON_CP_PACKET1 0x40000000 115495584Sanholt#define RADEON_CP_PACKET2 0x80000000 115595584Sanholt#define RADEON_CP_PACKET3 0xC0000000 1156148211Sanholt# define RADEON_CP_NOP 0x00001000 1157148211Sanholt# define RADEON_CP_NEXT_CHAR 0x00001900 1158148211Sanholt# define RADEON_CP_PLY_NEXTSCAN 0x00001D00 1159148211Sanholt# define RADEON_CP_SET_SCISSORS 0x00001E00 1160189499Srnoland /* GEN_INDX_PRIM is unsupported starting with R300 */ 116195584Sanholt# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 116295584Sanholt# define RADEON_WAIT_FOR_IDLE 0x00002600 1163112015Sanholt# define RADEON_3D_DRAW_VBUF 0x00002800 116495584Sanholt# define RADEON_3D_DRAW_IMMD 0x00002900 1165112015Sanholt# define RADEON_3D_DRAW_INDX 0x00002A00 1166148211Sanholt# define RADEON_CP_LOAD_PALETTE 0x00002C00 1167112015Sanholt# define RADEON_3D_LOAD_VBPNTR 0x00002F00 1168145132Sanholt# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 1169145132Sanholt# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 1170145132Sanholt# define RADEON_3D_CLEAR_ZMASK 0x00003200 1171148211Sanholt# define RADEON_CP_INDX_BUFFER 0x00003300 1172148211Sanholt# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 1173148211Sanholt# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 1174148211Sanholt# define RADEON_CP_3D_DRAW_INDX_2 0x00003600 1175145132Sanholt# define RADEON_3D_CLEAR_HIZ 0x00003700 1176148211Sanholt# define RADEON_CP_3D_CLEAR_CMASK 0x00003802 117795584Sanholt# define RADEON_CNTL_HOSTDATA_BLT 0x00009400 117895584Sanholt# define RADEON_CNTL_PAINT_MULTI 0x00009A00 117995584Sanholt# define RADEON_CNTL_BITBLT_MULTI 0x00009B00 1180112015Sanholt# define RADEON_CNTL_SET_SCISSORS 0xC0001E00 118195584Sanholt 1182189499Srnoland# define R600_IT_INDIRECT_BUFFER 0x00003200 1183189499Srnoland# define R600_IT_ME_INITIALIZE 0x00004400 1184189499Srnoland# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1185189499Srnoland# define R600_IT_EVENT_WRITE 0x00004600 1186189499Srnoland# define R600_IT_SET_CONFIG_REG 0x00006800 1187189499Srnoland# define R600_SET_CONFIG_REG_OFFSET 0x00008000 1188189499Srnoland# define R600_SET_CONFIG_REG_END 0x0000ac00 1189189499Srnoland 119095584Sanholt#define RADEON_CP_PACKET_MASK 0xC0000000 119195584Sanholt#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 119295584Sanholt#define RADEON_CP_PACKET0_REG_MASK 0x000007ff 119395584Sanholt#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 119495584Sanholt#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 119595584Sanholt 1196261455Seadler#define RADEON_VTX_Z_PRESENT (1U << 31) 1197112015Sanholt#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 119895584Sanholt 119995584Sanholt#define RADEON_PRIM_TYPE_NONE (0 << 0) 120095584Sanholt#define RADEON_PRIM_TYPE_POINT (1 << 0) 120195584Sanholt#define RADEON_PRIM_TYPE_LINE (2 << 0) 120295584Sanholt#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 120395584Sanholt#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 120495584Sanholt#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 120595584Sanholt#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 120695584Sanholt#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 120795584Sanholt#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 120895584Sanholt#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 120995584Sanholt#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1210112015Sanholt#define RADEON_PRIM_TYPE_MASK 0xf 121195584Sanholt#define RADEON_PRIM_WALK_IND (1 << 4) 121295584Sanholt#define RADEON_PRIM_WALK_LIST (2 << 4) 121395584Sanholt#define RADEON_PRIM_WALK_RING (3 << 4) 121495584Sanholt#define RADEON_COLOR_ORDER_BGRA (0 << 6) 121595584Sanholt#define RADEON_COLOR_ORDER_RGBA (1 << 6) 121695584Sanholt#define RADEON_MAOS_ENABLE (1 << 7) 121795584Sanholt#define RADEON_VTX_FMT_R128_MODE (0 << 8) 121895584Sanholt#define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 121995584Sanholt#define RADEON_NUM_VERTICES_SHIFT 16 122095584Sanholt 122195584Sanholt#define RADEON_COLOR_FORMAT_CI8 2 122295584Sanholt#define RADEON_COLOR_FORMAT_ARGB1555 3 122395584Sanholt#define RADEON_COLOR_FORMAT_RGB565 4 122495584Sanholt#define RADEON_COLOR_FORMAT_ARGB8888 6 122595584Sanholt#define RADEON_COLOR_FORMAT_RGB332 7 122695584Sanholt#define RADEON_COLOR_FORMAT_RGB8 9 122795584Sanholt#define RADEON_COLOR_FORMAT_ARGB4444 15 122895584Sanholt 122995584Sanholt#define RADEON_TXFORMAT_I8 0 123095584Sanholt#define RADEON_TXFORMAT_AI88 1 123195584Sanholt#define RADEON_TXFORMAT_RGB332 2 123295584Sanholt#define RADEON_TXFORMAT_ARGB1555 3 123395584Sanholt#define RADEON_TXFORMAT_RGB565 4 123495584Sanholt#define RADEON_TXFORMAT_ARGB4444 5 123595584Sanholt#define RADEON_TXFORMAT_ARGB8888 6 123695584Sanholt#define RADEON_TXFORMAT_RGBA8888 7 1237119098Sanholt#define RADEON_TXFORMAT_Y8 8 1238112015Sanholt#define RADEON_TXFORMAT_VYUY422 10 1239112015Sanholt#define RADEON_TXFORMAT_YVYU422 11 1240112015Sanholt#define RADEON_TXFORMAT_DXT1 12 1241112015Sanholt#define RADEON_TXFORMAT_DXT23 14 1242112015Sanholt#define RADEON_TXFORMAT_DXT45 15 124395584Sanholt 1244112015Sanholt#define R200_PP_TXCBLEND_0 0x2f00 1245112015Sanholt#define R200_PP_TXCBLEND_1 0x2f10 1246112015Sanholt#define R200_PP_TXCBLEND_2 0x2f20 1247112015Sanholt#define R200_PP_TXCBLEND_3 0x2f30 1248112015Sanholt#define R200_PP_TXCBLEND_4 0x2f40 1249112015Sanholt#define R200_PP_TXCBLEND_5 0x2f50 1250112015Sanholt#define R200_PP_TXCBLEND_6 0x2f60 1251112015Sanholt#define R200_PP_TXCBLEND_7 0x2f70 1252145132Sanholt#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1253112015Sanholt#define R200_PP_TFACTOR_0 0x2ee0 1254112015Sanholt#define R200_SE_VTX_FMT_0 0x2088 1255112015Sanholt#define R200_SE_VAP_CNTL 0x2080 1256112015Sanholt#define R200_SE_TCL_MATRIX_SEL_0 0x2230 1257145132Sanholt#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1258145132Sanholt#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1259145132Sanholt#define R200_PP_TXFILTER_5 0x2ca0 1260145132Sanholt#define R200_PP_TXFILTER_4 0x2c80 1261145132Sanholt#define R200_PP_TXFILTER_3 0x2c60 1262145132Sanholt#define R200_PP_TXFILTER_2 0x2c40 1263145132Sanholt#define R200_PP_TXFILTER_1 0x2c20 1264145132Sanholt#define R200_PP_TXFILTER_0 0x2c00 1265112015Sanholt#define R200_PP_TXOFFSET_5 0x2d78 1266112015Sanholt#define R200_PP_TXOFFSET_4 0x2d60 1267112015Sanholt#define R200_PP_TXOFFSET_3 0x2d48 1268112015Sanholt#define R200_PP_TXOFFSET_2 0x2d30 1269112015Sanholt#define R200_PP_TXOFFSET_1 0x2d18 1270112015Sanholt#define R200_PP_TXOFFSET_0 0x2d00 1271112015Sanholt 1272112015Sanholt#define R200_PP_CUBIC_FACES_0 0x2c18 1273112015Sanholt#define R200_PP_CUBIC_FACES_1 0x2c38 1274112015Sanholt#define R200_PP_CUBIC_FACES_2 0x2c58 1275112015Sanholt#define R200_PP_CUBIC_FACES_3 0x2c78 1276112015Sanholt#define R200_PP_CUBIC_FACES_4 0x2c98 1277112015Sanholt#define R200_PP_CUBIC_FACES_5 0x2cb8 1278112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1279112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1280112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1281112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1282112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1283112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1284112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1285112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1286112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1287112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1288112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1289112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1290112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1291112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1292112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1293112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1294112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1295112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1296112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1297112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1298112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1299112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1300112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1301112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1302112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1303112015Sanholt#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1304112015Sanholt#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1305112015Sanholt#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1306112015Sanholt#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1307112015Sanholt#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1308112015Sanholt 1309112015Sanholt#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1310112015Sanholt#define R200_SE_VTE_CNTL 0x20b0 1311112015Sanholt#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1312112015Sanholt#define R200_PP_TAM_DEBUG3 0x2d9c 1313112015Sanholt#define R200_PP_CNTL_X 0x2cc4 1314112015Sanholt#define R200_SE_VAP_CNTL_STATUS 0x2140 1315112015Sanholt#define R200_RE_SCISSOR_TL_0 0x1cd8 1316112015Sanholt#define R200_RE_SCISSOR_TL_1 0x1ce0 1317112015Sanholt#define R200_RE_SCISSOR_TL_2 0x1ce8 1318145132Sanholt#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1319112015Sanholt#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1320112015Sanholt#define R200_SE_VTX_STATE_CNTL 0x2180 1321112015Sanholt#define R200_RE_POINTSIZE 0x2648 1322112015Sanholt#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1323112015Sanholt 1324145132Sanholt#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1325119098Sanholt#define RADEON_PP_TEX_SIZE_1 0x1d0c 1326119098Sanholt#define RADEON_PP_TEX_SIZE_2 0x1d14 1327112015Sanholt 1328145132Sanholt#define RADEON_PP_CUBIC_FACES_0 0x1d24 1329145132Sanholt#define RADEON_PP_CUBIC_FACES_1 0x1d28 1330145132Sanholt#define RADEON_PP_CUBIC_FACES_2 0x1d2c 1331145132Sanholt#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1332145132Sanholt#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1333145132Sanholt#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1334119098Sanholt 1335162132Sanholt#define RADEON_SE_TCL_STATE_FLUSH 0x2284 1336162132Sanholt 1337112015Sanholt#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1338112015Sanholt#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1339112015Sanholt#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1340112015Sanholt#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1341112015Sanholt#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1342112015Sanholt#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1343112015Sanholt#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1344112015Sanholt#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1345112015Sanholt#define R200_3D_DRAW_IMMD_2 0xC0003500 1346112015Sanholt#define R200_SE_VTX_FMT_1 0x208c 1347145132Sanholt#define R200_RE_CNTL 0x1c50 1348112015Sanholt 1349130331Sanholt#define R200_RB3D_BLENDCOLOR 0x3218 1350112015Sanholt 1351145132Sanholt#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1352145132Sanholt 1353189499Srnoland#define R200_PP_TRI_PERF 0x2cf8 1354145132Sanholt 1355152909Sanholt#define R200_PP_AFS_0 0x2f80 1356189499Srnoland#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1357152909Sanholt 1358162132Sanholt#define R200_VAP_PVS_CNTL_1 0x22D0 1359162132Sanholt 1360189499Srnoland#define RADEON_CRTC_CRNT_FRAME 0x0214 1361189499Srnoland#define RADEON_CRTC2_CRNT_FRAME 0x0314 1362152909Sanholt 1363182080Srnoland#define R500_D1CRTC_STATUS 0x609c 1364182080Srnoland#define R500_D2CRTC_STATUS 0x689c 1365182080Srnoland#define R500_CRTC_V_BLANK (1<<0) 1366152909Sanholt 1367182080Srnoland#define R500_D1CRTC_FRAME_COUNT 0x60a4 1368182080Srnoland#define R500_D2CRTC_FRAME_COUNT 0x68a4 1369152909Sanholt 1370182080Srnoland#define R500_D1MODE_V_COUNTER 0x6530 1371182080Srnoland#define R500_D2MODE_V_COUNTER 0x6d30 1372182080Srnoland 1373182080Srnoland#define R500_D1MODE_VBLANK_STATUS 0x6534 1374182080Srnoland#define R500_D2MODE_VBLANK_STATUS 0x6d34 1375182080Srnoland#define R500_VBLANK_OCCURED (1<<0) 1376182080Srnoland#define R500_VBLANK_ACK (1<<4) 1377182080Srnoland#define R500_VBLANK_STAT (1<<12) 1378182080Srnoland#define R500_VBLANK_INT (1<<16) 1379182080Srnoland 1380182080Srnoland#define R500_DxMODE_INT_MASK 0x6540 1381182080Srnoland#define R500_D1MODE_INT_MASK (1<<0) 1382182080Srnoland#define R500_D2MODE_INT_MASK (1<<8) 1383182080Srnoland 1384182080Srnoland#define R500_DISP_INTERRUPT_STATUS 0x7edc 1385182080Srnoland#define R500_D1_VBLANK_INTERRUPT (1 << 4) 1386182080Srnoland#define R500_D2_VBLANK_INTERRUPT (1 << 5) 1387182080Srnoland 1388189499Srnoland/* R6xx/R7xx registers */ 1389189499Srnoland#define R600_MC_VM_FB_LOCATION 0x2180 1390189499Srnoland#define R600_MC_VM_AGP_TOP 0x2184 1391189499Srnoland#define R600_MC_VM_AGP_BOT 0x2188 1392189499Srnoland#define R600_MC_VM_AGP_BASE 0x218c 1393189499Srnoland#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 1394189499Srnoland#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 1395189499Srnoland#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 1396189499Srnoland 1397189499Srnoland#define R700_MC_VM_FB_LOCATION 0x2024 1398189499Srnoland#define R700_MC_VM_AGP_TOP 0x2028 1399189499Srnoland#define R700_MC_VM_AGP_BOT 0x202c 1400189499Srnoland#define R700_MC_VM_AGP_BASE 0x2030 1401189499Srnoland#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 1402189499Srnoland#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 1403189499Srnoland#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c 1404189499Srnoland 1405189499Srnoland#define R600_MCD_RD_A_CNTL 0x219c 1406189499Srnoland#define R600_MCD_RD_B_CNTL 0x21a0 1407189499Srnoland 1408189499Srnoland#define R600_MCD_WR_A_CNTL 0x21a4 1409189499Srnoland#define R600_MCD_WR_B_CNTL 0x21a8 1410189499Srnoland 1411189499Srnoland#define R600_MCD_RD_SYS_CNTL 0x2200 1412189499Srnoland#define R600_MCD_WR_SYS_CNTL 0x2214 1413189499Srnoland 1414189499Srnoland#define R600_MCD_RD_GFX_CNTL 0x21fc 1415189499Srnoland#define R600_MCD_RD_HDP_CNTL 0x2204 1416189499Srnoland#define R600_MCD_RD_PDMA_CNTL 0x2208 1417189499Srnoland#define R600_MCD_RD_SEM_CNTL 0x220c 1418189499Srnoland#define R600_MCD_WR_GFX_CNTL 0x2210 1419189499Srnoland#define R600_MCD_WR_HDP_CNTL 0x2218 1420189499Srnoland#define R600_MCD_WR_PDMA_CNTL 0x221c 1421189499Srnoland#define R600_MCD_WR_SEM_CNTL 0x2220 1422189499Srnoland 1423189499Srnoland# define R600_MCD_L1_TLB (1 << 0) 1424189499Srnoland# define R600_MCD_L1_FRAG_PROC (1 << 1) 1425189499Srnoland# define R600_MCD_L1_STRICT_ORDERING (1 << 2) 1426189499Srnoland 1427189499Srnoland# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6) 1428189499Srnoland# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 1429189499Srnoland# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 1430189499Srnoland# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 1431189499Srnoland# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 1432189499Srnoland 1433189499Srnoland# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 1434189499Srnoland# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 1435189499Srnoland 1436189499Srnoland# define R600_MCD_SEMAPHORE_MODE (1 << 10) 1437189499Srnoland# define R600_MCD_WAIT_L2_QUERY (1 << 11) 1438189499Srnoland# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12) 1439189499Srnoland# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 1440189499Srnoland 1441189499Srnoland#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 1442189499Srnoland#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 1443189499Srnoland#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c 1444189499Srnoland 1445189499Srnoland#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 1446189499Srnoland#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 1447189499Srnoland#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c 1448189499Srnoland#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 1449189499Srnoland 1450189499Srnoland# define R700_ENABLE_L1_TLB (1 << 0) 1451189499Srnoland# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 1452189499Srnoland# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 1453189499Srnoland# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 1454189499Srnoland# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15) 1455189499Srnoland# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18) 1456189499Srnoland 1457189499Srnoland#define R700_MC_ARB_RAMCFG 0x2760 1458189499Srnoland# define R700_NOOFBANK_SHIFT 0 1459189499Srnoland# define R700_NOOFBANK_MASK 0x3 1460189499Srnoland# define R700_NOOFRANK_SHIFT 2 1461189499Srnoland# define R700_NOOFRANK_MASK 0x1 1462189499Srnoland# define R700_NOOFROWS_SHIFT 3 1463189499Srnoland# define R700_NOOFROWS_MASK 0x7 1464189499Srnoland# define R700_NOOFCOLS_SHIFT 6 1465189499Srnoland# define R700_NOOFCOLS_MASK 0x3 1466189499Srnoland# define R700_CHANSIZE_SHIFT 8 1467189499Srnoland# define R700_CHANSIZE_MASK 0x1 1468189499Srnoland# define R700_BURSTLENGTH_SHIFT 9 1469189499Srnoland# define R700_BURSTLENGTH_MASK 0x1 1470189499Srnoland#define R600_RAMCFG 0x2408 1471189499Srnoland# define R600_NOOFBANK_SHIFT 0 1472189499Srnoland# define R600_NOOFBANK_MASK 0x1 1473189499Srnoland# define R600_NOOFRANK_SHIFT 1 1474189499Srnoland# define R600_NOOFRANK_MASK 0x1 1475189499Srnoland# define R600_NOOFROWS_SHIFT 2 1476189499Srnoland# define R600_NOOFROWS_MASK 0x7 1477189499Srnoland# define R600_NOOFCOLS_SHIFT 5 1478189499Srnoland# define R600_NOOFCOLS_MASK 0x3 1479189499Srnoland# define R600_CHANSIZE_SHIFT 7 1480189499Srnoland# define R600_CHANSIZE_MASK 0x1 1481189499Srnoland# define R600_BURSTLENGTH_SHIFT 8 1482189499Srnoland# define R600_BURSTLENGTH_MASK 0x1 1483189499Srnoland 1484189499Srnoland#define R600_VM_L2_CNTL 0x1400 1485189499Srnoland# define R600_VM_L2_CACHE_EN (1 << 0) 1486189499Srnoland# define R600_VM_L2_FRAG_PROC (1 << 1) 1487189499Srnoland# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9) 1488189499Srnoland# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13) 1489189499Srnoland# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14) 1490189499Srnoland 1491189499Srnoland#define R600_VM_L2_CNTL2 0x1404 1492189499Srnoland# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0) 1493189499Srnoland# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1) 1494189499Srnoland#define R600_VM_L2_CNTL3 0x1408 1495189499Srnoland# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0) 1496189499Srnoland# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5) 1497189499Srnoland# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10) 1498189499Srnoland# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0) 1499189499Srnoland# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6) 1500189499Srnoland 1501189499Srnoland#define R600_VM_L2_STATUS 0x140c 1502189499Srnoland 1503189499Srnoland#define R600_VM_CONTEXT0_CNTL 0x1410 1504189499Srnoland# define R600_VM_ENABLE_CONTEXT (1 << 0) 1505189499Srnoland# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1) 1506189499Srnoland 1507189499Srnoland#define R600_VM_CONTEXT0_CNTL2 0x1430 1508189499Srnoland#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470 1509189499Srnoland#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 1510189499Srnoland#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0 1511189499Srnoland#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 1512189499Srnoland#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 1513189499Srnoland#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4 1514189499Srnoland 1515189499Srnoland#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 1516189499Srnoland#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 1517189499Srnoland#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c 1518189499Srnoland 1519189499Srnoland#define R600_HDP_HOST_PATH_CNTL 0x2c00 1520189499Srnoland 1521189499Srnoland#define R600_GRBM_CNTL 0x8000 1522189499Srnoland# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0) 1523189499Srnoland 1524189499Srnoland#define R600_GRBM_STATUS 0x8010 1525189499Srnoland# define R600_CMDFIFO_AVAIL_MASK 0x1f 1526189499Srnoland# define R700_CMDFIFO_AVAIL_MASK 0xf 1527261455Seadler# define R600_GUI_ACTIVE (1U << 31) 1528189499Srnoland#define R600_GRBM_STATUS2 0x8014 1529189499Srnoland#define R600_GRBM_SOFT_RESET 0x8020 1530189499Srnoland# define R600_SOFT_RESET_CP (1 << 0) 1531189499Srnoland#define R600_WAIT_UNTIL 0x8040 1532189499Srnoland 1533189499Srnoland#define R600_CP_SEM_WAIT_TIMER 0x85bc 1534189499Srnoland#define R600_CP_ME_CNTL 0x86d8 1535189499Srnoland# define R600_CP_ME_HALT (1 << 28) 1536189499Srnoland#define R600_CP_QUEUE_THRESHOLDS 0x8760 1537189499Srnoland# define R600_ROQ_IB1_START(x) ((x) << 0) 1538189499Srnoland# define R600_ROQ_IB2_START(x) ((x) << 8) 1539189499Srnoland#define R600_CP_MEQ_THRESHOLDS 0x8764 1540189499Srnoland# define R700_STQ_SPLIT(x) ((x) << 0) 1541189499Srnoland# define R600_MEQ_END(x) ((x) << 16) 1542189499Srnoland# define R600_ROQ_END(x) ((x) << 24) 1543189499Srnoland#define R600_CP_PERFMON_CNTL 0x87fc 1544189499Srnoland#define R600_CP_RB_BASE 0xc100 1545189499Srnoland#define R600_CP_RB_CNTL 0xc104 1546189499Srnoland# define R600_RB_BUFSZ(x) ((x) << 0) 1547189499Srnoland# define R600_RB_BLKSZ(x) ((x) << 8) 1548189499Srnoland# define R600_RB_NO_UPDATE (1 << 27) 1549261455Seadler# define R600_RB_RPTR_WR_ENA (1U << 31) 1550189499Srnoland#define R600_CP_RB_RPTR_WR 0xc108 1551189499Srnoland#define R600_CP_RB_RPTR_ADDR 0xc10c 1552189499Srnoland#define R600_CP_RB_RPTR_ADDR_HI 0xc110 1553189499Srnoland#define R600_CP_RB_WPTR 0xc114 1554189499Srnoland#define R600_CP_RB_WPTR_ADDR 0xc118 1555189499Srnoland#define R600_CP_RB_WPTR_ADDR_HI 0xc11c 1556189499Srnoland#define R600_CP_RB_RPTR 0x8700 1557189499Srnoland#define R600_CP_RB_WPTR_DELAY 0x8704 1558189499Srnoland#define R600_CP_PFP_UCODE_ADDR 0xc150 1559189499Srnoland#define R600_CP_PFP_UCODE_DATA 0xc154 1560189499Srnoland#define R600_CP_ME_RAM_RADDR 0xc158 1561189499Srnoland#define R600_CP_ME_RAM_WADDR 0xc15c 1562189499Srnoland#define R600_CP_ME_RAM_DATA 0xc160 1563189499Srnoland#define R600_CP_DEBUG 0xc1fc 1564189499Srnoland 1565189499Srnoland#define R600_PA_CL_ENHANCE 0x8a14 1566189499Srnoland# define R600_CLIP_VTX_REORDER_ENA (1 << 0) 1567189499Srnoland# define R600_NUM_CLIP_SEQ(x) ((x) << 1) 1568189499Srnoland#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10 1569189499Srnoland#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20 1570189499Srnoland#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24 1571189499Srnoland# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1572189499Srnoland# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1573189499Srnoland#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40 1574189499Srnoland#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44 1575189499Srnoland#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48 1576189499Srnoland#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c 1577189499Srnoland# define R600_S0_X(x) ((x) << 0) 1578189499Srnoland# define R600_S0_Y(x) ((x) << 4) 1579189499Srnoland# define R600_S1_X(x) ((x) << 8) 1580189499Srnoland# define R600_S1_Y(x) ((x) << 12) 1581189499Srnoland# define R600_S2_X(x) ((x) << 16) 1582189499Srnoland# define R600_S2_Y(x) ((x) << 20) 1583189499Srnoland# define R600_S3_X(x) ((x) << 24) 1584189499Srnoland# define R600_S3_Y(x) ((x) << 28) 1585189499Srnoland# define R600_S4_X(x) ((x) << 0) 1586189499Srnoland# define R600_S4_Y(x) ((x) << 4) 1587189499Srnoland# define R600_S5_X(x) ((x) << 8) 1588189499Srnoland# define R600_S5_Y(x) ((x) << 12) 1589189499Srnoland# define R600_S6_X(x) ((x) << 16) 1590189499Srnoland# define R600_S6_Y(x) ((x) << 20) 1591189499Srnoland# define R600_S7_X(x) ((x) << 24) 1592189499Srnoland# define R600_S7_Y(x) ((x) << 28) 1593189499Srnoland#define R600_PA_SC_FIFO_SIZE 0x8bd0 1594189499Srnoland# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1595189499Srnoland# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8) 1596189499Srnoland# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16) 1597189499Srnoland#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc 1598189499Srnoland# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1599189499Srnoland# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 1600189499Srnoland# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 1601189499Srnoland#define R600_PA_SC_ENHANCE 0x8bf0 1602189499Srnoland# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1603189499Srnoland# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 1604189499Srnoland#define R600_PA_SC_CLIPRECT_RULE 0x2820c 1605189499Srnoland#define R700_PA_SC_EDGERULE 0x28230 1606189499Srnoland#define R600_PA_SC_LINE_STIPPLE 0x28a0c 1607189499Srnoland#define R600_PA_SC_MODE_CNTL 0x28a4c 1608189499Srnoland#define R600_PA_SC_AA_CONFIG 0x28c04 1609189499Srnoland 1610189499Srnoland#define R600_SX_EXPORT_BUFFER_SIZES 0x900c 1611189499Srnoland# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0) 1612189499Srnoland# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8) 1613189499Srnoland# define R600_SMX_BUFFER_SIZE(x) ((x) << 16) 1614189499Srnoland#define R600_SX_DEBUG_1 0x9054 1615189499Srnoland# define R600_SMX_EVENT_RELEASE (1 << 0) 1616189499Srnoland# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1617189499Srnoland#define R700_SX_DEBUG_1 0x9058 1618189499Srnoland# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1619189499Srnoland#define R600_SX_MISC 0x28350 1620189499Srnoland 1621189499Srnoland#define R600_DB_DEBUG 0x9830 1622261455Seadler# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31) 1623189499Srnoland#define R600_DB_WATERMARKS 0x9838 1624189499Srnoland# define R600_DEPTH_FREE(x) ((x) << 0) 1625189499Srnoland# define R600_DEPTH_FLUSH(x) ((x) << 5) 1626189499Srnoland# define R600_DEPTH_PENDING_FREE(x) ((x) << 15) 1627189499Srnoland# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20) 1628189499Srnoland#define R700_DB_DEBUG3 0x98b0 1629189499Srnoland# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) 1630189499Srnoland#define RV700_DB_DEBUG4 0x9b8c 1631189499Srnoland# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 1632189499Srnoland 1633189499Srnoland#define R600_VGT_CACHE_INVALIDATION 0x88c4 1634189499Srnoland# define R600_CACHE_INVALIDATION(x) ((x) << 0) 1635189499Srnoland# define R600_VC_ONLY 0 1636189499Srnoland# define R600_TC_ONLY 1 1637189499Srnoland# define R600_VC_AND_TC 2 1638189499Srnoland# define R700_AUTO_INVLD_EN(x) ((x) << 6) 1639189499Srnoland# define R700_NO_AUTO 0 1640189499Srnoland# define R700_ES_AUTO 1 1641189499Srnoland# define R700_GS_AUTO 2 1642189499Srnoland# define R700_ES_AND_GS_AUTO 3 1643189499Srnoland#define R600_VGT_GS_PER_ES 0x88c8 1644189499Srnoland#define R600_VGT_ES_PER_GS 0x88cc 1645189499Srnoland#define R600_VGT_GS_PER_VS 0x88e8 1646189499Srnoland#define R600_VGT_GS_VERTEX_REUSE 0x88d4 1647189499Srnoland#define R600_VGT_NUM_INSTANCES 0x8974 1648189499Srnoland#define R600_VGT_STRMOUT_EN 0x28ab0 1649189499Srnoland#define R600_VGT_EVENT_INITIATOR 0x28a90 1650189499Srnoland# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 1651189499Srnoland#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58 1652189499Srnoland# define R600_VTX_REUSE_DEPTH_MASK 0xff 1653189499Srnoland#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c 1654189499Srnoland# define R600_DEALLOC_DIST_MASK 0x7f 1655189499Srnoland 1656189499Srnoland#define R600_CB_COLOR0_BASE 0x28040 1657189499Srnoland#define R600_CB_COLOR1_BASE 0x28044 1658189499Srnoland#define R600_CB_COLOR2_BASE 0x28048 1659189499Srnoland#define R600_CB_COLOR3_BASE 0x2804c 1660189499Srnoland#define R600_CB_COLOR4_BASE 0x28050 1661189499Srnoland#define R600_CB_COLOR5_BASE 0x28054 1662189499Srnoland#define R600_CB_COLOR6_BASE 0x28058 1663189499Srnoland#define R600_CB_COLOR7_BASE 0x2805c 1664189499Srnoland#define R600_CB_COLOR7_FRAG 0x280fc 1665189499Srnoland 1666189499Srnoland#define R600_TC_CNTL 0x9608 1667189499Srnoland# define R600_TC_L2_SIZE(x) ((x) << 5) 1668189499Srnoland# define R600_L2_DISABLE_LATE_HIT (1 << 9) 1669189499Srnoland 1670189499Srnoland#define R600_ARB_POP 0x2418 1671189499Srnoland# define R600_ENABLE_TC128 (1 << 30) 1672189499Srnoland#define R600_ARB_GDEC_RD_CNTL 0x246c 1673189499Srnoland 1674189499Srnoland#define R600_TA_CNTL_AUX 0x9508 1675189499Srnoland# define R600_DISABLE_CUBE_WRAP (1 << 0) 1676189499Srnoland# define R600_DISABLE_CUBE_ANISO (1 << 1) 1677189499Srnoland# define R700_GETLOD_SELECT(x) ((x) << 2) 1678189499Srnoland# define R600_SYNC_GRADIENT (1 << 24) 1679189499Srnoland# define R600_SYNC_WALKER (1 << 25) 1680189499Srnoland# define R600_SYNC_ALIGNER (1 << 26) 1681189499Srnoland# define R600_BILINEAR_PRECISION_6_BIT (0 << 31) 1682261455Seadler# define R600_BILINEAR_PRECISION_8_BIT (1U << 31) 1683189499Srnoland 1684189499Srnoland#define R700_TCP_CNTL 0x9610 1685189499Srnoland 1686189499Srnoland#define R600_SMX_DC_CTL0 0xa020 1687189499Srnoland# define R700_USE_HASH_FUNCTION (1 << 0) 1688189499Srnoland# define R700_CACHE_DEPTH(x) ((x) << 1) 1689189499Srnoland# define R700_FLUSH_ALL_ON_EVENT (1 << 10) 1690189499Srnoland# define R700_STALL_ON_EVENT (1 << 11) 1691189499Srnoland#define R700_SMX_EVENT_CTL 0xa02c 1692189499Srnoland# define R700_ES_FLUSH_CTL(x) ((x) << 0) 1693189499Srnoland# define R700_GS_FLUSH_CTL(x) ((x) << 3) 1694189499Srnoland# define R700_ACK_FLUSH_CTL(x) ((x) << 6) 1695189499Srnoland# define R700_SYNC_FLUSH_CTL (1 << 8) 1696189499Srnoland 1697189499Srnoland#define R600_SQ_CONFIG 0x8c00 1698189499Srnoland# define R600_VC_ENABLE (1 << 0) 1699189499Srnoland# define R600_EXPORT_SRC_C (1 << 1) 1700189499Srnoland# define R600_DX9_CONSTS (1 << 2) 1701189499Srnoland# define R600_ALU_INST_PREFER_VECTOR (1 << 3) 1702189499Srnoland# define R600_DX10_CLAMP (1 << 4) 1703189499Srnoland# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8) 1704189499Srnoland# define R600_PS_PRIO(x) ((x) << 24) 1705189499Srnoland# define R600_VS_PRIO(x) ((x) << 26) 1706189499Srnoland# define R600_GS_PRIO(x) ((x) << 28) 1707189499Srnoland# define R600_ES_PRIO(x) ((x) << 30) 1708189499Srnoland#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04 1709189499Srnoland# define R600_NUM_PS_GPRS(x) ((x) << 0) 1710189499Srnoland# define R600_NUM_VS_GPRS(x) ((x) << 16) 1711189499Srnoland# define R700_DYN_GPR_ENABLE (1 << 27) 1712189499Srnoland# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 1713189499Srnoland#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08 1714189499Srnoland# define R600_NUM_GS_GPRS(x) ((x) << 0) 1715189499Srnoland# define R600_NUM_ES_GPRS(x) ((x) << 16) 1716189499Srnoland#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c 1717189499Srnoland# define R600_NUM_PS_THREADS(x) ((x) << 0) 1718189499Srnoland# define R600_NUM_VS_THREADS(x) ((x) << 8) 1719189499Srnoland# define R600_NUM_GS_THREADS(x) ((x) << 16) 1720189499Srnoland# define R600_NUM_ES_THREADS(x) ((x) << 24) 1721189499Srnoland#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10 1722189499Srnoland# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0) 1723189499Srnoland# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16) 1724189499Srnoland#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14 1725189499Srnoland# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0) 1726189499Srnoland# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16) 1727189499Srnoland#define R600_SQ_MS_FIFO_SIZES 0x8cf0 1728189499Srnoland# define R600_CACHE_FIFO_SIZE(x) ((x) << 0) 1729189499Srnoland# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8) 1730189499Srnoland# define R600_DONE_FIFO_HIWATER(x) ((x) << 16) 1731189499Srnoland# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 1732189499Srnoland#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0 1733189499Srnoland# define R700_SIMDA_RING0(x) ((x) << 0) 1734189499Srnoland# define R700_SIMDA_RING1(x) ((x) << 8) 1735189499Srnoland# define R700_SIMDB_RING0(x) ((x) << 16) 1736189499Srnoland# define R700_SIMDB_RING1(x) ((x) << 24) 1737189499Srnoland#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4 1738189499Srnoland#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8 1739189499Srnoland#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc 1740189499Srnoland#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0 1741189499Srnoland#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4 1742189499Srnoland#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8 1743189499Srnoland#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc 1744189499Srnoland 1745189499Srnoland#define R600_SPI_PS_IN_CONTROL_0 0x286cc 1746189499Srnoland# define R600_NUM_INTERP(x) ((x) << 0) 1747189499Srnoland# define R600_POSITION_ENA (1 << 8) 1748189499Srnoland# define R600_POSITION_CENTROID (1 << 9) 1749189499Srnoland# define R600_POSITION_ADDR(x) ((x) << 10) 1750189499Srnoland# define R600_PARAM_GEN(x) ((x) << 15) 1751189499Srnoland# define R600_PARAM_GEN_ADDR(x) ((x) << 19) 1752189499Srnoland# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26) 1753189499Srnoland# define R600_PERSP_GRADIENT_ENA (1 << 28) 1754189499Srnoland# define R600_LINEAR_GRADIENT_ENA (1 << 29) 1755189499Srnoland# define R600_POSITION_SAMPLE (1 << 30) 1756261455Seadler# define R600_BARYC_AT_SAMPLE_ENA (1U << 31) 1757189499Srnoland#define R600_SPI_PS_IN_CONTROL_1 0x286d0 1758189499Srnoland# define R600_GEN_INDEX_PIX (1 << 0) 1759189499Srnoland# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) 1760189499Srnoland# define R600_FRONT_FACE_ENA (1 << 8) 1761189499Srnoland# define R600_FRONT_FACE_CHAN(x) ((x) << 9) 1762189499Srnoland# define R600_FRONT_FACE_ALL_BITS (1 << 11) 1763189499Srnoland# define R600_FRONT_FACE_ADDR(x) ((x) << 12) 1764189499Srnoland# define R600_FOG_ADDR(x) ((x) << 17) 1765189499Srnoland# define R600_FIXED_PT_POSITION_ENA (1 << 24) 1766189499Srnoland# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25) 1767189499Srnoland# define R700_POSITION_ULC (1 << 30) 1768189499Srnoland#define R600_SPI_INPUT_Z 0x286d8 1769189499Srnoland 1770189499Srnoland#define R600_SPI_CONFIG_CNTL 0x9100 1771189499Srnoland# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0) 1772189499Srnoland# define R600_DISABLE_INTERP_1 (1 << 5) 1773189499Srnoland#define R600_SPI_CONFIG_CNTL_1 0x913c 1774189499Srnoland# define R600_VTX_DONE_DELAY(x) ((x) << 0) 1775189499Srnoland# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4) 1776189499Srnoland 1777189499Srnoland#define R600_GB_TILING_CONFIG 0x98f0 1778189499Srnoland# define R600_PIPE_TILING(x) ((x) << 1) 1779189499Srnoland# define R600_BANK_TILING(x) ((x) << 4) 1780189499Srnoland# define R600_GROUP_SIZE(x) ((x) << 6) 1781189499Srnoland# define R600_ROW_TILING(x) ((x) << 8) 1782189499Srnoland# define R600_BANK_SWAPS(x) ((x) << 11) 1783189499Srnoland# define R600_SAMPLE_SPLIT(x) ((x) << 14) 1784189499Srnoland# define R600_BACKEND_MAP(x) ((x) << 16) 1785189499Srnoland#define R600_DCP_TILING_CONFIG 0x6ca0 1786189499Srnoland#define R600_HDP_TILING_CONFIG 0x2f3c 1787189499Srnoland 1788189499Srnoland#define R600_CC_RB_BACKEND_DISABLE 0x98f4 1789189499Srnoland#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88 1790189499Srnoland# define R600_BACKEND_DISABLE(x) ((x) << 16) 1791189499Srnoland 1792189499Srnoland#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950 1793189499Srnoland#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954 1794189499Srnoland# define R600_INACTIVE_QD_PIPES(x) ((x) << 8) 1795189499Srnoland# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8) 1796189499Srnoland# define R600_INACTIVE_SIMDS(x) ((x) << 16) 1797189499Srnoland# define R600_INACTIVE_SIMDS_MASK (0xff << 16) 1798189499Srnoland 1799189499Srnoland#define R700_CGTS_SYS_TCC_DISABLE 0x3f90 1800189499Srnoland#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94 1801189499Srnoland#define R700_CGTS_TCC_DISABLE 0x9148 1802189499Srnoland#define R700_CGTS_USER_TCC_DISABLE 0x914c 1803189499Srnoland 180495584Sanholt/* Constants */ 180595584Sanholt#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 180695584Sanholt 180795584Sanholt#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 180895584Sanholt#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 180995584Sanholt#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1810112015Sanholt#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 181195584Sanholt#define RADEON_LAST_DISPATCH 1 181295584Sanholt 1813189499Srnoland#define R600_LAST_FRAME_REG R600_SCRATCH_REG0 1814189499Srnoland#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1 1815189499Srnoland#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2 1816189499Srnoland#define R600_LAST_SWI_REG R600_SCRATCH_REG3 1817189499Srnoland 181895584Sanholt#define RADEON_MAX_VB_AGE 0x7fffffff 181995584Sanholt#define RADEON_MAX_VB_VERTS (0xffff) 182095584Sanholt 182195584Sanholt#define RADEON_RING_HIGH_MARK 128 182295584Sanholt 1823152909Sanholt#define RADEON_PCIGART_TABLE_SIZE (32*1024) 1824152909Sanholt 1825189499Srnoland#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1826189499Srnoland#define RADEON_WRITE(reg, val) \ 1827189499Srnolanddo { \ 1828189499Srnoland if (reg < 0x10000) { \ 1829189499Srnoland DRM_WRITE32(dev_priv->mmio, (reg), (val)); \ 1830189499Srnoland } else { \ 1831189499Srnoland DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \ 1832189499Srnoland DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \ 1833189499Srnoland } \ 1834189499Srnoland} while (0) 1835112015Sanholt#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1836112015Sanholt#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 183795584Sanholt 1838189499Srnoland#define RADEON_WRITE_PLL(addr, val) \ 183995584Sanholtdo { \ 1840189499Srnoland RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ 184195584Sanholt ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1842189499Srnoland RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ 184395584Sanholt} while (0) 184495584Sanholt 1845189499Srnoland#define RADEON_WRITE_PCIE(addr, val) \ 1846148211Sanholtdo { \ 1847189499Srnoland RADEON_WRITE8(RADEON_PCIE_INDEX, \ 1848148211Sanholt ((addr) & 0xff)); \ 1849189499Srnoland RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ 1850148211Sanholt} while (0) 1851148211Sanholt 1852189499Srnoland#define R500_WRITE_MCIND(addr, val) \ 1853182080Srnolanddo { \ 1854182080Srnoland RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1855182080Srnoland RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1856182080Srnoland RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1857182080Srnoland} while (0) 1858182080Srnoland 1859189499Srnoland#define RS480_WRITE_MCIND(addr, val) \ 1860182080Srnolanddo { \ 1861189499Srnoland RADEON_WRITE(RS480_NB_MC_INDEX, \ 1862182080Srnoland ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1863189499Srnoland RADEON_WRITE(RS480_NB_MC_DATA, (val)); \ 1864189499Srnoland RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \ 1865182080Srnoland} while (0) 1866182080Srnoland 1867189499Srnoland#define RS690_WRITE_MCIND(addr, val) \ 1868182080Srnolanddo { \ 1869182080Srnoland RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1870182080Srnoland RADEON_WRITE(RS690_MC_DATA, val); \ 1871182080Srnoland RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1872182080Srnoland} while (0) 1873182080Srnoland 1874189499Srnoland#define RS600_WRITE_MCIND(addr, val) \ 1875189499Srnolanddo { \ 1876189499Srnoland RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \ 1877189499Srnoland RADEON_WRITE(RS600_MC_DATA, val); \ 1878189499Srnoland} while (0) 1879189499Srnoland 1880189499Srnoland#define IGP_WRITE_MCIND(addr, val) \ 1881182080Srnolanddo { \ 1882189499Srnoland if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ 1883189499Srnoland ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ 1884189499Srnoland RS690_WRITE_MCIND(addr, val); \ 1885189499Srnoland else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \ 1886189499Srnoland RS600_WRITE_MCIND(addr, val); \ 1887189499Srnoland else \ 1888189499Srnoland RS480_WRITE_MCIND(addr, val); \ 1889182080Srnoland} while (0) 1890182080Srnoland 189195584Sanholt#define CP_PACKET0( reg, n ) \ 189295584Sanholt (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 189395584Sanholt#define CP_PACKET0_TABLE( reg, n ) \ 189495584Sanholt (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 189595584Sanholt#define CP_PACKET1( reg0, reg1 ) \ 189695584Sanholt (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 189795584Sanholt#define CP_PACKET2() \ 189895584Sanholt (RADEON_CP_PACKET2) 189995584Sanholt#define CP_PACKET3( pkt, n ) \ 190095584Sanholt (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 190195584Sanholt 190295584Sanholt/* ================================================================ 190395584Sanholt * Engine control helper macros 190495584Sanholt */ 190595584Sanholt 190695584Sanholt#define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1907196470Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1908196470Srnoland OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1909196470Srnoland else \ 1910196470Srnoland OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 191195584Sanholt OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 191295584Sanholt RADEON_WAIT_HOST_IDLECLEAN) ); \ 191395584Sanholt} while (0) 191495584Sanholt 191595584Sanholt#define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1916196470Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1917196470Srnoland OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1918196470Srnoland else \ 1919196470Srnoland OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 192095584Sanholt OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 192195584Sanholt RADEON_WAIT_HOST_IDLECLEAN) ); \ 192295584Sanholt} while (0) 192395584Sanholt 192495584Sanholt#define RADEON_WAIT_UNTIL_IDLE() do { \ 1925196470Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1926196470Srnoland OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1927196470Srnoland else \ 1928196470Srnoland OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 192995584Sanholt OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 193095584Sanholt RADEON_WAIT_3D_IDLECLEAN | \ 193195584Sanholt RADEON_WAIT_HOST_IDLECLEAN) ); \ 193295584Sanholt} while (0) 193395584Sanholt 193495584Sanholt#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1935196470Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1936196470Srnoland OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1937196470Srnoland else \ 1938196470Srnoland OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 193995584Sanholt OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 194095584Sanholt} while (0) 194195584Sanholt 194295584Sanholt#define RADEON_FLUSH_CACHE() do { \ 1943182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1944189499Srnoland OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1945189499Srnoland OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1946182080Srnoland } else { \ 1947189499Srnoland OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1948189499Srnoland OUT_RING(R300_RB3D_DC_FLUSH); \ 1949189499Srnoland } \ 195095584Sanholt} while (0) 195195584Sanholt 195295584Sanholt#define RADEON_PURGE_CACHE() do { \ 1953182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1954189499Srnoland OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1955189499Srnoland OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1956182080Srnoland } else { \ 1957189499Srnoland OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1958189499Srnoland OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \ 1959189499Srnoland } \ 196095584Sanholt} while (0) 196195584Sanholt 196295584Sanholt#define RADEON_FLUSH_ZCACHE() do { \ 1963182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1964189499Srnoland OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1965189499Srnoland OUT_RING(RADEON_RB3D_ZC_FLUSH); \ 1966182080Srnoland } else { \ 1967189499Srnoland OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1968189499Srnoland OUT_RING(R300_ZC_FLUSH); \ 1969189499Srnoland } \ 197095584Sanholt} while (0) 197195584Sanholt 197295584Sanholt#define RADEON_PURGE_ZCACHE() do { \ 1973182080Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1974189499Srnoland OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1975189499Srnoland OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1976182080Srnoland } else { \ 1977189499Srnoland OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1978189499Srnoland OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 1979189499Srnoland } \ 198095584Sanholt} while (0) 198195584Sanholt 198295584Sanholt/* ================================================================ 198395584Sanholt * Misc helper macros 198495584Sanholt */ 198595584Sanholt 1986145132Sanholt/* Perfbox functionality only. 1987112015Sanholt */ 198895584Sanholt#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 198995584Sanholtdo { \ 1990112015Sanholt if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1991113995Sanholt u32 head = GET_RING_HEAD( dev_priv ); \ 1992112015Sanholt if (head == dev_priv->ring.tail) \ 1993112015Sanholt dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 199495584Sanholt } \ 199595584Sanholt} while (0) 199695584Sanholt 199795584Sanholt#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 1998189499Srnolanddo { \ 1999189499Srnoland drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 200095584Sanholt if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 2001189499Srnoland int __ret; \ 2002189499Srnoland if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 2003189499Srnoland __ret = r600_do_cp_idle(dev_priv); \ 2004189499Srnoland else \ 2005189499Srnoland __ret = radeon_do_cp_idle(dev_priv); \ 200695584Sanholt if ( __ret ) return __ret; \ 200795584Sanholt sarea_priv->last_dispatch = 0; \ 200895584Sanholt radeon_freelist_reset( dev ); \ 200995584Sanholt } \ 201095584Sanholt} while (0) 201195584Sanholt 201295584Sanholt#define RADEON_DISPATCH_AGE( age ) do { \ 201395584Sanholt OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 201495584Sanholt OUT_RING( age ); \ 201595584Sanholt} while (0) 201695584Sanholt 201795584Sanholt#define RADEON_FRAME_AGE( age ) do { \ 201895584Sanholt OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 201995584Sanholt OUT_RING( age ); \ 202095584Sanholt} while (0) 202195584Sanholt 202295584Sanholt#define RADEON_CLEAR_AGE( age ) do { \ 202395584Sanholt OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 202495584Sanholt OUT_RING( age ); \ 202595584Sanholt} while (0) 202695584Sanholt 2027189499Srnoland#define R600_DISPATCH_AGE(age) do { \ 2028189499Srnoland OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2029189499Srnoland OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2030189499Srnoland OUT_RING(age); \ 2031189499Srnoland} while (0) 2032189499Srnoland 2033189499Srnoland#define R600_FRAME_AGE(age) do { \ 2034189499Srnoland OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2035189499Srnoland OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2036189499Srnoland OUT_RING(age); \ 2037189499Srnoland} while (0) 2038189499Srnoland 2039189499Srnoland#define R600_CLEAR_AGE(age) do { \ 2040189499Srnoland OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2041189499Srnoland OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2042189499Srnoland OUT_RING(age); \ 2043189499Srnoland} while (0) 2044189499Srnoland 204595584Sanholt/* ================================================================ 204695584Sanholt * Ring control 204795584Sanholt */ 204895584Sanholt 204995584Sanholt#define RADEON_VERBOSE 0 205095584Sanholt 2051189499Srnoland#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring; 205295584Sanholt 2053196470Srnoland#define RADEON_RING_ALIGN 16 2054196470Srnoland 205595584Sanholt#define BEGIN_RING( n ) do { \ 205695584Sanholt if ( RADEON_VERBOSE ) { \ 2057182080Srnoland DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 205895584Sanholt } \ 2059196470Srnoland _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN - 1)); \ 2060196470Srnoland _align_nr += n; \ 2061196470Srnoland if ( dev_priv->ring.space <= (_align_nr) * sizeof(u32) ) { \ 2062196470Srnoland COMMIT_RING(); \ 2063196470Srnoland radeon_wait_ring( dev_priv, (_align_nr) * sizeof(u32) ); \ 206495584Sanholt } \ 2065112015Sanholt _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 206695584Sanholt ring = dev_priv->ring.start; \ 206795584Sanholt write = dev_priv->ring.tail; \ 206895584Sanholt mask = dev_priv->ring.tail_mask; \ 206995584Sanholt} while (0) 207095584Sanholt 207195584Sanholt#define ADVANCE_RING() do { \ 207295584Sanholt if ( RADEON_VERBOSE ) { \ 207395584Sanholt DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 207495584Sanholt write, dev_priv->ring.tail ); \ 207595584Sanholt } \ 2076112015Sanholt if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 2077182080Srnoland DRM_ERROR( \ 2078112015Sanholt "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 2079112015Sanholt ((dev_priv->ring.tail + _nr) & mask), \ 2080189499Srnoland write, __LINE__); \ 2081112015Sanholt } else \ 2082112015Sanholt dev_priv->ring.tail = write; \ 208395584Sanholt} while (0) 208495584Sanholt 2085189499Srnolandextern void radeon_commit_ring(drm_radeon_private_t *dev_priv); 2086189499Srnoland 2087112015Sanholt#define COMMIT_RING() do { \ 2088189499Srnoland radeon_commit_ring(dev_priv); \ 2089189499Srnoland } while(0) 2090112015Sanholt 209195584Sanholt#define OUT_RING( x ) do { \ 209295584Sanholt if ( RADEON_VERBOSE ) { \ 209395584Sanholt DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 209495584Sanholt (unsigned int)(x), write ); \ 209595584Sanholt } \ 209695584Sanholt ring[write++] = (x); \ 209795584Sanholt write &= mask; \ 209895584Sanholt} while (0) 209995584Sanholt 2100112015Sanholt#define OUT_RING_REG( reg, val ) do { \ 2101112015Sanholt OUT_RING( CP_PACKET0( reg, 0 ) ); \ 2102112015Sanholt OUT_RING( val ); \ 2103112015Sanholt} while (0) 210495584Sanholt 2105189499Srnoland#define OUT_RING_TABLE( tab, sz ) do { \ 2106112015Sanholt int _size = (sz); \ 2107145132Sanholt int *_tab = (int *)(tab); \ 2108112015Sanholt \ 2109112015Sanholt if (write + _size > mask) { \ 2110145132Sanholt int _i = (mask+1) - write; \ 2111145132Sanholt _size -= _i; \ 2112189499Srnoland while (_i > 0 ) { \ 2113145132Sanholt *(int *)(ring + write) = *_tab++; \ 2114145132Sanholt write++; \ 2115145132Sanholt _i--; \ 2116145132Sanholt } \ 2117112015Sanholt write = 0; \ 2118145132Sanholt _tab += _i; \ 2119112015Sanholt } \ 2120145132Sanholt while (_size > 0) { \ 2121145132Sanholt *(ring + write) = *_tab++; \ 2122145132Sanholt write++; \ 2123145132Sanholt _size--; \ 2124145132Sanholt } \ 2125112015Sanholt write &= mask; \ 2126112015Sanholt} while (0) 2127112015Sanholt 2128145132Sanholt#endif /* __RADEON_DRV_H__ */ 2129