i915_drv.h revision 194540
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3/* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/drm/i915_drv.h 194540 2009-06-20 16:45:14Z rnoland $"); 32 33#ifndef _I915_DRV_H_ 34#define _I915_DRV_H_ 35 36#include "dev/drm/i915_reg.h" 37 38/* General customization: 39 */ 40 41#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 42 43#define DRIVER_NAME "i915" 44#define DRIVER_DESC "Intel Graphics" 45#define DRIVER_DATE "20080730" 46 47enum pipe { 48 PIPE_A = 0, 49 PIPE_B, 50}; 51 52#define I915_NUM_PIPE 2 53 54/* Interface history: 55 * 56 * 1.1: Original. 57 * 1.2: Add Power Management 58 * 1.3: Add vblank support 59 * 1.4: Fix cmdbuffer path, add heap destroy 60 * 1.5: Add vblank pipe configuration 61 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 62 * - Support vertical blank on secondary display pipe 63 */ 64#define DRIVER_MAJOR 1 65#define DRIVER_MINOR 6 66#define DRIVER_PATCHLEVEL 0 67 68#define WATCH_COHERENCY 0 69#define WATCH_BUF 0 70#define WATCH_EXEC 0 71#define WATCH_LRU 0 72#define WATCH_RELOC 0 73#define WATCH_INACTIVE 0 74#define WATCH_PWRITE 0 75 76typedef struct _drm_i915_ring_buffer { 77 int tail_mask; 78 unsigned long Size; 79 u8 *virtual_start; 80 int head; 81 int tail; 82 int space; 83 drm_local_map_t map; 84 struct drm_gem_object *ring_obj; 85} drm_i915_ring_buffer_t; 86 87struct mem_block { 88 struct mem_block *next; 89 struct mem_block *prev; 90 int start; 91 int size; 92 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 93}; 94 95struct opregion_header; 96struct opregion_acpi; 97struct opregion_swsci; 98struct opregion_asle; 99 100struct intel_opregion { 101 struct opregion_header *header; 102 struct opregion_acpi *acpi; 103 struct opregion_swsci *swsci; 104 struct opregion_asle *asle; 105 int enabled; 106}; 107 108typedef struct drm_i915_private { 109 struct drm_device *dev; 110 111 drm_local_map_t *sarea; 112 drm_local_map_t *mmio_map; 113 114 drm_i915_sarea_t *sarea_priv; 115 drm_i915_ring_buffer_t ring; 116 117 drm_dma_handle_t *status_page_dmah; 118 void *hw_status_page; 119 dma_addr_t dma_status_page; 120 uint32_t counter; 121 unsigned int status_gfx_addr; 122 drm_local_map_t hws_map; 123 struct drm_gem_object *hws_obj; 124 125 unsigned int cpp; 126 int back_offset; 127 int front_offset; 128 int current_page; 129 int page_flipping; 130 131 wait_queue_head_t irq_queue; 132 atomic_t irq_received; 133 /** Protects user_irq_refcount and irq_mask_reg */ 134 DRM_SPINTYPE user_irq_lock; 135 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ 136 int user_irq_refcount; 137 /** Cached value of IER to avoid reads in updating the bitfield */ 138 u32 irq_mask_reg; 139 u32 pipestat[2]; 140 141 int tex_lru_log_granularity; 142 int allow_batchbuffer; 143 struct mem_block *agp_heap; 144 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 145 int vblank_pipe; 146 147 struct intel_opregion opregion; 148 149 /* Register state */ 150 u8 saveLBB; 151 u32 saveDSPACNTR; 152 u32 saveDSPBCNTR; 153 u32 saveDSPARB; 154 u32 saveRENDERSTANDBY; 155 u32 saveHWS; 156 u32 savePIPEACONF; 157 u32 savePIPEBCONF; 158 u32 savePIPEASRC; 159 u32 savePIPEBSRC; 160 u32 saveFPA0; 161 u32 saveFPA1; 162 u32 saveDPLL_A; 163 u32 saveDPLL_A_MD; 164 u32 saveHTOTAL_A; 165 u32 saveHBLANK_A; 166 u32 saveHSYNC_A; 167 u32 saveVTOTAL_A; 168 u32 saveVBLANK_A; 169 u32 saveVSYNC_A; 170 u32 saveBCLRPAT_A; 171 u32 savePIPEASTAT; 172 u32 saveDSPASTRIDE; 173 u32 saveDSPASIZE; 174 u32 saveDSPAPOS; 175 u32 saveDSPAADDR; 176 u32 saveDSPASURF; 177 u32 saveDSPATILEOFF; 178 u32 savePFIT_PGM_RATIOS; 179 u32 saveBLC_PWM_CTL; 180 u32 saveBLC_PWM_CTL2; 181 u32 saveFPB0; 182 u32 saveFPB1; 183 u32 saveDPLL_B; 184 u32 saveDPLL_B_MD; 185 u32 saveHTOTAL_B; 186 u32 saveHBLANK_B; 187 u32 saveHSYNC_B; 188 u32 saveVTOTAL_B; 189 u32 saveVBLANK_B; 190 u32 saveVSYNC_B; 191 u32 saveBCLRPAT_B; 192 u32 savePIPEBSTAT; 193 u32 saveDSPBSTRIDE; 194 u32 saveDSPBSIZE; 195 u32 saveDSPBPOS; 196 u32 saveDSPBADDR; 197 u32 saveDSPBSURF; 198 u32 saveDSPBTILEOFF; 199 u32 saveVGA0; 200 u32 saveVGA1; 201 u32 saveVGA_PD; 202 u32 saveVGACNTRL; 203 u32 saveADPA; 204 u32 saveLVDS; 205 u32 savePP_ON_DELAYS; 206 u32 savePP_OFF_DELAYS; 207 u32 saveDVOA; 208 u32 saveDVOB; 209 u32 saveDVOC; 210 u32 savePP_ON; 211 u32 savePP_OFF; 212 u32 savePP_CONTROL; 213 u32 savePP_DIVISOR; 214 u32 savePFIT_CONTROL; 215 u32 save_palette_a[256]; 216 u32 save_palette_b[256]; 217 u32 saveFBC_CFB_BASE; 218 u32 saveFBC_LL_BASE; 219 u32 saveFBC_CONTROL; 220 u32 saveFBC_CONTROL2; 221 u32 saveIER; 222 u32 saveIIR; 223 u32 saveIMR; 224 u32 saveCACHE_MODE_0; 225 u32 saveD_STATE; 226 u32 saveCG_2D_DIS; 227 u32 saveMI_ARB_STATE; 228 u32 saveSWF0[16]; 229 u32 saveSWF1[16]; 230 u32 saveSWF2[3]; 231 u8 saveMSR; 232 u8 saveSR[8]; 233 u8 saveGR[25]; 234 u8 saveAR_INDEX; 235 u8 saveAR[21]; 236 u8 saveDACMASK; 237 u8 saveCR[37]; 238 239 struct { 240#ifdef __linux__ 241 struct drm_mm gtt_space; 242#endif 243 /** 244 * List of objects currently involved in rendering from the 245 * ringbuffer. 246 * 247 * A reference is held on the buffer while on this list. 248 */ 249 struct list_head active_list; 250 251 /** 252 * List of objects which are not in the ringbuffer but which 253 * still have a write_domain which needs to be flushed before 254 * unbinding. 255 * 256 * A reference is held on the buffer while on this list. 257 */ 258 struct list_head flushing_list; 259 260 /** 261 * LRU list of objects which are not in the ringbuffer and 262 * are ready to unbind, but are still in the GTT. 263 * 264 * A reference is not held on the buffer while on this list, 265 * as merely being GTT-bound shouldn't prevent its being 266 * freed, and we'll pull it off the list in the free path. 267 */ 268 struct list_head inactive_list; 269 270 /** 271 * List of breadcrumbs associated with GPU requests currently 272 * outstanding. 273 */ 274 struct list_head request_list; 275#ifdef __linux__ 276 /** 277 * We leave the user IRQ off as much as possible, 278 * but this means that requests will finish and never 279 * be retired once the system goes idle. Set a timer to 280 * fire periodically while the ring is running. When it 281 * fires, go retire requests. 282 */ 283 struct delayed_work retire_work; 284#endif 285 uint32_t next_gem_seqno; 286 287 /** 288 * Waiting sequence number, if any 289 */ 290 uint32_t waiting_gem_seqno; 291 292 /** 293 * Last seq seen at irq time 294 */ 295 uint32_t irq_gem_seqno; 296 297 /** 298 * Flag if the X Server, and thus DRM, is not currently in 299 * control of the device. 300 * 301 * This is set between LeaveVT and EnterVT. It needs to be 302 * replaced with a semaphore. It also needs to be 303 * transitioned away from for kernel modesetting. 304 */ 305 int suspended; 306 307 /** 308 * Flag if the hardware appears to be wedged. 309 * 310 * This is set when attempts to idle the device timeout. 311 * It prevents command submission from occuring and makes 312 * every pending request fail 313 */ 314 int wedged; 315 316 /** Bit 6 swizzling required for X tiling */ 317 uint32_t bit_6_swizzle_x; 318 /** Bit 6 swizzling required for Y tiling */ 319 uint32_t bit_6_swizzle_y; 320 } mm; 321} drm_i915_private_t; 322 323enum intel_chip_family { 324 CHIP_I8XX = 0x01, 325 CHIP_I9XX = 0x02, 326 CHIP_I915 = 0x04, 327 CHIP_I965 = 0x08, 328}; 329 330/** driver private structure attached to each drm_gem_object */ 331struct drm_i915_gem_object { 332 struct drm_gem_object *obj; 333 334 /** Current space allocated to this object in the GTT, if any. */ 335 struct drm_mm_node *gtt_space; 336 337 /** This object's place on the active/flushing/inactive lists */ 338 struct list_head list; 339 340 /** 341 * This is set if the object is on the active or flushing lists 342 * (has pending rendering), and is not set if it's on inactive (ready 343 * to be unbound). 344 */ 345 int active; 346 347 /** 348 * This is set if the object has been written to since last bound 349 * to the GTT 350 */ 351 int dirty; 352 353 /** AGP memory structure for our GTT binding. */ 354 DRM_AGP_MEM *agp_mem; 355 356 struct page **page_list; 357 358 /** 359 * Current offset of the object in GTT space. 360 * 361 * This is the same as gtt_space->start 362 */ 363 uint32_t gtt_offset; 364 365 /** Boolean whether this object has a valid gtt offset. */ 366 int gtt_bound; 367 368 /** How many users have pinned this object in GTT space */ 369 int pin_count; 370 371 /** Breadcrumb of last rendering to the buffer. */ 372 uint32_t last_rendering_seqno; 373 374 /** Current tiling mode for the object. */ 375 uint32_t tiling_mode; 376 377 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ 378 uint32_t agp_type; 379 380 /** 381 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when 382 * GEM_DOMAIN_CPU is not in the object's read domain. 383 */ 384 uint8_t *page_cpu_valid; 385}; 386 387/** 388 * Request queue structure. 389 * 390 * The request queue allows us to note sequence numbers that have been emitted 391 * and may be associated with active buffers to be retired. 392 * 393 * By keeping this list, we can avoid having to do questionable 394 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 395 * an emission time with seqnos for tracking how far ahead of the GPU we are. 396 */ 397struct drm_i915_gem_request { 398 /** GEM sequence number associated with this request. */ 399 uint32_t seqno; 400 401 /** Time at which this request was emitted, in jiffies. */ 402 unsigned long emitted_jiffies; 403 404 /** Cache domains that were flushed at the start of the request. */ 405 uint32_t flush_domains; 406 407 struct list_head list; 408}; 409 410struct drm_i915_file_private { 411 struct { 412 uint32_t last_gem_seqno; 413 uint32_t last_gem_throttle_seqno; 414 } mm; 415}; 416 417extern struct drm_ioctl_desc i915_ioctls[]; 418extern int i915_max_ioctl; 419 420 /* i915_dma.c */ 421extern void i915_kernel_lost_context(struct drm_device * dev); 422extern int i915_driver_load(struct drm_device *, unsigned long flags); 423extern int i915_driver_unload(struct drm_device *); 424extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 425extern void i915_driver_lastclose(struct drm_device * dev); 426extern void i915_driver_preclose(struct drm_device *dev, 427 struct drm_file *file_priv); 428extern void i915_driver_postclose(struct drm_device *dev, 429 struct drm_file *file_priv); 430extern int i915_driver_device_is_agp(struct drm_device * dev); 431extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 432 unsigned long arg); 433extern int i915_emit_box(struct drm_device *dev, 434 struct drm_clip_rect __user *boxes, 435 int i, int DR1, int DR4); 436 437/* i915_irq.c */ 438extern int i915_irq_emit(struct drm_device *dev, void *data, 439 struct drm_file *file_priv); 440extern int i915_irq_wait(struct drm_device *dev, void *data, 441 struct drm_file *file_priv); 442void i915_user_irq_get(struct drm_device *dev); 443void i915_user_irq_put(struct drm_device *dev); 444 445extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 446extern void i915_driver_irq_preinstall(struct drm_device * dev); 447extern int i915_driver_irq_postinstall(struct drm_device *dev); 448extern void i915_driver_irq_uninstall(struct drm_device * dev); 449extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 450 struct drm_file *file_priv); 451extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 452 struct drm_file *file_priv); 453extern int i915_enable_vblank(struct drm_device *dev, int crtc); 454extern void i915_disable_vblank(struct drm_device *dev, int crtc); 455extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 456extern u32 g45_get_vblank_counter(struct drm_device *dev, int crtc); 457extern int i915_vblank_swap(struct drm_device *dev, void *data, 458 struct drm_file *file_priv); 459 460void 461i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 462 463void 464i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 465 466 467/* i915_mem.c */ 468extern int i915_mem_alloc(struct drm_device *dev, void *data, 469 struct drm_file *file_priv); 470extern int i915_mem_free(struct drm_device *dev, void *data, 471 struct drm_file *file_priv); 472extern int i915_mem_init_heap(struct drm_device *dev, void *data, 473 struct drm_file *file_priv); 474extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 475 struct drm_file *file_priv); 476extern void i915_mem_takedown(struct mem_block **heap); 477extern void i915_mem_release(struct drm_device * dev, 478 struct drm_file *file_priv, struct mem_block *heap); 479#ifdef I915_HAVE_GEM 480/* i915_gem.c */ 481int i915_gem_init_ioctl(struct drm_device *dev, void *data, 482 struct drm_file *file_priv); 483int i915_gem_create_ioctl(struct drm_device *dev, void *data, 484 struct drm_file *file_priv); 485int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 486 struct drm_file *file_priv); 487int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 488 struct drm_file *file_priv); 489int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 490 struct drm_file *file_priv); 491int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 492 struct drm_file *file_priv); 493int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 494 struct drm_file *file_priv); 495int i915_gem_execbuffer(struct drm_device *dev, void *data, 496 struct drm_file *file_priv); 497int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 498 struct drm_file *file_priv); 499int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 500 struct drm_file *file_priv); 501int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 502 struct drm_file *file_priv); 503int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 504 struct drm_file *file_priv); 505int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 506 struct drm_file *file_priv); 507int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 508 struct drm_file *file_priv); 509int i915_gem_set_tiling(struct drm_device *dev, void *data, 510 struct drm_file *file_priv); 511int i915_gem_get_tiling(struct drm_device *dev, void *data, 512 struct drm_file *file_priv); 513void i915_gem_load(struct drm_device *dev); 514int i915_gem_proc_init(struct drm_minor *minor); 515void i915_gem_proc_cleanup(struct drm_minor *minor); 516int i915_gem_init_object(struct drm_gem_object *obj); 517void i915_gem_free_object(struct drm_gem_object *obj); 518int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 519void i915_gem_object_unpin(struct drm_gem_object *obj); 520void i915_gem_lastclose(struct drm_device *dev); 521uint32_t i915_get_gem_seqno(struct drm_device *dev); 522void i915_gem_retire_requests(struct drm_device *dev); 523void i915_gem_retire_work_handler(struct work_struct *work); 524void i915_gem_clflush_object(struct drm_gem_object *obj); 525 526/* i915_gem_tiling.c */ 527void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 528 529/* i915_gem_debug.c */ 530void i915_gem_dump_object(struct drm_gem_object *obj, int len, 531 const char *where, uint32_t mark); 532#if WATCH_INACTIVE 533void i915_verify_inactive(struct drm_device *dev, char *file, int line); 534#else 535#define i915_verify_inactive(dev, file, line) 536#endif 537void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); 538void i915_gem_dump_object(struct drm_gem_object *obj, int len, 539 const char *where, uint32_t mark); 540void i915_dump_lru(struct drm_device *dev, const char *where); 541#endif /* I915_HAVE_GEM */ 542 543/* i915_suspend.c */ 544extern int i915_save_state(struct drm_device *dev); 545extern int i915_restore_state(struct drm_device *dev); 546 547/* i915_opregion.c */ 548extern int intel_opregion_init(struct drm_device *dev); 549extern void intel_opregion_free(struct drm_device *dev); 550extern void opregion_asle_intr(struct drm_device *dev); 551extern void opregion_enable_asle(struct drm_device *dev); 552 553/** 554 * Lock test for when it's just for synchronization of ring access. 555 * 556 * In that case, we don't need to do it when GEM is initialized as nobody else 557 * has access to the ring. 558 */ 559#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ 560 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ 561 LOCK_TEST_WITH_RETURN(dev, file_priv); \ 562} while (0) 563 564#if defined(__FreeBSD__) 565typedef boolean_t bool; 566#endif 567 568#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 569#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 570#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 571#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 572#define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg)) 573#define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val)) 574 575#define I915_VERBOSE 0 576 577#define RING_LOCALS unsigned int outring, ringmask, outcount; \ 578 volatile char *virt; 579 580#define BEGIN_LP_RING(n) do { \ 581 if (I915_VERBOSE) \ 582 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 583 if (dev_priv->ring.space < (n)*4) \ 584 i915_wait_ring(dev, (n)*4, __func__); \ 585 outcount = 0; \ 586 outring = dev_priv->ring.tail; \ 587 ringmask = dev_priv->ring.tail_mask; \ 588 virt = dev_priv->ring.virtual_start; \ 589} while (0) 590 591#define OUT_RING(n) do { \ 592 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 593 *(volatile unsigned int *)(virt + outring) = (n); \ 594 outcount++; \ 595 outring += 4; \ 596 outring &= ringmask; \ 597} while (0) 598 599#define ADVANCE_LP_RING() do { \ 600 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 601 dev_priv->ring.tail = outring; \ 602 dev_priv->ring.space -= outcount * 4; \ 603 I915_WRITE(PRB0_TAIL, outring); \ 604} while(0) 605 606/** 607 * Reads a dword out of the status page, which is written to from the command 608 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 609 * MI_STORE_DATA_IMM. 610 * 611 * The following dwords have a reserved meaning: 612 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 613 * 0x04: ring 0 head pointer 614 * 0x05: ring 1 head pointer (915-class) 615 * 0x06: ring 2 head pointer (915-class) 616 * 0x10-0x1b: Context status DWords (GM45) 617 * 0x1f: Last written status offset. (GM45) 618 * 619 * The area from dword 0x20 to 0x3ff is available for driver usage. 620 */ 621#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 622#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 623#define I915_GEM_HWS_INDEX 0x20 624#define I915_BREADCRUMB_INDEX 0x21 625 626extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 627 628#define IS_I830(dev) ((dev)->pci_device == 0x3577) 629#define IS_845G(dev) ((dev)->pci_device == 0x2562) 630#define IS_I85X(dev) ((dev)->pci_device == 0x3582) 631#define IS_I855(dev) ((dev)->pci_device == 0x3582) 632#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 633 634#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) 635#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 636#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 637#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ 638 (dev)->pci_device == 0x27AE) 639#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 640 (dev)->pci_device == 0x2982 || \ 641 (dev)->pci_device == 0x2992 || \ 642 (dev)->pci_device == 0x29A2 || \ 643 (dev)->pci_device == 0x2A02 || \ 644 (dev)->pci_device == 0x2A12 || \ 645 (dev)->pci_device == 0x2A42 || \ 646 (dev)->pci_device == 0x2E02 || \ 647 (dev)->pci_device == 0x2E12 || \ 648 (dev)->pci_device == 0x2E22) 649 650#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 651 652#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 653 654#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ 655 (dev)->pci_device == 0x2E12 || \ 656 (dev)->pci_device == 0x2E22 || \ 657 IS_GM45(dev)) 658 659#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 660 (dev)->pci_device == 0x29B2 || \ 661 (dev)->pci_device == 0x29D2) 662 663#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 664 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 665 666#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 667 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) 668 669#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 670 671#define PRIMARY_RINGBUFFER_SIZE (128*1024) 672 673#endif 674