i915_drv.h revision 190020
11541Srgrimes/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 21541Srgrimes */ 31541Srgrimes/* 41541Srgrimes * 51541Srgrimes * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 61541Srgrimes * All Rights Reserved. 71541Srgrimes * 81541Srgrimes * Permission is hereby granted, free of charge, to any person obtaining a 91541Srgrimes * copy of this software and associated documentation files (the 101541Srgrimes * "Software"), to deal in the Software without restriction, including 111541Srgrimes * without limitation the rights to use, copy, modify, merge, publish, 121541Srgrimes * distribute, sub license, and/or sell copies of the Software, and to 131541Srgrimes * permit persons to whom the Software is furnished to do so, subject to 141541Srgrimes * the following conditions: 151541Srgrimes * 161541Srgrimes * The above copyright notice and this permission notice (including the 171541Srgrimes * next paragraph) shall be included in all copies or substantial portions 181541Srgrimes * of the Software. 191541Srgrimes * 201541Srgrimes * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 211541Srgrimes * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 221541Srgrimes * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 231541Srgrimes * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 241541Srgrimes * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 251541Srgrimes * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 261541Srgrimes * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 271541Srgrimes * 281541Srgrimes */ 291541Srgrimes 301541Srgrimes#include <sys/cdefs.h> 311541Srgrimes__FBSDID("$FreeBSD: head/sys/dev/drm/i915_drv.h 190020 2009-03-19 08:22:56Z rnoland $"); 321541Srgrimes 3385052Sru#ifndef _I915_DRV_H_ 3450477Speter#define _I915_DRV_H_ 351541Srgrimes 361541Srgrimes#include "dev/drm/i915_reg.h" 372168Spaul 382168Spaul/* General customization: 392168Spaul */ 401541Srgrimes 411541Srgrimes#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 428876Srgrimes 431541Srgrimes#define DRIVER_NAME "i915" 441541Srgrimes#define DRIVER_DESC "Intel Graphics" 451541Srgrimes#define DRIVER_DATE "20080730" 461541Srgrimes 471541Srgrimesenum pipe { 481541Srgrimes PIPE_A = 0, 491541Srgrimes PIPE_B, 501541Srgrimes}; 511541Srgrimes 521541Srgrimes#define I915_NUM_PIPE 2 531541Srgrimes 541541Srgrimes/* Interface history: 551541Srgrimes * 561541Srgrimes * 1.1: Original. 571541Srgrimes * 1.2: Add Power Management 581541Srgrimes * 1.3: Add vblank support 591541Srgrimes * 1.4: Fix cmdbuffer path, add heap destroy 601541Srgrimes * 1.5: Add vblank pipe configuration 61122922Sandre * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 62122922Sandre * - Support vertical blank on secondary display pipe 63122922Sandre */ 64122922Sandre#define DRIVER_MAJOR 1 65122922Sandre#define DRIVER_MINOR 6 66122922Sandre#define DRIVER_PATCHLEVEL 0 671541Srgrimes 681541Srgrimes#define WATCH_COHERENCY 0 691541Srgrimes#define WATCH_BUF 0 701541Srgrimes#define WATCH_EXEC 0 711541Srgrimes#define WATCH_LRU 0 7213765Smpp#define WATCH_RELOC 0 7313765Smpp#define WATCH_INACTIVE 0 741541Srgrimes#define WATCH_PWRITE 0 751541Srgrimes 761541Srgrimestypedef struct _drm_i915_ring_buffer { 771541Srgrimes int tail_mask; 785791Swollman unsigned long Size; 791541Srgrimes u8 *virtual_start; 801541Srgrimes int head; 811541Srgrimes int tail; 821541Srgrimes int space; 831541Srgrimes drm_local_map_t map; 841541Srgrimes struct drm_gem_object *ring_obj; 851541Srgrimes} drm_i915_ring_buffer_t; 861541Srgrimes 871541Srgrimesstruct mem_block { 881541Srgrimes struct mem_block *next; 891541Srgrimes struct mem_block *prev; 905833Sbde int start; 915833Sbde int size; 925833Sbde struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 935833Sbde}; 945833Sbde 951541Srgrimesstruct opregion_header; 961541Srgrimesstruct opregion_acpi; 971541Srgrimesstruct opregion_swsci; 981541Srgrimesstruct opregion_asle; 991541Srgrimes 1001541Srgrimesstruct intel_opregion { 1011541Srgrimes struct opregion_header *header; 1021541Srgrimes struct opregion_acpi *acpi; 1031541Srgrimes struct opregion_swsci *swsci; 1041541Srgrimes struct opregion_asle *asle; 1051541Srgrimes int enabled; 1061541Srgrimes}; 1071541Srgrimes 1081541Srgrimestypedef struct drm_i915_private { 1091541Srgrimes struct drm_device *dev; 1107197Swollman 1111541Srgrimes drm_local_map_t *sarea; 112122922Sandre drm_local_map_t *mmio_map; 113127828Sluigi 114127828Sluigi drm_i915_sarea_t *sarea_priv; 1151541Srgrimes drm_i915_ring_buffer_t ring; 1161541Srgrimes 1171541Srgrimes drm_dma_handle_t *status_page_dmah; 1185791Swollman void *hw_status_page; 119120727Ssam dma_addr_t dma_status_page; 120120727Ssam uint32_t counter; 121120727Ssam unsigned int status_gfx_addr; 122120727Ssam drm_local_map_t hws_map; 1231541Srgrimes struct drm_gem_object *hws_obj; 1241541Srgrimes 1251541Srgrimes unsigned int cpp; 1261541Srgrimes int back_offset; 1271541Srgrimes int front_offset; 1281541Srgrimes int current_page; 1291541Srgrimes int page_flipping; 1301541Srgrimes 1311541Srgrimes wait_queue_head_t irq_queue; 1321541Srgrimes atomic_t irq_received; 1331541Srgrimes /** Protects user_irq_refcount and irq_mask_reg */ 1341541Srgrimes DRM_SPINTYPE user_irq_lock; 1351541Srgrimes /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ 1361541Srgrimes int user_irq_refcount; 1371541Srgrimes /** Cached value of IER to avoid reads in updating the bitfield */ 1381541Srgrimes u32 irq_mask_reg; 1394104Swollman u32 pipestat[2]; 1404104Swollman 1411541Srgrimes int tex_lru_log_granularity; 1421541Srgrimes int allow_batchbuffer; 1431541Srgrimes struct mem_block *agp_heap; 1441541Srgrimes unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 1451541Srgrimes int vblank_pipe; 1461541Srgrimes 1471541Srgrimes struct intel_opregion opregion; 14886764Sjlemon 1491541Srgrimes /* Register state */ 1501541Srgrimes u8 saveLBB; 15117835Sjulian u32 saveDSPACNTR; 1521541Srgrimes u32 saveDSPBCNTR; 1531541Srgrimes u32 saveDSPARB; 1541541Srgrimes u32 saveRENDERSTANDBY; 1551541Srgrimes u32 saveHWS; 1561541Srgrimes u32 savePIPEACONF; 157122921Sandre u32 savePIPEBCONF; 158122921Sandre u32 savePIPEASRC; 159122921Sandre u32 savePIPEBSRC; 160122921Sandre u32 saveFPA0; 161122921Sandre u32 saveFPA1; 1625099Swollman u32 saveDPLL_A; 1635099Swollman u32 saveDPLL_A_MD; 16418839Swollman u32 saveHTOTAL_A; 1656245Swollman u32 saveHBLANK_A; 16615652Swollman u32 saveHSYNC_A; 16715652Swollman u32 saveVTOTAL_A; 16815652Swollman u32 saveVBLANK_A; 16915652Swollman u32 saveVSYNC_A; 1701541Srgrimes u32 saveBCLRPAT_A; 1711541Srgrimes u32 savePIPEASTAT; 1721541Srgrimes u32 saveDSPASTRIDE; 1731541Srgrimes u32 saveDSPASIZE; 1741541Srgrimes u32 saveDSPAPOS; 1751541Srgrimes u32 saveDSPAADDR; 1761541Srgrimes u32 saveDSPASURF; 1771541Srgrimes u32 saveDSPATILEOFF; 1781541Srgrimes u32 savePFIT_PGM_RATIOS; 1791541Srgrimes u32 saveBLC_PWM_CTL; 1801541Srgrimes u32 saveBLC_PWM_CTL2; 1811541Srgrimes u32 saveFPB0; 1821541Srgrimes u32 saveFPB1; 1831541Srgrimes u32 saveDPLL_B; 1841541Srgrimes u32 saveDPLL_B_MD; 1851541Srgrimes u32 saveHTOTAL_B; 1861541Srgrimes u32 saveHBLANK_B; 1871541Srgrimes u32 saveHSYNC_B; 1881541Srgrimes u32 saveVTOTAL_B; 1891541Srgrimes u32 saveVBLANK_B; 1901541Srgrimes u32 saveVSYNC_B; 1911541Srgrimes u32 saveBCLRPAT_B; 1921541Srgrimes u32 savePIPEBSTAT; 1931541Srgrimes u32 saveDSPBSTRIDE; 1941541Srgrimes u32 saveDSPBSIZE; 1951541Srgrimes u32 saveDSPBPOS; 1961541Srgrimes u32 saveDSPBADDR; 1971541Srgrimes u32 saveDSPBSURF; 1981541Srgrimes u32 saveDSPBTILEOFF; 1995791Swollman u32 saveVGA0; 2001541Srgrimes u32 saveVGA1; 20151252Sru u32 saveVGA_PD; 20251252Sru u32 saveVGACNTRL; 20351252Sru u32 saveADPA; 2041541Srgrimes u32 saveLVDS; 2051541Srgrimes u32 savePP_ON_DELAYS; 2061541Srgrimes u32 savePP_OFF_DELAYS; 2071541Srgrimes u32 saveDVOA; 2081541Srgrimes u32 saveDVOB; 2091541Srgrimes u32 saveDVOC; 2101541Srgrimes u32 savePP_ON; 2111541Srgrimes u32 savePP_OFF; 2121541Srgrimes u32 savePP_CONTROL; 2131541Srgrimes u32 savePP_DIVISOR; 2141541Srgrimes u32 savePFIT_CONTROL; 2151541Srgrimes u32 save_palette_a[256]; 2161541Srgrimes u32 save_palette_b[256]; 2171541Srgrimes u32 saveFBC_CFB_BASE; 21821666Swollman u32 saveFBC_LL_BASE; 21921666Swollman u32 saveFBC_CONTROL; 22089498Sru u32 saveFBC_CONTROL2; 2211541Srgrimes u32 saveIER; 22251252Sru u32 saveIIR; 22351252Sru u32 saveIMR; 22451252Sru u32 saveCACHE_MODE_0; 2251541Srgrimes u32 saveD_STATE; 2261541Srgrimes u32 saveCG_2D_DIS; 22751252Sru u32 saveMI_ARB_STATE; 2281541Srgrimes u32 saveSWF0[16]; 2291541Srgrimes u32 saveSWF1[16]; 2301541Srgrimes u32 saveSWF2[3]; 2311541Srgrimes u8 saveMSR; 2321541Srgrimes u8 saveSR[8]; 2331541Srgrimes u8 saveGR[25]; 2341541Srgrimes u8 saveAR_INDEX; 23551252Sru u8 saveAR[21]; 2361541Srgrimes u8 saveDACMASK; 2371541Srgrimes u8 saveCR[37]; 2381541Srgrimes 2391541Srgrimes struct { 2401541Srgrimes#ifdef __linux__ 2411541Srgrimes struct drm_mm gtt_space; 2421541Srgrimes#endif 2431541Srgrimes /** 2441541Srgrimes * List of objects currently involved in rendering from the 2451541Srgrimes * ringbuffer. 2461541Srgrimes * 2471541Srgrimes * A reference is held on the buffer while on this list. 2481541Srgrimes */ 2491541Srgrimes struct list_head active_list; 2501541Srgrimes 2511541Srgrimes /** 2521541Srgrimes * List of objects which are not in the ringbuffer but which 2531541Srgrimes * still have a write_domain which needs to be flushed before 2541541Srgrimes * unbinding. 2551541Srgrimes * 2561541Srgrimes * A reference is held on the buffer while on this list. 2571541Srgrimes */ 2581541Srgrimes struct list_head flushing_list; 2591541Srgrimes 2601541Srgrimes /** 2611541Srgrimes * LRU list of objects which are not in the ringbuffer and 26285074Sru * are ready to unbind, but are still in the GTT. 26385074Sru * 26485074Sru * A reference is not held on the buffer while on this list, 2651541Srgrimes * as merely being GTT-bound shouldn't prevent its being 2661541Srgrimes * freed, and we'll pull it off the list in the free path. 26755205Speter */ 268117752Shsu struct list_head inactive_list; 269120727Ssam 270120727Ssam /** 271120727Ssam * List of breadcrumbs associated with GPU requests currently 272120727Ssam * outstanding. 273120727Ssam */ 274120727Ssam struct list_head request_list; 275117752Shsu#ifdef __linux__ 276122334Ssam /** 277122334Ssam * We leave the user IRQ off as much as possible, 278122334Ssam * but this means that requests will finish and never 279122334Ssam * be retired once the system goes idle. Set a timer to 280122334Ssam * fire periodically while the ring is running. When it 281122334Ssam * fires, go retire requests. 282122334Ssam */ 283122334Ssam struct delayed_work retire_work; 284122334Ssam#endif 285122334Ssam uint32_t next_gem_seqno; 286122334Ssam 287122334Ssam /** 288122334Ssam * Waiting sequence number, if any 289122334Ssam */ 290122334Ssam uint32_t waiting_gem_seqno; 291122334Ssam 292122334Ssam /** 293122334Ssam * Last seq seen at irq time 294122334Ssam */ 295122334Ssam uint32_t irq_gem_seqno; 296122334Ssam 297122334Ssam /** 29846568Speter * Flag if the X Server, and thus DRM, is not currently in 299122334Ssam * control of the device. 300122334Ssam * 301122334Ssam * This is set between LeaveVT and EnterVT. It needs to be 302120727Ssam * replaced with a semaphore. It also needs to be 3031541Srgrimes * transitioned away from for kernel modesetting. 3049759Sbde */ 3051541Srgrimes int suspended; 30621666Swollman 30721666Swollman /** 30892725Salfred * Flag if the hardware appears to be wedged. 30992725Salfred * 31092725Salfred * This is set when attempts to idle the device timeout. 31192725Salfred * It prevents command submission from occuring and makes 31292725Salfred * every pending request fail 31392725Salfred */ 31492725Salfred int wedged; 315120727Ssam 31692725Salfred /** Bit 6 swizzling required for X tiling */ 31792725Salfred uint32_t bit_6_swizzle_x; 318120727Ssam /** Bit 6 swizzling required for Y tiling */ 319120727Ssam uint32_t bit_6_swizzle_y; 320121770Ssam } mm; 32192725Salfred} drm_i915_private_t; 32292725Salfred 32392725Salfredenum intel_chip_family { 32492725Salfred CHIP_I8XX = 0x01, 325120727Ssam CHIP_I9XX = 0x02, 32692725Salfred CHIP_I915 = 0x04, 32792725Salfred CHIP_I965 = 0x08, 32892725Salfred}; 329111767Smdodd 3301541Srgrimes/** driver private structure attached to each drm_gem_object */ 3312168Spaulstruct drm_i915_gem_object { 3322168Spaul struct drm_gem_object *obj; 333 334 /** Current space allocated to this object in the GTT, if any. */ 335 struct drm_mm_node *gtt_space; 336 337 /** This object's place on the active/flushing/inactive lists */ 338 struct list_head list; 339 340 /** 341 * This is set if the object is on the active or flushing lists 342 * (has pending rendering), and is not set if it's on inactive (ready 343 * to be unbound). 344 */ 345 int active; 346 347 /** 348 * This is set if the object has been written to since last bound 349 * to the GTT 350 */ 351 int dirty; 352 353 /** AGP memory structure for our GTT binding. */ 354 DRM_AGP_MEM *agp_mem; 355 356 struct page **page_list; 357 358 /** 359 * Current offset of the object in GTT space. 360 * 361 * This is the same as gtt_space->start 362 */ 363 uint32_t gtt_offset; 364 365 /** Boolean whether this object has a valid gtt offset. */ 366 int gtt_bound; 367 368 /** How many users have pinned this object in GTT space */ 369 int pin_count; 370 371 /** Breadcrumb of last rendering to the buffer. */ 372 uint32_t last_rendering_seqno; 373 374 /** Current tiling mode for the object. */ 375 uint32_t tiling_mode; 376 377 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ 378 uint32_t agp_type; 379 380 /** 381 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when 382 * GEM_DOMAIN_CPU is not in the object's read domain. 383 */ 384 uint8_t *page_cpu_valid; 385}; 386 387/** 388 * Request queue structure. 389 * 390 * The request queue allows us to note sequence numbers that have been emitted 391 * and may be associated with active buffers to be retired. 392 * 393 * By keeping this list, we can avoid having to do questionable 394 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 395 * an emission time with seqnos for tracking how far ahead of the GPU we are. 396 */ 397struct drm_i915_gem_request { 398 /** GEM sequence number associated with this request. */ 399 uint32_t seqno; 400 401 /** Time at which this request was emitted, in jiffies. */ 402 unsigned long emitted_jiffies; 403 404 /** Cache domains that were flushed at the start of the request. */ 405 uint32_t flush_domains; 406 407 struct list_head list; 408}; 409 410struct drm_i915_file_private { 411 struct { 412 uint32_t last_gem_seqno; 413 uint32_t last_gem_throttle_seqno; 414 } mm; 415}; 416 417extern struct drm_ioctl_desc i915_ioctls[]; 418extern int i915_max_ioctl; 419 420 /* i915_dma.c */ 421extern void i915_kernel_lost_context(struct drm_device * dev); 422extern int i915_driver_load(struct drm_device *, unsigned long flags); 423extern int i915_driver_unload(struct drm_device *); 424extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 425extern void i915_driver_lastclose(struct drm_device * dev); 426extern void i915_driver_preclose(struct drm_device *dev, 427 struct drm_file *file_priv); 428extern void i915_driver_postclose(struct drm_device *dev, 429 struct drm_file *file_priv); 430extern int i915_driver_device_is_agp(struct drm_device * dev); 431extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 432 unsigned long arg); 433extern int i915_emit_box(struct drm_device *dev, 434 struct drm_clip_rect __user *boxes, 435 int i, int DR1, int DR4); 436 437/* i915_irq.c */ 438extern int i915_irq_emit(struct drm_device *dev, void *data, 439 struct drm_file *file_priv); 440extern int i915_irq_wait(struct drm_device *dev, void *data, 441 struct drm_file *file_priv); 442void i915_user_irq_get(struct drm_device *dev); 443void i915_user_irq_put(struct drm_device *dev); 444 445extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 446extern void i915_driver_irq_preinstall(struct drm_device * dev); 447extern int i915_driver_irq_postinstall(struct drm_device *dev); 448extern void i915_driver_irq_uninstall(struct drm_device * dev); 449extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 450 struct drm_file *file_priv); 451extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 452 struct drm_file *file_priv); 453extern int i915_enable_vblank(struct drm_device *dev, int crtc); 454extern void i915_disable_vblank(struct drm_device *dev, int crtc); 455extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 456extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); 457extern int i915_vblank_swap(struct drm_device *dev, void *data, 458 struct drm_file *file_priv); 459 460void 461i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 462 463void 464i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 465 466 467/* i915_mem.c */ 468extern int i915_mem_alloc(struct drm_device *dev, void *data, 469 struct drm_file *file_priv); 470extern int i915_mem_free(struct drm_device *dev, void *data, 471 struct drm_file *file_priv); 472extern int i915_mem_init_heap(struct drm_device *dev, void *data, 473 struct drm_file *file_priv); 474extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 475 struct drm_file *file_priv); 476extern void i915_mem_takedown(struct mem_block **heap); 477extern void i915_mem_release(struct drm_device * dev, 478 struct drm_file *file_priv, struct mem_block *heap); 479#ifdef I915_HAVE_GEM 480/* i915_gem.c */ 481int i915_gem_init_ioctl(struct drm_device *dev, void *data, 482 struct drm_file *file_priv); 483int i915_gem_create_ioctl(struct drm_device *dev, void *data, 484 struct drm_file *file_priv); 485int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 486 struct drm_file *file_priv); 487int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 488 struct drm_file *file_priv); 489int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 490 struct drm_file *file_priv); 491int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 492 struct drm_file *file_priv); 493int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 494 struct drm_file *file_priv); 495int i915_gem_execbuffer(struct drm_device *dev, void *data, 496 struct drm_file *file_priv); 497int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 498 struct drm_file *file_priv); 499int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 500 struct drm_file *file_priv); 501int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 502 struct drm_file *file_priv); 503int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 504 struct drm_file *file_priv); 505int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 506 struct drm_file *file_priv); 507int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 508 struct drm_file *file_priv); 509int i915_gem_set_tiling(struct drm_device *dev, void *data, 510 struct drm_file *file_priv); 511int i915_gem_get_tiling(struct drm_device *dev, void *data, 512 struct drm_file *file_priv); 513void i915_gem_load(struct drm_device *dev); 514int i915_gem_proc_init(struct drm_minor *minor); 515void i915_gem_proc_cleanup(struct drm_minor *minor); 516int i915_gem_init_object(struct drm_gem_object *obj); 517void i915_gem_free_object(struct drm_gem_object *obj); 518int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 519void i915_gem_object_unpin(struct drm_gem_object *obj); 520void i915_gem_lastclose(struct drm_device *dev); 521uint32_t i915_get_gem_seqno(struct drm_device *dev); 522void i915_gem_retire_requests(struct drm_device *dev); 523void i915_gem_retire_work_handler(struct work_struct *work); 524void i915_gem_clflush_object(struct drm_gem_object *obj); 525 526/* i915_gem_tiling.c */ 527void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 528 529/* i915_gem_debug.c */ 530void i915_gem_dump_object(struct drm_gem_object *obj, int len, 531 const char *where, uint32_t mark); 532#if WATCH_INACTIVE 533void i915_verify_inactive(struct drm_device *dev, char *file, int line); 534#else 535#define i915_verify_inactive(dev, file, line) 536#endif 537void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); 538void i915_gem_dump_object(struct drm_gem_object *obj, int len, 539 const char *where, uint32_t mark); 540void i915_dump_lru(struct drm_device *dev, const char *where); 541#endif /* I915_HAVE_GEM */ 542 543/* i915_suspend.c */ 544extern int i915_save_state(struct drm_device *dev); 545extern int i915_restore_state(struct drm_device *dev); 546 547/* i915_opregion.c */ 548extern int intel_opregion_init(struct drm_device *dev); 549extern void intel_opregion_free(struct drm_device *dev); 550extern void opregion_asle_intr(struct drm_device *dev); 551extern void opregion_enable_asle(struct drm_device *dev); 552 553/** 554 * Lock test for when it's just for synchronization of ring access. 555 * 556 * In that case, we don't need to do it when GEM is initialized as nobody else 557 * has access to the ring. 558 */ 559#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ 560 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ 561 LOCK_TEST_WITH_RETURN(dev, file_priv); \ 562} while (0) 563 564#if defined(__FreeBSD__) 565typedef boolean_t bool; 566#endif 567 568#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 569#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 570#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 571#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 572#define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg)) 573#define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val)) 574 575#define I915_VERBOSE 0 576 577#define RING_LOCALS unsigned int outring, ringmask, outcount; \ 578 volatile char *virt; 579 580#define BEGIN_LP_RING(n) do { \ 581 if (I915_VERBOSE) \ 582 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 583 if (dev_priv->ring.space < (n)*4) \ 584 i915_wait_ring(dev, (n)*4, __func__); \ 585 outcount = 0; \ 586 outring = dev_priv->ring.tail; \ 587 ringmask = dev_priv->ring.tail_mask; \ 588 virt = dev_priv->ring.virtual_start; \ 589} while (0) 590 591#define OUT_RING(n) do { \ 592 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 593 *(volatile unsigned int *)(virt + outring) = (n); \ 594 outcount++; \ 595 outring += 4; \ 596 outring &= ringmask; \ 597} while (0) 598 599#define ADVANCE_LP_RING() do { \ 600 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 601 dev_priv->ring.tail = outring; \ 602 dev_priv->ring.space -= outcount * 4; \ 603 I915_WRITE(PRB0_TAIL, outring); \ 604} while(0) 605 606/** 607 * Reads a dword out of the status page, which is written to from the command 608 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 609 * MI_STORE_DATA_IMM. 610 * 611 * The following dwords have a reserved meaning: 612 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 613 * 0x04: ring 0 head pointer 614 * 0x05: ring 1 head pointer (915-class) 615 * 0x06: ring 2 head pointer (915-class) 616 * 0x10-0x1b: Context status DWords (GM45) 617 * 0x1f: Last written status offset. (GM45) 618 * 619 * The area from dword 0x20 to 0x3ff is available for driver usage. 620 */ 621#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 622#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 623#define I915_GEM_HWS_INDEX 0x20 624#define I915_BREADCRUMB_INDEX 0x21 625 626extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 627 628#define IS_I830(dev) ((dev)->pci_device == 0x3577) 629#define IS_845G(dev) ((dev)->pci_device == 0x2562) 630#define IS_I85X(dev) ((dev)->pci_device == 0x3582) 631#define IS_I855(dev) ((dev)->pci_device == 0x3582) 632#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 633 634#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) 635#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 636#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 637#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ 638 (dev)->pci_device == 0x27AE) 639#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 640 (dev)->pci_device == 0x2982 || \ 641 (dev)->pci_device == 0x2992 || \ 642 (dev)->pci_device == 0x29A2 || \ 643 (dev)->pci_device == 0x2A02 || \ 644 (dev)->pci_device == 0x2A12 || \ 645 (dev)->pci_device == 0x2A42 || \ 646 (dev)->pci_device == 0x2E02 || \ 647 (dev)->pci_device == 0x2E12 || \ 648 (dev)->pci_device == 0x2E22) 649 650#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 651 652#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 653 654#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ 655 (dev)->pci_device == 0x2E12 || \ 656 (dev)->pci_device == 0x2E22 || \ 657 IS_GM45(dev)) 658 659#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 660 (dev)->pci_device == 0x29B2 || \ 661 (dev)->pci_device == 0x29D2) 662 663#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 664 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 665 666#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 667 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) 668 669#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 670 671#define PRIMARY_RINGBUFFER_SIZE (128*1024) 672 673#endif 674