i915_drv.h revision 189049
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3/* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/drm/i915_drv.h 189049 2009-02-25 18:44:50Z rnoland $"); 32 33#ifndef _I915_DRV_H_ 34#define _I915_DRV_H_ 35 36#include "dev/drm/i915_reg.h" 37 38/* General customization: 39 */ 40 41#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 42 43#define DRIVER_NAME "i915" 44#define DRIVER_DESC "Intel Graphics" 45#define DRIVER_DATE "20080730" 46 47enum pipe { 48 PIPE_A = 0, 49 PIPE_B, 50}; 51 52/* Interface history: 53 * 54 * 1.1: Original. 55 * 1.2: Add Power Management 56 * 1.3: Add vblank support 57 * 1.4: Fix cmdbuffer path, add heap destroy 58 * 1.5: Add vblank pipe configuration 59 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 60 * - Support vertical blank on secondary display pipe 61 */ 62#define DRIVER_MAJOR 1 63#define DRIVER_MINOR 6 64#define DRIVER_PATCHLEVEL 0 65 66#define WATCH_COHERENCY 0 67#define WATCH_BUF 0 68#define WATCH_EXEC 0 69#define WATCH_LRU 0 70#define WATCH_RELOC 0 71#define WATCH_INACTIVE 0 72#define WATCH_PWRITE 0 73 74typedef struct _drm_i915_ring_buffer { 75 int tail_mask; 76 unsigned long Size; 77 u8 *virtual_start; 78 int head; 79 int tail; 80 int space; 81 drm_local_map_t map; 82 struct drm_gem_object *ring_obj; 83} drm_i915_ring_buffer_t; 84 85struct mem_block { 86 struct mem_block *next; 87 struct mem_block *prev; 88 int start; 89 int size; 90 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 91}; 92 93struct opregion_header; 94struct opregion_acpi; 95struct opregion_swsci; 96struct opregion_asle; 97 98struct intel_opregion { 99 struct opregion_header *header; 100 struct opregion_acpi *acpi; 101 struct opregion_swsci *swsci; 102 struct opregion_asle *asle; 103 int enabled; 104}; 105 106typedef struct drm_i915_private { 107 struct drm_device *dev; 108 109 drm_local_map_t *sarea; 110 drm_local_map_t *mmio_map; 111 112 drm_i915_sarea_t *sarea_priv; 113 drm_i915_ring_buffer_t ring; 114 115 drm_dma_handle_t *status_page_dmah; 116 void *hw_status_page; 117 dma_addr_t dma_status_page; 118 uint32_t counter; 119 unsigned int status_gfx_addr; 120 drm_local_map_t hws_map; 121 struct drm_gem_object *hws_obj; 122 123 unsigned int cpp; 124 int back_offset; 125 int front_offset; 126 int current_page; 127 int page_flipping; 128 129 wait_queue_head_t irq_queue; 130 atomic_t irq_received; 131 /** Protects user_irq_refcount and irq_mask_reg */ 132 DRM_SPINTYPE user_irq_lock; 133 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ 134 int user_irq_refcount; 135 /** Cached value of IER to avoid reads in updating the bitfield */ 136 u32 irq_mask_reg; 137 u32 pipestat[2]; 138 139 int tex_lru_log_granularity; 140 int allow_batchbuffer; 141 struct mem_block *agp_heap; 142 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 143 int vblank_pipe; 144 145 struct intel_opregion opregion; 146 147 /* Register state */ 148 u8 saveLBB; 149 u32 saveDSPACNTR; 150 u32 saveDSPBCNTR; 151 u32 saveDSPARB; 152 u32 savePIPEACONF; 153 u32 savePIPEBCONF; 154 u32 savePIPEASRC; 155 u32 savePIPEBSRC; 156 u32 saveFPA0; 157 u32 saveFPA1; 158 u32 saveDPLL_A; 159 u32 saveDPLL_A_MD; 160 u32 saveHTOTAL_A; 161 u32 saveHBLANK_A; 162 u32 saveHSYNC_A; 163 u32 saveVTOTAL_A; 164 u32 saveVBLANK_A; 165 u32 saveVSYNC_A; 166 u32 saveBCLRPAT_A; 167 u32 savePIPEASTAT; 168 u32 saveDSPASTRIDE; 169 u32 saveDSPASIZE; 170 u32 saveDSPAPOS; 171 u32 saveDSPAADDR; 172 u32 saveDSPASURF; 173 u32 saveDSPATILEOFF; 174 u32 savePFIT_PGM_RATIOS; 175 u32 saveBLC_PWM_CTL; 176 u32 saveBLC_PWM_CTL2; 177 u32 saveFPB0; 178 u32 saveFPB1; 179 u32 saveDPLL_B; 180 u32 saveDPLL_B_MD; 181 u32 saveHTOTAL_B; 182 u32 saveHBLANK_B; 183 u32 saveHSYNC_B; 184 u32 saveVTOTAL_B; 185 u32 saveVBLANK_B; 186 u32 saveVSYNC_B; 187 u32 saveBCLRPAT_B; 188 u32 savePIPEBSTAT; 189 u32 saveDSPBSTRIDE; 190 u32 saveDSPBSIZE; 191 u32 saveDSPBPOS; 192 u32 saveDSPBADDR; 193 u32 saveDSPBSURF; 194 u32 saveDSPBTILEOFF; 195 u32 saveVGA0; 196 u32 saveVGA1; 197 u32 saveVGA_PD; 198 u32 saveVGACNTRL; 199 u32 saveADPA; 200 u32 saveLVDS; 201 u32 savePP_ON_DELAYS; 202 u32 savePP_OFF_DELAYS; 203 u32 saveDVOA; 204 u32 saveDVOB; 205 u32 saveDVOC; 206 u32 savePP_ON; 207 u32 savePP_OFF; 208 u32 savePP_CONTROL; 209 u32 savePP_DIVISOR; 210 u32 savePFIT_CONTROL; 211 u32 save_palette_a[256]; 212 u32 save_palette_b[256]; 213 u32 saveFBC_CFB_BASE; 214 u32 saveFBC_LL_BASE; 215 u32 saveFBC_CONTROL; 216 u32 saveFBC_CONTROL2; 217 u32 saveIER; 218 u32 saveIIR; 219 u32 saveIMR; 220 u32 saveCACHE_MODE_0; 221 u32 saveD_STATE; 222 u32 saveCG_2D_DIS; 223 u32 saveMI_ARB_STATE; 224 u32 saveSWF0[16]; 225 u32 saveSWF1[16]; 226 u32 saveSWF2[3]; 227 u8 saveMSR; 228 u8 saveSR[8]; 229 u8 saveGR[25]; 230 u8 saveAR_INDEX; 231 u8 saveAR[21]; 232 u8 saveDACMASK; 233 u8 saveDACDATA[256*3]; /* 256 3-byte colors */ 234 u8 saveCR[37]; 235 struct { 236#ifdef __linux__ 237 struct drm_mm gtt_space; 238#endif 239 /** 240 * List of objects currently involved in rendering from the 241 * ringbuffer. 242 * 243 * A reference is held on the buffer while on this list. 244 */ 245 struct list_head active_list; 246 247 /** 248 * List of objects which are not in the ringbuffer but which 249 * still have a write_domain which needs to be flushed before 250 * unbinding. 251 * 252 * A reference is held on the buffer while on this list. 253 */ 254 struct list_head flushing_list; 255 256 /** 257 * LRU list of objects which are not in the ringbuffer and 258 * are ready to unbind, but are still in the GTT. 259 * 260 * A reference is not held on the buffer while on this list, 261 * as merely being GTT-bound shouldn't prevent its being 262 * freed, and we'll pull it off the list in the free path. 263 */ 264 struct list_head inactive_list; 265 266 /** 267 * List of breadcrumbs associated with GPU requests currently 268 * outstanding. 269 */ 270 struct list_head request_list; 271#ifdef __linux__ 272 /** 273 * We leave the user IRQ off as much as possible, 274 * but this means that requests will finish and never 275 * be retired once the system goes idle. Set a timer to 276 * fire periodically while the ring is running. When it 277 * fires, go retire requests. 278 */ 279 struct delayed_work retire_work; 280#endif 281 uint32_t next_gem_seqno; 282 283 /** 284 * Waiting sequence number, if any 285 */ 286 uint32_t waiting_gem_seqno; 287 288 /** 289 * Last seq seen at irq time 290 */ 291 uint32_t irq_gem_seqno; 292 293 /** 294 * Flag if the X Server, and thus DRM, is not currently in 295 * control of the device. 296 * 297 * This is set between LeaveVT and EnterVT. It needs to be 298 * replaced with a semaphore. It also needs to be 299 * transitioned away from for kernel modesetting. 300 */ 301 int suspended; 302 303 /** 304 * Flag if the hardware appears to be wedged. 305 * 306 * This is set when attempts to idle the device timeout. 307 * It prevents command submission from occuring and makes 308 * every pending request fail 309 */ 310 int wedged; 311 312 /** Bit 6 swizzling required for X tiling */ 313 uint32_t bit_6_swizzle_x; 314 /** Bit 6 swizzling required for Y tiling */ 315 uint32_t bit_6_swizzle_y; 316 } mm; 317} drm_i915_private_t; 318 319enum intel_chip_family { 320 CHIP_I8XX = 0x01, 321 CHIP_I9XX = 0x02, 322 CHIP_I915 = 0x04, 323 CHIP_I965 = 0x08, 324}; 325 326/** driver private structure attached to each drm_gem_object */ 327struct drm_i915_gem_object { 328 struct drm_gem_object *obj; 329 330 /** Current space allocated to this object in the GTT, if any. */ 331 struct drm_mm_node *gtt_space; 332 333 /** This object's place on the active/flushing/inactive lists */ 334 struct list_head list; 335 336 /** 337 * This is set if the object is on the active or flushing lists 338 * (has pending rendering), and is not set if it's on inactive (ready 339 * to be unbound). 340 */ 341 int active; 342 343 /** 344 * This is set if the object has been written to since last bound 345 * to the GTT 346 */ 347 int dirty; 348 349 /** AGP memory structure for our GTT binding. */ 350 DRM_AGP_MEM *agp_mem; 351 352 struct page **page_list; 353 354 /** 355 * Current offset of the object in GTT space. 356 * 357 * This is the same as gtt_space->start 358 */ 359 uint32_t gtt_offset; 360 361 /** Boolean whether this object has a valid gtt offset. */ 362 int gtt_bound; 363 364 /** How many users have pinned this object in GTT space */ 365 int pin_count; 366 367 /** Breadcrumb of last rendering to the buffer. */ 368 uint32_t last_rendering_seqno; 369 370 /** Current tiling mode for the object. */ 371 uint32_t tiling_mode; 372 373 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ 374 uint32_t agp_type; 375 376 /** 377 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when 378 * GEM_DOMAIN_CPU is not in the object's read domain. 379 */ 380 uint8_t *page_cpu_valid; 381}; 382 383/** 384 * Request queue structure. 385 * 386 * The request queue allows us to note sequence numbers that have been emitted 387 * and may be associated with active buffers to be retired. 388 * 389 * By keeping this list, we can avoid having to do questionable 390 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 391 * an emission time with seqnos for tracking how far ahead of the GPU we are. 392 */ 393struct drm_i915_gem_request { 394 /** GEM sequence number associated with this request. */ 395 uint32_t seqno; 396 397 /** Time at which this request was emitted, in jiffies. */ 398 unsigned long emitted_jiffies; 399 400 /** Cache domains that were flushed at the start of the request. */ 401 uint32_t flush_domains; 402 403 struct list_head list; 404}; 405 406struct drm_i915_file_private { 407 struct { 408 uint32_t last_gem_seqno; 409 uint32_t last_gem_throttle_seqno; 410 } mm; 411}; 412 413extern struct drm_ioctl_desc i915_ioctls[]; 414extern int i915_max_ioctl; 415 416 /* i915_dma.c */ 417extern void i915_kernel_lost_context(struct drm_device * dev); 418extern int i915_driver_load(struct drm_device *, unsigned long flags); 419extern int i915_driver_unload(struct drm_device *); 420extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 421extern void i915_driver_lastclose(struct drm_device * dev); 422extern void i915_driver_preclose(struct drm_device *dev, 423 struct drm_file *file_priv); 424extern void i915_driver_postclose(struct drm_device *dev, 425 struct drm_file *file_priv); 426extern int i915_driver_device_is_agp(struct drm_device * dev); 427extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 428 unsigned long arg); 429extern int i915_emit_box(struct drm_device *dev, 430 struct drm_clip_rect __user *boxes, 431 int i, int DR1, int DR4); 432 433/* i915_irq.c */ 434extern int i915_irq_emit(struct drm_device *dev, void *data, 435 struct drm_file *file_priv); 436extern int i915_irq_wait(struct drm_device *dev, void *data, 437 struct drm_file *file_priv); 438void i915_user_irq_get(struct drm_device *dev); 439void i915_user_irq_put(struct drm_device *dev); 440 441extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 442extern void i915_driver_irq_preinstall(struct drm_device * dev); 443extern int i915_driver_irq_postinstall(struct drm_device *dev); 444extern void i915_driver_irq_uninstall(struct drm_device * dev); 445extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 446 struct drm_file *file_priv); 447extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 448 struct drm_file *file_priv); 449extern int i915_enable_vblank(struct drm_device *dev, int crtc); 450extern void i915_disable_vblank(struct drm_device *dev, int crtc); 451extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 452extern int i915_vblank_swap(struct drm_device *dev, void *data, 453 struct drm_file *file_priv); 454 455void 456i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 457 458void 459i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 460 461 462/* i915_mem.c */ 463extern int i915_mem_alloc(struct drm_device *dev, void *data, 464 struct drm_file *file_priv); 465extern int i915_mem_free(struct drm_device *dev, void *data, 466 struct drm_file *file_priv); 467extern int i915_mem_init_heap(struct drm_device *dev, void *data, 468 struct drm_file *file_priv); 469extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 470 struct drm_file *file_priv); 471extern void i915_mem_takedown(struct mem_block **heap); 472extern void i915_mem_release(struct drm_device * dev, 473 struct drm_file *file_priv, struct mem_block *heap); 474#ifdef I915_HAVE_GEM 475/* i915_gem.c */ 476int i915_gem_init_ioctl(struct drm_device *dev, void *data, 477 struct drm_file *file_priv); 478int i915_gem_create_ioctl(struct drm_device *dev, void *data, 479 struct drm_file *file_priv); 480int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 481 struct drm_file *file_priv); 482int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 483 struct drm_file *file_priv); 484int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 485 struct drm_file *file_priv); 486int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 487 struct drm_file *file_priv); 488int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 489 struct drm_file *file_priv); 490int i915_gem_execbuffer(struct drm_device *dev, void *data, 491 struct drm_file *file_priv); 492int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 493 struct drm_file *file_priv); 494int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 495 struct drm_file *file_priv); 496int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 497 struct drm_file *file_priv); 498int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 499 struct drm_file *file_priv); 500int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 501 struct drm_file *file_priv); 502int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 503 struct drm_file *file_priv); 504int i915_gem_set_tiling(struct drm_device *dev, void *data, 505 struct drm_file *file_priv); 506int i915_gem_get_tiling(struct drm_device *dev, void *data, 507 struct drm_file *file_priv); 508void i915_gem_load(struct drm_device *dev); 509int i915_gem_proc_init(struct drm_minor *minor); 510void i915_gem_proc_cleanup(struct drm_minor *minor); 511int i915_gem_init_object(struct drm_gem_object *obj); 512void i915_gem_free_object(struct drm_gem_object *obj); 513int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 514void i915_gem_object_unpin(struct drm_gem_object *obj); 515void i915_gem_lastclose(struct drm_device *dev); 516uint32_t i915_get_gem_seqno(struct drm_device *dev); 517void i915_gem_retire_requests(struct drm_device *dev); 518void i915_gem_retire_work_handler(struct work_struct *work); 519void i915_gem_clflush_object(struct drm_gem_object *obj); 520 521/* i915_gem_tiling.c */ 522void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 523 524/* i915_gem_debug.c */ 525void i915_gem_dump_object(struct drm_gem_object *obj, int len, 526 const char *where, uint32_t mark); 527#if WATCH_INACTIVE 528void i915_verify_inactive(struct drm_device *dev, char *file, int line); 529#else 530#define i915_verify_inactive(dev, file, line) 531#endif 532void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); 533void i915_gem_dump_object(struct drm_gem_object *obj, int len, 534 const char *where, uint32_t mark); 535void i915_dump_lru(struct drm_device *dev, const char *where); 536#endif /* I915_HAVE_GEM */ 537 538/* i915_suspend.c */ 539extern int i915_save_state(struct drm_device *dev); 540extern int i915_restore_state(struct drm_device *dev); 541 542/* i915_opregion.c */ 543extern int intel_opregion_init(struct drm_device *dev); 544extern void intel_opregion_free(struct drm_device *dev); 545extern void opregion_asle_intr(struct drm_device *dev); 546extern void opregion_enable_asle(struct drm_device *dev); 547 548/** 549 * Lock test for when it's just for synchronization of ring access. 550 * 551 * In that case, we don't need to do it when GEM is initialized as nobody else 552 * has access to the ring. 553 */ 554#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ 555 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ 556 LOCK_TEST_WITH_RETURN(dev, file_priv); \ 557} while (0) 558 559#if defined(__FreeBSD__) 560typedef boolean_t bool; 561#endif 562 563#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 564#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 565#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 566#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 567#define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg)) 568#define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val)) 569 570#define I915_VERBOSE 0 571 572#define RING_LOCALS unsigned int outring, ringmask, outcount; \ 573 volatile char *virt; 574 575#define BEGIN_LP_RING(n) do { \ 576 if (I915_VERBOSE) \ 577 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 578 if (dev_priv->ring.space < (n)*4) \ 579 i915_wait_ring(dev, (n)*4, __func__); \ 580 outcount = 0; \ 581 outring = dev_priv->ring.tail; \ 582 ringmask = dev_priv->ring.tail_mask; \ 583 virt = dev_priv->ring.virtual_start; \ 584} while (0) 585 586#define OUT_RING(n) do { \ 587 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 588 *(volatile unsigned int *)(virt + outring) = (n); \ 589 outcount++; \ 590 outring += 4; \ 591 outring &= ringmask; \ 592} while (0) 593 594#define ADVANCE_LP_RING() do { \ 595 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 596 dev_priv->ring.tail = outring; \ 597 dev_priv->ring.space -= outcount * 4; \ 598 I915_WRITE(PRB0_TAIL, outring); \ 599} while(0) 600 601/** 602 * Reads a dword out of the status page, which is written to from the command 603 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 604 * MI_STORE_DATA_IMM. 605 * 606 * The following dwords have a reserved meaning: 607 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 608 * 0x04: ring 0 head pointer 609 * 0x05: ring 1 head pointer (915-class) 610 * 0x06: ring 2 head pointer (915-class) 611 * 0x10-0x1b: Context status DWords (GM45) 612 * 0x1f: Last written status offset. (GM45) 613 * 614 * The area from dword 0x20 to 0x3ff is available for driver usage. 615 */ 616#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 617#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 618#define I915_GEM_HWS_INDEX 0x20 619#define I915_BREADCRUMB_INDEX 0x21 620 621extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 622 623#define IS_I830(dev) ((dev)->pci_device == 0x3577) 624#define IS_845G(dev) ((dev)->pci_device == 0x2562) 625#define IS_I85X(dev) ((dev)->pci_device == 0x3582) 626#define IS_I855(dev) ((dev)->pci_device == 0x3582) 627#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 628 629#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) 630#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 631#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 632#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ 633 (dev)->pci_device == 0x27AE) 634#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 635 (dev)->pci_device == 0x2982 || \ 636 (dev)->pci_device == 0x2992 || \ 637 (dev)->pci_device == 0x29A2 || \ 638 (dev)->pci_device == 0x2A02 || \ 639 (dev)->pci_device == 0x2A12 || \ 640 (dev)->pci_device == 0x2A42 || \ 641 (dev)->pci_device == 0x2E02 || \ 642 (dev)->pci_device == 0x2E12 || \ 643 (dev)->pci_device == 0x2E22) 644 645#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 646 647#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 648 649#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ 650 (dev)->pci_device == 0x2E12 || \ 651 (dev)->pci_device == 0x2E22) 652 653#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 654 (dev)->pci_device == 0x29B2 || \ 655 (dev)->pci_device == 0x29D2) 656 657#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 658 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 659 660#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 661 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) 662 663#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 664 665#define PRIMARY_RINGBUFFER_SIZE (128*1024) 666 667#endif 668