1152909Sanholt/*- 2152909Sanholt * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 3152909Sanholt * All Rights Reserved. 4182080Srnoland * 5152909Sanholt * Permission is hereby granted, free of charge, to any person obtaining a 6152909Sanholt * copy of this software and associated documentation files (the 7152909Sanholt * "Software"), to deal in the Software without restriction, including 8152909Sanholt * without limitation the rights to use, copy, modify, merge, publish, 9152909Sanholt * distribute, sub license, and/or sell copies of the Software, and to 10152909Sanholt * permit persons to whom the Software is furnished to do so, subject to 11152909Sanholt * the following conditions: 12182080Srnoland * 13152909Sanholt * The above copyright notice and this permission notice (including the 14152909Sanholt * next paragraph) shall be included in all copies or substantial portions 15152909Sanholt * of the Software. 16182080Srnoland * 17152909Sanholt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18152909Sanholt * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19152909Sanholt * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20152909Sanholt * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 21152909Sanholt * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22152909Sanholt * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23152909Sanholt * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24182080Srnoland * 25152909Sanholt */ 26145132Sanholt 27152909Sanholt#include <sys/cdefs.h> 28152909Sanholt__FBSDID("$FreeBSD$"); 29152909Sanholt 30145132Sanholt#ifndef _I915_DRM_H_ 31145132Sanholt#define _I915_DRM_H_ 32145132Sanholt 33145132Sanholt/* Please note that modifications to all structs defined here are 34145132Sanholt * subject to backwards-compatibility constraints. 35145132Sanholt */ 36145132Sanholt 37152909Sanholt#include "dev/drm/drm.h" 38145132Sanholt 39145132Sanholt/* Each region is a minimum of 16k, and there are at most 255 of them. 40145132Sanholt */ 41145132Sanholt#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use 42145132Sanholt * of chars for next/prev indices */ 43145132Sanholt#define I915_LOG_MIN_TEX_REGION_SIZE 14 44145132Sanholt 45145132Sanholttypedef struct _drm_i915_init { 46145132Sanholt enum { 47145132Sanholt I915_INIT_DMA = 0x01, 48145132Sanholt I915_CLEANUP_DMA = 0x02, 49182080Srnoland I915_RESUME_DMA = 0x03, 50182080Srnoland 51182080Srnoland /* Since this struct isn't versioned, just used a new 52182080Srnoland * 'func' code to indicate the presence of dri2 sarea 53182080Srnoland * info. */ 54182080Srnoland I915_INIT_DMA2 = 0x04 55145132Sanholt } func; 56145132Sanholt unsigned int mmio_offset; 57145132Sanholt int sarea_priv_offset; 58145132Sanholt unsigned int ring_start; 59145132Sanholt unsigned int ring_end; 60145132Sanholt unsigned int ring_size; 61145132Sanholt unsigned int front_offset; 62145132Sanholt unsigned int back_offset; 63145132Sanholt unsigned int depth_offset; 64145132Sanholt unsigned int w; 65145132Sanholt unsigned int h; 66145132Sanholt unsigned int pitch; 67145132Sanholt unsigned int pitch_bits; 68145132Sanholt unsigned int back_pitch; 69145132Sanholt unsigned int depth_pitch; 70145132Sanholt unsigned int cpp; 71145132Sanholt unsigned int chipset; 72182080Srnoland unsigned int sarea_handle; 73145132Sanholt} drm_i915_init_t; 74145132Sanholt 75182080Srnolandtypedef struct drm_i915_sarea { 76182080Srnoland struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 77145132Sanholt int last_upload; /* last time texture was uploaded */ 78145132Sanholt int last_enqueue; /* last time a buffer was enqueued */ 79145132Sanholt int last_dispatch; /* age of the most recently dispatched buffer */ 80145132Sanholt int ctxOwner; /* last context to upload state */ 81145132Sanholt int texAge; 82145132Sanholt int pf_enabled; /* is pageflipping allowed? */ 83145132Sanholt int pf_active; 84145132Sanholt int pf_current_page; /* which buffer is being displayed? */ 85145132Sanholt int perf_boxes; /* performance boxes to be displayed */ 86157617Sanholt int width, height; /* screen size in pixels */ 87157617Sanholt 88157617Sanholt drm_handle_t front_handle; 89157617Sanholt int front_offset; 90157617Sanholt int front_size; 91157617Sanholt 92157617Sanholt drm_handle_t back_handle; 93157617Sanholt int back_offset; 94157617Sanholt int back_size; 95157617Sanholt 96157617Sanholt drm_handle_t depth_handle; 97157617Sanholt int depth_offset; 98157617Sanholt int depth_size; 99157617Sanholt 100157617Sanholt drm_handle_t tex_handle; 101157617Sanholt int tex_offset; 102157617Sanholt int tex_size; 103157617Sanholt int log_tex_granularity; 104157617Sanholt int pitch; 105157617Sanholt int rotation; /* 0, 90, 180 or 270 */ 106157617Sanholt int rotated_offset; 107157617Sanholt int rotated_size; 108157617Sanholt int rotated_pitch; 109162132Sanholt int virtualX, virtualY; 110162132Sanholt 111162132Sanholt unsigned int front_tiled; 112162132Sanholt unsigned int back_tiled; 113162132Sanholt unsigned int depth_tiled; 114162132Sanholt unsigned int rotated_tiled; 115162132Sanholt unsigned int rotated2_tiled; 116182080Srnoland 117182080Srnoland int planeA_x; 118182080Srnoland int planeA_y; 119182080Srnoland int planeA_w; 120182080Srnoland int planeA_h; 121182080Srnoland int planeB_x; 122182080Srnoland int planeB_y; 123182080Srnoland int planeB_w; 124182080Srnoland int planeB_h; 125182080Srnoland 126182080Srnoland /* Triple buffering */ 127182080Srnoland drm_handle_t third_handle; 128182080Srnoland int third_offset; 129182080Srnoland int third_size; 130182080Srnoland unsigned int third_tiled; 131182080Srnoland 132182080Srnoland /* buffer object handles for the static buffers. May change 133182080Srnoland * over the lifetime of the client, though it doesn't in our current 134182080Srnoland * implementation. 135182080Srnoland */ 136182080Srnoland unsigned int front_bo_handle; 137182080Srnoland unsigned int back_bo_handle; 138182080Srnoland unsigned int third_bo_handle; 139182080Srnoland unsigned int depth_bo_handle; 140145132Sanholt} drm_i915_sarea_t; 141145132Sanholt 142182080Srnoland/* Driver specific fence types and classes. 143182080Srnoland */ 144182080Srnoland 145182080Srnoland/* The only fence class we support */ 146182080Srnoland#define DRM_I915_FENCE_CLASS_ACCEL 0 147182080Srnoland/* Fence type that guarantees read-write flush */ 148182080Srnoland#define DRM_I915_FENCE_TYPE_RW 2 149182080Srnoland/* MI_FLUSH programmed just before the fence */ 150182080Srnoland#define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000 151182080Srnoland 152145132Sanholt/* Flags for perf_boxes 153145132Sanholt */ 154145132Sanholt#define I915_BOX_RING_EMPTY 0x1 155145132Sanholt#define I915_BOX_FLIP 0x2 156145132Sanholt#define I915_BOX_WAIT 0x4 157145132Sanholt#define I915_BOX_TEXTURE_LOAD 0x8 158145132Sanholt#define I915_BOX_LOST_CONTEXT 0x10 159145132Sanholt 160145132Sanholt/* I915 specific ioctls 161145132Sanholt * The device specific ioctl range is 0x40 to 0x79. 162145132Sanholt */ 163145132Sanholt#define DRM_I915_INIT 0x00 164145132Sanholt#define DRM_I915_FLUSH 0x01 165145132Sanholt#define DRM_I915_FLIP 0x02 166145132Sanholt#define DRM_I915_BATCHBUFFER 0x03 167145132Sanholt#define DRM_I915_IRQ_EMIT 0x04 168145132Sanholt#define DRM_I915_IRQ_WAIT 0x05 169145132Sanholt#define DRM_I915_GETPARAM 0x06 170145132Sanholt#define DRM_I915_SETPARAM 0x07 171145132Sanholt#define DRM_I915_ALLOC 0x08 172145132Sanholt#define DRM_I915_FREE 0x09 173145132Sanholt#define DRM_I915_INIT_HEAP 0x0a 174145132Sanholt#define DRM_I915_CMDBUFFER 0x0b 175157617Sanholt#define DRM_I915_DESTROY_HEAP 0x0c 176162132Sanholt#define DRM_I915_SET_VBLANK_PIPE 0x0d 177162132Sanholt#define DRM_I915_GET_VBLANK_PIPE 0x0e 178182080Srnoland#define DRM_I915_VBLANK_SWAP 0x0f 179182080Srnoland#define DRM_I915_MMIO 0x10 180182080Srnoland#define DRM_I915_HWS_ADDR 0x11 181182080Srnoland#define DRM_I915_EXECBUFFER 0x12 182183573Srnoland#define DRM_I915_GEM_INIT 0x13 183183573Srnoland#define DRM_I915_GEM_EXECBUFFER 0x14 184183573Srnoland#define DRM_I915_GEM_PIN 0x15 185183573Srnoland#define DRM_I915_GEM_UNPIN 0x16 186183573Srnoland#define DRM_I915_GEM_BUSY 0x17 187183573Srnoland#define DRM_I915_GEM_THROTTLE 0x18 188183573Srnoland#define DRM_I915_GEM_ENTERVT 0x19 189183573Srnoland#define DRM_I915_GEM_LEAVEVT 0x1a 190183573Srnoland#define DRM_I915_GEM_CREATE 0x1b 191183573Srnoland#define DRM_I915_GEM_PREAD 0x1c 192183573Srnoland#define DRM_I915_GEM_PWRITE 0x1d 193183573Srnoland#define DRM_I915_GEM_MMAP 0x1e 194183573Srnoland#define DRM_I915_GEM_SET_DOMAIN 0x1f 195183573Srnoland#define DRM_I915_GEM_SW_FINISH 0x20 196183573Srnoland#define DRM_I915_GEM_SET_TILING 0x21 197183573Srnoland#define DRM_I915_GEM_GET_TILING 0x22 198145132Sanholt 199145132Sanholt#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 200145132Sanholt#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 201182080Srnoland#define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t) 202145132Sanholt#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 203145132Sanholt#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 204145132Sanholt#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 205145132Sanholt#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 206145132Sanholt#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 207145132Sanholt#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 208145132Sanholt#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 209145132Sanholt#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 210145132Sanholt#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 211157617Sanholt#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 212162132Sanholt#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 213162132Sanholt#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 214182080Srnoland#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 215182080Srnoland#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio) 216182080Srnoland#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer) 217183573Srnoland#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 218183573Srnoland#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 219183573Srnoland#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 220183573Srnoland#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 221183573Srnoland#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 222183573Srnoland#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 223183573Srnoland#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 224183573Srnoland#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 225183573Srnoland#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 226183573Srnoland#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 227183573Srnoland#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 228183573Srnoland#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 229183573Srnoland#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 230183573Srnoland#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 231183573Srnoland#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 232183573Srnoland#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 233145132Sanholt 234182080Srnoland/* Asynchronous page flipping: 235182080Srnoland */ 236182080Srnolandtypedef struct drm_i915_flip { 237182080Srnoland /* 238182080Srnoland * This is really talking about planes, and we could rename it 239182080Srnoland * except for the fact that some of the duplicated i915_drm.h files 240182080Srnoland * out there check for HAVE_I915_FLIP and so might pick up this 241182080Srnoland * version. 242182080Srnoland */ 243182080Srnoland int pipes; 244182080Srnoland} drm_i915_flip_t; 245157617Sanholt 246145132Sanholt/* Allow drivers to submit batchbuffers directly to hardware, relying 247145132Sanholt * on the security mechanisms provided by hardware. 248145132Sanholt */ 249182080Srnolandtypedef struct drm_i915_batchbuffer { 250145132Sanholt int start; /* agp offset */ 251145132Sanholt int used; /* nr bytes in use */ 252145132Sanholt int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 253145132Sanholt int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 254145132Sanholt int num_cliprects; /* mulitpass with multiple cliprects? */ 255182080Srnoland struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 256145132Sanholt} drm_i915_batchbuffer_t; 257145132Sanholt 258145132Sanholt/* As above, but pass a pointer to userspace buffer which can be 259145132Sanholt * validated by the kernel prior to sending to hardware. 260145132Sanholt */ 261145132Sanholttypedef struct _drm_i915_cmdbuffer { 262145132Sanholt char __user *buf; /* pointer to userspace command buffer */ 263145132Sanholt int sz; /* nr bytes in buf */ 264145132Sanholt int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ 265145132Sanholt int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ 266145132Sanholt int num_cliprects; /* mulitpass with multiple cliprects? */ 267182080Srnoland struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ 268145132Sanholt} drm_i915_cmdbuffer_t; 269145132Sanholt 270145132Sanholt/* Userspace can request & wait on irq's: 271145132Sanholt */ 272145132Sanholttypedef struct drm_i915_irq_emit { 273145132Sanholt int __user *irq_seq; 274145132Sanholt} drm_i915_irq_emit_t; 275145132Sanholt 276145132Sanholttypedef struct drm_i915_irq_wait { 277145132Sanholt int irq_seq; 278145132Sanholt} drm_i915_irq_wait_t; 279145132Sanholt 280145132Sanholt/* Ioctl to query kernel params: 281145132Sanholt */ 282145132Sanholt#define I915_PARAM_IRQ_ACTIVE 1 283145132Sanholt#define I915_PARAM_ALLOW_BATCHBUFFER 2 284157617Sanholt#define I915_PARAM_LAST_DISPATCH 3 285182080Srnoland#define I915_PARAM_CHIPSET_ID 4 286183573Srnoland#define I915_PARAM_HAS_GEM 5 287145132Sanholt 288145132Sanholttypedef struct drm_i915_getparam { 289145132Sanholt int param; 290145132Sanholt int __user *value; 291145132Sanholt} drm_i915_getparam_t; 292145132Sanholt 293145132Sanholt/* Ioctl to set kernel params: 294145132Sanholt */ 295145132Sanholt#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 296145132Sanholt#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 297145132Sanholt#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 298145132Sanholt 299145132Sanholttypedef struct drm_i915_setparam { 300145132Sanholt int param; 301145132Sanholt int value; 302145132Sanholt} drm_i915_setparam_t; 303145132Sanholt 304145132Sanholt/* A memory manager for regions of shared memory: 305145132Sanholt */ 306145132Sanholt#define I915_MEM_REGION_AGP 1 307145132Sanholt 308145132Sanholttypedef struct drm_i915_mem_alloc { 309145132Sanholt int region; 310145132Sanholt int alignment; 311145132Sanholt int size; 312145132Sanholt int __user *region_offset; /* offset from start of fb or agp */ 313145132Sanholt} drm_i915_mem_alloc_t; 314145132Sanholt 315145132Sanholttypedef struct drm_i915_mem_free { 316145132Sanholt int region; 317145132Sanholt int region_offset; 318145132Sanholt} drm_i915_mem_free_t; 319145132Sanholt 320145132Sanholttypedef struct drm_i915_mem_init_heap { 321145132Sanholt int region; 322145132Sanholt int size; 323145132Sanholt int start; 324145132Sanholt} drm_i915_mem_init_heap_t; 325145132Sanholt 326157617Sanholt/* Allow memory manager to be torn down and re-initialized (eg on 327157617Sanholt * rotate): 328157617Sanholt */ 329157617Sanholttypedef struct drm_i915_mem_destroy_heap { 330182080Srnoland int region; 331157617Sanholt} drm_i915_mem_destroy_heap_t; 332157617Sanholt 333162132Sanholt/* Allow X server to configure which pipes to monitor for vblank signals 334162132Sanholt */ 335162132Sanholt#define DRM_I915_VBLANK_PIPE_A 1 336162132Sanholt#define DRM_I915_VBLANK_PIPE_B 2 337162132Sanholt 338162132Sanholttypedef struct drm_i915_vblank_pipe { 339162132Sanholt int pipe; 340162132Sanholt} drm_i915_vblank_pipe_t; 341162132Sanholt 342182080Srnoland/* Schedule buffer swap at given vertical blank: 343182080Srnoland */ 344182080Srnolandtypedef struct drm_i915_vblank_swap { 345182080Srnoland drm_drawable_t drawable; 346182080Srnoland enum drm_vblank_seq_type seqtype; 347182080Srnoland unsigned int sequence; 348182080Srnoland} drm_i915_vblank_swap_t; 349182080Srnoland 350182080Srnoland#define I915_MMIO_READ 0 351182080Srnoland#define I915_MMIO_WRITE 1 352182080Srnoland 353182080Srnoland#define I915_MMIO_MAY_READ 0x1 354182080Srnoland#define I915_MMIO_MAY_WRITE 0x2 355182080Srnoland 356182080Srnoland#define MMIO_REGS_IA_PRIMATIVES_COUNT 0 357182080Srnoland#define MMIO_REGS_IA_VERTICES_COUNT 1 358182080Srnoland#define MMIO_REGS_VS_INVOCATION_COUNT 2 359182080Srnoland#define MMIO_REGS_GS_PRIMITIVES_COUNT 3 360182080Srnoland#define MMIO_REGS_GS_INVOCATION_COUNT 4 361182080Srnoland#define MMIO_REGS_CL_PRIMITIVES_COUNT 5 362182080Srnoland#define MMIO_REGS_CL_INVOCATION_COUNT 6 363182080Srnoland#define MMIO_REGS_PS_INVOCATION_COUNT 7 364182080Srnoland#define MMIO_REGS_PS_DEPTH_COUNT 8 365182080Srnoland 366182080Srnolandtypedef struct drm_i915_mmio_entry { 367182080Srnoland unsigned int flag; 368182080Srnoland unsigned int offset; 369182080Srnoland unsigned int size; 370182080Srnoland} drm_i915_mmio_entry_t; 371182080Srnoland 372182080Srnolandtypedef struct drm_i915_mmio { 373182080Srnoland unsigned int read_write:1; 374182080Srnoland unsigned int reg:31; 375182080Srnoland void __user *data; 376182080Srnoland} drm_i915_mmio_t; 377182080Srnoland 378182080Srnolandtypedef struct drm_i915_hws_addr { 379182080Srnoland uint64_t addr; 380182080Srnoland} drm_i915_hws_addr_t; 381182080Srnoland 382182080Srnoland/* 383182080Srnoland * Relocation header is 4 uint32_ts 384182080Srnoland * 0 - 32 bit reloc count 385182080Srnoland * 1 - 32-bit relocation type 386182080Srnoland * 2-3 - 64-bit user buffer handle ptr for another list of relocs. 387182080Srnoland */ 388182080Srnoland#define I915_RELOC_HEADER 4 389182080Srnoland 390182080Srnoland/* 391182080Srnoland * type 0 relocation has 4-uint32_t stride 392182080Srnoland * 0 - offset into buffer 393182080Srnoland * 1 - delta to add in 394182080Srnoland * 2 - buffer handle 395182080Srnoland * 3 - reserved (for optimisations later). 396182080Srnoland */ 397182080Srnoland/* 398182080Srnoland * type 1 relocation has 4-uint32_t stride. 399182080Srnoland * Hangs off the first item in the op list. 400182080Srnoland * Performed after all valiations are done. 401182080Srnoland * Try to group relocs into the same relocatee together for 402182080Srnoland * performance reasons. 403182080Srnoland * 0 - offset into buffer 404182080Srnoland * 1 - delta to add in 405182080Srnoland * 2 - buffer index in op list. 406182080Srnoland * 3 - relocatee index in op list. 407182080Srnoland */ 408182080Srnoland#define I915_RELOC_TYPE_0 0 409182080Srnoland#define I915_RELOC0_STRIDE 4 410182080Srnoland#define I915_RELOC_TYPE_1 1 411182080Srnoland#define I915_RELOC1_STRIDE 4 412182080Srnoland 413182080Srnoland 414182080Srnolandstruct drm_i915_op_arg { 415182080Srnoland uint64_t next; 416182080Srnoland uint64_t reloc_ptr; 417182080Srnoland int handled; 418182080Srnoland unsigned int pad64; 419182080Srnoland union { 420182080Srnoland struct drm_bo_op_req req; 421182080Srnoland struct drm_bo_arg_rep rep; 422182080Srnoland } d; 423182080Srnoland 424182080Srnoland}; 425182080Srnoland 426182080Srnolandstruct drm_i915_execbuffer { 427182080Srnoland uint64_t ops_list; 428182080Srnoland uint32_t num_buffers; 429182080Srnoland struct drm_i915_batchbuffer batch; 430182080Srnoland drm_context_t context; /* for lockless use in the future */ 431182080Srnoland struct drm_fence_arg fence_arg; 432182080Srnoland}; 433182080Srnoland 434183573Srnolandstruct drm_i915_gem_init { 435183573Srnoland /** 436183573Srnoland * Beginning offset in the GTT to be managed by the DRM memory 437183573Srnoland * manager. 438183573Srnoland */ 439183573Srnoland uint64_t gtt_start; 440183573Srnoland /** 441183573Srnoland * Ending offset in the GTT to be managed by the DRM memory 442183573Srnoland * manager. 443183573Srnoland */ 444183573Srnoland uint64_t gtt_end; 445183573Srnoland}; 446183573Srnoland 447183573Srnolandstruct drm_i915_gem_create { 448183573Srnoland /** 449183573Srnoland * Requested size for the object. 450183573Srnoland * 451183573Srnoland * The (page-aligned) allocated size for the object will be returned. 452183573Srnoland */ 453183573Srnoland uint64_t size; 454183573Srnoland /** 455183573Srnoland * Returned handle for the object. 456183573Srnoland * 457183573Srnoland * Object handles are nonzero. 458183573Srnoland */ 459183573Srnoland uint32_t handle; 460183573Srnoland uint32_t pad; 461183573Srnoland}; 462183573Srnoland 463183573Srnolandstruct drm_i915_gem_pread { 464183573Srnoland /** Handle for the object being read. */ 465183573Srnoland uint32_t handle; 466183573Srnoland uint32_t pad; 467183573Srnoland /** Offset into the object to read from */ 468183573Srnoland uint64_t offset; 469183573Srnoland /** Length of data to read */ 470183573Srnoland uint64_t size; 471183573Srnoland /** Pointer to write the data into. */ 472183573Srnoland uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */ 473183573Srnoland}; 474183573Srnoland 475183573Srnolandstruct drm_i915_gem_pwrite { 476183573Srnoland /** Handle for the object being written to. */ 477183573Srnoland uint32_t handle; 478183573Srnoland uint32_t pad; 479183573Srnoland /** Offset into the object to write to */ 480183573Srnoland uint64_t offset; 481183573Srnoland /** Length of data to write */ 482183573Srnoland uint64_t size; 483183573Srnoland /** Pointer to read the data from. */ 484183573Srnoland uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */ 485183573Srnoland}; 486183573Srnoland 487183573Srnolandstruct drm_i915_gem_mmap { 488183573Srnoland /** Handle for the object being mapped. */ 489183573Srnoland uint32_t handle; 490183573Srnoland uint32_t pad; 491183573Srnoland /** Offset in the object to map. */ 492183573Srnoland uint64_t offset; 493183573Srnoland /** 494183573Srnoland * Length of data to map. 495183573Srnoland * 496183573Srnoland * The value will be page-aligned. 497183573Srnoland */ 498183573Srnoland uint64_t size; 499183573Srnoland /** Returned pointer the data was mapped at */ 500183573Srnoland uint64_t addr_ptr; /* void *, but pointers are not 32/64 compatible */ 501183573Srnoland}; 502183573Srnoland 503183573Srnolandstruct drm_i915_gem_set_domain { 504183573Srnoland /** Handle for the object */ 505183573Srnoland uint32_t handle; 506183573Srnoland 507183573Srnoland /** New read domains */ 508183573Srnoland uint32_t read_domains; 509183573Srnoland 510183573Srnoland /** New write domain */ 511183573Srnoland uint32_t write_domain; 512183573Srnoland}; 513183573Srnoland 514183573Srnolandstruct drm_i915_gem_sw_finish { 515183573Srnoland /** Handle for the object */ 516183573Srnoland uint32_t handle; 517183573Srnoland}; 518183573Srnoland 519183573Srnolandstruct drm_i915_gem_relocation_entry { 520183573Srnoland /** 521183573Srnoland * Handle of the buffer being pointed to by this relocation entry. 522183573Srnoland * 523183573Srnoland * It's appealing to make this be an index into the mm_validate_entry 524183573Srnoland * list to refer to the buffer, but this allows the driver to create 525183573Srnoland * a relocation list for state buffers and not re-write it per 526183573Srnoland * exec using the buffer. 527183573Srnoland */ 528183573Srnoland uint32_t target_handle; 529183573Srnoland 530183573Srnoland /** 531183573Srnoland * Value to be added to the offset of the target buffer to make up 532183573Srnoland * the relocation entry. 533183573Srnoland */ 534183573Srnoland uint32_t delta; 535183573Srnoland 536183573Srnoland /** Offset in the buffer the relocation entry will be written into */ 537183573Srnoland uint64_t offset; 538183573Srnoland 539183573Srnoland /** 540183573Srnoland * Offset value of the target buffer that the relocation entry was last 541183573Srnoland * written as. 542183573Srnoland * 543183573Srnoland * If the buffer has the same offset as last time, we can skip syncing 544183573Srnoland * and writing the relocation. This value is written back out by 545183573Srnoland * the execbuffer ioctl when the relocation is written. 546183573Srnoland */ 547183573Srnoland uint64_t presumed_offset; 548183573Srnoland 549183573Srnoland /** 550183573Srnoland * Target memory domains read by this operation. 551183573Srnoland */ 552183573Srnoland uint32_t read_domains; 553183573Srnoland 554183573Srnoland /** 555183573Srnoland * Target memory domains written by this operation. 556183573Srnoland * 557183573Srnoland * Note that only one domain may be written by the whole 558183573Srnoland * execbuffer operation, so that where there are conflicts, 559183573Srnoland * the application will get -EINVAL back. 560183573Srnoland */ 561183573Srnoland uint32_t write_domain; 562183573Srnoland}; 563183573Srnoland 564183573Srnoland/** @{ 565183573Srnoland * Intel memory domains 566183573Srnoland * 567183573Srnoland * Most of these just align with the various caches in 568183573Srnoland * the system and are used to flush and invalidate as 569183573Srnoland * objects end up cached in different domains. 570183573Srnoland */ 571183573Srnoland/** CPU cache */ 572183573Srnoland#define I915_GEM_DOMAIN_CPU 0x00000001 573183573Srnoland/** Render cache, used by 2D and 3D drawing */ 574183573Srnoland#define I915_GEM_DOMAIN_RENDER 0x00000002 575183573Srnoland/** Sampler cache, used by texture engine */ 576183573Srnoland#define I915_GEM_DOMAIN_SAMPLER 0x00000004 577183573Srnoland/** Command queue, used to load batch buffers */ 578183573Srnoland#define I915_GEM_DOMAIN_COMMAND 0x00000008 579183573Srnoland/** Instruction cache, used by shader programs */ 580183573Srnoland#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 581183573Srnoland/** Vertex address cache */ 582183573Srnoland#define I915_GEM_DOMAIN_VERTEX 0x00000020 583183573Srnoland/** GTT domain - aperture and scanout */ 584183573Srnoland#define I915_GEM_DOMAIN_GTT 0x00000040 585183573Srnoland/** @} */ 586183573Srnoland 587183573Srnolandstruct drm_i915_gem_exec_object { 588183573Srnoland /** 589183573Srnoland * User's handle for a buffer to be bound into the GTT for this 590183573Srnoland * operation. 591183573Srnoland */ 592183573Srnoland uint32_t handle; 593183573Srnoland 594183573Srnoland /** Number of relocations to be performed on this buffer */ 595183573Srnoland uint32_t relocation_count; 596183573Srnoland /** 597183573Srnoland * Pointer to array of struct drm_i915_gem_relocation_entry containing 598183573Srnoland * the relocations to be performed in this buffer. 599183573Srnoland */ 600183573Srnoland uint64_t relocs_ptr; 601183573Srnoland 602183573Srnoland /** Required alignment in graphics aperture */ 603183573Srnoland uint64_t alignment; 604183573Srnoland 605183573Srnoland /** 606183573Srnoland * Returned value of the updated offset of the object, for future 607183573Srnoland * presumed_offset writes. 608183573Srnoland */ 609183573Srnoland uint64_t offset; 610183573Srnoland}; 611183573Srnoland 612183573Srnolandstruct drm_i915_gem_execbuffer { 613183573Srnoland /** 614183573Srnoland * List of buffers to be validated with their relocations to be 615183573Srnoland * performend on them. 616183573Srnoland * 617183573Srnoland * This is a pointer to an array of struct drm_i915_gem_validate_entry. 618183573Srnoland * 619183573Srnoland * These buffers must be listed in an order such that all relocations 620183573Srnoland * a buffer is performing refer to buffers that have already appeared 621183573Srnoland * in the validate list. 622183573Srnoland */ 623183573Srnoland uint64_t buffers_ptr; 624183573Srnoland uint32_t buffer_count; 625183573Srnoland 626183573Srnoland /** Offset in the batchbuffer to start execution from. */ 627183573Srnoland uint32_t batch_start_offset; 628183573Srnoland /** Bytes used in batchbuffer from batch_start_offset */ 629183573Srnoland uint32_t batch_len; 630183573Srnoland uint32_t DR1; 631183573Srnoland uint32_t DR4; 632183573Srnoland uint32_t num_cliprects; 633183573Srnoland uint64_t cliprects_ptr; /* struct drm_clip_rect *cliprects */ 634183573Srnoland}; 635183573Srnoland 636183573Srnolandstruct drm_i915_gem_pin { 637183573Srnoland /** Handle of the buffer to be pinned. */ 638183573Srnoland uint32_t handle; 639183573Srnoland uint32_t pad; 640183573Srnoland 641183573Srnoland /** alignment required within the aperture */ 642183573Srnoland uint64_t alignment; 643183573Srnoland 644183573Srnoland /** Returned GTT offset of the buffer. */ 645183573Srnoland uint64_t offset; 646183573Srnoland}; 647183573Srnoland 648183573Srnolandstruct drm_i915_gem_unpin { 649183573Srnoland /** Handle of the buffer to be unpinned. */ 650183573Srnoland uint32_t handle; 651183573Srnoland uint32_t pad; 652183573Srnoland}; 653183573Srnoland 654183573Srnolandstruct drm_i915_gem_busy { 655183573Srnoland /** Handle of the buffer to check for busy */ 656183573Srnoland uint32_t handle; 657183573Srnoland 658183573Srnoland /** Return busy status (1 if busy, 0 if idle) */ 659183573Srnoland uint32_t busy; 660183573Srnoland}; 661183573Srnoland 662183573Srnoland#define I915_TILING_NONE 0 663183573Srnoland#define I915_TILING_X 1 664183573Srnoland#define I915_TILING_Y 2 665183573Srnoland 666183573Srnoland#define I915_BIT_6_SWIZZLE_NONE 0 667183573Srnoland#define I915_BIT_6_SWIZZLE_9 1 668183573Srnoland#define I915_BIT_6_SWIZZLE_9_10 2 669183573Srnoland#define I915_BIT_6_SWIZZLE_9_11 3 670183573Srnoland#define I915_BIT_6_SWIZZLE_9_10_11 4 671183573Srnoland/* Not seen by userland */ 672183573Srnoland#define I915_BIT_6_SWIZZLE_UNKNOWN 5 673183573Srnoland 674183573Srnolandstruct drm_i915_gem_set_tiling { 675183573Srnoland /** Handle of the buffer to have its tiling state updated */ 676183573Srnoland uint32_t handle; 677183573Srnoland 678183573Srnoland /** 679183573Srnoland * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 680183573Srnoland * I915_TILING_Y). 681183573Srnoland * 682183573Srnoland * This value is to be set on request, and will be updated by the 683183573Srnoland * kernel on successful return with the actual chosen tiling layout. 684183573Srnoland * 685183573Srnoland * The tiling mode may be demoted to I915_TILING_NONE when the system 686183573Srnoland * has bit 6 swizzling that can't be managed correctly by GEM. 687183573Srnoland * 688183573Srnoland * Buffer contents become undefined when changing tiling_mode. 689183573Srnoland */ 690183573Srnoland uint32_t tiling_mode; 691183573Srnoland 692183573Srnoland /** 693183573Srnoland * Stride in bytes for the object when in I915_TILING_X or 694183573Srnoland * I915_TILING_Y. 695183573Srnoland */ 696183573Srnoland uint32_t stride; 697183573Srnoland 698183573Srnoland /** 699183573Srnoland * Returned address bit 6 swizzling required for CPU access through 700183573Srnoland * mmap mapping. 701183573Srnoland */ 702183573Srnoland uint32_t swizzle_mode; 703183573Srnoland}; 704183573Srnoland 705183573Srnolandstruct drm_i915_gem_get_tiling { 706183573Srnoland /** Handle of the buffer to get tiling state for. */ 707183573Srnoland uint32_t handle; 708183573Srnoland 709183573Srnoland /** 710183573Srnoland * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, 711183573Srnoland * I915_TILING_Y). 712183573Srnoland */ 713183573Srnoland uint32_t tiling_mode; 714183573Srnoland 715183573Srnoland /** 716183573Srnoland * Returned address bit 6 swizzling required for CPU access through 717183573Srnoland * mmap mapping. 718183573Srnoland */ 719183573Srnoland uint32_t swizzle_mode; 720183573Srnoland}; 721183573Srnoland 722145132Sanholt#endif /* _I915_DRM_H_ */ 723