if_dc.c revision 92739
1168404Spjd/* 2168404Spjd * Copyright (c) 1997, 1998, 1999 3168404Spjd * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4168404Spjd * 5168404Spjd * Redistribution and use in source and binary forms, with or without 6168404Spjd * modification, are permitted provided that the following conditions 7168404Spjd * are met: 8168404Spjd * 1. Redistributions of source code must retain the above copyright 9168404Spjd * notice, this list of conditions and the following disclaimer. 10168404Spjd * 2. Redistributions in binary form must reproduce the above copyright 11168404Spjd * notice, this list of conditions and the following disclaimer in the 12168404Spjd * documentation and/or other materials provided with the distribution. 13168404Spjd * 3. All advertising materials mentioning features or use of this software 14168404Spjd * must display the following acknowledgement: 15168404Spjd * This product includes software developed by Bill Paul. 16168404Spjd * 4. Neither the name of the author nor the names of any co-contributors 17168404Spjd * may be used to endorse or promote products derived from this software 18168404Spjd * without specific prior written permission. 19168404Spjd * 20168404Spjd * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21168404Spjd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22219089Spjd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23229578Smm * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24249643Smm * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25252140Sdelphij * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26168404Spjd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27168404Spjd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28168404Spjd * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29168404Spjd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30168404Spjd * THE POSSIBILITY OF SUCH DAMAGE. 31168404Spjd * 32168404Spjd * $FreeBSD: head/sys/dev/dc/if_dc.c 92739 2002-03-20 02:08:01Z alfred $ 33168404Spjd */ 34168404Spjd 35168404Spjd/* 36168404Spjd * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37168404Spjd * series chips and several workalikes including the following: 38168404Spjd * 39168404Spjd * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40168404Spjd * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41168404Spjd * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42168404Spjd * ASIX Electronics AX88140A (www.asix.com.tw) 43168404Spjd * ASIX Electronics AX88141 (www.asix.com.tw) 44168404Spjd * ADMtek AL981 (www.admtek.com.tw) 45168404Spjd * ADMtek AN985 (www.admtek.com.tw) 46168404Spjd * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47168404Spjd * Accton EN1217 (www.accton.com) 48168404Spjd * Xircom X3201 (www.xircom.com) 49168404Spjd * Abocom FE2500 50185029Spjd * Conexant LANfinity (www.conexant.com) 51185029Spjd * 52168404Spjd * Datasheets for the 21143 are available at developer.intel.com. 53168404Spjd * Datasheets for the clone parts can be found at their respective sites. 54168404Spjd * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55168404Spjd * The PNIC II is essentially a Macronix 98715A chip; the only difference 56185029Spjd * worth noting is that its multicast hash table is only 128 bits wide 57168404Spjd * instead of 512. 58168404Spjd * 59168404Spjd * Written by Bill Paul <wpaul@ee.columbia.edu> 60168404Spjd * Electrical Engineering Department 61252751Sdelphij * Columbia University, New York City 62168404Spjd */ 63168404Spjd 64168404Spjd/* 65252751Sdelphij * The Intel 21143 is the successor to the DEC 21140. It is basically 66168404Spjd * the same as the 21140 but with a few new features. The 21143 supports 67168404Spjd * three kinds of media attachments: 68168404Spjd * 69168404Spjd * o MII port, for 10Mbps and 100Mbps support and NWAY 70168404Spjd * autonegotiation provided by an external PHY. 71168404Spjd * o SYM port, for symbol mode 100Mbps support. 72168404Spjd * o 10baseT port. 73168404Spjd * o AUI/BNC port. 74168404Spjd * 75168404Spjd * The 100Mbps SYM port and 10baseT port can be used together in 76168404Spjd * combination with the internal NWAY support to create a 10/100 77168404Spjd * autosensing configuration. 78185029Spjd * 79168404Spjd * Note that not all tulip workalikes are handled in this driver: we only 80252751Sdelphij * deal with those which are relatively well behaved. The Winbond is 81168404Spjd * handled separately due to its different register offsets and the 82168404Spjd * special handling needed for its various bugs. The PNIC is handled 83168404Spjd * here, but I'm not thrilled about it. 84168404Spjd * 85168404Spjd * All of the workalike chips use some form of MII transceiver support 86168404Spjd * with the exception of the Macronix chips, which also have a SYM port. 87168404Spjd * The ASIX AX88140A is also documented to have a SYM port, but all 88168404Spjd * the cards I've seen use an MII transceiver, probably because the 89168404Spjd * AX88140A doesn't support internal NWAY. 90168404Spjd */ 91168404Spjd 92168404Spjd#include <sys/param.h> 93168404Spjd#include <sys/systm.h> 94168404Spjd#include <sys/sockio.h> 95168404Spjd#include <sys/mbuf.h> 96168404Spjd#include <sys/malloc.h> 97168404Spjd#include <sys/kernel.h> 98168404Spjd#include <sys/socket.h> 99168404Spjd#include <sys/sysctl.h> 100168404Spjd 101168404Spjd#include <net/if.h> 102168404Spjd#include <net/if_arp.h> 103168404Spjd#include <net/ethernet.h> 104168404Spjd#include <net/if_dl.h> 105168404Spjd#include <net/if_media.h> 106168404Spjd#include <net/if_types.h> 107168404Spjd#include <net/if_vlan_var.h> 108168404Spjd 109168404Spjd#include <net/bpf.h> 110168404Spjd 111168404Spjd#include <vm/vm.h> /* for vtophys */ 112185029Spjd#include <vm/pmap.h> /* for vtophys */ 113185029Spjd#include <machine/bus_pio.h> 114185029Spjd#include <machine/bus_memio.h> 115185029Spjd#include <machine/bus.h> 116185029Spjd#include <machine/resource.h> 117185029Spjd#include <sys/bus.h> 118185029Spjd#include <sys/rman.h> 119185029Spjd 120168404Spjd#include <dev/mii/mii.h> 121168404Spjd#include <dev/mii/miivar.h> 122168404Spjd 123168404Spjd#include <pci/pcireg.h> 124252140Sdelphij#include <pci/pcivar.h> 125168404Spjd 126168404Spjd#define DC_USEIOSPACE 127168404Spjd#ifdef __alpha__ 128185029Spjd#define SRM_MEDIA 129219089Spjd#endif 130168404Spjd 131168404Spjd#include <pci/if_dcreg.h> 132168404Spjd 133168404SpjdMODULE_DEPEND(dc, miibus, 1, 1, 1); 134168404Spjd 135251419Ssmh/* "controller miibus0" required. See GENERIC if you get errors here. */ 136219089Spjd#include "miibus_if.h" 137168404Spjd 138168404Spjd#ifndef lint 139191902Skmacystatic const char rcsid[] = 140191902Skmacy "$FreeBSD: head/sys/dev/dc/if_dc.c 92739 2002-03-20 02:08:01Z alfred $"; 141243674Smm#endif 142243674Smm 143243674Smm/* 144243674Smm * Various supported device vendors/types and their names. 145243674Smm */ 146243674Smmstatic struct dc_type dc_devs[] = { 147243674Smm { DC_VENDORID_DEC, DC_DEVICEID_21143, 148243674Smm "Intel 21143 10/100BaseTX" }, 149168404Spjd { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 150168404Spjd "Davicom DM9100 10/100BaseTX" }, 151168404Spjd { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152168404Spjd "Davicom DM9102 10/100BaseTX" }, 153185029Spjd { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154185029Spjd "Davicom DM9102A 10/100BaseTX" }, 155185029Spjd { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 156185029Spjd "ADMtek AL981 10/100BaseTX" }, 157168404Spjd { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 158168404Spjd "ADMtek AN985 10/100BaseTX" }, 159168404Spjd { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160168404Spjd "ASIX AX88140A 10/100BaseTX" }, 161168404Spjd { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 162168404Spjd "ASIX AX88141 10/100BaseTX" }, 163168404Spjd { DC_VENDORID_MX, DC_DEVICEID_98713, 164168404Spjd "Macronix 98713 10/100BaseTX" }, 165168404Spjd { DC_VENDORID_MX, DC_DEVICEID_98713, 166168404Spjd "Macronix 98713A 10/100BaseTX" }, 167168404Spjd { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168208373Smm "Compex RL100-TX 10/100BaseTX" }, 169208373Smm { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 170208373Smm "Compex RL100-TX 10/100BaseTX" }, 171208373Smm { DC_VENDORID_MX, DC_DEVICEID_987x5, 172208373Smm "Macronix 98715/98715A 10/100BaseTX" }, 173208373Smm { DC_VENDORID_MX, DC_DEVICEID_987x5, 174168404Spjd "Macronix 98715AEC-C 10/100BaseTX" }, 175168404Spjd { DC_VENDORID_MX, DC_DEVICEID_987x5, 176168404Spjd "Macronix 98725 10/100BaseTX" }, 177168404Spjd { DC_VENDORID_MX, DC_DEVICEID_98727, 178168404Spjd "Macronix 98727/98732 10/100BaseTX" }, 179168404Spjd { DC_VENDORID_LO, DC_DEVICEID_82C115, 180208373Smm "LC82C115 PNIC II 10/100BaseTX" }, 181194043Skmacy { DC_VENDORID_LO, DC_DEVICEID_82C168, 182168404Spjd "82c168 PNIC 10/100BaseTX" }, 183168404Spjd { DC_VENDORID_LO, DC_DEVICEID_82C168, 184185029Spjd "82c169 PNIC 10/100BaseTX" }, 185185029Spjd { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 186185029Spjd "Accton EN1217 10/100BaseTX" }, 187185029Spjd { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 188185029Spjd "Accton EN2242 MiniPCI 10/100BaseTX" }, 189168404Spjd { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 190168404Spjd "Xircom X3201 10/100BaseTX" }, 191185029Spjd { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 192185029Spjd "Abocom FE2500 10/100BaseTX" }, 193185029Spjd { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 194208373Smm "Conexant LANfinity MiniPCI 10/100BaseTX" }, 195208373Smm { 0, 0, NULL } 196208373Smm}; 197248547Smm 198185029Spjdstatic int dc_probe (device_t); 199185029Spjdstatic int dc_attach (device_t); 200185029Spjdstatic int dc_detach (device_t); 201185029Spjdstatic void dc_acpi (device_t); 202168473Spjdstatic struct dc_type *dc_devtype (device_t); 203217367Smdfstatic int dc_newbuf (struct dc_softc *, int, struct mbuf *); 204168473Spjdstatic int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 205217367Smdfstatic int dc_coal (struct dc_softc *, struct mbuf **); 206168473Spjdstatic void dc_pnic_rx_bug_war (struct dc_softc *, int); 207168404Spjdstatic int dc_rx_resync (struct dc_softc *); 208168404Spjdstatic void dc_rxeof (struct dc_softc *); 209185029Spjdstatic void dc_txeof (struct dc_softc *); 210168404Spjdstatic void dc_tick (void *); 211168404Spjdstatic void dc_tx_underrun (struct dc_softc *); 212168404Spjdstatic void dc_intr (void *); 213168404Spjdstatic void dc_start (struct ifnet *); 214168404Spjdstatic int dc_ioctl (struct ifnet *, u_long, caddr_t); 215185029Spjdstatic void dc_init (void *); 216185029Spjdstatic void dc_stop (struct dc_softc *); 217185029Spjdstatic void dc_watchdog (struct ifnet *); 218185029Spjdstatic void dc_shutdown (device_t); 219185029Spjdstatic int dc_ifmedia_upd (struct ifnet *); 220185029Spjdstatic void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 221185029Spjd 222185029Spjdstatic void dc_delay (struct dc_softc *); 223168404Spjdstatic void dc_eeprom_idle (struct dc_softc *); 224168404Spjdstatic void dc_eeprom_putbyte (struct dc_softc *, int); 225168404Spjdstatic void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 226168404Spjdstatic void dc_eeprom_getword_pnic 227168404Spjd (struct dc_softc *, int, u_int16_t *); 228168404Spjdstatic void dc_eeprom_getword_xircom 229168404Spjd (struct dc_softc *, int, u_int16_t *); 230185029Spjdstatic void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 231185029Spjd 232185029Spjdstatic void dc_mii_writebit (struct dc_softc *, int); 233185029Spjdstatic int dc_mii_readbit (struct dc_softc *); 234185029Spjdstatic void dc_mii_sync (struct dc_softc *); 235185029Spjdstatic void dc_mii_send (struct dc_softc *, u_int32_t, int); 236185029Spjdstatic int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 237185029Spjdstatic int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 238168404Spjdstatic int dc_miibus_readreg (device_t, int, int); 239168404Spjdstatic int dc_miibus_writereg (device_t, int, int, int); 240205264Skmacystatic void dc_miibus_statchg (device_t); 241205231Skmacystatic void dc_miibus_mediainit (device_t); 242205231Skmacy 243205231Skmacystatic void dc_setcfg (struct dc_softc *, int); 244205231Skmacystatic u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 245205231Skmacystatic u_int32_t dc_crc_be (caddr_t); 246205231Skmacystatic void dc_setfilt_21143 (struct dc_softc *); 247205231Skmacystatic void dc_setfilt_asix (struct dc_softc *); 248205231Skmacystatic void dc_setfilt_admtek (struct dc_softc *); 249205231Skmacystatic void dc_setfilt_xircom (struct dc_softc *); 250205231Skmacy 251205231Skmacystatic void dc_setfilt (struct dc_softc *); 252205231Skmacy 253205231Skmacystatic void dc_reset (struct dc_softc *); 254206796Spjdstatic int dc_list_rx_init (struct dc_softc *); 255205231Skmacystatic int dc_list_tx_init (struct dc_softc *); 256168404Spjd 257185029Spjdstatic void dc_parse_21143_srom (struct dc_softc *); 258185029Spjdstatic void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 259205231Skmacystatic void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 260205264Skmacystatic void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 261168404Spjdstatic void dc_apply_fixup (struct dc_softc *, int); 262168404Spjd 263206796Spjd#ifdef DC_USEIOSPACE 264205231Skmacy#define DC_RES SYS_RES_IOPORT 265185029Spjd#define DC_RID DC_PCI_CFBIO 266168404Spjd#else 267168404Spjd#define DC_RES SYS_RES_MEMORY 268168404Spjd#define DC_RID DC_PCI_CFBMA 269168404Spjd#endif 270168404Spjd 271185029Spjdstatic device_method_t dc_methods[] = { 272168404Spjd /* Device interface */ 273168404Spjd DEVMETHOD(device_probe, dc_probe), 274168404Spjd DEVMETHOD(device_attach, dc_attach), 275168404Spjd DEVMETHOD(device_detach, dc_detach), 276168404Spjd DEVMETHOD(device_shutdown, dc_shutdown), 277168404Spjd 278168404Spjd /* bus interface */ 279168404Spjd DEVMETHOD(bus_print_child, bus_generic_print_child), 280168404Spjd DEVMETHOD(bus_driver_added, bus_generic_driver_added), 281168404Spjd 282168404Spjd /* MII interface */ 283168404Spjd DEVMETHOD(miibus_readreg, dc_miibus_readreg), 284168404Spjd DEVMETHOD(miibus_writereg, dc_miibus_writereg), 285168404Spjd DEVMETHOD(miibus_statchg, dc_miibus_statchg), 286168404Spjd DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 287168404Spjd 288205231Skmacy { 0, 0 } 289168404Spjd}; 290205231Skmacy 291168404Spjdstatic driver_t dc_driver = { 292252749Sdelphij "dc", 293252749Sdelphij dc_methods, 294252749Sdelphij sizeof(struct dc_softc) 295252749Sdelphij}; 296252749Sdelphij 297252749Sdelphijstatic devclass_t dc_devclass; 298168404Spjd#ifdef __i386__ 299252749Sdelphijstatic int dc_quick=1; 300252749SdelphijSYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 301252749Sdelphij &dc_quick,0,"do not mdevget in dc driver"); 302252749Sdelphij#endif 303252749Sdelphij 304168404SpjdDRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 305208373SmmDRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 306208373SmmDRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 307208373Smm 308168404Spjd#define DC_SETBIT(sc, reg, x) \ 309168404Spjd CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 310168404Spjd 311168404Spjd#define DC_CLRBIT(sc, reg, x) \ 312168404Spjd CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 313168404Spjd 314168404Spjd#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 315168404Spjd#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 316168404Spjd 317168404Spjd#define IS_MPSAFE 0 318185029Spjd 319208373Smmstatic void dc_delay(sc) 320208373Smm struct dc_softc *sc; 321185029Spjd{ 322185029Spjd int idx; 323185029Spjd 324185029Spjd for (idx = (300 / 33) + 1; idx > 0; idx--) 325208373Smm CSR_READ_4(sc, DC_BUSCTL); 326208373Smm} 327185029Spjd 328185029Spjdstatic void dc_eeprom_idle(sc) 329185029Spjd struct dc_softc *sc; 330185029Spjd{ 331185029Spjd register int i; 332185029Spjd 333185029Spjd CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 334185029Spjd dc_delay(sc); 335185029Spjd DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 336185029Spjd dc_delay(sc); 337185029Spjd DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 338252140Sdelphij dc_delay(sc); 339185029Spjd DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 340252140Sdelphij dc_delay(sc); 341252140Sdelphij 342252140Sdelphij for (i = 0; i < 25; i++) { 343205231Skmacy DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 344205231Skmacy dc_delay(sc); 345205231Skmacy DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 346206796Spjd dc_delay(sc); 347205231Skmacy } 348205231Skmacy 349205231Skmacy DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 350205231Skmacy dc_delay(sc); 351205231Skmacy DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 352205231Skmacy dc_delay(sc); 353205231Skmacy CSR_WRITE_4(sc, DC_SIO, 0x00000000); 354205231Skmacy 355248547Smm return; 356248547Smm} 357248547Smm 358248547Smm/* 359168404Spjd * Send a read command and address to the EEPROM, check for ACK. 360168404Spjd */ 361168404Spjdstatic void dc_eeprom_putbyte(sc, addr) 362168404Spjd struct dc_softc *sc; 363168404Spjd int addr; 364168404Spjd{ 365168404Spjd register int d, i; 366168404Spjd 367168404Spjd /* 368168404Spjd * The AN985 has a 93C66 EEPROM on it instead of 369168404Spjd * a 93C46. It uses a different bit sequence for 370168404Spjd * specifying the "read" opcode. 371168404Spjd */ 372168404Spjd if (DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc)) 373168404Spjd d = addr | (DC_EECMD_READ << 2); 374168404Spjd else 375168404Spjd d = addr | DC_EECMD_READ; 376205231Skmacy 377168404Spjd /* 378205231Skmacy * Feed in each bit and strobe the clock. 379168404Spjd */ 380168404Spjd for (i = 0x400; i; i >>= 1) { 381168404Spjd if (d & i) { 382208373Smm SIO_SET(DC_SIO_EE_DATAIN); 383208373Smm } else { 384208373Smm SIO_CLR(DC_SIO_EE_DATAIN); 385168404Spjd } 386168404Spjd dc_delay(sc); 387168404Spjd SIO_SET(DC_SIO_EE_CLK); 388168404Spjd dc_delay(sc); 389168404Spjd SIO_CLR(DC_SIO_EE_CLK); 390168404Spjd dc_delay(sc); 391168404Spjd } 392168404Spjd 393168404Spjd return; 394185029Spjd} 395185029Spjd 396208373Smm/* 397208373Smm * Read a word of data stored in the EEPROM at address 'addr.' 398185029Spjd * The PNIC 82c168/82c169 has its own non-standard way to read 399185029Spjd * the EEPROM. 400185029Spjd */ 401185029Spjdstatic void dc_eeprom_getword_pnic(sc, addr, dest) 402208373Smm struct dc_softc *sc; 403208373Smm int addr; 404185029Spjd u_int16_t *dest; 405185029Spjd{ 406185029Spjd register int i; 407185029Spjd u_int32_t r; 408185029Spjd 409185029Spjd CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 410185029Spjd 411185029Spjd for (i = 0; i < DC_TIMEOUT; i++) { 412185029Spjd DELAY(1); 413185029Spjd r = CSR_READ_4(sc, DC_SIO); 414185029Spjd if (!(r & DC_PN_SIOCTL_BUSY)) { 415252140Sdelphij *dest = (u_int16_t)(r & 0xFFFF); 416185029Spjd return; 417252140Sdelphij } 418252140Sdelphij } 419252140Sdelphij 420206796Spjd return; 421206796Spjd} 422206796Spjd 423206796Spjd/* 424206796Spjd * Read a word of data stored in the EEPROM at address 'addr.' 425206796Spjd * The Xircom X3201 has its own non-standard way to read 426206796Spjd * the EEPROM, too. 427206796Spjd */ 428206796Spjdstatic void dc_eeprom_getword_xircom(sc, addr, dest) 429206796Spjd struct dc_softc *sc; 430206796Spjd int addr; 431248547Smm u_int16_t *dest; 432248547Smm{ 433248547Smm SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 434248547Smm 435248547Smm addr *= 2; 436168404Spjd CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 437168404Spjd *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 438168404Spjd addr += 1; 439168404Spjd CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 440168404Spjd *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 441252751Sdelphij 442168404Spjd SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 443206796Spjd return; 444168404Spjd} 445168404Spjd 446168404Spjd/* 447168404Spjd * Read a word of data stored in the EEPROM at address 'addr.' 448168404Spjd */ 449168404Spjdstatic void dc_eeprom_getword(sc, addr, dest) 450168404Spjd struct dc_softc *sc; 451168404Spjd int addr; 452168404Spjd u_int16_t *dest; 453168404Spjd{ 454168404Spjd register int i; 455168404Spjd u_int16_t word = 0; 456168404Spjd 457168404Spjd /* Force EEPROM to idle state. */ 458168404Spjd dc_eeprom_idle(sc); 459168404Spjd 460168404Spjd /* Enter EEPROM access mode. */ 461168404Spjd CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 462168404Spjd dc_delay(sc); 463168404Spjd DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 464168404Spjd dc_delay(sc); 465168404Spjd DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 466168404Spjd dc_delay(sc); 467168404Spjd DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 468168404Spjd dc_delay(sc); 469168404Spjd 470168404Spjd /* 471168404Spjd * Send address of word we want to read. 472168404Spjd */ 473168404Spjd dc_eeprom_putbyte(sc, addr); 474168404Spjd 475168404Spjd /* 476168404Spjd * Start reading bits from EEPROM. 477206796Spjd */ 478168404Spjd for (i = 0x8000; i; i >>= 1) { 479168404Spjd SIO_SET(DC_SIO_EE_CLK); 480168404Spjd dc_delay(sc); 481168404Spjd if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 482185029Spjd word |= i; 483168404Spjd dc_delay(sc); 484168404Spjd SIO_CLR(DC_SIO_EE_CLK); 485168404Spjd dc_delay(sc); 486168404Spjd } 487168404Spjd 488168404Spjd /* Turn off EEPROM access mode. */ 489168404Spjd dc_eeprom_idle(sc); 490168404Spjd 491168404Spjd *dest = word; 492168404Spjd 493168404Spjd return; 494168404Spjd} 495168404Spjd 496168404Spjd/* 497168404Spjd * Read a sequence of words from the EEPROM. 498252140Sdelphij */ 499252140Sdelphijstatic void dc_read_eeprom(sc, dest, off, cnt, swap) 500252140Sdelphij struct dc_softc *sc; 501168404Spjd caddr_t dest; 502168404Spjd int off; 503209962Smm int cnt; 504185029Spjd int swap; 505185029Spjd{ 506185029Spjd int i; 507217367Smdf u_int16_t word = 0, *ptr; 508185029Spjd 509217367Smdf for (i = 0; i < cnt; i++) { 510185029Spjd if (DC_IS_PNIC(sc)) 511168404Spjd dc_eeprom_getword_pnic(sc, off + i, &word); 512185029Spjd else if (DC_IS_XIRCOM(sc)) 513185029Spjd dc_eeprom_getword_xircom(sc, off + i, &word); 514168404Spjd else 515168404Spjd dc_eeprom_getword(sc, off + i, &word); 516168404Spjd ptr = (u_int16_t *)(dest + (i * 2)); 517168404Spjd if (swap) 518168404Spjd *ptr = ntohs(word); 519168404Spjd else 520168404Spjd *ptr = word; 521168404Spjd } 522168404Spjd 523168404Spjd return; 524168404Spjd} 525168404Spjd 526168404Spjd/* 527168404Spjd * The following two routines are taken from the Macronix 98713 528168404Spjd * Application Notes pp.19-21. 529168404Spjd */ 530168404Spjd/* 531168404Spjd * Write a bit to the MII bus. 532168404Spjd */ 533168404Spjdstatic void dc_mii_writebit(sc, bit) 534168404Spjd struct dc_softc *sc; 535168404Spjd int bit; 536168404Spjd{ 537168404Spjd if (bit) 538168404Spjd CSR_WRITE_4(sc, DC_SIO, 539168404Spjd DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 540168404Spjd else 541219089Spjd CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 542168404Spjd 543168404Spjd DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 544168404Spjd DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 545168404Spjd 546168404Spjd return; 547168404Spjd} 548168404Spjd 549168404Spjd/* 550168404Spjd * Read a bit from the MII bus. 551168404Spjd */ 552168404Spjdstatic int dc_mii_readbit(sc) 553168404Spjd struct dc_softc *sc; 554209962Smm{ 555168404Spjd CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 556168404Spjd CSR_READ_4(sc, DC_SIO); 557168404Spjd DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 558168404Spjd DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 559168404Spjd if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 560168404Spjd return(1); 561168404Spjd 562168404Spjd return(0); 563168404Spjd} 564168404Spjd 565185029Spjd/* 566185029Spjd * Sync the PHYs by setting data bit and strobing the clock 32 times. 567185029Spjd */ 568168404Spjdstatic void dc_mii_sync(sc) 569168404Spjd struct dc_softc *sc; 570168404Spjd{ 571168404Spjd register int i; 572168404Spjd 573168404Spjd CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 574168404Spjd 575185029Spjd for (i = 0; i < 32; i++) 576209962Smm dc_mii_writebit(sc, 1); 577243674Smm 578243674Smm return; 579243674Smm} 580168404Spjd 581209962Smm/* 582208373Smm * Clock a series of bits through the MII. 583168404Spjd */ 584185029Spjdstatic void dc_mii_send(sc, bits, cnt) 585185029Spjd struct dc_softc *sc; 586168404Spjd u_int32_t bits; 587168404Spjd int cnt; 588168404Spjd{ 589168404Spjd int i; 590168404Spjd 591168404Spjd for (i = (0x1 << (cnt - 1)); i; i >>= 1) 592168404Spjd dc_mii_writebit(sc, bits & i); 593168404Spjd} 594168404Spjd 595168404Spjd/* 596168404Spjd * Read an PHY register through the MII. 597168404Spjd */ 598168404Spjdstatic int dc_mii_readreg(sc, frame) 599168404Spjd struct dc_softc *sc; 600168404Spjd struct dc_mii_frame *frame; 601185029Spjd 602185029Spjd{ 603185029Spjd int i, ack; 604185029Spjd 605168404Spjd DC_LOCK(sc); 606168404Spjd 607168404Spjd /* 608168404Spjd * Set up frame for RX. 609208373Smm */ 610168404Spjd frame->mii_stdelim = DC_MII_STARTDELIM; 611168404Spjd frame->mii_opcode = DC_MII_READOP; 612185029Spjd frame->mii_turnaround = 0; 613185029Spjd frame->mii_data = 0; 614185029Spjd 615185029Spjd /* 616185029Spjd * Sync the PHYs. 617185029Spjd */ 618185029Spjd dc_mii_sync(sc); 619168404Spjd 620168404Spjd /* 621185029Spjd * Send command/address info. 622185029Spjd */ 623185029Spjd dc_mii_send(sc, frame->mii_stdelim, 2); 624185029Spjd dc_mii_send(sc, frame->mii_opcode, 2); 625185029Spjd dc_mii_send(sc, frame->mii_phyaddr, 5); 626185029Spjd dc_mii_send(sc, frame->mii_regaddr, 5); 627185029Spjd 628168404Spjd#ifdef notdef 629168404Spjd /* Idle bit */ 630168404Spjd dc_mii_writebit(sc, 1); 631205253Skmacy dc_mii_writebit(sc, 0); 632168404Spjd#endif 633168404Spjd 634168404Spjd /* Check for ack */ 635168404Spjd ack = dc_mii_readbit(sc); 636168404Spjd 637168404Spjd /* 638168404Spjd * Now try reading data bits. If the ack failed, we still 639168404Spjd * need to clock through 16 cycles to keep the PHY(s) in sync. 640168404Spjd */ 641168404Spjd if (ack) { 642168404Spjd for(i = 0; i < 16; i++) { 643168404Spjd dc_mii_readbit(sc); 644205264Skmacy } 645168404Spjd goto fail; 646168404Spjd } 647168404Spjd 648168404Spjd for (i = 0x8000; i; i >>= 1) { 649168404Spjd if (!ack) { 650168404Spjd if (dc_mii_readbit(sc)) 651168404Spjd frame->mii_data |= i; 652168404Spjd } 653219089Spjd } 654219089Spjd 655168404Spjdfail: 656168404Spjd 657168404Spjd dc_mii_writebit(sc, 0); 658185029Spjd dc_mii_writebit(sc, 0); 659185029Spjd 660185029Spjd DC_UNLOCK(sc); 661185029Spjd 662208373Smm if (ack) 663252140Sdelphij return(1); 664252140Sdelphij return(0); 665252140Sdelphij} 666252140Sdelphij 667252140Sdelphij/* 668252140Sdelphij * Write to a PHY register through the MII. 669208373Smm */ 670208373Smmstatic int dc_mii_writereg(sc, frame) 671185029Spjd struct dc_softc *sc; 672185029Spjd struct dc_mii_frame *frame; 673185029Spjd 674185029Spjd{ 675252751Sdelphij DC_LOCK(sc); 676185029Spjd /* 677185029Spjd * Set up frame for TX. 678185029Spjd */ 679252140Sdelphij 680185029Spjd frame->mii_stdelim = DC_MII_STARTDELIM; 681208373Smm frame->mii_opcode = DC_MII_WRITEOP; 682219089Spjd frame->mii_turnaround = DC_MII_TURNAROUND; 683208373Smm 684208373Smm /* 685185029Spjd * Sync the PHYs. 686217367Smdf */ 687205231Skmacy dc_mii_sync(sc); 688217367Smdf 689205231Skmacy dc_mii_send(sc, frame->mii_stdelim, 2); 690217367Smdf dc_mii_send(sc, frame->mii_opcode, 2); 691205231Skmacy dc_mii_send(sc, frame->mii_phyaddr, 5); 692217367Smdf dc_mii_send(sc, frame->mii_regaddr, 5); 693205231Skmacy dc_mii_send(sc, frame->mii_turnaround, 2); 694217367Smdf dc_mii_send(sc, frame->mii_data, 16); 695208373Smm 696205231Skmacy /* Idle bit. */ 697205231Skmacy dc_mii_writebit(sc, 0); 698205231Skmacy dc_mii_writebit(sc, 0); 699208373Smm 700208373Smm DC_UNLOCK(sc); 701208373Smm 702208373Smm return(0); 703205231Skmacy} 704217367Smdf 705205231Skmacystatic int dc_miibus_readreg(dev, phy, reg) 706217367Smdf device_t dev; 707205231Skmacy int phy, reg; 708217367Smdf{ 709205231Skmacy struct dc_mii_frame frame; 710205231Skmacy struct dc_softc *sc; 711217367Smdf int i, rval, phy_reg = 0; 712205231Skmacy 713217367Smdf sc = device_get_softc(dev); 714205231Skmacy bzero((char *)&frame, sizeof(frame)); 715217367Smdf 716205231Skmacy /* 717205231Skmacy * Note: both the AL981 and AN985 have internal PHYs, 718217367Smdf * however the AL981 provides direct access to the PHY 719205231Skmacy * registers while the AN985 uses a serial MII interface. 720217367Smdf * The AN985's MII interface is also buggy in that you 721205231Skmacy * can read from any MII address (0 to 31), but only address 1 722205231Skmacy * behaves normally. To deal with both cases, we pretend 723217367Smdf * that the PHY is at MII address 1. 724205231Skmacy */ 725205231Skmacy if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 726205231Skmacy return(0); 727217367Smdf 728205231Skmacy /* 729217367Smdf * Note: the ukphy probes of the RS7112 report a PHY at 730205231Skmacy * MII address 0 (possibly HomePNA?) and 1 (ethernet) 731217367Smdf * so we only respond to correct one. 732205231Skmacy */ 733205231Skmacy if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 734217367Smdf return(0); 735205231Skmacy 736217367Smdf if (sc->dc_pmode != DC_PMODE_MII) { 737205231Skmacy if (phy == (MII_NPHY - 1)) { 738205231Skmacy switch(reg) { 739217367Smdf case MII_BMSR: 740205231Skmacy /* 741205231Skmacy * Fake something to make the probe 742205231Skmacy * code think there's a PHY here. 743217367Smdf */ 744205231Skmacy return(BMSR_MEDIAMASK); 745205231Skmacy break; 746185029Spjd case MII_PHYIDR1: 747185029Spjd if (DC_IS_PNIC(sc)) 748185029Spjd return(DC_VENDORID_LO); 749185029Spjd return(DC_VENDORID_DEC); 750185029Spjd break; 751185029Spjd case MII_PHYIDR2: 752185029Spjd if (DC_IS_PNIC(sc)) 753185029Spjd return(DC_DEVICEID_82C168); 754185029Spjd return(DC_DEVICEID_21143); 755185029Spjd break; 756185029Spjd default: 757208373Smm return(0); 758185029Spjd break; 759185029Spjd } 760185029Spjd } else 761185029Spjd return(0); 762185029Spjd } 763185029Spjd 764185029Spjd if (DC_IS_PNIC(sc)) { 765185029Spjd CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 766185029Spjd (phy << 23) | (reg << 18)); 767185029Spjd for (i = 0; i < DC_TIMEOUT; i++) { 768185029Spjd DELAY(1); 769185029Spjd rval = CSR_READ_4(sc, DC_PN_MII); 770185029Spjd if (!(rval & DC_PN_MII_BUSY)) { 771185029Spjd rval &= 0xFFFF; 772185029Spjd return(rval == 0xFFFF ? 0 : rval); 773252140Sdelphij } 774252140Sdelphij } 775252140Sdelphij return(0); 776252140Sdelphij } 777252140Sdelphij 778252140Sdelphij if (DC_IS_COMET(sc)) { 779185029Spjd switch(reg) { 780185029Spjd case MII_BMCR: 781185029Spjd phy_reg = DC_AL_BMCR; 782185029Spjd break; 783185029Spjd case MII_BMSR: 784185029Spjd phy_reg = DC_AL_BMSR; 785185029Spjd break; 786185029Spjd case MII_PHYIDR1: 787185029Spjd phy_reg = DC_AL_VENID; 788252140Sdelphij break; 789252140Sdelphij case MII_PHYIDR2: 790252140Sdelphij phy_reg = DC_AL_DEVID; 791252140Sdelphij break; 792252140Sdelphij case MII_ANAR: 793252140Sdelphij phy_reg = DC_AL_ANAR; 794252140Sdelphij break; 795252140Sdelphij case MII_ANLPAR: 796185029Spjd phy_reg = DC_AL_LPAR; 797185029Spjd break; 798185029Spjd case MII_ANER: 799185029Spjd phy_reg = DC_AL_ANER; 800185029Spjd break; 801185029Spjd default: 802185029Spjd printf("dc%d: phy_read: bad phy register %x\n", 803185029Spjd sc->dc_unit, reg); 804185029Spjd return(0); 805185029Spjd break; 806185029Spjd } 807185029Spjd 808185029Spjd rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 809185029Spjd 810185029Spjd if (rval == 0xFFFF) 811185029Spjd return(0); 812185029Spjd return(rval); 813185029Spjd } 814252140Sdelphij 815252140Sdelphij frame.mii_phyaddr = phy; 816252140Sdelphij frame.mii_regaddr = reg; 817252140Sdelphij if (sc->dc_type == DC_TYPE_98713) { 818252140Sdelphij phy_reg = CSR_READ_4(sc, DC_NETCFG); 819168404Spjd CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 820209962Smm } 821168404Spjd dc_mii_readreg(sc, &frame); 822168404Spjd if (sc->dc_type == DC_TYPE_98713) 823168404Spjd CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 824168404Spjd 825168404Spjd return(frame.mii_data); 826168404Spjd} 827168404Spjd 828168404Spjdstatic int dc_miibus_writereg(dev, phy, reg, data) 829168404Spjd device_t dev; 830168404Spjd int phy, reg, data; 831209962Smm{ 832168404Spjd struct dc_softc *sc; 833168404Spjd struct dc_mii_frame frame; 834168404Spjd int i, phy_reg = 0; 835168404Spjd 836168404Spjd sc = device_get_softc(dev); 837168404Spjd bzero((char *)&frame, sizeof(frame)); 838168404Spjd 839168404Spjd if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 840168404Spjd return(0); 841168404Spjd 842168404Spjd if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 843168404Spjd return(0); 844168404Spjd 845168404Spjd if (DC_IS_PNIC(sc)) { 846219089Spjd CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 847219089Spjd (phy << 23) | (reg << 10) | data); 848219089Spjd for (i = 0; i < DC_TIMEOUT; i++) { 849219089Spjd if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 850219089Spjd break; 851219089Spjd } 852219089Spjd return(0); 853219089Spjd } 854219089Spjd 855168404Spjd if (DC_IS_COMET(sc)) { 856209962Smm switch(reg) { 857168404Spjd case MII_BMCR: 858168404Spjd phy_reg = DC_AL_BMCR; 859168404Spjd break; 860168404Spjd case MII_BMSR: 861168404Spjd phy_reg = DC_AL_BMSR; 862168404Spjd break; 863168404Spjd case MII_PHYIDR1: 864168404Spjd phy_reg = DC_AL_VENID; 865168404Spjd break; 866168404Spjd case MII_PHYIDR2: 867168404Spjd phy_reg = DC_AL_DEVID; 868168404Spjd break; 869168404Spjd case MII_ANAR: 870168404Spjd phy_reg = DC_AL_ANAR; 871168404Spjd break; 872168404Spjd case MII_ANLPAR: 873168404Spjd phy_reg = DC_AL_LPAR; 874168404Spjd break; 875168404Spjd case MII_ANER: 876168404Spjd phy_reg = DC_AL_ANER; 877168404Spjd break; 878168404Spjd default: 879168404Spjd printf("dc%d: phy_write: bad phy register %x\n", 880168404Spjd sc->dc_unit, reg); 881168404Spjd return(0); 882168404Spjd break; 883168404Spjd } 884168404Spjd 885168404Spjd CSR_WRITE_4(sc, phy_reg, data); 886168404Spjd return(0); 887168404Spjd } 888168404Spjd 889168404Spjd frame.mii_phyaddr = phy; 890168404Spjd frame.mii_regaddr = reg; 891168404Spjd frame.mii_data = data; 892168404Spjd 893168404Spjd if (sc->dc_type == DC_TYPE_98713) { 894168404Spjd phy_reg = CSR_READ_4(sc, DC_NETCFG); 895168404Spjd CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 896168404Spjd } 897168404Spjd dc_mii_writereg(sc, &frame); 898168404Spjd if (sc->dc_type == DC_TYPE_98713) 899168404Spjd CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 900168404Spjd 901168404Spjd return(0); 902168404Spjd} 903168404Spjd 904168404Spjdstatic void dc_miibus_statchg(dev) 905168404Spjd device_t dev; 906168404Spjd{ 907168404Spjd struct dc_softc *sc; 908168404Spjd struct mii_data *mii; 909168404Spjd struct ifmedia *ifm; 910168404Spjd 911168404Spjd sc = device_get_softc(dev); 912168404Spjd if (DC_IS_ADMTEK(sc)) 913168404Spjd return; 914168404Spjd 915168404Spjd mii = device_get_softc(sc->dc_miibus); 916168404Spjd ifm = &mii->mii_media; 917168404Spjd if (DC_IS_DAVICOM(sc) && 918168404Spjd IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 919168404Spjd dc_setcfg(sc, ifm->ifm_media); 920168404Spjd sc->dc_if_media = ifm->ifm_media; 921168404Spjd } else { 922168404Spjd dc_setcfg(sc, mii->mii_media_active); 923168404Spjd sc->dc_if_media = mii->mii_media_active; 924168404Spjd } 925168404Spjd 926168404Spjd return; 927168404Spjd} 928168404Spjd 929168404Spjd/* 930168404Spjd * Special support for DM9102A cards with HomePNA PHYs. Note: 931168404Spjd * with the Davicom DM9102A/DM9801 eval board that I have, it seems 932168404Spjd * to be impossible to talk to the management interface of the DM9801 933168404Spjd * PHY (its MDIO pin is not connected to anything). Consequently, 934168404Spjd * the driver has to just 'know' about the additional mode and deal 935168404Spjd * with it itself. *sigh* 936168404Spjd */ 937168404Spjdstatic void dc_miibus_mediainit(dev) 938168404Spjd device_t dev; 939168404Spjd{ 940168404Spjd struct dc_softc *sc; 941168404Spjd struct mii_data *mii; 942168404Spjd struct ifmedia *ifm; 943168404Spjd int rev; 944168404Spjd 945168404Spjd rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 946168404Spjd 947168404Spjd sc = device_get_softc(dev); 948168404Spjd mii = device_get_softc(sc->dc_miibus); 949168404Spjd ifm = &mii->mii_media; 950168404Spjd 951168404Spjd if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 952168404Spjd ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 953168404Spjd 954168404Spjd return; 955168404Spjd} 956168404Spjd 957168404Spjd#define DC_POLY 0xEDB88320 958168404Spjd#define DC_BITS_512 9 959168404Spjd#define DC_BITS_128 7 960168404Spjd#define DC_BITS_64 6 961168404Spjd 962168404Spjdstatic u_int32_t dc_crc_le(sc, addr) 963168404Spjd struct dc_softc *sc; 964168404Spjd caddr_t addr; 965168404Spjd{ 966168404Spjd u_int32_t idx, bit, data, crc; 967168404Spjd 968168404Spjd /* Compute CRC for the address value. */ 969168404Spjd crc = 0xFFFFFFFF; /* initial value */ 970168404Spjd 971168404Spjd for (idx = 0; idx < 6; idx++) { 972168404Spjd for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 973168404Spjd crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 974168404Spjd } 975185029Spjd 976208373Smm /* 977185029Spjd * The hash table on the PNIC II and the MX98715AEC-C/D/E 978168404Spjd * chips is only 128 bits wide. 979168404Spjd */ 980168404Spjd if (sc->dc_flags & DC_128BIT_HASH) 981185029Spjd return (crc & ((1 << DC_BITS_128) - 1)); 982185029Spjd 983185029Spjd /* The hash table on the MX98715BEC is only 64 bits wide. */ 984185029Spjd if (sc->dc_flags & DC_64BIT_HASH) 985185029Spjd return (crc & ((1 << DC_BITS_64) - 1)); 986185029Spjd 987185029Spjd /* Xircom's hash filtering table is different (read: weird) */ 988219089Spjd /* Xircom uses the LEAST significant bits */ 989208373Smm if (DC_IS_XIRCOM(sc)) { 990208373Smm if ((crc & 0x180) == 0x180) 991185029Spjd return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 992185029Spjd else 993185029Spjd return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 994168404Spjd } 995168404Spjd 996168404Spjd return (crc & ((1 << DC_BITS_512) - 1)); 997168404Spjd} 998168404Spjd 999168404Spjd/* 1000168404Spjd * Calculate CRC of a multicast group address, return the lower 6 bits. 1001168404Spjd */ 1002168404Spjdstatic u_int32_t dc_crc_be(addr) 1003168404Spjd caddr_t addr; 1004219089Spjd{ 1005168404Spjd u_int32_t crc, carry; 1006168404Spjd int i, j; 1007185029Spjd u_int8_t c; 1008208373Smm 1009168404Spjd /* Compute CRC for the address value. */ 1010168404Spjd crc = 0xFFFFFFFF; /* initial value */ 1011185029Spjd 1012185029Spjd for (i = 0; i < 6; i++) { 1013185029Spjd c = *(addr + i); 1014185029Spjd for (j = 0; j < 8; j++) { 1015185029Spjd carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1016185029Spjd crc <<= 1; 1017219089Spjd c >>= 1; 1018208373Smm if (carry) 1019185029Spjd crc = (crc ^ 0x04c11db6) | carry; 1020185029Spjd } 1021168404Spjd } 1022168404Spjd 1023168404Spjd /* return the filter bit position */ 1024168404Spjd return((crc >> 26) & 0x0000003F); 1025168404Spjd} 1026168404Spjd 1027168404Spjd/* 1028168404Spjd * 21143-style RX filter setup routine. Filter programming is done by 1029168404Spjd * downloading a special setup frame into the TX engine. 21143, Macronix, 1030168404Spjd * PNIC, PNIC II and Davicom chips are programmed this way. 1031168404Spjd * 1032168404Spjd * We always program the chip using 'hash perfect' mode, i.e. one perfect 1033168404Spjd * address (our node address) and a 512-bit hash filter for multicast 1034168404Spjd * frames. We also sneak the broadcast address into the hash filter since 1035168404Spjd * we need that too. 1036168404Spjd */ 1037168404Spjdvoid dc_setfilt_21143(sc) 1038168404Spjd struct dc_softc *sc; 1039168404Spjd{ 1040168404Spjd struct dc_desc *sframe; 1041168404Spjd u_int32_t h, *sp; 1042168404Spjd struct ifmultiaddr *ifma; 1043168404Spjd struct ifnet *ifp; 1044168404Spjd int i; 1045168404Spjd 1046168404Spjd ifp = &sc->arpcom.ac_if; 1047168404Spjd 1048168404Spjd i = sc->dc_cdata.dc_tx_prod; 1049168696Spjd DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1050168404Spjd sc->dc_cdata.dc_tx_cnt++; 1051168404Spjd sframe = &sc->dc_ldata->dc_tx_list[i]; 1052168404Spjd sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1053168404Spjd bzero((char *)sp, DC_SFRAME_LEN); 1054168404Spjd 1055168404Spjd sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1056168404Spjd sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1057168404Spjd DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1058168404Spjd 1059168404Spjd sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1060168404Spjd 1061168404Spjd /* If we want promiscuous mode, set the allframes bit. */ 1062168404Spjd if (ifp->if_flags & IFF_PROMISC) 1063168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1064185029Spjd else 1065168404Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1066168404Spjd 1067168404Spjd if (ifp->if_flags & IFF_ALLMULTI) 1068168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1069168404Spjd else 1070168404Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1071168404Spjd 1072168404Spjd TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1073168404Spjd if (ifma->ifma_addr->sa_family != AF_LINK) 1074168404Spjd continue; 1075168404Spjd h = dc_crc_le(sc, 1076168404Spjd LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1077168404Spjd sp[h >> 4] |= 1 << (h & 0xF); 1078168404Spjd } 1079168404Spjd 1080168404Spjd if (ifp->if_flags & IFF_BROADCAST) { 1081168404Spjd h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1082168404Spjd sp[h >> 4] |= 1 << (h & 0xF); 1083168404Spjd } 1084168404Spjd 1085168404Spjd /* Set our MAC address */ 1086168404Spjd sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1087168404Spjd sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1088168404Spjd sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1089168404Spjd 1090168404Spjd sframe->dc_status = DC_TXSTAT_OWN; 1091168404Spjd CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1092168404Spjd 1093168404Spjd /* 1094168404Spjd * The PNIC takes an exceedingly long time to process its 1095168404Spjd * setup frame; wait 10ms after posting the setup frame 1096168404Spjd * before proceeding, just so it has time to swallow its 1097168404Spjd * medicine. 1098185029Spjd */ 1099185029Spjd DELAY(10000); 1100185029Spjd 1101185029Spjd ifp->if_timer = 5; 1102185029Spjd 1103185029Spjd return; 1104185029Spjd} 1105185029Spjd 1106185029Spjdvoid dc_setfilt_admtek(sc) 1107185029Spjd struct dc_softc *sc; 1108185029Spjd{ 1109185029Spjd struct ifnet *ifp; 1110185029Spjd int h = 0; 1111185029Spjd u_int32_t hashes[2] = { 0, 0 }; 1112168404Spjd struct ifmultiaddr *ifma; 1113185029Spjd 1114168404Spjd ifp = &sc->arpcom.ac_if; 1115185029Spjd 1116168404Spjd /* Init our MAC address */ 1117168404Spjd CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1118168404Spjd CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1119168404Spjd 1120168404Spjd /* If we want promiscuous mode, set the allframes bit. */ 1121168404Spjd if (ifp->if_flags & IFF_PROMISC) 1122168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1123168404Spjd else 1124168404Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1125168404Spjd 1126168404Spjd if (ifp->if_flags & IFF_ALLMULTI) 1127243674Smm DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1128243674Smm else 1129243674Smm DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1130168404Spjd 1131168404Spjd /* first, zot all the existing hash bits */ 1132243674Smm CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1133243674Smm CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1134243674Smm 1135243674Smm /* 1136243674Smm * If we're already in promisc or allmulti mode, we 1137243674Smm * don't have to bother programming the multicast filter. 1138243674Smm */ 1139243674Smm if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1140243674Smm return; 1141243674Smm 1142243674Smm /* now program new ones */ 1143243674Smm TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1144243674Smm if (ifma->ifma_addr->sa_family != AF_LINK) 1145243674Smm continue; 1146243674Smm h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1147243674Smm if (h < 32) 1148243674Smm hashes[0] |= (1 << h); 1149243674Smm else 1150243674Smm hashes[1] |= (1 << (h - 32)); 1151243674Smm } 1152243674Smm 1153243674Smm CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1154243674Smm CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1155243674Smm 1156243674Smm return; 1157243674Smm} 1158243674Smm 1159243674Smmvoid dc_setfilt_asix(sc) 1160243674Smm struct dc_softc *sc; 1161243674Smm{ 1162243674Smm struct ifnet *ifp; 1163243674Smm int h = 0; 1164243674Smm u_int32_t hashes[2] = { 0, 0 }; 1165243674Smm struct ifmultiaddr *ifma; 1166243674Smm 1167243674Smm ifp = &sc->arpcom.ac_if; 1168243674Smm 1169243674Smm /* Init our MAC address */ 1170243674Smm CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1171243674Smm CSR_WRITE_4(sc, DC_AX_FILTDATA, 1172243674Smm *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1173243674Smm CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1174243674Smm CSR_WRITE_4(sc, DC_AX_FILTDATA, 1175243674Smm *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1176243674Smm 1177168404Spjd /* If we want promiscuous mode, set the allframes bit. */ 1178168404Spjd if (ifp->if_flags & IFF_PROMISC) 1179168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1180185029Spjd else 1181185029Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1182185029Spjd 1183185029Spjd if (ifp->if_flags & IFF_ALLMULTI) 1184185029Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1185185029Spjd else 1186185029Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1187168404Spjd 1188168404Spjd /* 1189168404Spjd * The ASIX chip has a special bit to enable reception 1190168404Spjd * of broadcast frames. 1191168404Spjd */ 1192168404Spjd if (ifp->if_flags & IFF_BROADCAST) 1193219089Spjd DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1194219089Spjd else 1195219089Spjd DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1196219089Spjd 1197219089Spjd /* first, zot all the existing hash bits */ 1198219089Spjd CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1199219089Spjd CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1200168404Spjd CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1201243674Smm CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1202243674Smm 1203243674Smm /* 1204243674Smm * If we're already in promisc or allmulti mode, we 1205168404Spjd * don't have to bother programming the multicast filter. 1206168404Spjd */ 1207168404Spjd if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1208168404Spjd return; 1209168404Spjd 1210219089Spjd /* now program new ones */ 1211219089Spjd TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1212168404Spjd if (ifma->ifma_addr->sa_family != AF_LINK) 1213168404Spjd continue; 1214168404Spjd h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1215219089Spjd if (h < 32) 1216219089Spjd hashes[0] |= (1 << h); 1217219089Spjd else 1218168404Spjd hashes[1] |= (1 << (h - 32)); 1219168404Spjd } 1220185029Spjd 1221219089Spjd CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1222243674Smm CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1223168404Spjd CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1224168404Spjd CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1225168404Spjd 1226205231Skmacy return; 1227205231Skmacy} 1228205231Skmacy 1229205231Skmacyvoid dc_setfilt_xircom(sc) 1230206796Spjd struct dc_softc *sc; 1231206796Spjd{ 1232205231Skmacy struct dc_desc *sframe; 1233206796Spjd u_int32_t h, *sp; 1234205231Skmacy struct ifmultiaddr *ifma; 1235205231Skmacy struct ifnet *ifp; 1236205231Skmacy int i; 1237205231Skmacy 1238205231Skmacy ifp = &sc->arpcom.ac_if; 1239205231Skmacy DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1240205231Skmacy 1241205231Skmacy i = sc->dc_cdata.dc_tx_prod; 1242205231Skmacy DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1243168404Spjd sc->dc_cdata.dc_tx_cnt++; 1244168404Spjd sframe = &sc->dc_ldata->dc_tx_list[i]; 1245168404Spjd sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1246168404Spjd bzero((char *)sp, DC_SFRAME_LEN); 1247168404Spjd 1248168404Spjd sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1249206796Spjd sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1250206796Spjd DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1251205231Skmacy 1252205231Skmacy sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1253168404Spjd 1254205231Skmacy /* If we want promiscuous mode, set the allframes bit. */ 1255205231Skmacy if (ifp->if_flags & IFF_PROMISC) 1256205231Skmacy DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1257168404Spjd else 1258185029Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1259168404Spjd 1260243674Smm if (ifp->if_flags & IFF_ALLMULTI) 1261168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1262168404Spjd else 1263168404Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1264168404Spjd 1265185029Spjd TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1266185029Spjd if (ifma->ifma_addr->sa_family != AF_LINK) 1267206794Spjd continue; 1268185029Spjd h = dc_crc_le(sc, 1269168404Spjd LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1270168404Spjd sp[h >> 4] |= 1 << (h & 0xF); 1271168404Spjd } 1272168404Spjd 1273168404Spjd if (ifp->if_flags & IFF_BROADCAST) { 1274168404Spjd h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1275168404Spjd sp[h >> 4] |= 1 << (h & 0xF); 1276168404Spjd } 1277168404Spjd 1278168404Spjd /* Set our MAC address */ 1279168404Spjd sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1280168404Spjd sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1281168404Spjd sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1282168404Spjd 1283168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1284168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1285185029Spjd ifp->if_flags |= IFF_RUNNING; 1286205231Skmacy sframe->dc_status = DC_TXSTAT_OWN; 1287205231Skmacy CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1288185029Spjd 1289205231Skmacy /* 1290205231Skmacy * wait some time... 1291205231Skmacy */ 1292168404Spjd DELAY(1000); 1293205231Skmacy 1294168404Spjd ifp->if_timer = 5; 1295185029Spjd 1296206794Spjd return; 1297168404Spjd} 1298168404Spjd 1299168404Spjdstatic void dc_setfilt(sc) 1300168404Spjd struct dc_softc *sc; 1301168404Spjd{ 1302168404Spjd if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1303168404Spjd DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1304168404Spjd dc_setfilt_21143(sc); 1305168404Spjd 1306168404Spjd if (DC_IS_ASIX(sc)) 1307168404Spjd dc_setfilt_asix(sc); 1308168404Spjd 1309168404Spjd if (DC_IS_ADMTEK(sc)) 1310168404Spjd dc_setfilt_admtek(sc); 1311205231Skmacy 1312205231Skmacy if (DC_IS_XIRCOM(sc)) 1313168404Spjd dc_setfilt_xircom(sc); 1314168404Spjd 1315168404Spjd return; 1316168404Spjd} 1317168404Spjd 1318219089Spjd/* 1319168404Spjd * In order to fiddle with the 1320168404Spjd * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1321168404Spjd * first have to put the transmit and/or receive logic in the idle state. 1322168404Spjd */ 1323168404Spjdstatic void dc_setcfg(sc, media) 1324168404Spjd struct dc_softc *sc; 1325168404Spjd int media; 1326168404Spjd{ 1327168404Spjd int i, restart = 0; 1328205231Skmacy u_int32_t isr; 1329185029Spjd 1330168404Spjd if (IFM_SUBTYPE(media) == IFM_NONE) 1331205231Skmacy return; 1332205231Skmacy 1333168404Spjd if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1334205231Skmacy restart = 1; 1335168404Spjd DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1336168404Spjd 1337205231Skmacy for (i = 0; i < DC_TIMEOUT; i++) { 1338168404Spjd isr = CSR_READ_4(sc, DC_ISR); 1339168404Spjd if (isr & DC_ISR_TX_IDLE && 1340168404Spjd (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1341219089Spjd break; 1342168404Spjd DELAY(10); 1343168404Spjd } 1344168404Spjd 1345168404Spjd if (i == DC_TIMEOUT) 1346168404Spjd printf("dc%d: failed to force tx and " 1347168404Spjd "rx to idle state\n", sc->dc_unit); 1348185029Spjd } 1349185029Spjd 1350168404Spjd if (IFM_SUBTYPE(media) == IFM_100_TX) { 1351168404Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1352205231Skmacy DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1353168404Spjd if (sc->dc_pmode == DC_PMODE_MII) { 1354168404Spjd int watchdogreg; 1355206796Spjd 1356185029Spjd if (DC_IS_INTEL(sc)) { 1357168404Spjd /* there's a write enable bit here that reads as 1 */ 1358205231Skmacy watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1359205231Skmacy watchdogreg &= ~DC_WDOG_CTLWREN; 1360168404Spjd watchdogreg |= DC_WDOG_JABBERDIS; 1361205231Skmacy CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1362168404Spjd } else { 1363205231Skmacy DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1364168404Spjd } 1365168404Spjd DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1366168404Spjd DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1367168404Spjd if (sc->dc_type == DC_TYPE_98713) 1368168404Spjd DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1369168404Spjd DC_NETCFG_SCRAMBLER)); 1370168404Spjd if (!DC_IS_DAVICOM(sc)) 1371185029Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1372168404Spjd DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1373168404Spjd if (DC_IS_INTEL(sc)) 1374205231Skmacy dc_apply_fixup(sc, IFM_AUTO); 1375168404Spjd } else { 1376168404Spjd if (DC_IS_PNIC(sc)) { 1377168404Spjd DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1378168404Spjd DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1379219089Spjd DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1380168404Spjd } 1381168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1382168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1383168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1384168404Spjd if (DC_IS_INTEL(sc)) 1385168404Spjd dc_apply_fixup(sc, 1386168404Spjd (media & IFM_GMASK) == IFM_FDX ? 1387168404Spjd IFM_100_TX|IFM_FDX : IFM_100_TX); 1388168404Spjd } 1389168404Spjd } 1390185029Spjd 1391185029Spjd if (IFM_SUBTYPE(media) == IFM_10_T) { 1392185029Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1393185029Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1394185029Spjd if (sc->dc_pmode == DC_PMODE_MII) { 1395185029Spjd int watchdogreg; 1396168404Spjd 1397168404Spjd /* there's a write enable bit here that reads as 1 */ 1398185029Spjd if (DC_IS_INTEL(sc)) { 1399208373Smm watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1400185029Spjd watchdogreg &= ~DC_WDOG_CTLWREN; 1401208373Smm watchdogreg |= DC_WDOG_JABBERDIS; 1402208373Smm CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1403208373Smm } else { 1404208373Smm DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1405208373Smm } 1406208373Smm DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1407208373Smm DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1408208373Smm if (sc->dc_type == DC_TYPE_98713) 1409208373Smm DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1410208373Smm if (!DC_IS_DAVICOM(sc)) 1411208373Smm DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1412208373Smm DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1413208373Smm if (DC_IS_INTEL(sc)) 1414208373Smm dc_apply_fixup(sc, IFM_AUTO); 1415208373Smm } else { 1416208373Smm if (DC_IS_PNIC(sc)) { 1417208373Smm DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1418185029Spjd DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1419185029Spjd DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1420185029Spjd } 1421185029Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1422185029Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1423208373Smm DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1424185029Spjd if (DC_IS_INTEL(sc)) { 1425208373Smm DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1426208373Smm DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1427208373Smm if ((media & IFM_GMASK) == IFM_FDX) 1428208373Smm DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1429208373Smm else 1430208373Smm DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1431208373Smm DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1432208373Smm DC_CLRBIT(sc, DC_10BTCTRL, 1433208373Smm DC_TCTL_AUTONEGENBL); 1434208373Smm dc_apply_fixup(sc, 1435208373Smm (media & IFM_GMASK) == IFM_FDX ? 1436208373Smm IFM_10_T|IFM_FDX : IFM_10_T); 1437208373Smm DELAY(20000); 1438208373Smm } 1439208373Smm } 1440208373Smm } 1441208373Smm 1442185029Spjd /* 1443185029Spjd * If this is a Davicom DM9102A card with a DM9801 HomePNA 1444185029Spjd * PHY and we want HomePNA mode, set the portsel bit to turn 1445185029Spjd * on the external MII port. 1446185029Spjd */ 1447185029Spjd if (DC_IS_DAVICOM(sc)) { 1448185029Spjd if (IFM_SUBTYPE(media) == IFM_homePNA) { 1449185029Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1450185029Spjd sc->dc_link = 1; 1451185029Spjd } else { 1452185029Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1453185029Spjd } 1454185029Spjd } 1455185029Spjd 1456185029Spjd if ((media & IFM_GMASK) == IFM_FDX) { 1457185029Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1458185029Spjd if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1459185029Spjd DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1460185029Spjd } else { 1461185029Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1462185029Spjd if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1463185029Spjd DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1464185029Spjd } 1465185029Spjd 1466185029Spjd if (restart) 1467168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1468168404Spjd 1469168404Spjd return; 1470168404Spjd} 1471168404Spjd 1472168404Spjdstatic void dc_reset(sc) 1473168404Spjd struct dc_softc *sc; 1474185029Spjd{ 1475168404Spjd register int i; 1476168404Spjd 1477168404Spjd DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1478229578Smm 1479168404Spjd for (i = 0; i < DC_TIMEOUT; i++) { 1480168404Spjd DELAY(10); 1481185029Spjd if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1482168404Spjd break; 1483168404Spjd } 1484168404Spjd 1485168404Spjd if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1486168404Spjd DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1487168404Spjd DELAY(10000); 1488168404Spjd DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1489168404Spjd i = 0; 1490168404Spjd } 1491168404Spjd 1492168404Spjd if (i == DC_TIMEOUT) 1493168404Spjd printf("dc%d: reset never completed!\n", sc->dc_unit); 1494168404Spjd 1495168404Spjd /* Wait a little while for the chip to get its brains in order. */ 1496168404Spjd DELAY(1000); 1497209962Smm 1498209962Smm CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1499209962Smm CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1500209962Smm CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1501209962Smm 1502209962Smm /* 1503209962Smm * Bring the SIA out of reset. In some cases, it looks 1504209962Smm * like failing to unreset the SIA soon enough gets it 1505209962Smm * into a state where it will never come out of reset 1506209962Smm * until we reset the whole chip again. 1507209962Smm */ 1508209962Smm if (DC_IS_INTEL(sc)) { 1509209962Smm DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1510209962Smm CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1511209962Smm CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1512209962Smm } 1513209962Smm 1514209962Smm return; 1515209962Smm} 1516209962Smm 1517209962Smmstatic struct dc_type *dc_devtype(dev) 1518209962Smm device_t dev; 1519209962Smm{ 1520209962Smm struct dc_type *t; 1521209962Smm u_int32_t rev; 1522209962Smm 1523209962Smm t = dc_devs; 1524209962Smm 1525219089Spjd while(t->dc_name != NULL) { 1526219089Spjd if ((pci_get_vendor(dev) == t->dc_vid) && 1527209962Smm (pci_get_device(dev) == t->dc_did)) { 1528209962Smm /* Check the PCI revision */ 1529209962Smm rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1530209962Smm if (t->dc_did == DC_DEVICEID_98713 && 1531219089Spjd rev >= DC_REVISION_98713A) 1532219089Spjd t++; 1533219089Spjd if (t->dc_did == DC_DEVICEID_98713_CP && 1534219089Spjd rev >= DC_REVISION_98713A) 1535219089Spjd t++; 1536219089Spjd if (t->dc_did == DC_DEVICEID_987x5 && 1537219089Spjd rev >= DC_REVISION_98715AEC_C) 1538219089Spjd t++; 1539219089Spjd if (t->dc_did == DC_DEVICEID_987x5 && 1540219089Spjd rev >= DC_REVISION_98725) 1541219089Spjd t++; 1542219089Spjd if (t->dc_did == DC_DEVICEID_AX88140A && 1543219089Spjd rev >= DC_REVISION_88141) 1544219089Spjd t++; 1545219089Spjd if (t->dc_did == DC_DEVICEID_82C168 && 1546219089Spjd rev >= DC_REVISION_82C169) 1547168404Spjd t++; 1548168404Spjd if (t->dc_did == DC_DEVICEID_DM9102 && 1549168404Spjd rev >= DC_REVISION_DM9102A) 1550168404Spjd t++; 1551168404Spjd return(t); 1552168404Spjd } 1553168404Spjd t++; 1554219089Spjd } 1555219089Spjd 1556185029Spjd return(NULL); 1557168404Spjd} 1558168404Spjd 1559168404Spjd/* 1560168404Spjd * Probe for a 21143 or clone chip. Check the PCI vendor and device 1561168404Spjd * IDs against our list and return a device name if we find a match. 1562168404Spjd * We do a little bit of extra work to identify the exact type of 1563168404Spjd * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1564168404Spjd * but different revision IDs. The same is true for 98715/98715A 1565248547Smm * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1566248547Smm * cases, the exact chip revision affects driver behavior. 1567248547Smm */ 1568248547Smmstatic int dc_probe(dev) 1569248547Smm device_t dev; 1570248547Smm{ 1571248547Smm struct dc_type *t; 1572248547Smm 1573248547Smm t = dc_devtype(dev); 1574248547Smm 1575248547Smm if (t != NULL) { 1576168404Spjd device_set_desc(dev, t->dc_name); 1577168404Spjd return(0); 1578168404Spjd } 1579168404Spjd 1580168404Spjd return(ENXIO); 1581168404Spjd} 1582168404Spjd 1583168404Spjdstatic void dc_acpi(dev) 1584168404Spjd device_t dev; 1585168404Spjd{ 1586168404Spjd int unit; 1587185029Spjd 1588185029Spjd unit = device_get_unit(dev); 1589185029Spjd 1590168404Spjd if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1591219089Spjd u_int32_t iobase, membase, irq; 1592185029Spjd 1593219089Spjd /* Save important PCI config data. */ 1594168404Spjd iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1595168404Spjd membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1596219089Spjd irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1597219089Spjd 1598185029Spjd /* Reset the power state. */ 1599219089Spjd printf("dc%d: chip is in D%d power mode " 1600219089Spjd "-- setting to D0\n", unit, 1601168404Spjd pci_get_powerstate(dev)); 1602168404Spjd pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1603168404Spjd 1604208373Smm /* Restore PCI config data. */ 1605168404Spjd pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1606168404Spjd pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1607168404Spjd pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1608168404Spjd } 1609168404Spjd 1610168404Spjd return; 1611168404Spjd} 1612168404Spjd 1613185029Spjdstatic void dc_apply_fixup(sc, media) 1614185029Spjd struct dc_softc *sc; 1615185029Spjd int media; 1616185029Spjd{ 1617168404Spjd struct dc_mediainfo *m; 1618243674Smm u_int8_t *p; 1619185029Spjd int i; 1620243674Smm u_int32_t reg; 1621243674Smm 1622185029Spjd m = sc->dc_mi; 1623185029Spjd 1624185029Spjd while (m != NULL) { 1625243674Smm if (m->dc_media == media) 1626243674Smm break; 1627185029Spjd m = m->dc_next; 1628185029Spjd } 1629185029Spjd 1630185029Spjd if (m == NULL) 1631185029Spjd return; 1632185029Spjd 1633243674Smm for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1634185029Spjd reg = (p[0] | (p[1] << 8)) << 16; 1635185029Spjd CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1636185029Spjd } 1637185029Spjd 1638168404Spjd for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1639168404Spjd reg = (p[0] | (p[1] << 8)) << 16; 1640168404Spjd CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1641168404Spjd } 1642168404Spjd 1643168404Spjd return; 1644168404Spjd} 1645168404Spjd 1646168404Spjdstatic void dc_decode_leaf_sia(sc, l) 1647168404Spjd struct dc_softc *sc; 1648168404Spjd struct dc_eblock_sia *l; 1649243674Smm{ 1650243674Smm struct dc_mediainfo *m; 1651243674Smm 1652219089Spjd m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1653168404Spjd bzero(m, sizeof(struct dc_mediainfo)); 1654168404Spjd if (l->dc_sia_code == DC_SIA_CODE_10BT) 1655243674Smm m->dc_media = IFM_10_T; 1656208373Smm 1657168404Spjd if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1658168404Spjd m->dc_media = IFM_10_T|IFM_FDX; 1659243674Smm 1660208373Smm if (l->dc_sia_code == DC_SIA_CODE_10B2) 1661185029Spjd m->dc_media = IFM_10_2; 1662168404Spjd 1663168404Spjd if (l->dc_sia_code == DC_SIA_CODE_10B5) 1664168404Spjd m->dc_media = IFM_10_5; 1665185029Spjd 1666185029Spjd m->dc_gp_len = 2; 1667168404Spjd m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1668168404Spjd 1669185029Spjd m->dc_next = sc->dc_mi; 1670185029Spjd sc->dc_mi = m; 1671185029Spjd 1672168404Spjd sc->dc_pmode = DC_PMODE_SIA; 1673168404Spjd 1674168404Spjd return; 1675168404Spjd} 1676248547Smm 1677248547Smmstatic void dc_decode_leaf_sym(sc, l) 1678248547Smm struct dc_softc *sc; 1679248547Smm struct dc_eblock_sym *l; 1680248547Smm{ 1681248547Smm struct dc_mediainfo *m; 1682248547Smm 1683248547Smm m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1684248547Smm bzero(m, sizeof(struct dc_mediainfo)); 1685248547Smm if (l->dc_sym_code == DC_SYM_CODE_100BT) 1686168404Spjd m->dc_media = IFM_100_TX; 1687168404Spjd 1688168404Spjd if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1689168404Spjd m->dc_media = IFM_100_TX|IFM_FDX; 1690168404Spjd 1691168404Spjd m->dc_gp_len = 2; 1692168404Spjd m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1693168404Spjd 1694168404Spjd m->dc_next = sc->dc_mi; 1695168404Spjd sc->dc_mi = m; 1696168404Spjd 1697168404Spjd sc->dc_pmode = DC_PMODE_SYM; 1698219089Spjd 1699168404Spjd return; 1700168404Spjd} 1701168404Spjd 1702168404Spjdstatic void dc_decode_leaf_mii(sc, l) 1703168404Spjd struct dc_softc *sc; 1704168404Spjd struct dc_eblock_mii *l; 1705168404Spjd{ 1706168404Spjd u_int8_t *p; 1707168404Spjd struct dc_mediainfo *m; 1708168404Spjd 1709168404Spjd m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1710168404Spjd bzero(m, sizeof(struct dc_mediainfo)); 1711168404Spjd /* We abuse IFM_AUTO to represent MII. */ 1712168404Spjd m->dc_media = IFM_AUTO; 1713219089Spjd m->dc_gp_len = l->dc_gpr_len; 1714168404Spjd 1715219089Spjd p = (u_int8_t *)l; 1716219089Spjd p += sizeof(struct dc_eblock_mii); 1717219089Spjd m->dc_gp_ptr = p; 1718219089Spjd p += 2 * l->dc_gpr_len; 1719219089Spjd m->dc_reset_len = *p; 1720219089Spjd p++; 1721219089Spjd m->dc_reset_ptr = p; 1722219089Spjd 1723219089Spjd m->dc_next = sc->dc_mi; 1724219089Spjd sc->dc_mi = m; 1725219089Spjd 1726219089Spjd return; 1727219089Spjd} 1728185029Spjd 1729219089Spjdstatic void dc_parse_21143_srom(sc) 1730219089Spjd struct dc_softc *sc; 1731219089Spjd{ 1732219089Spjd struct dc_leaf_hdr *lhdr; 1733251419Ssmh struct dc_eblock_hdr *hdr; 1734251419Ssmh int i, loff; 1735219089Spjd char *ptr; 1736219089Spjd 1737252140Sdelphij loff = sc->dc_srom[27]; 1738219089Spjd lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1739219089Spjd 1740219089Spjd ptr = (char *)lhdr; 1741219089Spjd ptr += sizeof(struct dc_leaf_hdr) - 1; 1742219089Spjd for (i = 0; i < lhdr->dc_mcnt; i++) { 1743219089Spjd hdr = (struct dc_eblock_hdr *)ptr; 1744219089Spjd switch(hdr->dc_type) { 1745185029Spjd case DC_EBLOCK_MII: 1746185029Spjd dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1747185029Spjd break; 1748168404Spjd case DC_EBLOCK_SIA: 1749168404Spjd dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1750219089Spjd break; 1751168404Spjd case DC_EBLOCK_SYM: 1752168404Spjd dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1753168404Spjd break; 1754168404Spjd default: 1755168404Spjd /* Don't care. Yet. */ 1756168404Spjd break; 1757219089Spjd } 1758168404Spjd ptr += (hdr->dc_len & 0x7F); 1759168404Spjd ptr++; 1760168404Spjd } 1761168404Spjd 1762168404Spjd return; 1763168404Spjd} 1764219089Spjd 1765168404Spjd/* 1766168404Spjd * Attach the interface. Allocate softc structures, do ifmedia 1767168404Spjd * setup and ethernet/BPF attach. 1768168404Spjd */ 1769168404Spjdstatic int dc_attach(dev) 1770168404Spjd device_t dev; 1771168404Spjd{ 1772168404Spjd int tmp = 0; 1773168404Spjd u_char eaddr[ETHER_ADDR_LEN]; 1774219089Spjd u_int32_t command; 1775219089Spjd struct dc_softc *sc; 1776219089Spjd struct ifnet *ifp; 1777219089Spjd u_int32_t revision; 1778168404Spjd int unit, error = 0, rid, mac_offset; 1779168404Spjd 1780168404Spjd sc = device_get_softc(dev); 1781168404Spjd unit = device_get_unit(dev); 1782168404Spjd bzero(sc, sizeof(struct dc_softc)); 1783168404Spjd 1784168404Spjd mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1785168404Spjd DC_LOCK(sc); 1786168404Spjd 1787168404Spjd /* 1788168404Spjd * Handle power management nonsense. 1789168404Spjd */ 1790168404Spjd dc_acpi(dev); 1791168404Spjd 1792168404Spjd /* 1793168404Spjd * Map control/status registers. 1794168404Spjd */ 1795168404Spjd pci_enable_busmaster(dev); 1796168404Spjd pci_enable_io(dev, SYS_RES_IOPORT); 1797168404Spjd pci_enable_io(dev, SYS_RES_MEMORY); 1798219089Spjd command = pci_read_config(dev, PCIR_COMMAND, 4); 1799219089Spjd 1800219089Spjd#ifdef DC_USEIOSPACE 1801168404Spjd if (!(command & PCIM_CMD_PORTEN)) { 1802219089Spjd printf("dc%d: failed to enable I/O ports!\n", unit); 1803168404Spjd error = ENXIO; 1804219089Spjd goto fail; 1805219089Spjd } 1806219089Spjd#else 1807168404Spjd if (!(command & PCIM_CMD_MEMEN)) { 1808219089Spjd printf("dc%d: failed to enable memory mapping!\n", unit); 1809168404Spjd error = ENXIO; 1810168404Spjd goto fail; 1811168404Spjd } 1812168404Spjd#endif 1813168404Spjd 1814168404Spjd rid = DC_RID; 1815168404Spjd sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1816168404Spjd 0, ~0, 1, RF_ACTIVE); 1817168404Spjd 1818168404Spjd if (sc->dc_res == NULL) { 1819168404Spjd printf("dc%d: couldn't map ports/memory\n", unit); 1820168404Spjd error = ENXIO; 1821168404Spjd goto fail; 1822168404Spjd } 1823168404Spjd 1824168404Spjd sc->dc_btag = rman_get_bustag(sc->dc_res); 1825219089Spjd sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1826168404Spjd 1827219089Spjd /* Allocate interrupt */ 1828168404Spjd rid = 0; 1829168404Spjd sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1830168404Spjd RF_SHAREABLE | RF_ACTIVE); 1831168404Spjd 1832249643Smm if (sc->dc_irq == NULL) { 1833168404Spjd printf("dc%d: couldn't map interrupt\n", unit); 1834168404Spjd bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1835168404Spjd error = ENXIO; 1836168404Spjd goto fail; 1837249643Smm } 1838168404Spjd 1839168404Spjd error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 1840219089Spjd (IS_MPSAFE ? INTR_MPSAFE : 0), 1841168404Spjd dc_intr, sc, &sc->dc_intrhand); 1842168404Spjd 1843168404Spjd if (error) { 1844168404Spjd bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1845168404Spjd bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1846219089Spjd printf("dc%d: couldn't set up irq\n", unit); 1847219089Spjd goto fail; 1848168404Spjd } 1849168404Spjd 1850168404Spjd /* Need this info to decide on a chip type. */ 1851168404Spjd sc->dc_info = dc_devtype(dev); 1852168404Spjd revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1853168404Spjd 1854168404Spjd switch(sc->dc_info->dc_did) { 1855168404Spjd case DC_DEVICEID_21143: 1856168404Spjd sc->dc_type = DC_TYPE_21143; 1857219089Spjd sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1858168404Spjd sc->dc_flags |= DC_REDUCED_MII_POLL; 1859168404Spjd /* Save EEPROM contents so we can parse them later. */ 1860168404Spjd dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1861168404Spjd break; 1862168404Spjd case DC_DEVICEID_DM9100: 1863168404Spjd case DC_DEVICEID_DM9102: 1864168404Spjd sc->dc_type = DC_TYPE_DM9102; 1865168404Spjd sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1866168404Spjd sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1867168404Spjd sc->dc_pmode = DC_PMODE_MII; 1868168404Spjd /* Increase the latency timer value. */ 1869168404Spjd command = pci_read_config(dev, DC_PCI_CFLT, 4); 1870168404Spjd command &= 0xFFFF00FF; 1871168404Spjd command |= 0x00008000; 1872168404Spjd pci_write_config(dev, DC_PCI_CFLT, command, 4); 1873248547Smm break; 1874248547Smm case DC_DEVICEID_AL981: 1875248547Smm sc->dc_type = DC_TYPE_AL981; 1876248547Smm sc->dc_flags |= DC_TX_USE_TX_INTR; 1877248547Smm sc->dc_flags |= DC_TX_ADMTEK_WAR; 1878248547Smm sc->dc_pmode = DC_PMODE_MII; 1879248547Smm break; 1880248547Smm case DC_DEVICEID_AN985: 1881248547Smm case DC_DEVICEID_FE2500: 1882248547Smm case DC_DEVICEID_EN2242: 1883248547Smm sc->dc_type = DC_TYPE_AN985; 1884248547Smm sc->dc_flags |= DC_TX_USE_TX_INTR; 1885248547Smm sc->dc_flags |= DC_TX_ADMTEK_WAR; 1886248547Smm sc->dc_pmode = DC_PMODE_MII; 1887248547Smm break; 1888248547Smm case DC_DEVICEID_98713: 1889248547Smm case DC_DEVICEID_98713_CP: 1890248547Smm if (revision < DC_REVISION_98713A) { 1891248547Smm sc->dc_type = DC_TYPE_98713; 1892248547Smm } 1893248547Smm if (revision >= DC_REVISION_98713A) { 1894248547Smm sc->dc_type = DC_TYPE_98713A; 1895248547Smm sc->dc_flags |= DC_21143_NWAY; 1896248547Smm } 1897248547Smm sc->dc_flags |= DC_REDUCED_MII_POLL; 1898248547Smm sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1899248547Smm break; 1900248547Smm case DC_DEVICEID_987x5: 1901248547Smm case DC_DEVICEID_EN1217: 1902248547Smm /* 1903248547Smm * Macronix MX98715AEC-C/D/E parts have only a 1904248547Smm * 128-bit hash table. We need to deal with these 1905248547Smm * in the same manner as the PNIC II so that we 1906248547Smm * get the right number of bits out of the 1907248547Smm * CRC routine. 1908248547Smm */ 1909248547Smm if (revision >= DC_REVISION_98715AEC_C && 1910248547Smm revision < DC_REVISION_98725) 1911248547Smm sc->dc_flags |= DC_128BIT_HASH; 1912248547Smm sc->dc_type = DC_TYPE_987x5; 1913248547Smm sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1914248547Smm sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1915168404Spjd break; 1916168404Spjd case DC_DEVICEID_98727: 1917168404Spjd sc->dc_type = DC_TYPE_987x5; 1918168404Spjd sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1919168404Spjd sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1920168404Spjd break; 1921168404Spjd case DC_DEVICEID_82C115: 1922185029Spjd sc->dc_type = DC_TYPE_PNICII; 1923185029Spjd sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1924185029Spjd sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1925185029Spjd break; 1926168404Spjd case DC_DEVICEID_82C168: 1927168404Spjd sc->dc_type = DC_TYPE_PNIC; 1928209962Smm sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1929168404Spjd sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1930168404Spjd sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1931168404Spjd if (revision < DC_REVISION_82C169) 1932168404Spjd sc->dc_pmode = DC_PMODE_SYM; 1933205231Skmacy break; 1934168404Spjd case DC_DEVICEID_AX88140A: 1935205231Skmacy sc->dc_type = DC_TYPE_ASIX; 1936205231Skmacy sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1937168404Spjd sc->dc_flags |= DC_REDUCED_MII_POLL; 1938168404Spjd sc->dc_pmode = DC_PMODE_MII; 1939168404Spjd break; 1940205231Skmacy case DC_DEVICEID_X3201: 1941205231Skmacy sc->dc_type = DC_TYPE_XIRCOM; 1942168404Spjd sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1943168404Spjd DC_TX_ALIGN; 1944168404Spjd /* 1945168404Spjd * We don't actually need to coalesce, but we're doing 1946206796Spjd * it to obtain a double word aligned buffer. 1947205231Skmacy * The DC_TX_COALESCE flag is required. 1948205231Skmacy */ 1949205231Skmacy break; 1950205231Skmacy case DC_DEVICEID_RS7112: 1951205231Skmacy sc->dc_type = DC_TYPE_CONEXANT; 1952205231Skmacy sc->dc_flags |= DC_TX_INTR_ALWAYS; 1953205231Skmacy sc->dc_flags |= DC_REDUCED_MII_POLL; 1954205231Skmacy sc->dc_pmode = DC_PMODE_MII; 1955205231Skmacy dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 256, 0); 1956205231Skmacy break; 1957205231Skmacy default: 1958205231Skmacy printf("dc%d: unknown device: %x\n", sc->dc_unit, 1959205231Skmacy sc->dc_info->dc_did); 1960205231Skmacy break; 1961205231Skmacy } 1962206796Spjd 1963205231Skmacy /* Save the cache line size. */ 1964205231Skmacy if (DC_IS_DAVICOM(sc)) 1965205231Skmacy sc->dc_cachesize = 0; 1966205231Skmacy else 1967206796Spjd sc->dc_cachesize = pci_read_config(dev, 1968168404Spjd DC_PCI_CFLT, 4) & 0xFF; 1969205231Skmacy 1970205231Skmacy /* Reset the adapter. */ 1971205231Skmacy dc_reset(sc); 1972185029Spjd 1973185029Spjd /* Take 21143 out of snooze mode */ 1974205231Skmacy if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1975168404Spjd command = pci_read_config(dev, DC_PCI_CFDD, 4); 1976168404Spjd command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1977185029Spjd pci_write_config(dev, DC_PCI_CFDD, command, 4); 1978168404Spjd } 1979219089Spjd 1980219089Spjd /* 1981168404Spjd * Try to learn something about the supported media. 1982168404Spjd * We know that ASIX and ADMtek and Davicom devices 1983168404Spjd * will *always* be using MII media, so that's a no-brainer. 1984168404Spjd * The tricky ones are the Macronix/PNIC II and the 1985168404Spjd * Intel 21143. 1986168404Spjd */ 1987168404Spjd if (DC_IS_INTEL(sc)) 1988168404Spjd dc_parse_21143_srom(sc); 1989168404Spjd else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1990168404Spjd if (sc->dc_type == DC_TYPE_98713) 1991243674Smm sc->dc_pmode = DC_PMODE_MII; 1992168404Spjd else 1993168404Spjd sc->dc_pmode = DC_PMODE_SYM; 1994168404Spjd } else if (!sc->dc_pmode) 1995219089Spjd sc->dc_pmode = DC_PMODE_MII; 1996185029Spjd 1997185029Spjd /* 1998185029Spjd * Get station address from the EEPROM. 1999168404Spjd */ 2000168404Spjd switch(sc->dc_type) { 2001168404Spjd case DC_TYPE_98713: 2002185029Spjd case DC_TYPE_98713A: 2003185029Spjd case DC_TYPE_987x5: 2004168404Spjd case DC_TYPE_PNICII: 2005168404Spjd dc_read_eeprom(sc, (caddr_t)&mac_offset, 2006168404Spjd (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2007168404Spjd dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2008168404Spjd break; 2009168404Spjd case DC_TYPE_PNIC: 2010168404Spjd dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2011168404Spjd break; 2012168404Spjd case DC_TYPE_DM9102: 2013168404Spjd case DC_TYPE_21143: 2014168404Spjd case DC_TYPE_ASIX: 2015168404Spjd dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2016168404Spjd break; 2017219089Spjd case DC_TYPE_AL981: 2018168404Spjd case DC_TYPE_AN985: 2019219089Spjd dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2020168404Spjd break; 2021168404Spjd case DC_TYPE_CONEXANT: 2022168404Spjd bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2023168404Spjd break; 2024208373Smm case DC_TYPE_XIRCOM: 2025208373Smm dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 2026208373Smm break; 2027208373Smm default: 2028208373Smm dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2029208373Smm break; 2030208373Smm } 2031208373Smm 2032208373Smm /* 2033208373Smm * A 21143 or clone chip was detected. Inform the world. 2034208373Smm */ 2035208373Smm printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2036208373Smm 2037208373Smm sc->dc_unit = unit; 2038208373Smm bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2039185029Spjd 2040185029Spjd sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2041185029Spjd M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2042185029Spjd 2043185029Spjd if (sc->dc_ldata == NULL) { 2044185029Spjd printf("dc%d: no memory for list buffers!\n", unit); 2045185029Spjd bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2046168404Spjd bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2047168404Spjd bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2048168404Spjd error = ENXIO; 2049168404Spjd goto fail; 2050205231Skmacy } 2051205231Skmacy 2052205231Skmacy bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2053206796Spjd 2054205231Skmacy ifp = &sc->arpcom.ac_if; 2055205231Skmacy ifp->if_softc = sc; 2056205231Skmacy ifp->if_unit = unit; 2057168404Spjd ifp->if_name = "dc"; 2058168404Spjd /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2059168404Spjd ifp->if_mtu = ETHERMTU; 2060168404Spjd ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2061168404Spjd ifp->if_ioctl = dc_ioctl; 2062205231Skmacy ifp->if_output = ether_output; 2063205231Skmacy ifp->if_start = dc_start; 2064206796Spjd ifp->if_watchdog = dc_watchdog; 2065206796Spjd ifp->if_init = dc_init; 2066205231Skmacy ifp->if_baudrate = 10000000; 2067168404Spjd ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2068205231Skmacy 2069205231Skmacy /* 2070205231Skmacy * Do MII setup. If this is a 21143, check for a PHY on the 2071205231Skmacy * MII bus after applying any necessary fixups to twiddle the 2072205231Skmacy * GPIO bits. If we don't end up finding a PHY, restore the 2073205231Skmacy * old selection (SIA only or SIA/SYM) and attach the dcphy 2074205231Skmacy * driver instead. 2075206796Spjd */ 2076205231Skmacy if (DC_IS_INTEL(sc)) { 2077205231Skmacy dc_apply_fixup(sc, IFM_AUTO); 2078205231Skmacy tmp = sc->dc_pmode; 2079206796Spjd sc->dc_pmode = DC_PMODE_MII; 2080168404Spjd } 2081168404Spjd 2082168404Spjd error = mii_phy_probe(dev, &sc->dc_miibus, 2083168404Spjd dc_ifmedia_upd, dc_ifmedia_sts); 2084168404Spjd 2085168404Spjd if (error && DC_IS_INTEL(sc)) { 2086185029Spjd sc->dc_pmode = tmp; 2087249643Smm if (sc->dc_pmode != DC_PMODE_SIA) 2088185029Spjd sc->dc_pmode = DC_PMODE_SYM; 2089185029Spjd sc->dc_flags |= DC_21143_NWAY; 2090185029Spjd mii_phy_probe(dev, &sc->dc_miibus, 2091185029Spjd dc_ifmedia_upd, dc_ifmedia_sts); 2092185029Spjd /* 2093185029Spjd * For non-MII cards, we need to have the 21143 2094185029Spjd * drive the LEDs. Except there are some systems 2095185029Spjd * like the NEC VersaPro NoteBook PC which have no 2096185029Spjd * LEDs, and twiddling these bits has adverse effects 2097185029Spjd * on them. (I.e. you suddenly can't get a link.) 2098209962Smm */ 2099185029Spjd if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2100185029Spjd sc->dc_flags |= DC_TULIP_LEDS; 2101185029Spjd error = 0; 2102185029Spjd } 2103209962Smm 2104185029Spjd if (error) { 2105185029Spjd printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2106205231Skmacy bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2107205231Skmacy bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2108185029Spjd bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2109168404Spjd error = ENXIO; 2110168404Spjd goto fail; 2111168404Spjd } 2112168404Spjd 2113168404Spjd if (DC_IS_XIRCOM(sc)) { 2114168404Spjd /* 2115168404Spjd * setup General Purpose Port mode and data so the tulip 2116168404Spjd * can talk to the MII. 2117209962Smm */ 2118168404Spjd CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2119168404Spjd DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2120219089Spjd DELAY(10); 2121205231Skmacy CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2122205231Skmacy DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2123168404Spjd DELAY(10); 2124168404Spjd } 2125205231Skmacy 2126205231Skmacy /* 2127205231Skmacy * Call MI attach routine. 2128168404Spjd */ 2129168404Spjd ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2130205231Skmacy 2131205231Skmacy /* 2132205231Skmacy * Tell the upper layer(s) we support long frames. 2133205231Skmacy */ 2134205231Skmacy ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2135205231Skmacy 2136205231Skmacy callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2137206796Spjd 2138205231Skmacy#ifdef SRM_MEDIA 2139205231Skmacy sc->dc_srm_media = 0; 2140205231Skmacy 2141205231Skmacy /* Remember the SRM console media setting */ 2142205231Skmacy if (DC_IS_INTEL(sc)) { 2143185029Spjd command = pci_read_config(dev, DC_PCI_CFDD, 4); 2144185029Spjd command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2145185029Spjd switch ((command >> 8) & 0xff) { 2146185029Spjd case 3: 2147219089Spjd sc->dc_srm_media = IFM_10_T; 2148219089Spjd break; 2149219089Spjd case 4: 2150219089Spjd sc->dc_srm_media = IFM_10_T | IFM_FDX; 2151219089Spjd break; 2152168404Spjd case 5: 2153219089Spjd sc->dc_srm_media = IFM_100_TX; 2154219089Spjd break; 2155219089Spjd case 6: 2156168404Spjd sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2157168404Spjd break; 2158168404Spjd } 2159168404Spjd if (sc->dc_srm_media) 2160168404Spjd sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2161185029Spjd } 2162185029Spjd#endif 2163185029Spjd 2164185029Spjd DC_UNLOCK(sc); 2165185029Spjd return(0); 2166185029Spjd 2167185029Spjdfail: 2168185029Spjd DC_UNLOCK(sc); 2169185029Spjd mtx_destroy(&sc->dc_mtx); 2170185029Spjd return(error); 2171185029Spjd} 2172185029Spjd 2173185029Spjdstatic int dc_detach(dev) 2174185029Spjd device_t dev; 2175168404Spjd{ 2176168404Spjd struct dc_softc *sc; 2177168404Spjd struct ifnet *ifp; 2178219089Spjd struct dc_mediainfo *m; 2179219089Spjd 2180219089Spjd sc = device_get_softc(dev); 2181219089Spjd 2182219089Spjd DC_LOCK(sc); 2183219089Spjd 2184219089Spjd ifp = &sc->arpcom.ac_if; 2185219089Spjd 2186219089Spjd dc_stop(sc); 2187219089Spjd ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2188219089Spjd 2189219089Spjd bus_generic_detach(dev); 2190219089Spjd device_delete_child(dev, sc->dc_miibus); 2191219089Spjd 2192168404Spjd bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2193168404Spjd bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2194205231Skmacy bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2195206796Spjd 2196205231Skmacy contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2197206796Spjd if (sc->dc_pnic_rx_buf != NULL) 2198205231Skmacy free(sc->dc_pnic_rx_buf, M_DEVBUF); 2199205231Skmacy 2200206796Spjd while(sc->dc_mi != NULL) { 2201205231Skmacy m = sc->dc_mi->dc_next; 2202205231Skmacy free(sc->dc_mi, M_DEVBUF); 2203185029Spjd sc->dc_mi = m; 2204205231Skmacy } 2205205231Skmacy 2206205231Skmacy DC_UNLOCK(sc); 2207205231Skmacy mtx_destroy(&sc->dc_mtx); 2208185029Spjd 2209185029Spjd return(0); 2210168404Spjd} 2211168404Spjd 2212168404Spjd/* 2213168404Spjd * Initialize the transmit descriptors. 2214168404Spjd */ 2215168404Spjdstatic int dc_list_tx_init(sc) 2216168404Spjd struct dc_softc *sc; 2217168404Spjd{ 2218168404Spjd struct dc_chain_data *cd; 2219168404Spjd struct dc_list_data *ld; 2220168404Spjd int i, nexti; 2221168404Spjd 2222168404Spjd cd = &sc->dc_cdata; 2223208373Smm ld = sc->dc_ldata; 2224168404Spjd for (i = 0; i < DC_TX_LIST_CNT; i++) { 2225208373Smm nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2226208373Smm ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2227208373Smm cd->dc_tx_chain[i] = NULL; 2228168404Spjd ld->dc_tx_list[i].dc_data = 0; 2229209275Smm ld->dc_tx_list[i].dc_ctl = 0; 2230209275Smm } 2231209275Smm 2232208373Smm cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2233208373Smm 2234208373Smm return(0); 2235209962Smm} 2236208373Smm 2237168404Spjd 2238168404Spjd/* 2239208373Smm * Initialize the RX descriptors and allocate mbufs for them. Note that 2240208373Smm * we arrange the descriptors in a closed ring, so that the last descriptor 2241209962Smm * points back to the first. 2242185029Spjd */ 2243185029Spjdstatic int dc_list_rx_init(sc) 2244185029Spjd struct dc_softc *sc; 2245208373Smm{ 2246208373Smm struct dc_chain_data *cd; 2247208373Smm struct dc_list_data *ld; 2248168404Spjd int i, nexti; 2249208373Smm 2250208373Smm cd = &sc->dc_cdata; 2251208373Smm ld = sc->dc_ldata; 2252208373Smm 2253209962Smm for (i = 0; i < DC_RX_LIST_CNT; i++) { 2254208373Smm if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2255168404Spjd return(ENOBUFS); 2256168404Spjd nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2257208373Smm ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2258208373Smm } 2259208373Smm 2260209962Smm cd->dc_rx_prod = 0; 2261208373Smm 2262208373Smm return(0); 2263168404Spjd} 2264208373Smm 2265208373Smm/* 2266208373Smm * Initialize an RX descriptor and attach an MBUF cluster. 2267168404Spjd */ 2268208373Smmstatic int dc_newbuf(sc, i, m) 2269168404Spjd struct dc_softc *sc; 2270208373Smm int i; 2271208373Smm struct mbuf *m; 2272209962Smm{ 2273208373Smm struct mbuf *m_new = NULL; 2274185029Spjd struct dc_desc *c; 2275208373Smm 2276208373Smm c = &sc->dc_ldata->dc_rx_list[i]; 2277208373Smm 2278208373Smm if (m == NULL) { 2279208373Smm MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2280209962Smm if (m_new == NULL) 2281168404Spjd return(ENOBUFS); 2282168404Spjd 2283168404Spjd MCLGET(m_new, M_DONTWAIT); 2284168404Spjd if (!(m_new->m_flags & M_EXT)) { 2285168404Spjd m_freem(m_new); 2286168404Spjd return(ENOBUFS); 2287191903Skmacy } 2288191903Skmacy m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2289191903Skmacy } else { 2290191903Skmacy m_new = m; 2291191903Skmacy m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2292206796Spjd m_new->m_data = m_new->m_ext.ext_buf; 2293168404Spjd } 2294191903Skmacy 2295191903Skmacy m_adj(m_new, sizeof(u_int64_t)); 2296191903Skmacy 2297191903Skmacy /* 2298191903Skmacy * If this is a PNIC chip, zero the buffer. This is part 2299191903Skmacy * of the workaround for the receive bug in the 82c168 and 2300191903Skmacy * 82c169 chips. 2301219089Spjd */ 2302168404Spjd if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2303219089Spjd bzero((char *)mtod(m_new, char *), m_new->m_len); 2304168404Spjd 2305168404Spjd sc->dc_cdata.dc_rx_chain[i] = m_new; 2306168404Spjd c->dc_data = vtophys(mtod(m_new, caddr_t)); 2307168404Spjd c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2308168404Spjd c->dc_status = DC_RXSTAT_OWN; 2309168404Spjd 2310168404Spjd return(0); 2311168404Spjd} 2312191903Skmacy 2313191903Skmacy/* 2314191903Skmacy * Grrrrr. 2315168404Spjd * The PNIC chip has a terrible bug in it that manifests itself during 2316168404Spjd * periods of heavy activity. The exact mode of failure if difficult to 2317168404Spjd * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2318185029Spjd * will happen on slow machines. The bug is that sometimes instead of 2319168404Spjd * uploading one complete frame during reception, it uploads what looks 2320168404Spjd * like the entire contents of its FIFO memory. The frame we want is at 2321168404Spjd * the end of the whole mess, but we never know exactly how much data has 2322185029Spjd * been uploaded, so salvaging the frame is hard. 2323168404Spjd * 2324209962Smm * There is only one way to do it reliably, and it's disgusting. 2325209962Smm * Here's what we know: 2326209962Smm * 2327229578Smm * - We know there will always be somewhere between one and three extra 2328209962Smm * descriptors uploaded. 2329205231Skmacy * 2330209962Smm * - We know the desired received frame will always be at the end of the 2331185029Spjd * total data upload. 2332185029Spjd * 2333185029Spjd * - We know the size of the desired received frame because it will be 2334205231Skmacy * provided in the length field of the status word in the last descriptor. 2335209962Smm * 2336185029Spjd * Here's what we do: 2337185029Spjd * 2338185029Spjd * - When we allocate buffers for the receive ring, we bzero() them. 2339205231Skmacy * This means that we know that the buffer contents should be all 2340209962Smm * zeros, except for data uploaded by the chip. 2341185029Spjd * 2342185029Spjd * - We also force the PNIC chip to upload frames that include the 2343185029Spjd * ethernet CRC at the end. 2344205231Skmacy * 2345209962Smm * - We gather all of the bogus frame data into a single buffer. 2346185029Spjd * 2347185029Spjd * - We then position a pointer at the end of this buffer and scan 2348185029Spjd * backwards until we encounter the first non-zero byte of data. 2349168404Spjd * This is the end of the received frame. We know we will encounter 2350209962Smm * some data at the end of the frame because the CRC will always be 2351209962Smm * there, so even if the sender transmits a packet of all zeros, 2352168404Spjd * we won't be fooled. 2353168404Spjd * 2354168404Spjd * - We know the size of the actual received frame, so we subtract 2355168404Spjd * that value from the current pointer location. This brings us 2356185029Spjd * to the start of the actual received packet. 2357168404Spjd * 2358168404Spjd * - We copy this into an mbuf and pass it on, along with the actual 2359168404Spjd * frame length. 2360168404Spjd * 2361168404Spjd * The performance hit is tremendous, but it beats dropping frames all 2362168404Spjd * the time. 2363168404Spjd */ 2364168404Spjd 2365168404Spjd#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2366168404Spjdstatic void dc_pnic_rx_bug_war(sc, idx) 2367168404Spjd struct dc_softc *sc; 2368168404Spjd int idx; 2369168404Spjd{ 2370168404Spjd struct dc_desc *cur_rx; 2371168404Spjd struct dc_desc *c = NULL; 2372168404Spjd struct mbuf *m = NULL; 2373168404Spjd unsigned char *ptr; 2374168404Spjd int i, total_len; 2375168404Spjd u_int32_t rxstat = 0; 2376168404Spjd 2377168404Spjd i = sc->dc_pnic_rx_bug_save; 2378168404Spjd cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2379168404Spjd ptr = sc->dc_pnic_rx_buf; 2380168404Spjd bzero(ptr, sizeof(DC_RXLEN * 5)); 2381168404Spjd 2382168404Spjd /* Copy all the bytes from the bogus buffers. */ 2383168404Spjd while (1) { 2384168404Spjd c = &sc->dc_ldata->dc_rx_list[i]; 2385168404Spjd rxstat = c->dc_status; 2386168404Spjd m = sc->dc_cdata.dc_rx_chain[i]; 2387168404Spjd bcopy(mtod(m, char *), ptr, DC_RXLEN); 2388185029Spjd ptr += DC_RXLEN; 2389168404Spjd /* If this is the last buffer, break out. */ 2390168404Spjd if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2391168404Spjd break; 2392168404Spjd dc_newbuf(sc, i, m); 2393168404Spjd DC_INC(i, DC_RX_LIST_CNT); 2394168404Spjd } 2395219089Spjd 2396197816Skmacy /* Find the length of the actual receive frame. */ 2397197816Skmacy total_len = DC_RXBYTES(rxstat); 2398168404Spjd 2399191902Skmacy /* Scan backwards until we hit a non-zero byte. */ 2400212780Savg while(*ptr == 0x00) 2401212780Savg ptr--; 2402191902Skmacy 2403212783Savg /* Round off. */ 2404191902Skmacy if ((uintptr_t)(ptr) & 0x3) 2405191902Skmacy ptr -= 1; 2406219089Spjd 2407168404Spjd /* Now find the start of the frame. */ 2408185029Spjd ptr -= total_len; 2409185029Spjd if (ptr < sc->dc_pnic_rx_buf) 2410185029Spjd ptr = sc->dc_pnic_rx_buf; 2411185029Spjd 2412185029Spjd /* 2413185029Spjd * Now copy the salvaged frame to the last mbuf and fake up 2414185029Spjd * the status word to make it look like a successful 2415185029Spjd * frame reception. 2416185029Spjd */ 2417185029Spjd dc_newbuf(sc, i, m); 2418185029Spjd bcopy(ptr, mtod(m, char *), total_len); 2419185029Spjd cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2420185029Spjd 2421185029Spjd return; 2422185029Spjd} 2423168404Spjd 2424185029Spjd/* 2425168404Spjd * This routine searches the RX ring for dirty descriptors in the 2426168404Spjd * event that the rxeof routine falls out of sync with the chip's 2427168404Spjd * current descriptor pointer. This may happen sometimes as a result 2428168404Spjd * of a "no RX buffer available" condition that happens when the chip 2429168404Spjd * consumes all of the RX buffers before the driver has a chance to 2430168404Spjd * process the RX ring. This routine may need to be called more than 2431168404Spjd * once to bring the driver back in sync with the chip, however we 2432168404Spjd * should still be getting RX DONE interrupts to drive the search 2433168404Spjd * for new packets in the RX ring, so we should catch up eventually. 2434168404Spjd */ 2435168404Spjdstatic int dc_rx_resync(sc) 2436168404Spjd struct dc_softc *sc; 2437168404Spjd{ 2438168404Spjd int i, pos; 2439168404Spjd struct dc_desc *cur_rx; 2440168404Spjd 2441185029Spjd pos = sc->dc_cdata.dc_rx_prod; 2442168404Spjd 2443168404Spjd for (i = 0; i < DC_RX_LIST_CNT; i++) { 2444168404Spjd cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2445168404Spjd if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2446168404Spjd break; 2447168404Spjd DC_INC(pos, DC_RX_LIST_CNT); 2448219089Spjd } 2449175633Spjd 2450168404Spjd /* If the ring really is empty, then just return. */ 2451219089Spjd if (i == DC_RX_LIST_CNT) 2452168404Spjd return(0); 2453168404Spjd 2454168404Spjd /* We've fallen behing the chip: catch it. */ 2455168404Spjd sc->dc_cdata.dc_rx_prod = pos; 2456168404Spjd 2457168404Spjd return(EAGAIN); 2458168404Spjd} 2459168404Spjd 2460208454Spjd/* 2461208454Spjd * A frame has been uploaded: pass the resulting mbuf chain up to 2462208454Spjd * the higher level protocols. 2463168404Spjd */ 2464168404Spjdstatic void dc_rxeof(sc) 2465168404Spjd struct dc_softc *sc; 2466168404Spjd{ 2467168404Spjd struct ether_header *eh; 2468168404Spjd struct mbuf *m; 2469168404Spjd struct ifnet *ifp; 2470168404Spjd struct dc_desc *cur_rx; 2471185029Spjd int i, total_len = 0; 2472185029Spjd u_int32_t rxstat; 2473185029Spjd 2474185029Spjd ifp = &sc->arpcom.ac_if; 2475185029Spjd i = sc->dc_cdata.dc_rx_prod; 2476185029Spjd 2477185029Spjd while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2478168404Spjd 2479168404Spjd#ifdef DEVICE_POLLING 2480168404Spjd if (ifp->if_ipending & IFF_POLLING) { 2481168404Spjd if (sc->rxcycles <= 0) 2482168404Spjd break; 2483168404Spjd sc->rxcycles--; 2484168404Spjd } 2485168404Spjd#endif /* DEVICE_POLLING */ 2486168404Spjd cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2487185029Spjd rxstat = cur_rx->dc_status; 2488168404Spjd m = sc->dc_cdata.dc_rx_chain[i]; 2489168404Spjd total_len = DC_RXBYTES(rxstat); 2490168404Spjd 2491168404Spjd if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2492168404Spjd if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2493168404Spjd if (rxstat & DC_RXSTAT_FIRSTFRAG) 2494168404Spjd sc->dc_pnic_rx_bug_save = i; 2495168404Spjd if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2496168404Spjd DC_INC(i, DC_RX_LIST_CNT); 2497168404Spjd continue; 2498168404Spjd } 2499168404Spjd dc_pnic_rx_bug_war(sc, i); 2500168404Spjd rxstat = cur_rx->dc_status; 2501168404Spjd total_len = DC_RXBYTES(rxstat); 2502168404Spjd } 2503168404Spjd } 2504168404Spjd 2505168404Spjd sc->dc_cdata.dc_rx_chain[i] = NULL; 2506168404Spjd 2507168404Spjd /* 2508168404Spjd * If an error occurs, update stats, clear the 2509168404Spjd * status word and leave the mbuf cluster in place: 2510168404Spjd * it should simply get re-used next time this descriptor 2511168404Spjd * comes up in the ring. However, don't report long 2512168404Spjd * frames as errors since they could be vlans 2513168404Spjd */ 2514168404Spjd if ((rxstat & DC_RXSTAT_RXERR)){ 2515168404Spjd if (!(rxstat & DC_RXSTAT_GIANT) || 2516168404Spjd (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2517168404Spjd DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2518168404Spjd DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2519168404Spjd ifp->if_ierrors++; 2520168404Spjd if (rxstat & DC_RXSTAT_COLLSEEN) 2521168404Spjd ifp->if_collisions++; 2522168404Spjd dc_newbuf(sc, i, m); 2523168404Spjd if (rxstat & DC_RXSTAT_CRCERR) { 2524168404Spjd DC_INC(i, DC_RX_LIST_CNT); 2525168404Spjd continue; 2526168404Spjd } else { 2527168404Spjd dc_init(sc); 2528168404Spjd return; 2529168404Spjd } 2530168404Spjd } 2531168404Spjd } 2532168404Spjd 2533219089Spjd /* No errors; receive the packet. */ 2534168404Spjd total_len -= ETHER_CRC_LEN; 2535185029Spjd#ifdef __i386__ 2536168404Spjd /* 2537185029Spjd * On the x86 we do not have alignment problems, so try to 2538168404Spjd * allocate a new buffer for the receive ring, and pass up 2539168404Spjd * the one where the packet is already, saving the expensive 2540168404Spjd * copy done in m_devget(). 2541168404Spjd * If we are on an architecture with alignment problems, or 2542168404Spjd * if the allocation fails, then use m_devget and leave the 2543168404Spjd * existing buffer in the receive ring. 2544168404Spjd */ 2545185029Spjd if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2546185029Spjd m->m_pkthdr.rcvif = ifp; 2547219089Spjd m->m_pkthdr.len = m->m_len = total_len; 2548168404Spjd DC_INC(i, DC_RX_LIST_CNT); 2549168404Spjd } else 2550168404Spjd#endif 2551209275Smm { 2552168404Spjd struct mbuf *m0; 2553168404Spjd 2554168404Spjd m0 = m_devget(mtod(m, char *), total_len, 2555168404Spjd ETHER_ALIGN, ifp, NULL); 2556211762Savg dc_newbuf(sc, i, m); 2557211762Savg DC_INC(i, DC_RX_LIST_CNT); 2558185029Spjd if (m0 == NULL) { 2559185029Spjd ifp->if_ierrors++; 2560211762Savg continue; 2561168404Spjd } 2562168404Spjd m = m0; 2563168404Spjd } 2564168404Spjd 2565168404Spjd ifp->if_ipackets++; 2566168404Spjd eh = mtod(m, struct ether_header *); 2567168404Spjd 2568168404Spjd /* Remove header from mbuf and pass it on. */ 2569168404Spjd m_adj(m, sizeof(struct ether_header)); 2570168404Spjd ether_input(ifp, eh, m); 2571168404Spjd } 2572168404Spjd 2573168404Spjd sc->dc_cdata.dc_rx_prod = i; 2574168404Spjd} 2575168404Spjd 2576168404Spjd/* 2577168404Spjd * A frame was downloaded to the chip. It's safe for us to clean up 2578168404Spjd * the list buffers. 2579168404Spjd */ 2580168404Spjd 2581168404Spjdstatic void dc_txeof(sc) 2582168404Spjd struct dc_softc *sc; 2583168404Spjd{ 2584168404Spjd struct dc_desc *cur_tx = NULL; 2585208373Smm struct ifnet *ifp; 2586168404Spjd int idx; 2587185029Spjd 2588185029Spjd ifp = &sc->arpcom.ac_if; 2589185029Spjd 2590168404Spjd /* Clear the timeout timer. */ 2591168404Spjd ifp->if_timer = 0; 2592168404Spjd 2593168404Spjd /* 2594168404Spjd * Go through our tx list and free mbufs for those 2595168404Spjd * frames that have been transmitted. 2596168404Spjd */ 2597168404Spjd idx = sc->dc_cdata.dc_tx_cons; 2598168404Spjd while(idx != sc->dc_cdata.dc_tx_prod) { 2599168404Spjd u_int32_t txstat; 2600168404Spjd 2601168404Spjd cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2602209275Smm txstat = cur_tx->dc_status; 2603168404Spjd 2604208373Smm if (txstat & DC_TXSTAT_OWN) 2605168404Spjd break; 2606208373Smm 2607208373Smm if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2608168404Spjd cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2609168404Spjd sc->dc_cdata.dc_tx_cnt--; 2610209275Smm if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2611168404Spjd /* 2612208373Smm * Yes, the PNIC is so brain damaged 2613208373Smm * that it will sometimes generate a TX 2614168404Spjd * underrun error while DMAing the RX 2615168404Spjd * filter setup frame. If we detect this, 2616168404Spjd * we have to send the setup frame again, 2617168404Spjd * or else the filter won't be programmed 2618168404Spjd * correctly. 2619168404Spjd */ 2620168404Spjd if (DC_IS_PNIC(sc)) { 2621168404Spjd if (txstat & DC_TXSTAT_ERRSUM) 2622168404Spjd dc_setfilt(sc); 2623168404Spjd } 2624168404Spjd sc->dc_cdata.dc_tx_chain[idx] = NULL; 2625168404Spjd } 2626168404Spjd DC_INC(idx, DC_TX_LIST_CNT); 2627168404Spjd continue; 2628168404Spjd } 2629168404Spjd 2630168404Spjd if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2631168404Spjd /* 2632168404Spjd * XXX: Why does my Xircom taunt me so? 2633168404Spjd * For some reason it likes setting the CARRLOST flag 2634168404Spjd * even when the carrier is there. wtf?!? 2635168404Spjd * Who knows, but Conexant chips have the 2636168404Spjd * same problem. Maybe they took lessons 2637168404Spjd * from Xircom. 2638168404Spjd */ 2639168404Spjd if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2640168404Spjd sc->dc_pmode == DC_PMODE_MII && 2641168404Spjd ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2642168404Spjd DC_TXSTAT_NOCARRIER))) 2643168404Spjd txstat &= ~DC_TXSTAT_ERRSUM; 2644168404Spjd } else { 2645168404Spjd if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2646168404Spjd sc->dc_pmode == DC_PMODE_MII && 2647168404Spjd ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2648168404Spjd DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2649185029Spjd txstat &= ~DC_TXSTAT_ERRSUM; 2650168404Spjd } 2651185029Spjd 2652185029Spjd if (txstat & DC_TXSTAT_ERRSUM) { 2653185029Spjd ifp->if_oerrors++; 2654219089Spjd if (txstat & DC_TXSTAT_EXCESSCOLL) 2655185029Spjd ifp->if_collisions++; 2656185029Spjd if (txstat & DC_TXSTAT_LATECOLL) 2657185029Spjd ifp->if_collisions++; 2658185029Spjd if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2659185029Spjd dc_init(sc); 2660185029Spjd return; 2661185029Spjd } 2662185029Spjd } 2663185029Spjd 2664185029Spjd ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2665185029Spjd 2666219089Spjd ifp->if_opackets++; 2667185029Spjd if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2668168404Spjd m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2669168404Spjd sc->dc_cdata.dc_tx_chain[idx] = NULL; 2670168404Spjd } 2671168404Spjd 2672168404Spjd sc->dc_cdata.dc_tx_cnt--; 2673168404Spjd DC_INC(idx, DC_TX_LIST_CNT); 2674168404Spjd } 2675168404Spjd 2676168404Spjd sc->dc_cdata.dc_tx_cons = idx; 2677168404Spjd if (cur_tx != NULL) 2678168404Spjd ifp->if_flags &= ~IFF_OACTIVE; 2679168404Spjd 2680168404Spjd return; 2681168404Spjd} 2682168404Spjd 2683168404Spjdstatic void dc_tick(xsc) 2684168404Spjd void *xsc; 2685168404Spjd{ 2686168404Spjd struct dc_softc *sc; 2687168404Spjd struct mii_data *mii; 2688168404Spjd struct ifnet *ifp; 2689168404Spjd u_int32_t r; 2690168404Spjd 2691168404Spjd sc = xsc; 2692168404Spjd DC_LOCK(sc); 2693168404Spjd ifp = &sc->arpcom.ac_if; 2694168404Spjd mii = device_get_softc(sc->dc_miibus); 2695168404Spjd 2696168404Spjd if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2697168404Spjd if (sc->dc_flags & DC_21143_NWAY) { 2698168404Spjd r = CSR_READ_4(sc, DC_10BTSTAT); 2699168404Spjd if (IFM_SUBTYPE(mii->mii_media_active) == 2700168404Spjd IFM_100_TX && (r & DC_TSTAT_LS100)) { 2701168404Spjd sc->dc_link = 0; 2702168404Spjd mii_mediachg(mii); 2703168404Spjd } 2704168404Spjd if (IFM_SUBTYPE(mii->mii_media_active) == 2705168404Spjd IFM_10_T && (r & DC_TSTAT_LS10)) { 2706168404Spjd sc->dc_link = 0; 2707168404Spjd mii_mediachg(mii); 2708168404Spjd } 2709168404Spjd if (sc->dc_link == 0) 2710185029Spjd mii_tick(mii); 2711168404Spjd } else { 2712168404Spjd r = CSR_READ_4(sc, DC_ISR); 2713208373Smm if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2714168404Spjd sc->dc_cdata.dc_tx_cnt == 0) 2715168404Spjd mii_tick(mii); 2716168404Spjd if (!(mii->mii_media_status & IFM_ACTIVE)) 2717208373Smm sc->dc_link = 0; 2718185029Spjd } 2719168404Spjd } else 2720168404Spjd mii_tick(mii); 2721168404Spjd 2722168404Spjd /* 2723168404Spjd * When the init routine completes, we expect to be able to send 2724168404Spjd * packets right away, and in fact the network code will send a 2725168404Spjd * gratuitous ARP the moment the init routine marks the interface 2726168404Spjd * as running. However, even though the MAC may have been initialized, 2727168404Spjd * there may be a delay of a few seconds before the PHY completes 2728168404Spjd * autonegotiation and the link is brought up. Any transmissions 2729168404Spjd * made during that delay will be lost. Dealing with this is tricky: 2730168404Spjd * we can't just pause in the init routine while waiting for the 2731168404Spjd * PHY to come ready since that would bring the whole system to 2732168404Spjd * a screeching halt for several seconds. 2733168404Spjd * 2734208373Smm * What we do here is prevent the TX start routine from sending 2735185029Spjd * any packets until a link has been established. After the 2736168404Spjd * interface has been initialized, the tick routine will poll 2737168404Spjd * the state of the PHY until the IFM_ACTIVE flag is set. Until 2738168404Spjd * that time, packets will stay in the send queue, and once the 2739208373Smm * link comes up, they will be flushed out to the wire. 2740185029Spjd */ 2741168404Spjd if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2742209962Smm IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2743168404Spjd sc->dc_link++; 2744168404Spjd if (ifp->if_snd.ifq_head != NULL) 2745208373Smm dc_start(ifp); 2746168404Spjd } 2747168404Spjd 2748168404Spjd if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2749208373Smm callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2750185029Spjd else 2751168404Spjd callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2752168404Spjd 2753168404Spjd DC_UNLOCK(sc); 2754168404Spjd 2755168404Spjd return; 2756168404Spjd} 2757168404Spjd 2758168404Spjd/* 2759168404Spjd * A transmit underrun has occurred. Back off the transmit threshold, 2760168404Spjd * or switch to store and forward mode if we have to. 2761168404Spjd */ 2762168404Spjdstatic void dc_tx_underrun(sc) 2763168404Spjd struct dc_softc *sc; 2764168404Spjd{ 2765168404Spjd u_int32_t isr; 2766185029Spjd int i; 2767168404Spjd 2768168404Spjd if (DC_IS_DAVICOM(sc)) 2769168404Spjd dc_init(sc); 2770168404Spjd 2771168404Spjd if (DC_IS_INTEL(sc)) { 2772168404Spjd /* 2773168404Spjd * The real 21143 requires that the transmitter be idle 2774168404Spjd * in order to change the transmit threshold or store 2775168404Spjd * and forward state. 2776205231Skmacy */ 2777168404Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2778168404Spjd 2779168404Spjd for (i = 0; i < DC_TIMEOUT; i++) { 2780168404Spjd isr = CSR_READ_4(sc, DC_ISR); 2781168404Spjd if (isr & DC_ISR_TX_IDLE) 2782168404Spjd break; 2783168404Spjd DELAY(10); 2784168404Spjd } 2785168404Spjd if (i == DC_TIMEOUT) { 2786219089Spjd printf("dc%d: failed to force tx to idle state\n", 2787219089Spjd sc->dc_unit); 2788168404Spjd dc_init(sc); 2789168404Spjd } 2790168404Spjd } 2791168404Spjd 2792168404Spjd printf("dc%d: TX underrun -- ", sc->dc_unit); 2793168404Spjd sc->dc_txthresh += DC_TXTHRESH_INC; 2794168404Spjd if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2795168404Spjd printf("using store and forward mode\n"); 2796168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2797168404Spjd } else { 2798219089Spjd printf("increasing TX threshold\n"); 2799168404Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2800168404Spjd DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2801168404Spjd } 2802168404Spjd 2803219089Spjd if (DC_IS_INTEL(sc)) 2804219089Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2805168404Spjd 2806168404Spjd return; 2807168404Spjd} 2808168404Spjd 2809168404Spjd#ifdef DEVICE_POLLING 2810168404Spjdstatic poll_handler_t dc_poll; 2811168404Spjd 2812168404Spjdstatic void 2813168404Spjddc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2814168404Spjd{ 2815168404Spjd struct dc_softc *sc = ifp->if_softc; 2816168404Spjd 2817168404Spjd if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2818168404Spjd /* Re-enable interrupts. */ 2819168404Spjd CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2820219089Spjd return; 2821168404Spjd } 2822168404Spjd sc->rxcycles = count; 2823168404Spjd dc_rxeof(sc); 2824168404Spjd dc_txeof(sc); 2825168404Spjd if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2826168404Spjd dc_start(ifp); 2827168404Spjd 2828168404Spjd if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2829219089Spjd u_int32_t status; 2830168404Spjd 2831168404Spjd status = CSR_READ_4(sc, DC_ISR); 2832168404Spjd status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2833168404Spjd DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2834168404Spjd DC_ISR_BUS_ERR); 2835219089Spjd if (!status) 2836168404Spjd return; 2837168404Spjd /* ack what we have */ 2838168404Spjd CSR_WRITE_4(sc, DC_ISR, status); 2839168404Spjd 2840168404Spjd if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 2841168404Spjd u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2842168404Spjd ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2843168404Spjd 2844168404Spjd if (dc_rx_resync(sc)) 2845168404Spjd dc_rxeof(sc); 2846168404Spjd } 2847168404Spjd /* restart transmit unit if necessary */ 2848168404Spjd if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2849168404Spjd CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2850168404Spjd 2851168404Spjd if (status & DC_ISR_TX_UNDERRUN) 2852168404Spjd dc_tx_underrun(sc); 2853168404Spjd 2854168404Spjd if (status & DC_ISR_BUS_ERR) { 2855168404Spjd printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2856168404Spjd dc_reset(sc); 2857168404Spjd dc_init(sc); 2858219089Spjd } 2859168404Spjd } 2860168404Spjd} 2861168404Spjd#endif /* DEVICE_POLLING */ 2862168404Spjd 2863168404Spjdstatic void dc_intr(arg) 2864168404Spjd void *arg; 2865168404Spjd{ 2866168404Spjd struct dc_softc *sc; 2867168404Spjd struct ifnet *ifp; 2868168404Spjd u_int32_t status; 2869168404Spjd 2870168404Spjd sc = arg; 2871168404Spjd 2872168404Spjd if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2873168404Spjd return; 2874168404Spjd 2875168404Spjd DC_LOCK(sc); 2876168404Spjd ifp = &sc->arpcom.ac_if; 2877219089Spjd#ifdef DEVICE_POLLING 2878168404Spjd if (ifp->if_ipending & IFF_POLLING) 2879168404Spjd goto done; 2880168404Spjd if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2881168404Spjd CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2882168404Spjd goto done; 2883168404Spjd } 2884168404Spjd#endif /* DEVICE_POLLING */ 2885168404Spjd 2886168404Spjd /* Suppress unwanted interrupts */ 2887168404Spjd if (!(ifp->if_flags & IFF_UP)) { 2888168404Spjd if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2889168404Spjd dc_stop(sc); 2890168404Spjd DC_UNLOCK(sc); 2891243674Smm return; 2892168404Spjd } 2893168404Spjd 2894168404Spjd /* Disable interrupts. */ 2895219089Spjd CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2896168404Spjd 2897168404Spjd while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2898168404Spjd && status != 0xFFFFFFFF) { 2899168404Spjd 2900185029Spjd CSR_WRITE_4(sc, DC_ISR, status); 2901185029Spjd 2902185029Spjd if (status & DC_ISR_RX_OK) { 2903185029Spjd int curpkts; 2904185029Spjd curpkts = ifp->if_ipackets; 2905219089Spjd dc_rxeof(sc); 2906185029Spjd if (curpkts == ifp->if_ipackets) { 2907185029Spjd while(dc_rx_resync(sc)) 2908168404Spjd dc_rxeof(sc); 2909168404Spjd } 2910168404Spjd } 2911168404Spjd 2912168404Spjd if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2913168404Spjd dc_txeof(sc); 2914168404Spjd 2915168404Spjd if (status & DC_ISR_TX_IDLE) { 2916168404Spjd dc_txeof(sc); 2917168404Spjd if (sc->dc_cdata.dc_tx_cnt) { 2918219089Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2919219089Spjd CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2920249643Smm } 2921168404Spjd } 2922168404Spjd 2923185029Spjd if (status & DC_ISR_TX_UNDERRUN) 2924168404Spjd dc_tx_underrun(sc); 2925168404Spjd 2926168404Spjd if ((status & DC_ISR_RX_WATDOGTIMEO) 2927168404Spjd || (status & DC_ISR_RX_NOBUF)) { 2928168404Spjd int curpkts; 2929249643Smm curpkts = ifp->if_ipackets; 2930168404Spjd dc_rxeof(sc); 2931168404Spjd if (curpkts == ifp->if_ipackets) { 2932168404Spjd while(dc_rx_resync(sc)) 2933219089Spjd dc_rxeof(sc); 2934168404Spjd } 2935168404Spjd } 2936168404Spjd 2937168404Spjd if (status & DC_ISR_BUS_ERR) { 2938168404Spjd dc_reset(sc); 2939168404Spjd dc_init(sc); 2940168404Spjd } 2941168404Spjd } 2942168404Spjd 2943168404Spjd /* Re-enable interrupts. */ 2944168404Spjd CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2945168404Spjd 2946168404Spjd if (ifp->if_snd.ifq_head != NULL) 2947168404Spjd dc_start(ifp); 2948168404Spjd 2949168404Spjd#ifdef DEVICE_POLLING 2950168404Spjddone: 2951168404Spjd#endif /* DEVICE_POLLING */ 2952168404Spjd 2953168404Spjd DC_UNLOCK(sc); 2954168404Spjd 2955168404Spjd return; 2956168404Spjd} 2957168404Spjd 2958209962Smm/* 2959168404Spjd * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2960168404Spjd * pointers to the fragment pointers. 2961168404Spjd */ 2962185029Spjdstatic int dc_encap(sc, m_head, txidx) 2963185029Spjd struct dc_softc *sc; 2964168404Spjd struct mbuf *m_head; 2965185029Spjd u_int32_t *txidx; 2966185029Spjd{ 2967185029Spjd struct dc_desc *f = NULL; 2968206796Spjd struct mbuf *m; 2969168404Spjd int frag, cur, cnt = 0; 2970168404Spjd 2971168404Spjd /* 2972209101Smm * Start packing the mbufs in this chain into 2973243674Smm * the fragment pointers. Stop when we run out 2974243674Smm * of fragments or hit the end of the mbuf chain. 2975185029Spjd */ 2976185029Spjd m = m_head; 2977243674Smm cur = frag = *txidx; 2978185029Spjd 2979185029Spjd for (m = m_head; m != NULL; m = m->m_next) { 2980168404Spjd if (m->m_len != 0) { 2981185029Spjd if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2982243674Smm if (*txidx != sc->dc_cdata.dc_tx_prod && 2983243674Smm frag == (DC_TX_LIST_CNT - 1)) 2984243674Smm return(ENOBUFS); 2985168404Spjd } 2986219089Spjd if ((DC_TX_LIST_CNT - 2987219089Spjd (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2988219089Spjd return(ENOBUFS); 2989219089Spjd 2990219089Spjd f = &sc->dc_ldata->dc_tx_list[frag]; 2991219089Spjd f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2992219089Spjd if (cnt == 0) { 2993219089Spjd f->dc_status = 0; 2994219089Spjd f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2995219089Spjd } else 2996168404Spjd f->dc_status = DC_TXSTAT_OWN; 2997168404Spjd f->dc_data = vtophys(mtod(m, vm_offset_t)); 2998168404Spjd cur = frag; 2999168404Spjd DC_INC(frag, DC_TX_LIST_CNT); 3000248547Smm cnt++; 3001248547Smm } 3002168404Spjd } 3003248547Smm 3004168404Spjd if (m != NULL) 3005168404Spjd return(ENOBUFS); 3006168404Spjd 3007168404Spjd sc->dc_cdata.dc_tx_cnt += cnt; 3008168404Spjd sc->dc_cdata.dc_tx_chain[cur] = m_head; 3009168404Spjd sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3010168404Spjd if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3011219089Spjd sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3012219089Spjd if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3013219089Spjd sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3014168404Spjd if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3015219089Spjd sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3016168404Spjd sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3017168404Spjd *txidx = frag; 3018168404Spjd 3019168404Spjd return(0); 3020168404Spjd} 3021168404Spjd 3022168404Spjd/* 3023168404Spjd * Coalesce an mbuf chain into a single mbuf cluster buffer. 3024168404Spjd * Needed for some really badly behaved chips that just can't 3025168404Spjd * do scatter/gather correctly. 3026168404Spjd */ 3027168404Spjdstatic int dc_coal(sc, m_head) 3028168404Spjd struct dc_softc *sc; 3029168404Spjd struct mbuf **m_head; 3030168404Spjd{ 3031168404Spjd struct mbuf *m_new, *m; 3032168404Spjd 3033168404Spjd m = *m_head; 3034168404Spjd MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3035168404Spjd if (m_new == NULL) 3036168404Spjd return(ENOBUFS); 3037168404Spjd if (m->m_pkthdr.len > MHLEN) { 3038168404Spjd MCLGET(m_new, M_DONTWAIT); 3039168404Spjd if (!(m_new->m_flags & M_EXT)) { 3040168404Spjd m_freem(m_new); 3041168404Spjd return(ENOBUFS); 3042168404Spjd } 3043168404Spjd } 3044168404Spjd m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 3045168404Spjd m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 3046168404Spjd m_freem(m); 3047168404Spjd *m_head = m_new; 3048168404Spjd 3049168404Spjd return(0); 3050168404Spjd} 3051168404Spjd 3052168404Spjd/* 3053168404Spjd * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3054168404Spjd * to the mbuf data regions directly in the transmit lists. We also save a 3055168404Spjd * copy of the pointers since the transmit list fragment pointers are 3056168404Spjd * physical addresses. 3057168404Spjd */ 3058168404Spjd 3059168404Spjdstatic void dc_start(ifp) 3060168404Spjd struct ifnet *ifp; 3061168404Spjd{ 3062168404Spjd struct dc_softc *sc; 3063168404Spjd struct mbuf *m_head = NULL; 3064168404Spjd int idx; 3065168404Spjd 3066168404Spjd sc = ifp->if_softc; 3067168404Spjd 3068168404Spjd DC_LOCK(sc); 3069168404Spjd 3070168404Spjd if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3071168404Spjd DC_UNLOCK(sc); 3072168404Spjd return; 3073168404Spjd } 3074168404Spjd 3075168404Spjd if (ifp->if_flags & IFF_OACTIVE) { 3076168404Spjd DC_UNLOCK(sc); 3077168404Spjd return; 3078168404Spjd } 3079168404Spjd 3080168404Spjd idx = sc->dc_cdata.dc_tx_prod; 3081168404Spjd 3082168404Spjd while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3083168404Spjd IF_DEQUEUE(&ifp->if_snd, m_head); 3084168404Spjd if (m_head == NULL) 3085247406Smm break; 3086247406Smm 3087247406Smm if (sc->dc_flags & DC_TX_COALESCE && 3088168404Spjd (m_head->m_next != NULL || 3089168404Spjd sc->dc_flags & DC_TX_ALIGN)) { 3090248369Smm if (dc_coal(sc, &m_head)) { 3091168404Spjd IF_PREPEND(&ifp->if_snd, m_head); 3092185029Spjd ifp->if_flags |= IFF_OACTIVE; 3093229578Smm break; 3094168404Spjd } 3095168404Spjd } 3096219089Spjd 3097219089Spjd if (dc_encap(sc, m_head, &idx)) { 3098168404Spjd IF_PREPEND(&ifp->if_snd, m_head); 3099168404Spjd ifp->if_flags |= IFF_OACTIVE; 3100168404Spjd break; 3101168404Spjd } 3102168404Spjd 3103168404Spjd /* 3104168404Spjd * If there's a BPF listener, bounce a copy of this frame 3105168404Spjd * to him. 3106168404Spjd */ 3107168404Spjd if (ifp->if_bpf) 3108168404Spjd bpf_mtap(ifp, m_head); 3109168404Spjd 3110168404Spjd if (sc->dc_flags & DC_TX_ONE) { 3111168404Spjd ifp->if_flags |= IFF_OACTIVE; 3112168404Spjd break; 3113168404Spjd } 3114168404Spjd } 3115168404Spjd 3116168404Spjd /* Transmit */ 3117168404Spjd sc->dc_cdata.dc_tx_prod = idx; 3118168404Spjd if (!(sc->dc_flags & DC_TX_POLL)) 3119168404Spjd CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3120209962Smm 3121168404Spjd /* 3122168404Spjd * Set a timeout in case the chip goes out to lunch. 3123168404Spjd */ 3124168404Spjd ifp->if_timer = 5; 3125168404Spjd 3126168404Spjd DC_UNLOCK(sc); 3127168404Spjd 3128168404Spjd return; 3129168404Spjd} 3130168404Spjd 3131168404Spjdstatic void dc_init(xsc) 3132168404Spjd void *xsc; 3133168404Spjd{ 3134168404Spjd struct dc_softc *sc = xsc; 3135168404Spjd struct ifnet *ifp = &sc->arpcom.ac_if; 3136168404Spjd struct mii_data *mii; 3137168404Spjd 3138168404Spjd DC_LOCK(sc); 3139168404Spjd 3140168404Spjd mii = device_get_softc(sc->dc_miibus); 3141168404Spjd 3142168404Spjd /* 3143168404Spjd * Cancel pending I/O and free all RX/TX buffers. 3144168404Spjd */ 3145168404Spjd dc_stop(sc); 3146168404Spjd dc_reset(sc); 3147168404Spjd 3148168404Spjd /* 3149168404Spjd * Set cache alignment and burst length. 3150168404Spjd */ 3151219089Spjd if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3152168404Spjd CSR_WRITE_4(sc, DC_BUSCTL, 0); 3153168404Spjd else 3154168404Spjd CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3155168404Spjd /* 3156168404Spjd * Evenly share the bus between receive and transmit process. 3157168404Spjd */ 3158185029Spjd if (DC_IS_INTEL(sc)) 3159185029Spjd DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3160252140Sdelphij if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3161252140Sdelphij DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3162168404Spjd } else { 3163168404Spjd DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3164168404Spjd } 3165168404Spjd if (sc->dc_flags & DC_TX_POLL) 3166168404Spjd DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3167168404Spjd switch(sc->dc_cachesize) { 3168168404Spjd case 32: 3169168404Spjd DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3170168404Spjd break; 3171168404Spjd case 16: 3172168404Spjd DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3173185029Spjd break; 3174248369Smm case 8: 3175208373Smm DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3176168404Spjd break; 3177168404Spjd case 0: 3178168404Spjd default: 3179168404Spjd DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3180168404Spjd break; 3181168404Spjd } 3182168404Spjd 3183168404Spjd if (sc->dc_flags & DC_TX_STORENFWD) 3184219089Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3185168404Spjd else { 3186168404Spjd if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3187168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3188168404Spjd } else { 3189168404Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3190219089Spjd DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3191168404Spjd } 3192168404Spjd } 3193168404Spjd 3194168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3195168404Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3196168404Spjd 3197168404Spjd if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3198168404Spjd /* 3199168404Spjd * The app notes for the 98713 and 98715A say that 3200185029Spjd * in order to have the chips operate properly, a magic 3201185029Spjd * number must be written to CSR16. Macronix does not 3202252140Sdelphij * document the meaning of these bits so there's no way 3203252140Sdelphij * to know exactly what they do. The 98713 has a magic 3204168404Spjd * number all its own; the rest all use a different one. 3205168404Spjd */ 3206168404Spjd DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3207168404Spjd if (sc->dc_type == DC_TYPE_98713) 3208168404Spjd DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3209168404Spjd else 3210243674Smm DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3211168404Spjd } 3212168404Spjd 3213168404Spjd if (DC_IS_XIRCOM(sc)) { 3214168404Spjd /* 3215168404Spjd * setup General Purpose Port mode and data so the tulip 3216168404Spjd * can talk to the MII. 3217168404Spjd */ 3218185029Spjd CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3219185029Spjd DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3220252140Sdelphij DELAY(10); 3221252140Sdelphij CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3222185029Spjd DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3223168404Spjd DELAY(10); 3224168404Spjd } 3225168404Spjd 3226168404Spjd DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3227168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3228168404Spjd 3229168404Spjd /* Init circular RX list. */ 3230168404Spjd if (dc_list_rx_init(sc) == ENOBUFS) { 3231219089Spjd printf("dc%d: initialization failed: no " 3232219089Spjd "memory for rx buffers\n", sc->dc_unit); 3233168404Spjd dc_stop(sc); 3234168404Spjd DC_UNLOCK(sc); 3235219089Spjd return; 3236219089Spjd } 3237168404Spjd 3238168404Spjd /* 3239168404Spjd * Init tx descriptors. 3240168404Spjd */ 3241168404Spjd dc_list_tx_init(sc); 3242168404Spjd 3243168404Spjd /* 3244168404Spjd * Load the address of the RX list. 3245185029Spjd */ 3246185029Spjd CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3247208373Smm CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3248185029Spjd 3249185029Spjd /* 3250185029Spjd * Enable interrupts. 3251185029Spjd */ 3252185029Spjd#ifdef DEVICE_POLLING 3253185029Spjd /* 3254185029Spjd * ... but only if we are not polling, and make sure they are off in 3255185029Spjd * the case of polling. Some cards (e.g. fxp) turn interrupts on 3256185029Spjd * after a reset. 3257168404Spjd */ 3258168404Spjd if (ifp->if_ipending & IFF_POLLING) 3259252749Sdelphij CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3260252749Sdelphij else 3261252749Sdelphij#endif 3262252749Sdelphij CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3263168404Spjd CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3264219089Spjd 3265219089Spjd /* Enable transmitter. */ 3266168404Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3267168404Spjd 3268168404Spjd /* 3269168404Spjd * If this is an Intel 21143 and we're not using the 3270229568Smm * MII port, program the LED control pins so we get 3271229568Smm * link and activity indications. 3272229568Smm */ 3273168404Spjd if (sc->dc_flags & DC_TULIP_LEDS) { 3274208373Smm CSR_WRITE_4(sc, DC_WATCHDOG, 3275185029Spjd DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3276185029Spjd CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3277185029Spjd } 3278185029Spjd 3279185029Spjd /* 3280185029Spjd * Load the RX/multicast filter. We do this sort of late 3281185029Spjd * because the filter programming scheme on the 21143 and 3282208373Smm * some clones requires DMAing a setup frame via the TX 3283185029Spjd * engine, and we need the transmitter enabled for that. 3284185029Spjd */ 3285208373Smm dc_setfilt(sc); 3286208373Smm 3287185029Spjd /* Enable receiver. */ 3288185029Spjd DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3289185029Spjd CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3290185029Spjd 3291185029Spjd mii_mediachg(mii); 3292185029Spjd dc_setcfg(sc, sc->dc_if_media); 3293185029Spjd 3294185029Spjd ifp->if_flags |= IFF_RUNNING; 3295185029Spjd ifp->if_flags &= ~IFF_OACTIVE; 3296185029Spjd 3297185029Spjd /* Don't start the ticker if this is a homePNA link. */ 3298185029Spjd if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3299252140Sdelphij sc->dc_link = 1; 3300185029Spjd else { 3301248369Smm if (sc->dc_flags & DC_21143_NWAY) 3302248369Smm callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3303248369Smm else 3304248369Smm callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3305185029Spjd } 3306185029Spjd 3307185029Spjd#ifdef SRM_MEDIA 3308252140Sdelphij if(sc->dc_srm_media) { 3309252140Sdelphij struct ifreq ifr; 3310185029Spjd 3311252140Sdelphij ifr.ifr_media = sc->dc_srm_media; 3312252140Sdelphij ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3313252140Sdelphij sc->dc_srm_media = 0; 3314252140Sdelphij } 3315252140Sdelphij#endif 3316252140Sdelphij DC_UNLOCK(sc); 3317252140Sdelphij return; 3318252140Sdelphij} 3319252140Sdelphij 3320252140Sdelphij/* 3321252140Sdelphij * Set media options. 3322252140Sdelphij */ 3323252140Sdelphijstatic int dc_ifmedia_upd(ifp) 3324252140Sdelphij struct ifnet *ifp; 3325252140Sdelphij{ 3326252140Sdelphij struct dc_softc *sc; 3327252140Sdelphij struct mii_data *mii; 3328252140Sdelphij struct ifmedia *ifm; 3329185029Spjd 3330185029Spjd sc = ifp->if_softc; 3331252140Sdelphij mii = device_get_softc(sc->dc_miibus); 3332252140Sdelphij mii_mediachg(mii); 3333185029Spjd ifm = &mii->mii_media; 3334185029Spjd 3335185029Spjd if (DC_IS_DAVICOM(sc) && 3336185029Spjd IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3337185029Spjd dc_setcfg(sc, ifm->ifm_media); 3338185029Spjd else 3339185029Spjd sc->dc_link = 0; 3340185029Spjd 3341185029Spjd return(0); 3342185029Spjd} 3343185029Spjd 3344185029Spjd/* 3345185029Spjd * Report current media status. 3346185029Spjd */ 3347185029Spjdstatic void dc_ifmedia_sts(ifp, ifmr) 3348185029Spjd struct ifnet *ifp; 3349185029Spjd struct ifmediareq *ifmr; 3350185029Spjd{ 3351185029Spjd struct dc_softc *sc; 3352208373Smm struct mii_data *mii; 3353208373Smm struct ifmedia *ifm; 3354208373Smm 3355208373Smm sc = ifp->if_softc; 3356208373Smm mii = device_get_softc(sc->dc_miibus); 3357208373Smm mii_pollstat(mii); 3358208373Smm ifm = &mii->mii_media; 3359208373Smm if (DC_IS_DAVICOM(sc)) { 3360185029Spjd if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3361185029Spjd ifmr->ifm_active = ifm->ifm_media; 3362168404Spjd ifmr->ifm_status = 0; 3363185029Spjd return; 3364168404Spjd } 3365168404Spjd } 3366168404Spjd ifmr->ifm_active = mii->mii_media_active; 3367168404Spjd ifmr->ifm_status = mii->mii_media_status; 3368168404Spjd 3369168404Spjd return; 3370168404Spjd} 3371168404Spjd 3372168404Spjdstatic int dc_ioctl(ifp, command, data) 3373168404Spjd struct ifnet *ifp; 3374168404Spjd u_long command; 3375168404Spjd caddr_t data; 3376168404Spjd{ 3377168404Spjd struct dc_softc *sc = ifp->if_softc; 3378168404Spjd struct ifreq *ifr = (struct ifreq *) data; 3379168404Spjd struct mii_data *mii; 3380219089Spjd int error = 0; 3381219089Spjd 3382219089Spjd DC_LOCK(sc); 3383168404Spjd 3384168404Spjd switch(command) { 3385168404Spjd case SIOCSIFADDR: 3386168404Spjd case SIOCGIFADDR: 3387168404Spjd case SIOCSIFMTU: 3388252142Sdelphij error = ether_ioctl(ifp, command, data); 3389252142Sdelphij break; 3390252142Sdelphij case SIOCSIFFLAGS: 3391252142Sdelphij if (ifp->if_flags & IFF_UP) { 3392252142Sdelphij if (ifp->if_flags & IFF_RUNNING && 3393252142Sdelphij ifp->if_flags & IFF_PROMISC && 3394252142Sdelphij !(sc->dc_if_flags & IFF_PROMISC)) { 3395252142Sdelphij dc_setfilt(sc); 3396252142Sdelphij } else if (ifp->if_flags & IFF_RUNNING && 3397252142Sdelphij !(ifp->if_flags & IFF_PROMISC) && 3398252142Sdelphij sc->dc_if_flags & IFF_PROMISC) { 3399252142Sdelphij dc_setfilt(sc); 3400252142Sdelphij } else if (!(ifp->if_flags & IFF_RUNNING)) { 3401252142Sdelphij sc->dc_txthresh = 0; 3402252142Sdelphij dc_init(sc); 3403252142Sdelphij } 3404252142Sdelphij } else { 3405252142Sdelphij if (ifp->if_flags & IFF_RUNNING) 3406252142Sdelphij dc_stop(sc); 3407252142Sdelphij } 3408252142Sdelphij sc->dc_if_flags = ifp->if_flags; 3409252142Sdelphij error = 0; 3410252142Sdelphij break; 3411252142Sdelphij case SIOCADDMULTI: 3412252142Sdelphij case SIOCDELMULTI: 3413252142Sdelphij dc_setfilt(sc); 3414252142Sdelphij error = 0; 3415252142Sdelphij break; 3416168404Spjd case SIOCGIFMEDIA: 3417168404Spjd case SIOCSIFMEDIA: 3418168404Spjd mii = device_get_softc(sc->dc_miibus); 3419168404Spjd error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3420168404Spjd#ifdef SRM_MEDIA 3421168404Spjd if (sc->dc_srm_media) 3422168404Spjd sc->dc_srm_media = 0; 3423168404Spjd#endif 3424168404Spjd break; 3425168404Spjd default: 3426205231Skmacy error = EINVAL; 3427205231Skmacy break; 3428206796Spjd } 3429219089Spjd 3430168404Spjd DC_UNLOCK(sc); 3431168404Spjd 3432168404Spjd return(error); 3433168404Spjd} 3434168404Spjd 3435168404Spjdstatic void dc_watchdog(ifp) 3436219089Spjd struct ifnet *ifp; 3437168404Spjd{ 3438185029Spjd struct dc_softc *sc; 3439185029Spjd 3440185029Spjd sc = ifp->if_softc; 3441185029Spjd 3442185029Spjd DC_LOCK(sc); 3443185029Spjd 3444185029Spjd ifp->if_oerrors++; 3445219089Spjd printf("dc%d: watchdog timeout\n", sc->dc_unit); 3446185029Spjd 3447185029Spjd dc_stop(sc); 3448168404Spjd dc_reset(sc); 3449168404Spjd dc_init(sc); 3450168404Spjd 3451219089Spjd if (ifp->if_snd.ifq_head != NULL) 3452219089Spjd dc_start(ifp); 3453168404Spjd 3454168404Spjd DC_UNLOCK(sc); 3455168404Spjd 3456168404Spjd return; 3457168404Spjd} 3458168404Spjd 3459168404Spjd/* 3460168404Spjd * Stop the adapter and free any mbufs allocated to the 3461168404Spjd * RX and TX lists. 3462168404Spjd */ 3463168404Spjdstatic void dc_stop(sc) 3464168404Spjd struct dc_softc *sc; 3465168404Spjd{ 3466168404Spjd register int i; 3467168404Spjd struct ifnet *ifp; 3468168404Spjd 3469168404Spjd DC_LOCK(sc); 3470168404Spjd 3471168404Spjd ifp = &sc->arpcom.ac_if; 3472219089Spjd ifp->if_timer = 0; 3473168404Spjd 3474168404Spjd callout_stop(&sc->dc_stat_ch); 3475168404Spjd 3476168404Spjd ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3477168404Spjd#ifdef DEVICE_POLLING 3478205231Skmacy ether_poll_deregister(ifp); 3479205231Skmacy#endif 3480205231Skmacy 3481205231Skmacy DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3482168404Spjd CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3483168404Spjd CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3484168404Spjd CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3485185029Spjd sc->dc_link = 0; 3486185029Spjd 3487168404Spjd /* 3488205231Skmacy * Free data in the RX lists. 3489205231Skmacy */ 3490168404Spjd for (i = 0; i < DC_RX_LIST_CNT; i++) { 3491168404Spjd if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3492219089Spjd m_freem(sc->dc_cdata.dc_rx_chain[i]); 3493168404Spjd sc->dc_cdata.dc_rx_chain[i] = NULL; 3494168404Spjd } 3495168404Spjd } 3496168404Spjd bzero((char *)&sc->dc_ldata->dc_rx_list, 3497168404Spjd sizeof(sc->dc_ldata->dc_rx_list)); 3498219089Spjd 3499168404Spjd /* 3500168404Spjd * Free the TX list buffers. 3501168404Spjd */ 3502168404Spjd for (i = 0; i < DC_TX_LIST_CNT; i++) { 3503168404Spjd if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3504252749Sdelphij if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3505252749Sdelphij DC_TXCTL_SETUP) { 3506168404Spjd sc->dc_cdata.dc_tx_chain[i] = NULL; 3507185029Spjd continue; 3508168404Spjd } 3509168404Spjd m_freem(sc->dc_cdata.dc_tx_chain[i]); 3510168404Spjd sc->dc_cdata.dc_tx_chain[i] = NULL; 3511168404Spjd } 3512185029Spjd } 3513219089Spjd 3514185029Spjd bzero((char *)&sc->dc_ldata->dc_tx_list, 3515185029Spjd sizeof(sc->dc_ldata->dc_tx_list)); 3516168404Spjd 3517219089Spjd DC_UNLOCK(sc); 3518219089Spjd 3519219089Spjd return; 3520219089Spjd} 3521219089Spjd 3522219089Spjd/* 3523219089Spjd * Stop all chip I/O so that the kernel's probe routines don't 3524185029Spjd * get confused by errant DMAs when rebooting. 3525185029Spjd */ 3526168404Spjdstatic void dc_shutdown(dev) 3527168404Spjd device_t dev; 3528168404Spjd{ 3529168404Spjd struct dc_softc *sc; 3530168404Spjd 3531168404Spjd sc = device_get_softc(dev); 3532208373Smm 3533208373Smm dc_stop(sc); 3534208373Smm 3535219089Spjd return; 3536219089Spjd} 3537168404Spjd