if_dc.c revision 87902
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/dc/if_dc.c 87902 2001-12-14 17:56:12Z luigi $ 33 */ 34 35/* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * Conexant LANfinity (www.conexant.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64/* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92#include <sys/param.h> 93#include <sys/systm.h> 94#include <sys/sockio.h> 95#include <sys/mbuf.h> 96#include <sys/malloc.h> 97#include <sys/kernel.h> 98#include <sys/socket.h> 99#include <sys/sysctl.h> 100 101#include <net/if.h> 102#include <net/if_arp.h> 103#include <net/ethernet.h> 104#include <net/if_dl.h> 105#include <net/if_media.h> 106 107#include <net/bpf.h> 108 109#include <vm/vm.h> /* for vtophys */ 110#include <vm/pmap.h> /* for vtophys */ 111#include <machine/bus_pio.h> 112#include <machine/bus_memio.h> 113#include <machine/bus.h> 114#include <machine/resource.h> 115#include <sys/bus.h> 116#include <sys/rman.h> 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121#include <pci/pcireg.h> 122#include <pci/pcivar.h> 123 124#define DC_USEIOSPACE 125#ifdef __alpha__ 126#define SRM_MEDIA 127#endif 128 129#include <pci/if_dcreg.h> 130 131MODULE_DEPEND(dc, miibus, 1, 1, 1); 132 133/* "controller miibus0" required. See GENERIC if you get errors here. */ 134#include "miibus_if.h" 135 136#ifndef lint 137static const char rcsid[] = 138 "$FreeBSD: head/sys/dev/dc/if_dc.c 87902 2001-12-14 17:56:12Z luigi $"; 139#endif 140 141/* 142 * Various supported device vendors/types and their names. 143 */ 144static struct dc_type dc_devs[] = { 145 { DC_VENDORID_DEC, DC_DEVICEID_21143, 146 "Intel 21143 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 148 "Davicom DM9100 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 150 "Davicom DM9102 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102A 10/100BaseTX" }, 153 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 154 "ADMtek AL981 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 156 "ADMtek AN985 10/100BaseTX" }, 157 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 158 "ASIX AX88140A 10/100BaseTX" }, 159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160 "ASIX AX88141 10/100BaseTX" }, 161 { DC_VENDORID_MX, DC_DEVICEID_98713, 162 "Macronix 98713 10/100BaseTX" }, 163 { DC_VENDORID_MX, DC_DEVICEID_98713, 164 "Macronix 98713A 10/100BaseTX" }, 165 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 166 "Compex RL100-TX 10/100BaseTX" }, 167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168 "Compex RL100-TX 10/100BaseTX" }, 169 { DC_VENDORID_MX, DC_DEVICEID_987x5, 170 "Macronix 98715/98715A 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98715AEC-C 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98725 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_98727, 176 "Macronix 98727/98732 10/100BaseTX" }, 177 { DC_VENDORID_LO, DC_DEVICEID_82C115, 178 "LC82C115 PNIC II 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C168, 180 "82c168 PNIC 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C168, 182 "82c169 PNIC 10/100BaseTX" }, 183 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 184 "Accton EN1217 10/100BaseTX" }, 185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 186 "Accton EN2242 MiniPCI 10/100BaseTX" }, 187 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 188 "Xircom X3201 10/100BaseTX" }, 189 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 190 "Abocom FE2500 10/100BaseTX" }, 191 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 192 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 193 { 0, 0, NULL } 194}; 195 196static int dc_probe __P((device_t)); 197static int dc_attach __P((device_t)); 198static int dc_detach __P((device_t)); 199static void dc_acpi __P((device_t)); 200static struct dc_type *dc_devtype __P((device_t)); 201static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 202static int dc_encap __P((struct dc_softc *, struct mbuf *, 203 u_int32_t *)); 204static int dc_coal __P((struct dc_softc *, struct mbuf **)); 205static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 206static int dc_rx_resync __P((struct dc_softc *)); 207static void dc_rxeof __P((struct dc_softc *)); 208static void dc_txeof __P((struct dc_softc *)); 209static void dc_tick __P((void *)); 210static void dc_tx_underrun __P((struct dc_softc *)); 211static void dc_intr __P((void *)); 212static void dc_start __P((struct ifnet *)); 213static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 214static void dc_init __P((void *)); 215static void dc_stop __P((struct dc_softc *)); 216static void dc_watchdog __P((struct ifnet *)); 217static void dc_shutdown __P((device_t)); 218static int dc_ifmedia_upd __P((struct ifnet *)); 219static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 220 221static void dc_delay __P((struct dc_softc *)); 222static void dc_eeprom_idle __P((struct dc_softc *)); 223static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 224static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 225static void dc_eeprom_getword_pnic 226 __P((struct dc_softc *, int, u_int16_t *)); 227static void dc_eeprom_getword_xircom 228 __P((struct dc_softc *, int, u_int16_t *)); 229static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 230 int, int)); 231 232static void dc_mii_writebit __P((struct dc_softc *, int)); 233static int dc_mii_readbit __P((struct dc_softc *)); 234static void dc_mii_sync __P((struct dc_softc *)); 235static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 236static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 237static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 238static int dc_miibus_readreg __P((device_t, int, int)); 239static int dc_miibus_writereg __P((device_t, int, int, int)); 240static void dc_miibus_statchg __P((device_t)); 241static void dc_miibus_mediainit __P((device_t)); 242 243static void dc_setcfg __P((struct dc_softc *, int)); 244static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 245static u_int32_t dc_crc_be __P((caddr_t)); 246static void dc_setfilt_21143 __P((struct dc_softc *)); 247static void dc_setfilt_asix __P((struct dc_softc *)); 248static void dc_setfilt_admtek __P((struct dc_softc *)); 249static void dc_setfilt_xircom __P((struct dc_softc *)); 250 251static void dc_setfilt __P((struct dc_softc *)); 252 253static void dc_reset __P((struct dc_softc *)); 254static int dc_list_rx_init __P((struct dc_softc *)); 255static int dc_list_tx_init __P((struct dc_softc *)); 256 257static void dc_parse_21143_srom __P((struct dc_softc *)); 258static void dc_decode_leaf_sia __P((struct dc_softc *, 259 struct dc_eblock_sia *)); 260static void dc_decode_leaf_mii __P((struct dc_softc *, 261 struct dc_eblock_mii *)); 262static void dc_decode_leaf_sym __P((struct dc_softc *, 263 struct dc_eblock_sym *)); 264static void dc_apply_fixup __P((struct dc_softc *, int)); 265 266#ifdef DC_USEIOSPACE 267#define DC_RES SYS_RES_IOPORT 268#define DC_RID DC_PCI_CFBIO 269#else 270#define DC_RES SYS_RES_MEMORY 271#define DC_RID DC_PCI_CFBMA 272#endif 273 274static device_method_t dc_methods[] = { 275 /* Device interface */ 276 DEVMETHOD(device_probe, dc_probe), 277 DEVMETHOD(device_attach, dc_attach), 278 DEVMETHOD(device_detach, dc_detach), 279 DEVMETHOD(device_shutdown, dc_shutdown), 280 281 /* bus interface */ 282 DEVMETHOD(bus_print_child, bus_generic_print_child), 283 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 284 285 /* MII interface */ 286 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 287 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 288 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 289 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 290 291 { 0, 0 } 292}; 293 294static driver_t dc_driver = { 295 "dc", 296 dc_methods, 297 sizeof(struct dc_softc) 298}; 299 300static devclass_t dc_devclass; 301#ifdef __i386__ 302static int dc_quick=1; 303SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 304 &dc_quick,0,"do not mdevget in dc driver"); 305#endif 306 307DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 308DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 309DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 310 311#define DC_SETBIT(sc, reg, x) \ 312 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 313 314#define DC_CLRBIT(sc, reg, x) \ 315 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 316 317#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 318#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 319 320#define IS_MPSAFE 0 321 322static void dc_delay(sc) 323 struct dc_softc *sc; 324{ 325 int idx; 326 327 for (idx = (300 / 33) + 1; idx > 0; idx--) 328 CSR_READ_4(sc, DC_BUSCTL); 329} 330 331static void dc_eeprom_idle(sc) 332 struct dc_softc *sc; 333{ 334 register int i; 335 336 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 337 dc_delay(sc); 338 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 339 dc_delay(sc); 340 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 341 dc_delay(sc); 342 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 343 dc_delay(sc); 344 345 for (i = 0; i < 25; i++) { 346 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 347 dc_delay(sc); 348 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 349 dc_delay(sc); 350 } 351 352 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 353 dc_delay(sc); 354 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 355 dc_delay(sc); 356 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 357 358 return; 359} 360 361/* 362 * Send a read command and address to the EEPROM, check for ACK. 363 */ 364static void dc_eeprom_putbyte(sc, addr) 365 struct dc_softc *sc; 366 int addr; 367{ 368 register int d, i; 369 370 /* 371 * The AN985 has a 93C66 EEPROM on it instead of 372 * a 93C46. It uses a different bit sequence for 373 * specifying the "read" opcode. 374 */ 375 if (DC_IS_CENTAUR(sc) || DC_IS_CONEXANT(sc)) 376 d = addr | (DC_EECMD_READ << 2); 377 else 378 d = addr | DC_EECMD_READ; 379 380 /* 381 * Feed in each bit and strobe the clock. 382 */ 383 for (i = 0x400; i; i >>= 1) { 384 if (d & i) { 385 SIO_SET(DC_SIO_EE_DATAIN); 386 } else { 387 SIO_CLR(DC_SIO_EE_DATAIN); 388 } 389 dc_delay(sc); 390 SIO_SET(DC_SIO_EE_CLK); 391 dc_delay(sc); 392 SIO_CLR(DC_SIO_EE_CLK); 393 dc_delay(sc); 394 } 395 396 return; 397} 398 399/* 400 * Read a word of data stored in the EEPROM at address 'addr.' 401 * The PNIC 82c168/82c169 has its own non-standard way to read 402 * the EEPROM. 403 */ 404static void dc_eeprom_getword_pnic(sc, addr, dest) 405 struct dc_softc *sc; 406 int addr; 407 u_int16_t *dest; 408{ 409 register int i; 410 u_int32_t r; 411 412 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 413 414 for (i = 0; i < DC_TIMEOUT; i++) { 415 DELAY(1); 416 r = CSR_READ_4(sc, DC_SIO); 417 if (!(r & DC_PN_SIOCTL_BUSY)) { 418 *dest = (u_int16_t)(r & 0xFFFF); 419 return; 420 } 421 } 422 423 return; 424} 425 426/* 427 * Read a word of data stored in the EEPROM at address 'addr.' 428 * The Xircom X3201 has its own non-standard way to read 429 * the EEPROM, too. 430 */ 431static void dc_eeprom_getword_xircom(sc, addr, dest) 432 struct dc_softc *sc; 433 int addr; 434 u_int16_t *dest; 435{ 436 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 437 438 addr *= 2; 439 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 440 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 441 addr += 1; 442 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 443 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 444 445 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 446 return; 447} 448 449/* 450 * Read a word of data stored in the EEPROM at address 'addr.' 451 */ 452static void dc_eeprom_getword(sc, addr, dest) 453 struct dc_softc *sc; 454 int addr; 455 u_int16_t *dest; 456{ 457 register int i; 458 u_int16_t word = 0; 459 460 /* Force EEPROM to idle state. */ 461 dc_eeprom_idle(sc); 462 463 /* Enter EEPROM access mode. */ 464 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 465 dc_delay(sc); 466 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 467 dc_delay(sc); 468 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 469 dc_delay(sc); 470 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 471 dc_delay(sc); 472 473 /* 474 * Send address of word we want to read. 475 */ 476 dc_eeprom_putbyte(sc, addr); 477 478 /* 479 * Start reading bits from EEPROM. 480 */ 481 for (i = 0x8000; i; i >>= 1) { 482 SIO_SET(DC_SIO_EE_CLK); 483 dc_delay(sc); 484 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 485 word |= i; 486 dc_delay(sc); 487 SIO_CLR(DC_SIO_EE_CLK); 488 dc_delay(sc); 489 } 490 491 /* Turn off EEPROM access mode. */ 492 dc_eeprom_idle(sc); 493 494 *dest = word; 495 496 return; 497} 498 499/* 500 * Read a sequence of words from the EEPROM. 501 */ 502static void dc_read_eeprom(sc, dest, off, cnt, swap) 503 struct dc_softc *sc; 504 caddr_t dest; 505 int off; 506 int cnt; 507 int swap; 508{ 509 int i; 510 u_int16_t word = 0, *ptr; 511 512 for (i = 0; i < cnt; i++) { 513 if (DC_IS_PNIC(sc)) 514 dc_eeprom_getword_pnic(sc, off + i, &word); 515 else if (DC_IS_XIRCOM(sc)) 516 dc_eeprom_getword_xircom(sc, off + i, &word); 517 else 518 dc_eeprom_getword(sc, off + i, &word); 519 ptr = (u_int16_t *)(dest + (i * 2)); 520 if (swap) 521 *ptr = ntohs(word); 522 else 523 *ptr = word; 524 } 525 526 return; 527} 528 529/* 530 * The following two routines are taken from the Macronix 98713 531 * Application Notes pp.19-21. 532 */ 533/* 534 * Write a bit to the MII bus. 535 */ 536static void dc_mii_writebit(sc, bit) 537 struct dc_softc *sc; 538 int bit; 539{ 540 if (bit) 541 CSR_WRITE_4(sc, DC_SIO, 542 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 543 else 544 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 545 546 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 547 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 548 549 return; 550} 551 552/* 553 * Read a bit from the MII bus. 554 */ 555static int dc_mii_readbit(sc) 556 struct dc_softc *sc; 557{ 558 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 559 CSR_READ_4(sc, DC_SIO); 560 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 561 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 562 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 563 return(1); 564 565 return(0); 566} 567 568/* 569 * Sync the PHYs by setting data bit and strobing the clock 32 times. 570 */ 571static void dc_mii_sync(sc) 572 struct dc_softc *sc; 573{ 574 register int i; 575 576 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 577 578 for (i = 0; i < 32; i++) 579 dc_mii_writebit(sc, 1); 580 581 return; 582} 583 584/* 585 * Clock a series of bits through the MII. 586 */ 587static void dc_mii_send(sc, bits, cnt) 588 struct dc_softc *sc; 589 u_int32_t bits; 590 int cnt; 591{ 592 int i; 593 594 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 595 dc_mii_writebit(sc, bits & i); 596} 597 598/* 599 * Read an PHY register through the MII. 600 */ 601static int dc_mii_readreg(sc, frame) 602 struct dc_softc *sc; 603 struct dc_mii_frame *frame; 604 605{ 606 int i, ack; 607 608 DC_LOCK(sc); 609 610 /* 611 * Set up frame for RX. 612 */ 613 frame->mii_stdelim = DC_MII_STARTDELIM; 614 frame->mii_opcode = DC_MII_READOP; 615 frame->mii_turnaround = 0; 616 frame->mii_data = 0; 617 618 /* 619 * Sync the PHYs. 620 */ 621 dc_mii_sync(sc); 622 623 /* 624 * Send command/address info. 625 */ 626 dc_mii_send(sc, frame->mii_stdelim, 2); 627 dc_mii_send(sc, frame->mii_opcode, 2); 628 dc_mii_send(sc, frame->mii_phyaddr, 5); 629 dc_mii_send(sc, frame->mii_regaddr, 5); 630 631#ifdef notdef 632 /* Idle bit */ 633 dc_mii_writebit(sc, 1); 634 dc_mii_writebit(sc, 0); 635#endif 636 637 /* Check for ack */ 638 ack = dc_mii_readbit(sc); 639 640 /* 641 * Now try reading data bits. If the ack failed, we still 642 * need to clock through 16 cycles to keep the PHY(s) in sync. 643 */ 644 if (ack) { 645 for(i = 0; i < 16; i++) { 646 dc_mii_readbit(sc); 647 } 648 goto fail; 649 } 650 651 for (i = 0x8000; i; i >>= 1) { 652 if (!ack) { 653 if (dc_mii_readbit(sc)) 654 frame->mii_data |= i; 655 } 656 } 657 658fail: 659 660 dc_mii_writebit(sc, 0); 661 dc_mii_writebit(sc, 0); 662 663 DC_UNLOCK(sc); 664 665 if (ack) 666 return(1); 667 return(0); 668} 669 670/* 671 * Write to a PHY register through the MII. 672 */ 673static int dc_mii_writereg(sc, frame) 674 struct dc_softc *sc; 675 struct dc_mii_frame *frame; 676 677{ 678 DC_LOCK(sc); 679 /* 680 * Set up frame for TX. 681 */ 682 683 frame->mii_stdelim = DC_MII_STARTDELIM; 684 frame->mii_opcode = DC_MII_WRITEOP; 685 frame->mii_turnaround = DC_MII_TURNAROUND; 686 687 /* 688 * Sync the PHYs. 689 */ 690 dc_mii_sync(sc); 691 692 dc_mii_send(sc, frame->mii_stdelim, 2); 693 dc_mii_send(sc, frame->mii_opcode, 2); 694 dc_mii_send(sc, frame->mii_phyaddr, 5); 695 dc_mii_send(sc, frame->mii_regaddr, 5); 696 dc_mii_send(sc, frame->mii_turnaround, 2); 697 dc_mii_send(sc, frame->mii_data, 16); 698 699 /* Idle bit. */ 700 dc_mii_writebit(sc, 0); 701 dc_mii_writebit(sc, 0); 702 703 DC_UNLOCK(sc); 704 705 return(0); 706} 707 708static int dc_miibus_readreg(dev, phy, reg) 709 device_t dev; 710 int phy, reg; 711{ 712 struct dc_mii_frame frame; 713 struct dc_softc *sc; 714 int i, rval, phy_reg = 0; 715 716 sc = device_get_softc(dev); 717 bzero((char *)&frame, sizeof(frame)); 718 719 /* 720 * Note: both the AL981 and AN985 have internal PHYs, 721 * however the AL981 provides direct access to the PHY 722 * registers while the AN985 uses a serial MII interface. 723 * The AN985's MII interface is also buggy in that you 724 * can read from any MII address (0 to 31), but only address 1 725 * behaves normally. To deal with both cases, we pretend 726 * that the PHY is at MII address 1. 727 */ 728 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 729 return(0); 730 731 /* 732 * Note: the ukphy probes of the RS7112 report a PHY at 733 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 734 * so we only respond to correct one. 735 */ 736 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 737 return(0); 738 739 if (sc->dc_pmode != DC_PMODE_MII) { 740 if (phy == (MII_NPHY - 1)) { 741 switch(reg) { 742 case MII_BMSR: 743 /* 744 * Fake something to make the probe 745 * code think there's a PHY here. 746 */ 747 return(BMSR_MEDIAMASK); 748 break; 749 case MII_PHYIDR1: 750 if (DC_IS_PNIC(sc)) 751 return(DC_VENDORID_LO); 752 return(DC_VENDORID_DEC); 753 break; 754 case MII_PHYIDR2: 755 if (DC_IS_PNIC(sc)) 756 return(DC_DEVICEID_82C168); 757 return(DC_DEVICEID_21143); 758 break; 759 default: 760 return(0); 761 break; 762 } 763 } else 764 return(0); 765 } 766 767 if (DC_IS_PNIC(sc)) { 768 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 769 (phy << 23) | (reg << 18)); 770 for (i = 0; i < DC_TIMEOUT; i++) { 771 DELAY(1); 772 rval = CSR_READ_4(sc, DC_PN_MII); 773 if (!(rval & DC_PN_MII_BUSY)) { 774 rval &= 0xFFFF; 775 return(rval == 0xFFFF ? 0 : rval); 776 } 777 } 778 return(0); 779 } 780 781 if (DC_IS_COMET(sc)) { 782 switch(reg) { 783 case MII_BMCR: 784 phy_reg = DC_AL_BMCR; 785 break; 786 case MII_BMSR: 787 phy_reg = DC_AL_BMSR; 788 break; 789 case MII_PHYIDR1: 790 phy_reg = DC_AL_VENID; 791 break; 792 case MII_PHYIDR2: 793 phy_reg = DC_AL_DEVID; 794 break; 795 case MII_ANAR: 796 phy_reg = DC_AL_ANAR; 797 break; 798 case MII_ANLPAR: 799 phy_reg = DC_AL_LPAR; 800 break; 801 case MII_ANER: 802 phy_reg = DC_AL_ANER; 803 break; 804 default: 805 printf("dc%d: phy_read: bad phy register %x\n", 806 sc->dc_unit, reg); 807 return(0); 808 break; 809 } 810 811 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 812 813 if (rval == 0xFFFF) 814 return(0); 815 return(rval); 816 } 817 818 frame.mii_phyaddr = phy; 819 frame.mii_regaddr = reg; 820 if (sc->dc_type == DC_TYPE_98713) { 821 phy_reg = CSR_READ_4(sc, DC_NETCFG); 822 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 823 } 824 dc_mii_readreg(sc, &frame); 825 if (sc->dc_type == DC_TYPE_98713) 826 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 827 828 return(frame.mii_data); 829} 830 831static int dc_miibus_writereg(dev, phy, reg, data) 832 device_t dev; 833 int phy, reg, data; 834{ 835 struct dc_softc *sc; 836 struct dc_mii_frame frame; 837 int i, phy_reg = 0; 838 839 sc = device_get_softc(dev); 840 bzero((char *)&frame, sizeof(frame)); 841 842 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 843 return(0); 844 845 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 846 return(0); 847 848 if (DC_IS_PNIC(sc)) { 849 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 850 (phy << 23) | (reg << 10) | data); 851 for (i = 0; i < DC_TIMEOUT; i++) { 852 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 853 break; 854 } 855 return(0); 856 } 857 858 if (DC_IS_COMET(sc)) { 859 switch(reg) { 860 case MII_BMCR: 861 phy_reg = DC_AL_BMCR; 862 break; 863 case MII_BMSR: 864 phy_reg = DC_AL_BMSR; 865 break; 866 case MII_PHYIDR1: 867 phy_reg = DC_AL_VENID; 868 break; 869 case MII_PHYIDR2: 870 phy_reg = DC_AL_DEVID; 871 break; 872 case MII_ANAR: 873 phy_reg = DC_AL_ANAR; 874 break; 875 case MII_ANLPAR: 876 phy_reg = DC_AL_LPAR; 877 break; 878 case MII_ANER: 879 phy_reg = DC_AL_ANER; 880 break; 881 default: 882 printf("dc%d: phy_write: bad phy register %x\n", 883 sc->dc_unit, reg); 884 return(0); 885 break; 886 } 887 888 CSR_WRITE_4(sc, phy_reg, data); 889 return(0); 890 } 891 892 frame.mii_phyaddr = phy; 893 frame.mii_regaddr = reg; 894 frame.mii_data = data; 895 896 if (sc->dc_type == DC_TYPE_98713) { 897 phy_reg = CSR_READ_4(sc, DC_NETCFG); 898 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 899 } 900 dc_mii_writereg(sc, &frame); 901 if (sc->dc_type == DC_TYPE_98713) 902 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 903 904 return(0); 905} 906 907static void dc_miibus_statchg(dev) 908 device_t dev; 909{ 910 struct dc_softc *sc; 911 struct mii_data *mii; 912 struct ifmedia *ifm; 913 914 sc = device_get_softc(dev); 915 if (DC_IS_ADMTEK(sc)) 916 return; 917 918 mii = device_get_softc(sc->dc_miibus); 919 ifm = &mii->mii_media; 920 if (DC_IS_DAVICOM(sc) && 921 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 922 dc_setcfg(sc, ifm->ifm_media); 923 sc->dc_if_media = ifm->ifm_media; 924 } else { 925 dc_setcfg(sc, mii->mii_media_active); 926 sc->dc_if_media = mii->mii_media_active; 927 } 928 929 return; 930} 931 932/* 933 * Special support for DM9102A cards with HomePNA PHYs. Note: 934 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 935 * to be impossible to talk to the management interface of the DM9801 936 * PHY (its MDIO pin is not connected to anything). Consequently, 937 * the driver has to just 'know' about the additional mode and deal 938 * with it itself. *sigh* 939 */ 940static void dc_miibus_mediainit(dev) 941 device_t dev; 942{ 943 struct dc_softc *sc; 944 struct mii_data *mii; 945 struct ifmedia *ifm; 946 int rev; 947 948 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 949 950 sc = device_get_softc(dev); 951 mii = device_get_softc(sc->dc_miibus); 952 ifm = &mii->mii_media; 953 954 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 955 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 956 957 return; 958} 959 960#define DC_POLY 0xEDB88320 961#define DC_BITS_512 9 962#define DC_BITS_128 7 963#define DC_BITS_64 6 964 965static u_int32_t dc_crc_le(sc, addr) 966 struct dc_softc *sc; 967 caddr_t addr; 968{ 969 u_int32_t idx, bit, data, crc; 970 971 /* Compute CRC for the address value. */ 972 crc = 0xFFFFFFFF; /* initial value */ 973 974 for (idx = 0; idx < 6; idx++) { 975 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 976 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 977 } 978 979 /* 980 * The hash table on the PNIC II and the MX98715AEC-C/D/E 981 * chips is only 128 bits wide. 982 */ 983 if (sc->dc_flags & DC_128BIT_HASH) 984 return (crc & ((1 << DC_BITS_128) - 1)); 985 986 /* The hash table on the MX98715BEC is only 64 bits wide. */ 987 if (sc->dc_flags & DC_64BIT_HASH) 988 return (crc & ((1 << DC_BITS_64) - 1)); 989 990 /* Xircom's hash filtering table is different (read: weird) */ 991 /* Xircom uses the LEAST significant bits */ 992 if (DC_IS_XIRCOM(sc)) { 993 if ((crc & 0x180) == 0x180) 994 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 995 else 996 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 997 } 998 999 return (crc & ((1 << DC_BITS_512) - 1)); 1000} 1001 1002/* 1003 * Calculate CRC of a multicast group address, return the lower 6 bits. 1004 */ 1005static u_int32_t dc_crc_be(addr) 1006 caddr_t addr; 1007{ 1008 u_int32_t crc, carry; 1009 int i, j; 1010 u_int8_t c; 1011 1012 /* Compute CRC for the address value. */ 1013 crc = 0xFFFFFFFF; /* initial value */ 1014 1015 for (i = 0; i < 6; i++) { 1016 c = *(addr + i); 1017 for (j = 0; j < 8; j++) { 1018 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1019 crc <<= 1; 1020 c >>= 1; 1021 if (carry) 1022 crc = (crc ^ 0x04c11db6) | carry; 1023 } 1024 } 1025 1026 /* return the filter bit position */ 1027 return((crc >> 26) & 0x0000003F); 1028} 1029 1030/* 1031 * 21143-style RX filter setup routine. Filter programming is done by 1032 * downloading a special setup frame into the TX engine. 21143, Macronix, 1033 * PNIC, PNIC II and Davicom chips are programmed this way. 1034 * 1035 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1036 * address (our node address) and a 512-bit hash filter for multicast 1037 * frames. We also sneak the broadcast address into the hash filter since 1038 * we need that too. 1039 */ 1040void dc_setfilt_21143(sc) 1041 struct dc_softc *sc; 1042{ 1043 struct dc_desc *sframe; 1044 u_int32_t h, *sp; 1045 struct ifmultiaddr *ifma; 1046 struct ifnet *ifp; 1047 int i; 1048 1049 ifp = &sc->arpcom.ac_if; 1050 1051 i = sc->dc_cdata.dc_tx_prod; 1052 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1053 sc->dc_cdata.dc_tx_cnt++; 1054 sframe = &sc->dc_ldata->dc_tx_list[i]; 1055 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1056 bzero((char *)sp, DC_SFRAME_LEN); 1057 1058 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1059 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1060 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1061 1062 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1063 1064 /* If we want promiscuous mode, set the allframes bit. */ 1065 if (ifp->if_flags & IFF_PROMISC) 1066 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1067 else 1068 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1069 1070 if (ifp->if_flags & IFF_ALLMULTI) 1071 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1072 else 1073 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1074 1075 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1076 if (ifma->ifma_addr->sa_family != AF_LINK) 1077 continue; 1078 h = dc_crc_le(sc, 1079 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1080 sp[h >> 4] |= 1 << (h & 0xF); 1081 } 1082 1083 if (ifp->if_flags & IFF_BROADCAST) { 1084 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1085 sp[h >> 4] |= 1 << (h & 0xF); 1086 } 1087 1088 /* Set our MAC address */ 1089 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1090 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1091 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1092 1093 sframe->dc_status = DC_TXSTAT_OWN; 1094 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1095 1096 /* 1097 * The PNIC takes an exceedingly long time to process its 1098 * setup frame; wait 10ms after posting the setup frame 1099 * before proceeding, just so it has time to swallow its 1100 * medicine. 1101 */ 1102 DELAY(10000); 1103 1104 ifp->if_timer = 5; 1105 1106 return; 1107} 1108 1109void dc_setfilt_admtek(sc) 1110 struct dc_softc *sc; 1111{ 1112 struct ifnet *ifp; 1113 int h = 0; 1114 u_int32_t hashes[2] = { 0, 0 }; 1115 struct ifmultiaddr *ifma; 1116 1117 ifp = &sc->arpcom.ac_if; 1118 1119 /* Init our MAC address */ 1120 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1121 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1122 1123 /* If we want promiscuous mode, set the allframes bit. */ 1124 if (ifp->if_flags & IFF_PROMISC) 1125 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1126 else 1127 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1128 1129 if (ifp->if_flags & IFF_ALLMULTI) 1130 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1131 else 1132 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1133 1134 /* first, zot all the existing hash bits */ 1135 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1136 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1137 1138 /* 1139 * If we're already in promisc or allmulti mode, we 1140 * don't have to bother programming the multicast filter. 1141 */ 1142 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1143 return; 1144 1145 /* now program new ones */ 1146 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1147 if (ifma->ifma_addr->sa_family != AF_LINK) 1148 continue; 1149 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1150 if (h < 32) 1151 hashes[0] |= (1 << h); 1152 else 1153 hashes[1] |= (1 << (h - 32)); 1154 } 1155 1156 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1157 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1158 1159 return; 1160} 1161 1162void dc_setfilt_asix(sc) 1163 struct dc_softc *sc; 1164{ 1165 struct ifnet *ifp; 1166 int h = 0; 1167 u_int32_t hashes[2] = { 0, 0 }; 1168 struct ifmultiaddr *ifma; 1169 1170 ifp = &sc->arpcom.ac_if; 1171 1172 /* Init our MAC address */ 1173 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1174 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1175 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1176 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1177 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1178 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1179 1180 /* If we want promiscuous mode, set the allframes bit. */ 1181 if (ifp->if_flags & IFF_PROMISC) 1182 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1183 else 1184 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1185 1186 if (ifp->if_flags & IFF_ALLMULTI) 1187 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1188 else 1189 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1190 1191 /* 1192 * The ASIX chip has a special bit to enable reception 1193 * of broadcast frames. 1194 */ 1195 if (ifp->if_flags & IFF_BROADCAST) 1196 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1197 else 1198 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1199 1200 /* first, zot all the existing hash bits */ 1201 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1202 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1203 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1204 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1205 1206 /* 1207 * If we're already in promisc or allmulti mode, we 1208 * don't have to bother programming the multicast filter. 1209 */ 1210 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1211 return; 1212 1213 /* now program new ones */ 1214 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1215 if (ifma->ifma_addr->sa_family != AF_LINK) 1216 continue; 1217 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1218 if (h < 32) 1219 hashes[0] |= (1 << h); 1220 else 1221 hashes[1] |= (1 << (h - 32)); 1222 } 1223 1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1226 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1227 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1228 1229 return; 1230} 1231 1232void dc_setfilt_xircom(sc) 1233 struct dc_softc *sc; 1234{ 1235 struct dc_desc *sframe; 1236 u_int32_t h, *sp; 1237 struct ifmultiaddr *ifma; 1238 struct ifnet *ifp; 1239 int i; 1240 1241 ifp = &sc->arpcom.ac_if; 1242 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1243 1244 i = sc->dc_cdata.dc_tx_prod; 1245 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1246 sc->dc_cdata.dc_tx_cnt++; 1247 sframe = &sc->dc_ldata->dc_tx_list[i]; 1248 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1249 bzero((char *)sp, DC_SFRAME_LEN); 1250 1251 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1252 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1253 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1254 1255 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1256 1257 /* If we want promiscuous mode, set the allframes bit. */ 1258 if (ifp->if_flags & IFF_PROMISC) 1259 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1260 else 1261 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1262 1263 if (ifp->if_flags & IFF_ALLMULTI) 1264 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1265 else 1266 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1267 1268 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1269 if (ifma->ifma_addr->sa_family != AF_LINK) 1270 continue; 1271 h = dc_crc_le(sc, 1272 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1273 sp[h >> 4] |= 1 << (h & 0xF); 1274 } 1275 1276 if (ifp->if_flags & IFF_BROADCAST) { 1277 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1278 sp[h >> 4] |= 1 << (h & 0xF); 1279 } 1280 1281 /* Set our MAC address */ 1282 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1283 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1284 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1285 1286 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1287 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1288 ifp->if_flags |= IFF_RUNNING; 1289 sframe->dc_status = DC_TXSTAT_OWN; 1290 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1291 1292 /* 1293 * wait some time... 1294 */ 1295 DELAY(1000); 1296 1297 ifp->if_timer = 5; 1298 1299 return; 1300} 1301 1302static void dc_setfilt(sc) 1303 struct dc_softc *sc; 1304{ 1305 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1306 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1307 dc_setfilt_21143(sc); 1308 1309 if (DC_IS_ASIX(sc)) 1310 dc_setfilt_asix(sc); 1311 1312 if (DC_IS_ADMTEK(sc)) 1313 dc_setfilt_admtek(sc); 1314 1315 if (DC_IS_XIRCOM(sc)) 1316 dc_setfilt_xircom(sc); 1317 1318 return; 1319} 1320 1321/* 1322 * In order to fiddle with the 1323 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1324 * first have to put the transmit and/or receive logic in the idle state. 1325 */ 1326static void dc_setcfg(sc, media) 1327 struct dc_softc *sc; 1328 int media; 1329{ 1330 int i, restart = 0; 1331 u_int32_t isr; 1332 1333 if (IFM_SUBTYPE(media) == IFM_NONE) 1334 return; 1335 1336 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1337 restart = 1; 1338 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1339 1340 for (i = 0; i < DC_TIMEOUT; i++) { 1341 isr = CSR_READ_4(sc, DC_ISR); 1342 if (isr & DC_ISR_TX_IDLE && 1343 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1344 break; 1345 DELAY(10); 1346 } 1347 1348 if (i == DC_TIMEOUT) 1349 printf("dc%d: failed to force tx and " 1350 "rx to idle state\n", sc->dc_unit); 1351 } 1352 1353 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1354 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1355 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1356 if (sc->dc_pmode == DC_PMODE_MII) { 1357 int watchdogreg; 1358 1359 if (DC_IS_INTEL(sc)) { 1360 /* there's a write enable bit here that reads as 1 */ 1361 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1362 watchdogreg &= ~DC_WDOG_CTLWREN; 1363 watchdogreg |= DC_WDOG_JABBERDIS; 1364 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1365 } else { 1366 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1367 } 1368 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1369 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1370 if (sc->dc_type == DC_TYPE_98713) 1371 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1372 DC_NETCFG_SCRAMBLER)); 1373 if (!DC_IS_DAVICOM(sc)) 1374 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1375 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1376 if (DC_IS_INTEL(sc)) 1377 dc_apply_fixup(sc, IFM_AUTO); 1378 } else { 1379 if (DC_IS_PNIC(sc)) { 1380 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1381 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1382 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1383 } 1384 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1385 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1386 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1387 if (DC_IS_INTEL(sc)) 1388 dc_apply_fixup(sc, 1389 (media & IFM_GMASK) == IFM_FDX ? 1390 IFM_100_TX|IFM_FDX : IFM_100_TX); 1391 } 1392 } 1393 1394 if (IFM_SUBTYPE(media) == IFM_10_T) { 1395 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1396 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1397 if (sc->dc_pmode == DC_PMODE_MII) { 1398 int watchdogreg; 1399 1400 /* there's a write enable bit here that reads as 1 */ 1401 if (DC_IS_INTEL(sc)) { 1402 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1403 watchdogreg &= ~DC_WDOG_CTLWREN; 1404 watchdogreg |= DC_WDOG_JABBERDIS; 1405 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1406 } else { 1407 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1408 } 1409 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1410 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1411 if (sc->dc_type == DC_TYPE_98713) 1412 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1413 if (!DC_IS_DAVICOM(sc)) 1414 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1415 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1416 if (DC_IS_INTEL(sc)) 1417 dc_apply_fixup(sc, IFM_AUTO); 1418 } else { 1419 if (DC_IS_PNIC(sc)) { 1420 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1421 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1422 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1423 } 1424 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1425 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1426 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1427 if (DC_IS_INTEL(sc)) { 1428 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1429 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1430 if ((media & IFM_GMASK) == IFM_FDX) 1431 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1432 else 1433 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1434 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1435 DC_CLRBIT(sc, DC_10BTCTRL, 1436 DC_TCTL_AUTONEGENBL); 1437 dc_apply_fixup(sc, 1438 (media & IFM_GMASK) == IFM_FDX ? 1439 IFM_10_T|IFM_FDX : IFM_10_T); 1440 DELAY(20000); 1441 } 1442 } 1443 } 1444 1445 /* 1446 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1447 * PHY and we want HomePNA mode, set the portsel bit to turn 1448 * on the external MII port. 1449 */ 1450 if (DC_IS_DAVICOM(sc)) { 1451 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1452 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1453 sc->dc_link = 1; 1454 } else { 1455 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1456 } 1457 } 1458 1459 if ((media & IFM_GMASK) == IFM_FDX) { 1460 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1461 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1462 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1463 } else { 1464 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1465 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1466 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1467 } 1468 1469 if (restart) 1470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1471 1472 return; 1473} 1474 1475static void dc_reset(sc) 1476 struct dc_softc *sc; 1477{ 1478 register int i; 1479 1480 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1481 1482 for (i = 0; i < DC_TIMEOUT; i++) { 1483 DELAY(10); 1484 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1485 break; 1486 } 1487 1488 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1489 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1490 DELAY(10000); 1491 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1492 i = 0; 1493 } 1494 1495 if (i == DC_TIMEOUT) 1496 printf("dc%d: reset never completed!\n", sc->dc_unit); 1497 1498 /* Wait a little while for the chip to get its brains in order. */ 1499 DELAY(1000); 1500 1501 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1502 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1503 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1504 1505 /* 1506 * Bring the SIA out of reset. In some cases, it looks 1507 * like failing to unreset the SIA soon enough gets it 1508 * into a state where it will never come out of reset 1509 * until we reset the whole chip again. 1510 */ 1511 if (DC_IS_INTEL(sc)) { 1512 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1513 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1514 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1515 } 1516 1517 return; 1518} 1519 1520static struct dc_type *dc_devtype(dev) 1521 device_t dev; 1522{ 1523 struct dc_type *t; 1524 u_int32_t rev; 1525 1526 t = dc_devs; 1527 1528 while(t->dc_name != NULL) { 1529 if ((pci_get_vendor(dev) == t->dc_vid) && 1530 (pci_get_device(dev) == t->dc_did)) { 1531 /* Check the PCI revision */ 1532 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1533 if (t->dc_did == DC_DEVICEID_98713 && 1534 rev >= DC_REVISION_98713A) 1535 t++; 1536 if (t->dc_did == DC_DEVICEID_98713_CP && 1537 rev >= DC_REVISION_98713A) 1538 t++; 1539 if (t->dc_did == DC_DEVICEID_987x5 && 1540 rev >= DC_REVISION_98715AEC_C) 1541 t++; 1542 if (t->dc_did == DC_DEVICEID_987x5 && 1543 rev >= DC_REVISION_98725) 1544 t++; 1545 if (t->dc_did == DC_DEVICEID_AX88140A && 1546 rev >= DC_REVISION_88141) 1547 t++; 1548 if (t->dc_did == DC_DEVICEID_82C168 && 1549 rev >= DC_REVISION_82C169) 1550 t++; 1551 if (t->dc_did == DC_DEVICEID_DM9102 && 1552 rev >= DC_REVISION_DM9102A) 1553 t++; 1554 return(t); 1555 } 1556 t++; 1557 } 1558 1559 return(NULL); 1560} 1561 1562/* 1563 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1564 * IDs against our list and return a device name if we find a match. 1565 * We do a little bit of extra work to identify the exact type of 1566 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1567 * but different revision IDs. The same is true for 98715/98715A 1568 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1569 * cases, the exact chip revision affects driver behavior. 1570 */ 1571static int dc_probe(dev) 1572 device_t dev; 1573{ 1574 struct dc_type *t; 1575 1576 t = dc_devtype(dev); 1577 1578 if (t != NULL) { 1579 device_set_desc(dev, t->dc_name); 1580 return(0); 1581 } 1582 1583 return(ENXIO); 1584} 1585 1586static void dc_acpi(dev) 1587 device_t dev; 1588{ 1589 int unit; 1590 1591 unit = device_get_unit(dev); 1592 1593 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1594 u_int32_t iobase, membase, irq; 1595 1596 /* Save important PCI config data. */ 1597 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1598 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1599 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1600 1601 /* Reset the power state. */ 1602 printf("dc%d: chip is in D%d power mode " 1603 "-- setting to D0\n", unit, 1604 pci_get_powerstate(dev)); 1605 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1606 1607 /* Restore PCI config data. */ 1608 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1609 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1610 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1611 } 1612 1613 return; 1614} 1615 1616static void dc_apply_fixup(sc, media) 1617 struct dc_softc *sc; 1618 int media; 1619{ 1620 struct dc_mediainfo *m; 1621 u_int8_t *p; 1622 int i; 1623 u_int32_t reg; 1624 1625 m = sc->dc_mi; 1626 1627 while (m != NULL) { 1628 if (m->dc_media == media) 1629 break; 1630 m = m->dc_next; 1631 } 1632 1633 if (m == NULL) 1634 return; 1635 1636 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1637 reg = (p[0] | (p[1] << 8)) << 16; 1638 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1639 } 1640 1641 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1642 reg = (p[0] | (p[1] << 8)) << 16; 1643 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1644 } 1645 1646 return; 1647} 1648 1649static void dc_decode_leaf_sia(sc, l) 1650 struct dc_softc *sc; 1651 struct dc_eblock_sia *l; 1652{ 1653 struct dc_mediainfo *m; 1654 1655 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1656 bzero(m, sizeof(struct dc_mediainfo)); 1657 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1658 m->dc_media = IFM_10_T; 1659 1660 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1661 m->dc_media = IFM_10_T|IFM_FDX; 1662 1663 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1664 m->dc_media = IFM_10_2; 1665 1666 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1667 m->dc_media = IFM_10_5; 1668 1669 m->dc_gp_len = 2; 1670 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1671 1672 m->dc_next = sc->dc_mi; 1673 sc->dc_mi = m; 1674 1675 sc->dc_pmode = DC_PMODE_SIA; 1676 1677 return; 1678} 1679 1680static void dc_decode_leaf_sym(sc, l) 1681 struct dc_softc *sc; 1682 struct dc_eblock_sym *l; 1683{ 1684 struct dc_mediainfo *m; 1685 1686 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1687 bzero(m, sizeof(struct dc_mediainfo)); 1688 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1689 m->dc_media = IFM_100_TX; 1690 1691 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1692 m->dc_media = IFM_100_TX|IFM_FDX; 1693 1694 m->dc_gp_len = 2; 1695 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1696 1697 m->dc_next = sc->dc_mi; 1698 sc->dc_mi = m; 1699 1700 sc->dc_pmode = DC_PMODE_SYM; 1701 1702 return; 1703} 1704 1705static void dc_decode_leaf_mii(sc, l) 1706 struct dc_softc *sc; 1707 struct dc_eblock_mii *l; 1708{ 1709 u_int8_t *p; 1710 struct dc_mediainfo *m; 1711 1712 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1713 bzero(m, sizeof(struct dc_mediainfo)); 1714 /* We abuse IFM_AUTO to represent MII. */ 1715 m->dc_media = IFM_AUTO; 1716 m->dc_gp_len = l->dc_gpr_len; 1717 1718 p = (u_int8_t *)l; 1719 p += sizeof(struct dc_eblock_mii); 1720 m->dc_gp_ptr = p; 1721 p += 2 * l->dc_gpr_len; 1722 m->dc_reset_len = *p; 1723 p++; 1724 m->dc_reset_ptr = p; 1725 1726 m->dc_next = sc->dc_mi; 1727 sc->dc_mi = m; 1728 1729 return; 1730} 1731 1732static void dc_parse_21143_srom(sc) 1733 struct dc_softc *sc; 1734{ 1735 struct dc_leaf_hdr *lhdr; 1736 struct dc_eblock_hdr *hdr; 1737 int i, loff; 1738 char *ptr; 1739 1740 loff = sc->dc_srom[27]; 1741 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1742 1743 ptr = (char *)lhdr; 1744 ptr += sizeof(struct dc_leaf_hdr) - 1; 1745 for (i = 0; i < lhdr->dc_mcnt; i++) { 1746 hdr = (struct dc_eblock_hdr *)ptr; 1747 switch(hdr->dc_type) { 1748 case DC_EBLOCK_MII: 1749 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1750 break; 1751 case DC_EBLOCK_SIA: 1752 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1753 break; 1754 case DC_EBLOCK_SYM: 1755 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1756 break; 1757 default: 1758 /* Don't care. Yet. */ 1759 break; 1760 } 1761 ptr += (hdr->dc_len & 0x7F); 1762 ptr++; 1763 } 1764 1765 return; 1766} 1767 1768/* 1769 * Attach the interface. Allocate softc structures, do ifmedia 1770 * setup and ethernet/BPF attach. 1771 */ 1772static int dc_attach(dev) 1773 device_t dev; 1774{ 1775 int tmp = 0; 1776 u_char eaddr[ETHER_ADDR_LEN]; 1777 u_int32_t command; 1778 struct dc_softc *sc; 1779 struct ifnet *ifp; 1780 u_int32_t revision; 1781 int unit, error = 0, rid, mac_offset; 1782 1783 sc = device_get_softc(dev); 1784 unit = device_get_unit(dev); 1785 bzero(sc, sizeof(struct dc_softc)); 1786 1787 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1788 DC_LOCK(sc); 1789 1790 /* 1791 * Handle power management nonsense. 1792 */ 1793 dc_acpi(dev); 1794 1795 /* 1796 * Map control/status registers. 1797 */ 1798 pci_enable_busmaster(dev); 1799 pci_enable_io(dev, SYS_RES_IOPORT); 1800 pci_enable_io(dev, SYS_RES_MEMORY); 1801 command = pci_read_config(dev, PCIR_COMMAND, 4); 1802 1803#ifdef DC_USEIOSPACE 1804 if (!(command & PCIM_CMD_PORTEN)) { 1805 printf("dc%d: failed to enable I/O ports!\n", unit); 1806 error = ENXIO; 1807 goto fail; 1808 } 1809#else 1810 if (!(command & PCIM_CMD_MEMEN)) { 1811 printf("dc%d: failed to enable memory mapping!\n", unit); 1812 error = ENXIO; 1813 goto fail; 1814 } 1815#endif 1816 1817 rid = DC_RID; 1818 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1819 0, ~0, 1, RF_ACTIVE); 1820 1821 if (sc->dc_res == NULL) { 1822 printf("dc%d: couldn't map ports/memory\n", unit); 1823 error = ENXIO; 1824 goto fail; 1825 } 1826 1827 sc->dc_btag = rman_get_bustag(sc->dc_res); 1828 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1829 1830 /* Allocate interrupt */ 1831 rid = 0; 1832 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1833 RF_SHAREABLE | RF_ACTIVE); 1834 1835 if (sc->dc_irq == NULL) { 1836 printf("dc%d: couldn't map interrupt\n", unit); 1837 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1838 error = ENXIO; 1839 goto fail; 1840 } 1841 1842 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 1843 (IS_MPSAFE ? INTR_MPSAFE : 0), 1844 dc_intr, sc, &sc->dc_intrhand); 1845 1846 if (error) { 1847 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1848 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1849 printf("dc%d: couldn't set up irq\n", unit); 1850 goto fail; 1851 } 1852 1853 /* Need this info to decide on a chip type. */ 1854 sc->dc_info = dc_devtype(dev); 1855 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1856 1857 switch(sc->dc_info->dc_did) { 1858 case DC_DEVICEID_21143: 1859 sc->dc_type = DC_TYPE_21143; 1860 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1861 sc->dc_flags |= DC_REDUCED_MII_POLL; 1862 /* Save EEPROM contents so we can parse them later. */ 1863 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1864 break; 1865 case DC_DEVICEID_DM9100: 1866 case DC_DEVICEID_DM9102: 1867 sc->dc_type = DC_TYPE_DM9102; 1868 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1869 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1870 sc->dc_pmode = DC_PMODE_MII; 1871 /* Increase the latency timer value. */ 1872 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1873 command &= 0xFFFF00FF; 1874 command |= 0x00008000; 1875 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1876 break; 1877 case DC_DEVICEID_AL981: 1878 sc->dc_type = DC_TYPE_AL981; 1879 sc->dc_flags |= DC_TX_USE_TX_INTR; 1880 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1881 sc->dc_pmode = DC_PMODE_MII; 1882 break; 1883 case DC_DEVICEID_AN985: 1884 case DC_DEVICEID_FE2500: 1885 case DC_DEVICEID_EN2242: 1886 sc->dc_type = DC_TYPE_AN985; 1887 sc->dc_flags |= DC_TX_USE_TX_INTR; 1888 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1889 sc->dc_pmode = DC_PMODE_MII; 1890 break; 1891 case DC_DEVICEID_98713: 1892 case DC_DEVICEID_98713_CP: 1893 if (revision < DC_REVISION_98713A) { 1894 sc->dc_type = DC_TYPE_98713; 1895 } 1896 if (revision >= DC_REVISION_98713A) { 1897 sc->dc_type = DC_TYPE_98713A; 1898 sc->dc_flags |= DC_21143_NWAY; 1899 } 1900 sc->dc_flags |= DC_REDUCED_MII_POLL; 1901 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1902 break; 1903 case DC_DEVICEID_987x5: 1904 case DC_DEVICEID_EN1217: 1905 /* 1906 * Macronix MX98715AEC-C/D/E parts have only a 1907 * 128-bit hash table. We need to deal with these 1908 * in the same manner as the PNIC II so that we 1909 * get the right number of bits out of the 1910 * CRC routine. 1911 */ 1912 if (revision >= DC_REVISION_98715AEC_C && 1913 revision < DC_REVISION_98725) 1914 sc->dc_flags |= DC_128BIT_HASH; 1915 sc->dc_type = DC_TYPE_987x5; 1916 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1917 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1918 break; 1919 case DC_DEVICEID_98727: 1920 sc->dc_type = DC_TYPE_987x5; 1921 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1922 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1923 break; 1924 case DC_DEVICEID_82C115: 1925 sc->dc_type = DC_TYPE_PNICII; 1926 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1927 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1928 break; 1929 case DC_DEVICEID_82C168: 1930 sc->dc_type = DC_TYPE_PNIC; 1931 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1932 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1933 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1934 if (revision < DC_REVISION_82C169) 1935 sc->dc_pmode = DC_PMODE_SYM; 1936 break; 1937 case DC_DEVICEID_AX88140A: 1938 sc->dc_type = DC_TYPE_ASIX; 1939 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1940 sc->dc_flags |= DC_REDUCED_MII_POLL; 1941 sc->dc_pmode = DC_PMODE_MII; 1942 break; 1943 case DC_DEVICEID_X3201: 1944 sc->dc_type = DC_TYPE_XIRCOM; 1945 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1946 DC_TX_ALIGN ; 1947 /* 1948 * We don't actually need to coalesce, but we're doing 1949 * it to obtain a double word aligned buffer. 1950 * The DC_TX_COALESCE flag is required. 1951 */ 1952 break; 1953 case DC_DEVICEID_RS7112: 1954 sc->dc_type = DC_TYPE_CONEXANT; 1955 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1956 sc->dc_flags |= DC_REDUCED_MII_POLL; 1957 sc->dc_pmode = DC_PMODE_MII; 1958 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 256, 0); 1959 break; 1960 default: 1961 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1962 sc->dc_info->dc_did); 1963 break; 1964 } 1965 1966 /* Save the cache line size. */ 1967 if (DC_IS_DAVICOM(sc)) 1968 sc->dc_cachesize = 0; 1969 else 1970 sc->dc_cachesize = pci_read_config(dev, 1971 DC_PCI_CFLT, 4) & 0xFF; 1972 1973 /* Reset the adapter. */ 1974 dc_reset(sc); 1975 1976 /* Take 21143 out of snooze mode */ 1977 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1978 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1979 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1980 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1981 } 1982 1983 /* 1984 * Try to learn something about the supported media. 1985 * We know that ASIX and ADMtek and Davicom devices 1986 * will *always* be using MII media, so that's a no-brainer. 1987 * The tricky ones are the Macronix/PNIC II and the 1988 * Intel 21143. 1989 */ 1990 if (DC_IS_INTEL(sc)) 1991 dc_parse_21143_srom(sc); 1992 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1993 if (sc->dc_type == DC_TYPE_98713) 1994 sc->dc_pmode = DC_PMODE_MII; 1995 else 1996 sc->dc_pmode = DC_PMODE_SYM; 1997 } else if (!sc->dc_pmode) 1998 sc->dc_pmode = DC_PMODE_MII; 1999 2000 /* 2001 * Get station address from the EEPROM. 2002 */ 2003 switch(sc->dc_type) { 2004 case DC_TYPE_98713: 2005 case DC_TYPE_98713A: 2006 case DC_TYPE_987x5: 2007 case DC_TYPE_PNICII: 2008 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2009 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2010 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2011 break; 2012 case DC_TYPE_PNIC: 2013 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2014 break; 2015 case DC_TYPE_DM9102: 2016 case DC_TYPE_21143: 2017 case DC_TYPE_ASIX: 2018 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2019 break; 2020 case DC_TYPE_AL981: 2021 case DC_TYPE_AN985: 2022 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2023 break; 2024 case DC_TYPE_CONEXANT: 2025 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2026 break; 2027 case DC_TYPE_XIRCOM: 2028 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 2029 break; 2030 default: 2031 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2032 break; 2033 } 2034 2035 /* 2036 * A 21143 or clone chip was detected. Inform the world. 2037 */ 2038 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2039 2040 sc->dc_unit = unit; 2041 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2042 2043 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2044 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2045 2046 if (sc->dc_ldata == NULL) { 2047 printf("dc%d: no memory for list buffers!\n", unit); 2048 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2049 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2050 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2051 error = ENXIO; 2052 goto fail; 2053 } 2054 2055 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2056 2057 ifp = &sc->arpcom.ac_if; 2058 ifp->if_softc = sc; 2059 ifp->if_unit = unit; 2060 ifp->if_name = "dc"; 2061 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2062 ifp->if_mtu = ETHERMTU; 2063 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2064 ifp->if_ioctl = dc_ioctl; 2065 ifp->if_output = ether_output; 2066 ifp->if_start = dc_start; 2067 ifp->if_watchdog = dc_watchdog; 2068 ifp->if_init = dc_init; 2069 ifp->if_baudrate = 10000000; 2070 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2071 2072 /* 2073 * Do MII setup. If this is a 21143, check for a PHY on the 2074 * MII bus after applying any necessary fixups to twiddle the 2075 * GPIO bits. If we don't end up finding a PHY, restore the 2076 * old selection (SIA only or SIA/SYM) and attach the dcphy 2077 * driver instead. 2078 */ 2079 if (DC_IS_INTEL(sc)) { 2080 dc_apply_fixup(sc, IFM_AUTO); 2081 tmp = sc->dc_pmode; 2082 sc->dc_pmode = DC_PMODE_MII; 2083 } 2084 2085 error = mii_phy_probe(dev, &sc->dc_miibus, 2086 dc_ifmedia_upd, dc_ifmedia_sts); 2087 2088 if (error && DC_IS_INTEL(sc)) { 2089 sc->dc_pmode = tmp; 2090 if (sc->dc_pmode != DC_PMODE_SIA) 2091 sc->dc_pmode = DC_PMODE_SYM; 2092 sc->dc_flags |= DC_21143_NWAY; 2093 mii_phy_probe(dev, &sc->dc_miibus, 2094 dc_ifmedia_upd, dc_ifmedia_sts); 2095 /* 2096 * For non-MII cards, we need to have the 21143 2097 * drive the LEDs. Except there are some systems 2098 * like the NEC VersaPro NoteBook PC which have no 2099 * LEDs, and twiddling these bits has adverse effects 2100 * on them. (I.e. you suddenly can't get a link.) 2101 */ 2102 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2103 sc->dc_flags |= DC_TULIP_LEDS; 2104 error = 0; 2105 } 2106 2107 if (error) { 2108 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2109 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2110 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2111 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2112 error = ENXIO; 2113 goto fail; 2114 } 2115 2116 if (DC_IS_XIRCOM(sc)) { 2117 /* 2118 * setup General Purpose Port mode and data so the tulip 2119 * can talk to the MII. 2120 */ 2121 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2122 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2123 DELAY(10); 2124 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2125 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2126 DELAY(10); 2127 } 2128 2129 /* 2130 * Call MI attach routine. 2131 */ 2132 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2133 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2134 2135#ifdef SRM_MEDIA 2136 sc->dc_srm_media = 0; 2137 2138 /* Remember the SRM console media setting */ 2139 if (DC_IS_INTEL(sc)) { 2140 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2141 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2142 switch ((command >> 8) & 0xff) { 2143 case 3: 2144 sc->dc_srm_media = IFM_10_T; 2145 break; 2146 case 4: 2147 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2148 break; 2149 case 5: 2150 sc->dc_srm_media = IFM_100_TX; 2151 break; 2152 case 6: 2153 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2154 break; 2155 } 2156 if (sc->dc_srm_media) 2157 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2158 } 2159#endif 2160 2161 DC_UNLOCK(sc); 2162 return(0); 2163 2164fail: 2165 DC_UNLOCK(sc); 2166 mtx_destroy(&sc->dc_mtx); 2167 return(error); 2168} 2169 2170static int dc_detach(dev) 2171 device_t dev; 2172{ 2173 struct dc_softc *sc; 2174 struct ifnet *ifp; 2175 struct dc_mediainfo *m; 2176 2177 sc = device_get_softc(dev); 2178 2179 DC_LOCK(sc); 2180 2181 ifp = &sc->arpcom.ac_if; 2182 2183 dc_stop(sc); 2184 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2185 2186 bus_generic_detach(dev); 2187 device_delete_child(dev, sc->dc_miibus); 2188 2189 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2190 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2191 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2192 2193 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2194 if (sc->dc_pnic_rx_buf != NULL) 2195 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2196 2197 while(sc->dc_mi != NULL) { 2198 m = sc->dc_mi->dc_next; 2199 free(sc->dc_mi, M_DEVBUF); 2200 sc->dc_mi = m; 2201 } 2202 2203 DC_UNLOCK(sc); 2204 mtx_destroy(&sc->dc_mtx); 2205 2206 return(0); 2207} 2208 2209/* 2210 * Initialize the transmit descriptors. 2211 */ 2212static int dc_list_tx_init(sc) 2213 struct dc_softc *sc; 2214{ 2215 struct dc_chain_data *cd; 2216 struct dc_list_data *ld; 2217 int i, nexti; 2218 2219 cd = &sc->dc_cdata; 2220 ld = sc->dc_ldata; 2221 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2222 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2223 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2224 cd->dc_tx_chain[i] = NULL; 2225 ld->dc_tx_list[i].dc_data = 0; 2226 ld->dc_tx_list[i].dc_ctl = 0; 2227 } 2228 2229 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2230 2231 return(0); 2232} 2233 2234 2235/* 2236 * Initialize the RX descriptors and allocate mbufs for them. Note that 2237 * we arrange the descriptors in a closed ring, so that the last descriptor 2238 * points back to the first. 2239 */ 2240static int dc_list_rx_init(sc) 2241 struct dc_softc *sc; 2242{ 2243 struct dc_chain_data *cd; 2244 struct dc_list_data *ld; 2245 int i, nexti; 2246 2247 cd = &sc->dc_cdata; 2248 ld = sc->dc_ldata; 2249 2250 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2251 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2252 return(ENOBUFS); 2253 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2254 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2255 } 2256 2257 cd->dc_rx_prod = 0; 2258 2259 return(0); 2260} 2261 2262/* 2263 * Initialize an RX descriptor and attach an MBUF cluster. 2264 */ 2265static int dc_newbuf(sc, i, m) 2266 struct dc_softc *sc; 2267 int i; 2268 struct mbuf *m; 2269{ 2270 struct mbuf *m_new = NULL; 2271 struct dc_desc *c; 2272 2273 c = &sc->dc_ldata->dc_rx_list[i]; 2274 2275 if (m == NULL) { 2276 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2277 if (m_new == NULL) 2278 return(ENOBUFS); 2279 2280 MCLGET(m_new, M_DONTWAIT); 2281 if (!(m_new->m_flags & M_EXT)) { 2282 m_freem(m_new); 2283 return(ENOBUFS); 2284 } 2285 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2286 } else { 2287 m_new = m; 2288 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2289 m_new->m_data = m_new->m_ext.ext_buf; 2290 } 2291 2292 m_adj(m_new, sizeof(u_int64_t)); 2293 2294 /* 2295 * If this is a PNIC chip, zero the buffer. This is part 2296 * of the workaround for the receive bug in the 82c168 and 2297 * 82c169 chips. 2298 */ 2299 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2300 bzero((char *)mtod(m_new, char *), m_new->m_len); 2301 2302 sc->dc_cdata.dc_rx_chain[i] = m_new; 2303 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2304 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2305 c->dc_status = DC_RXSTAT_OWN; 2306 2307 return(0); 2308} 2309 2310/* 2311 * Grrrrr. 2312 * The PNIC chip has a terrible bug in it that manifests itself during 2313 * periods of heavy activity. The exact mode of failure if difficult to 2314 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2315 * will happen on slow machines. The bug is that sometimes instead of 2316 * uploading one complete frame during reception, it uploads what looks 2317 * like the entire contents of its FIFO memory. The frame we want is at 2318 * the end of the whole mess, but we never know exactly how much data has 2319 * been uploaded, so salvaging the frame is hard. 2320 * 2321 * There is only one way to do it reliably, and it's disgusting. 2322 * Here's what we know: 2323 * 2324 * - We know there will always be somewhere between one and three extra 2325 * descriptors uploaded. 2326 * 2327 * - We know the desired received frame will always be at the end of the 2328 * total data upload. 2329 * 2330 * - We know the size of the desired received frame because it will be 2331 * provided in the length field of the status word in the last descriptor. 2332 * 2333 * Here's what we do: 2334 * 2335 * - When we allocate buffers for the receive ring, we bzero() them. 2336 * This means that we know that the buffer contents should be all 2337 * zeros, except for data uploaded by the chip. 2338 * 2339 * - We also force the PNIC chip to upload frames that include the 2340 * ethernet CRC at the end. 2341 * 2342 * - We gather all of the bogus frame data into a single buffer. 2343 * 2344 * - We then position a pointer at the end of this buffer and scan 2345 * backwards until we encounter the first non-zero byte of data. 2346 * This is the end of the received frame. We know we will encounter 2347 * some data at the end of the frame because the CRC will always be 2348 * there, so even if the sender transmits a packet of all zeros, 2349 * we won't be fooled. 2350 * 2351 * - We know the size of the actual received frame, so we subtract 2352 * that value from the current pointer location. This brings us 2353 * to the start of the actual received packet. 2354 * 2355 * - We copy this into an mbuf and pass it on, along with the actual 2356 * frame length. 2357 * 2358 * The performance hit is tremendous, but it beats dropping frames all 2359 * the time. 2360 */ 2361 2362#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2363static void dc_pnic_rx_bug_war(sc, idx) 2364 struct dc_softc *sc; 2365 int idx; 2366{ 2367 struct dc_desc *cur_rx; 2368 struct dc_desc *c = NULL; 2369 struct mbuf *m = NULL; 2370 unsigned char *ptr; 2371 int i, total_len; 2372 u_int32_t rxstat = 0; 2373 2374 i = sc->dc_pnic_rx_bug_save; 2375 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2376 ptr = sc->dc_pnic_rx_buf; 2377 bzero(ptr, sizeof(DC_RXLEN * 5)); 2378 2379 /* Copy all the bytes from the bogus buffers. */ 2380 while (1) { 2381 c = &sc->dc_ldata->dc_rx_list[i]; 2382 rxstat = c->dc_status; 2383 m = sc->dc_cdata.dc_rx_chain[i]; 2384 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2385 ptr += DC_RXLEN; 2386 /* If this is the last buffer, break out. */ 2387 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2388 break; 2389 dc_newbuf(sc, i, m); 2390 DC_INC(i, DC_RX_LIST_CNT); 2391 } 2392 2393 /* Find the length of the actual receive frame. */ 2394 total_len = DC_RXBYTES(rxstat); 2395 2396 /* Scan backwards until we hit a non-zero byte. */ 2397 while(*ptr == 0x00) 2398 ptr--; 2399 2400 /* Round off. */ 2401 if ((uintptr_t)(ptr) & 0x3) 2402 ptr -= 1; 2403 2404 /* Now find the start of the frame. */ 2405 ptr -= total_len; 2406 if (ptr < sc->dc_pnic_rx_buf) 2407 ptr = sc->dc_pnic_rx_buf; 2408 2409 /* 2410 * Now copy the salvaged frame to the last mbuf and fake up 2411 * the status word to make it look like a successful 2412 * frame reception. 2413 */ 2414 dc_newbuf(sc, i, m); 2415 bcopy(ptr, mtod(m, char *), total_len); 2416 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2417 2418 return; 2419} 2420 2421/* 2422 * This routine searches the RX ring for dirty descriptors in the 2423 * event that the rxeof routine falls out of sync with the chip's 2424 * current descriptor pointer. This may happen sometimes as a result 2425 * of a "no RX buffer available" condition that happens when the chip 2426 * consumes all of the RX buffers before the driver has a chance to 2427 * process the RX ring. This routine may need to be called more than 2428 * once to bring the driver back in sync with the chip, however we 2429 * should still be getting RX DONE interrupts to drive the search 2430 * for new packets in the RX ring, so we should catch up eventually. 2431 */ 2432static int dc_rx_resync(sc) 2433 struct dc_softc *sc; 2434{ 2435 int i, pos; 2436 struct dc_desc *cur_rx; 2437 2438 pos = sc->dc_cdata.dc_rx_prod; 2439 2440 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2441 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2442 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2443 break; 2444 DC_INC(pos, DC_RX_LIST_CNT); 2445 } 2446 2447 /* If the ring really is empty, then just return. */ 2448 if (i == DC_RX_LIST_CNT) 2449 return(0); 2450 2451 /* We've fallen behing the chip: catch it. */ 2452 sc->dc_cdata.dc_rx_prod = pos; 2453 2454 return(EAGAIN); 2455} 2456 2457/* 2458 * A frame has been uploaded: pass the resulting mbuf chain up to 2459 * the higher level protocols. 2460 */ 2461static void dc_rxeof(sc) 2462 struct dc_softc *sc; 2463{ 2464 struct ether_header *eh; 2465 struct mbuf *m; 2466 struct ifnet *ifp; 2467 struct dc_desc *cur_rx; 2468 int i, total_len = 0; 2469 u_int32_t rxstat; 2470 2471 ifp = &sc->arpcom.ac_if; 2472 i = sc->dc_cdata.dc_rx_prod; 2473 2474 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2475 2476#ifdef DEVICE_POLLING 2477 if (ifp->if_ipending & IFF_POLLING) { 2478 if (sc->rxcycles <= 0) 2479 break; 2480 sc->rxcycles--; 2481 } 2482#endif /* DEVICE_POLLING */ 2483 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2484 rxstat = cur_rx->dc_status; 2485 m = sc->dc_cdata.dc_rx_chain[i]; 2486 total_len = DC_RXBYTES(rxstat); 2487 2488 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2489 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2490 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2491 sc->dc_pnic_rx_bug_save = i; 2492 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2493 DC_INC(i, DC_RX_LIST_CNT); 2494 continue; 2495 } 2496 dc_pnic_rx_bug_war(sc, i); 2497 rxstat = cur_rx->dc_status; 2498 total_len = DC_RXBYTES(rxstat); 2499 } 2500 } 2501 2502 sc->dc_cdata.dc_rx_chain[i] = NULL; 2503 2504 /* 2505 * If an error occurs, update stats, clear the 2506 * status word and leave the mbuf cluster in place: 2507 * it should simply get re-used next time this descriptor 2508 * comes up in the ring. 2509 */ 2510 if (rxstat & DC_RXSTAT_RXERR) { 2511 ifp->if_ierrors++; 2512 if (rxstat & DC_RXSTAT_COLLSEEN) 2513 ifp->if_collisions++; 2514 dc_newbuf(sc, i, m); 2515 if (rxstat & DC_RXSTAT_CRCERR) { 2516 DC_INC(i, DC_RX_LIST_CNT); 2517 continue; 2518 } else { 2519 dc_init(sc); 2520 return; 2521 } 2522 } 2523 2524 /* No errors; receive the packet. */ 2525 total_len -= ETHER_CRC_LEN; 2526#ifdef __i386__ 2527 /* 2528 * On the x86 we do not have alignment problems, so try to 2529 * allocate a new buffer for the receive ring, and pass up 2530 * the one where the packet is already, saving the expensive 2531 * copy done in m_devget(). 2532 * If we are on an architecture with alignment problems, or 2533 * if the allocation fails, then use m_devget and leave the 2534 * existing buffer in the receive ring. 2535 */ 2536 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2537 m->m_pkthdr.rcvif = ifp; 2538 m->m_pkthdr.len = m->m_len = total_len; 2539 DC_INC(i, DC_RX_LIST_CNT); 2540 } else 2541#endif 2542 { 2543 struct mbuf *m0; 2544 2545 m0 = m_devget(mtod(m, char *), total_len, 2546 ETHER_ALIGN, ifp, NULL); 2547 dc_newbuf(sc, i, m); 2548 DC_INC(i, DC_RX_LIST_CNT); 2549 if (m0 == NULL) { 2550 ifp->if_ierrors++; 2551 continue; 2552 } 2553 m = m0; 2554 } 2555 2556 ifp->if_ipackets++; 2557 eh = mtod(m, struct ether_header *); 2558 2559 /* Remove header from mbuf and pass it on. */ 2560 m_adj(m, sizeof(struct ether_header)); 2561 ether_input(ifp, eh, m); 2562 } 2563 2564 sc->dc_cdata.dc_rx_prod = i; 2565} 2566 2567/* 2568 * A frame was downloaded to the chip. It's safe for us to clean up 2569 * the list buffers. 2570 */ 2571 2572static void dc_txeof(sc) 2573 struct dc_softc *sc; 2574{ 2575 struct dc_desc *cur_tx = NULL; 2576 struct ifnet *ifp; 2577 int idx; 2578 2579 ifp = &sc->arpcom.ac_if; 2580 2581 /* Clear the timeout timer. */ 2582 ifp->if_timer = 0; 2583 2584 /* 2585 * Go through our tx list and free mbufs for those 2586 * frames that have been transmitted. 2587 */ 2588 idx = sc->dc_cdata.dc_tx_cons; 2589 while(idx != sc->dc_cdata.dc_tx_prod) { 2590 u_int32_t txstat; 2591 2592 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2593 txstat = cur_tx->dc_status; 2594 2595 if (txstat & DC_TXSTAT_OWN) 2596 break; 2597 2598 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2599 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2600 sc->dc_cdata.dc_tx_cnt--; 2601 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2602 /* 2603 * Yes, the PNIC is so brain damaged 2604 * that it will sometimes generate a TX 2605 * underrun error while DMAing the RX 2606 * filter setup frame. If we detect this, 2607 * we have to send the setup frame again, 2608 * or else the filter won't be programmed 2609 * correctly. 2610 */ 2611 if (DC_IS_PNIC(sc)) { 2612 if (txstat & DC_TXSTAT_ERRSUM) 2613 dc_setfilt(sc); 2614 } 2615 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2616 } 2617 DC_INC(idx, DC_TX_LIST_CNT); 2618 continue; 2619 } 2620 2621 if (DC_IS_XIRCOM(sc)) { 2622 /* 2623 * XXX: Why does my Xircom taunt me so? 2624 * For some reason it likes setting the CARRLOST flag 2625 * even when the carrier is there. wtf?!? */ 2626 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2627 sc->dc_pmode == DC_PMODE_MII && 2628 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2629 DC_TXSTAT_NOCARRIER))) 2630 txstat &= ~DC_TXSTAT_ERRSUM; 2631 } else { 2632 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2633 sc->dc_pmode == DC_PMODE_MII && 2634 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2635 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2636 txstat &= ~DC_TXSTAT_ERRSUM; 2637 } 2638 2639 if (txstat & DC_TXSTAT_ERRSUM) { 2640 ifp->if_oerrors++; 2641 if (txstat & DC_TXSTAT_EXCESSCOLL) 2642 ifp->if_collisions++; 2643 if (txstat & DC_TXSTAT_LATECOLL) 2644 ifp->if_collisions++; 2645 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2646 dc_init(sc); 2647 return; 2648 } 2649 } 2650 2651 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2652 2653 ifp->if_opackets++; 2654 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2655 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2656 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2657 } 2658 2659 sc->dc_cdata.dc_tx_cnt--; 2660 DC_INC(idx, DC_TX_LIST_CNT); 2661 } 2662 2663 sc->dc_cdata.dc_tx_cons = idx; 2664 if (cur_tx != NULL) 2665 ifp->if_flags &= ~IFF_OACTIVE; 2666 2667 return; 2668} 2669 2670static void dc_tick(xsc) 2671 void *xsc; 2672{ 2673 struct dc_softc *sc; 2674 struct mii_data *mii; 2675 struct ifnet *ifp; 2676 u_int32_t r; 2677 2678 sc = xsc; 2679 DC_LOCK(sc); 2680 ifp = &sc->arpcom.ac_if; 2681 mii = device_get_softc(sc->dc_miibus); 2682 2683 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2684 if (sc->dc_flags & DC_21143_NWAY) { 2685 r = CSR_READ_4(sc, DC_10BTSTAT); 2686 if (IFM_SUBTYPE(mii->mii_media_active) == 2687 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2688 sc->dc_link = 0; 2689 mii_mediachg(mii); 2690 } 2691 if (IFM_SUBTYPE(mii->mii_media_active) == 2692 IFM_10_T && (r & DC_TSTAT_LS10)) { 2693 sc->dc_link = 0; 2694 mii_mediachg(mii); 2695 } 2696 if (sc->dc_link == 0) 2697 mii_tick(mii); 2698 } else { 2699 r = CSR_READ_4(sc, DC_ISR); 2700 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2701 sc->dc_cdata.dc_tx_cnt == 0) 2702 mii_tick(mii); 2703 if (!(mii->mii_media_status & IFM_ACTIVE)) 2704 sc->dc_link = 0; 2705 } 2706 } else 2707 mii_tick(mii); 2708 2709 /* 2710 * When the init routine completes, we expect to be able to send 2711 * packets right away, and in fact the network code will send a 2712 * gratuitous ARP the moment the init routine marks the interface 2713 * as running. However, even though the MAC may have been initialized, 2714 * there may be a delay of a few seconds before the PHY completes 2715 * autonegotiation and the link is brought up. Any transmissions 2716 * made during that delay will be lost. Dealing with this is tricky: 2717 * we can't just pause in the init routine while waiting for the 2718 * PHY to come ready since that would bring the whole system to 2719 * a screeching halt for several seconds. 2720 * 2721 * What we do here is prevent the TX start routine from sending 2722 * any packets until a link has been established. After the 2723 * interface has been initialized, the tick routine will poll 2724 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2725 * that time, packets will stay in the send queue, and once the 2726 * link comes up, they will be flushed out to the wire. 2727 */ 2728 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2729 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2730 sc->dc_link++; 2731 if (ifp->if_snd.ifq_head != NULL) 2732 dc_start(ifp); 2733 } 2734 2735 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2736 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2737 else 2738 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2739 2740 DC_UNLOCK(sc); 2741 2742 return; 2743} 2744 2745/* 2746 * A transmit underrun has occurred. Back off the transmit threshold, 2747 * or switch to store and forward mode if we have to. 2748 */ 2749static void dc_tx_underrun(sc) 2750 struct dc_softc *sc; 2751{ 2752 u_int32_t isr; 2753 int i; 2754 2755 if (DC_IS_DAVICOM(sc)) 2756 dc_init(sc); 2757 2758 if (DC_IS_INTEL(sc)) { 2759 /* 2760 * The real 21143 requires that the transmitter be idle 2761 * in order to change the transmit threshold or store 2762 * and forward state. 2763 */ 2764 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2765 2766 for (i = 0; i < DC_TIMEOUT; i++) { 2767 isr = CSR_READ_4(sc, DC_ISR); 2768 if (isr & DC_ISR_TX_IDLE) 2769 break; 2770 DELAY(10); 2771 } 2772 if (i == DC_TIMEOUT) { 2773 printf("dc%d: failed to force tx to idle state\n", 2774 sc->dc_unit); 2775 dc_init(sc); 2776 } 2777 } 2778 2779 printf("dc%d: TX underrun -- ", sc->dc_unit); 2780 sc->dc_txthresh += DC_TXTHRESH_INC; 2781 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2782 printf("using store and forward mode\n"); 2783 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2784 } else { 2785 printf("increasing TX threshold\n"); 2786 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2787 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2788 } 2789 2790 if (DC_IS_INTEL(sc)) 2791 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2792 2793 return; 2794} 2795 2796#ifdef DEVICE_POLLING 2797static poll_handler_t dc_poll; 2798 2799static void 2800dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2801{ 2802 struct dc_softc *sc = ifp->if_softc; 2803 2804 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2805 /* Re-enable interrupts. */ 2806 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2807 return; 2808 } 2809 sc->rxcycles = count; 2810 dc_rxeof(sc); 2811 dc_txeof(sc); 2812 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2813 dc_start(ifp); 2814 2815 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2816 u_int32_t status; 2817 2818 status = CSR_READ_4(sc, DC_ISR); 2819 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2820 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2821 DC_ISR_BUS_ERR); 2822 if (!status) 2823 return ; 2824 /* ack what we have */ 2825 CSR_WRITE_4(sc, DC_ISR, status); 2826 2827 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2828 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2829 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2830 2831 if (dc_rx_resync(sc)) 2832 dc_rxeof(sc); 2833 } 2834 /* restart transmit unit if necessary */ 2835 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2836 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2837 2838 if (status & DC_ISR_TX_UNDERRUN) 2839 dc_tx_underrun(sc); 2840 2841 if (status & DC_ISR_BUS_ERR) { 2842 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2843 dc_reset(sc); 2844 dc_init(sc); 2845 } 2846 } 2847} 2848#endif /* DEVICE_POLLING */ 2849 2850static void dc_intr(arg) 2851 void *arg; 2852{ 2853 struct dc_softc *sc; 2854 struct ifnet *ifp; 2855 u_int32_t status; 2856 2857 sc = arg; 2858 2859 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2860 return ; 2861 2862 DC_LOCK(sc); 2863 ifp = &sc->arpcom.ac_if; 2864#ifdef DEVICE_POLLING 2865 if (ifp->if_ipending & IFF_POLLING) 2866 goto done; 2867 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 2868 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2869 goto done; 2870 } 2871#endif /* DEVICE_POLLING */ 2872 2873 /* Suppress unwanted interrupts */ 2874 if (!(ifp->if_flags & IFF_UP)) { 2875 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2876 dc_stop(sc); 2877 DC_UNLOCK(sc); 2878 return; 2879 } 2880 2881 /* Disable interrupts. */ 2882 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2883 2884 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2885 && status != 0xFFFFFFFF) { 2886 2887 CSR_WRITE_4(sc, DC_ISR, status); 2888 2889 if (status & DC_ISR_RX_OK) { 2890 int curpkts; 2891 curpkts = ifp->if_ipackets; 2892 dc_rxeof(sc); 2893 if (curpkts == ifp->if_ipackets) { 2894 while(dc_rx_resync(sc)) 2895 dc_rxeof(sc); 2896 } 2897 } 2898 2899 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2900 dc_txeof(sc); 2901 2902 if (status & DC_ISR_TX_IDLE) { 2903 dc_txeof(sc); 2904 if (sc->dc_cdata.dc_tx_cnt) { 2905 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2906 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2907 } 2908 } 2909 2910 if (status & DC_ISR_TX_UNDERRUN) 2911 dc_tx_underrun(sc); 2912 2913 if ((status & DC_ISR_RX_WATDOGTIMEO) 2914 || (status & DC_ISR_RX_NOBUF)) { 2915 int curpkts; 2916 curpkts = ifp->if_ipackets; 2917 dc_rxeof(sc); 2918 if (curpkts == ifp->if_ipackets) { 2919 while(dc_rx_resync(sc)) 2920 dc_rxeof(sc); 2921 } 2922 } 2923 2924 if (status & DC_ISR_BUS_ERR) { 2925 dc_reset(sc); 2926 dc_init(sc); 2927 } 2928 } 2929 2930 /* Re-enable interrupts. */ 2931 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2932 2933 if (ifp->if_snd.ifq_head != NULL) 2934 dc_start(ifp); 2935 2936done: 2937 DC_UNLOCK(sc); 2938 2939 return; 2940} 2941 2942/* 2943 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2944 * pointers to the fragment pointers. 2945 */ 2946static int dc_encap(sc, m_head, txidx) 2947 struct dc_softc *sc; 2948 struct mbuf *m_head; 2949 u_int32_t *txidx; 2950{ 2951 struct dc_desc *f = NULL; 2952 struct mbuf *m; 2953 int frag, cur, cnt = 0; 2954 2955 /* 2956 * Start packing the mbufs in this chain into 2957 * the fragment pointers. Stop when we run out 2958 * of fragments or hit the end of the mbuf chain. 2959 */ 2960 m = m_head; 2961 cur = frag = *txidx; 2962 2963 for (m = m_head; m != NULL; m = m->m_next) { 2964 if (m->m_len != 0) { 2965 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2966 if (*txidx != sc->dc_cdata.dc_tx_prod && 2967 frag == (DC_TX_LIST_CNT - 1)) 2968 return(ENOBUFS); 2969 } 2970 if ((DC_TX_LIST_CNT - 2971 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2972 return(ENOBUFS); 2973 2974 f = &sc->dc_ldata->dc_tx_list[frag]; 2975 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2976 if (cnt == 0) { 2977 f->dc_status = 0; 2978 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2979 } else 2980 f->dc_status = DC_TXSTAT_OWN; 2981 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2982 cur = frag; 2983 DC_INC(frag, DC_TX_LIST_CNT); 2984 cnt++; 2985 } 2986 } 2987 2988 if (m != NULL) 2989 return(ENOBUFS); 2990 2991 sc->dc_cdata.dc_tx_cnt += cnt; 2992 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2993 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2994 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2995 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2996 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2997 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2998 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2999 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3000 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3001 *txidx = frag; 3002 3003 return(0); 3004} 3005 3006/* 3007 * Coalesce an mbuf chain into a single mbuf cluster buffer. 3008 * Needed for some really badly behaved chips that just can't 3009 * do scatter/gather correctly. 3010 */ 3011static int dc_coal(sc, m_head) 3012 struct dc_softc *sc; 3013 struct mbuf **m_head; 3014{ 3015 struct mbuf *m_new, *m; 3016 3017 m = *m_head; 3018 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3019 if (m_new == NULL) 3020 return(ENOBUFS); 3021 if (m->m_pkthdr.len > MHLEN) { 3022 MCLGET(m_new, M_DONTWAIT); 3023 if (!(m_new->m_flags & M_EXT)) { 3024 m_freem(m_new); 3025 return(ENOBUFS); 3026 } 3027 } 3028 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 3029 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 3030 m_freem(m); 3031 *m_head = m_new; 3032 3033 return(0); 3034} 3035 3036/* 3037 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3038 * to the mbuf data regions directly in the transmit lists. We also save a 3039 * copy of the pointers since the transmit list fragment pointers are 3040 * physical addresses. 3041 */ 3042 3043static void dc_start(ifp) 3044 struct ifnet *ifp; 3045{ 3046 struct dc_softc *sc; 3047 struct mbuf *m_head = NULL; 3048 int idx; 3049 3050 sc = ifp->if_softc; 3051 3052 DC_LOCK(sc); 3053 3054 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3055 DC_UNLOCK(sc); 3056 return; 3057 } 3058 3059 if (ifp->if_flags & IFF_OACTIVE) { 3060 DC_UNLOCK(sc); 3061 return; 3062 } 3063 3064 idx = sc->dc_cdata.dc_tx_prod; 3065 3066 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3067 IF_DEQUEUE(&ifp->if_snd, m_head); 3068 if (m_head == NULL) 3069 break; 3070 3071 if (sc->dc_flags & DC_TX_COALESCE && 3072 (m_head->m_next != NULL || 3073 sc->dc_flags & DC_TX_ALIGN) ) { 3074 if (dc_coal(sc, &m_head)) { 3075 IF_PREPEND(&ifp->if_snd, m_head); 3076 ifp->if_flags |= IFF_OACTIVE; 3077 break; 3078 } 3079 } 3080 3081 if (dc_encap(sc, m_head, &idx)) { 3082 IF_PREPEND(&ifp->if_snd, m_head); 3083 ifp->if_flags |= IFF_OACTIVE; 3084 break; 3085 } 3086 3087 /* 3088 * If there's a BPF listener, bounce a copy of this frame 3089 * to him. 3090 */ 3091 if (ifp->if_bpf) 3092 bpf_mtap(ifp, m_head); 3093 3094 if (sc->dc_flags & DC_TX_ONE) { 3095 ifp->if_flags |= IFF_OACTIVE; 3096 break; 3097 } 3098 } 3099 3100 /* Transmit */ 3101 sc->dc_cdata.dc_tx_prod = idx; 3102 if (!(sc->dc_flags & DC_TX_POLL)) 3103 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3104 3105 /* 3106 * Set a timeout in case the chip goes out to lunch. 3107 */ 3108 ifp->if_timer = 5; 3109 3110 DC_UNLOCK(sc); 3111 3112 return; 3113} 3114 3115static void dc_init(xsc) 3116 void *xsc; 3117{ 3118 struct dc_softc *sc = xsc; 3119 struct ifnet *ifp = &sc->arpcom.ac_if; 3120 struct mii_data *mii; 3121 3122 DC_LOCK(sc); 3123 3124 mii = device_get_softc(sc->dc_miibus); 3125 3126 /* 3127 * Cancel pending I/O and free all RX/TX buffers. 3128 */ 3129 dc_stop(sc); 3130 dc_reset(sc); 3131 3132 /* 3133 * Set cache alignment and burst length. 3134 */ 3135 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3136 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3137 else 3138 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3139 /* 3140 * Evenly share the bus between receive and transmit process. 3141 */ 3142 if (DC_IS_INTEL(sc)) 3143 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3144 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3145 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3146 } else { 3147 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3148 } 3149 if (sc->dc_flags & DC_TX_POLL) 3150 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3151 switch(sc->dc_cachesize) { 3152 case 32: 3153 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3154 break; 3155 case 16: 3156 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3157 break; 3158 case 8: 3159 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3160 break; 3161 case 0: 3162 default: 3163 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3164 break; 3165 } 3166 3167 if (sc->dc_flags & DC_TX_STORENFWD) 3168 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3169 else { 3170 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3171 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3172 } else { 3173 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3174 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3175 } 3176 } 3177 3178 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3179 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3180 3181 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3182 /* 3183 * The app notes for the 98713 and 98715A say that 3184 * in order to have the chips operate properly, a magic 3185 * number must be written to CSR16. Macronix does not 3186 * document the meaning of these bits so there's no way 3187 * to know exactly what they do. The 98713 has a magic 3188 * number all its own; the rest all use a different one. 3189 */ 3190 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3191 if (sc->dc_type == DC_TYPE_98713) 3192 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3193 else 3194 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3195 } 3196 3197 if (DC_IS_XIRCOM(sc)) { 3198 /* 3199 * setup General Purpose Port mode and data so the tulip 3200 * can talk to the MII. 3201 */ 3202 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3203 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3204 DELAY(10); 3205 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3206 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3207 DELAY(10); 3208 } 3209 3210 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3211 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3212 3213 /* Init circular RX list. */ 3214 if (dc_list_rx_init(sc) == ENOBUFS) { 3215 printf("dc%d: initialization failed: no " 3216 "memory for rx buffers\n", sc->dc_unit); 3217 dc_stop(sc); 3218 DC_UNLOCK(sc); 3219 return; 3220 } 3221 3222 /* 3223 * Init tx descriptors. 3224 */ 3225 dc_list_tx_init(sc); 3226 3227 /* 3228 * Load the address of the RX list. 3229 */ 3230 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3231 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3232 3233 /* 3234 * Enable interrupts. 3235 */ 3236#ifdef DEVICE_POLLING 3237 /* 3238 * ... but only if we are not polling, and make sure they are off in 3239 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3240 * after a reset. 3241 */ 3242 if (ifp->if_ipending & IFF_POLLING) 3243 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3244 else 3245#endif 3246 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3247 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3248 3249 /* Enable transmitter. */ 3250 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3251 3252 /* 3253 * If this is an Intel 21143 and we're not using the 3254 * MII port, program the LED control pins so we get 3255 * link and activity indications. 3256 */ 3257 if (sc->dc_flags & DC_TULIP_LEDS) { 3258 CSR_WRITE_4(sc, DC_WATCHDOG, 3259 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3260 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3261 } 3262 3263 /* 3264 * Load the RX/multicast filter. We do this sort of late 3265 * because the filter programming scheme on the 21143 and 3266 * some clones requires DMAing a setup frame via the TX 3267 * engine, and we need the transmitter enabled for that. 3268 */ 3269 dc_setfilt(sc); 3270 3271 /* Enable receiver. */ 3272 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3273 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3274 3275 mii_mediachg(mii); 3276 dc_setcfg(sc, sc->dc_if_media); 3277 3278 ifp->if_flags |= IFF_RUNNING; 3279 ifp->if_flags &= ~IFF_OACTIVE; 3280 3281 /* Don't start the ticker if this is a homePNA link. */ 3282 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3283 sc->dc_link = 1; 3284 else { 3285 if (sc->dc_flags & DC_21143_NWAY) 3286 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3287 else 3288 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3289 } 3290 3291#ifdef SRM_MEDIA 3292 if(sc->dc_srm_media) { 3293 struct ifreq ifr; 3294 3295 ifr.ifr_media = sc->dc_srm_media; 3296 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3297 sc->dc_srm_media = 0; 3298 } 3299#endif 3300 DC_UNLOCK(sc); 3301 return; 3302} 3303 3304/* 3305 * Set media options. 3306 */ 3307static int dc_ifmedia_upd(ifp) 3308 struct ifnet *ifp; 3309{ 3310 struct dc_softc *sc; 3311 struct mii_data *mii; 3312 struct ifmedia *ifm; 3313 3314 sc = ifp->if_softc; 3315 mii = device_get_softc(sc->dc_miibus); 3316 mii_mediachg(mii); 3317 ifm = &mii->mii_media; 3318 3319 if (DC_IS_DAVICOM(sc) && 3320 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3321 dc_setcfg(sc, ifm->ifm_media); 3322 else 3323 sc->dc_link = 0; 3324 3325 return(0); 3326} 3327 3328/* 3329 * Report current media status. 3330 */ 3331static void dc_ifmedia_sts(ifp, ifmr) 3332 struct ifnet *ifp; 3333 struct ifmediareq *ifmr; 3334{ 3335 struct dc_softc *sc; 3336 struct mii_data *mii; 3337 struct ifmedia *ifm; 3338 3339 sc = ifp->if_softc; 3340 mii = device_get_softc(sc->dc_miibus); 3341 mii_pollstat(mii); 3342 ifm = &mii->mii_media; 3343 if (DC_IS_DAVICOM(sc)) { 3344 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3345 ifmr->ifm_active = ifm->ifm_media; 3346 ifmr->ifm_status = 0; 3347 return; 3348 } 3349 } 3350 ifmr->ifm_active = mii->mii_media_active; 3351 ifmr->ifm_status = mii->mii_media_status; 3352 3353 return; 3354} 3355 3356static int dc_ioctl(ifp, command, data) 3357 struct ifnet *ifp; 3358 u_long command; 3359 caddr_t data; 3360{ 3361 struct dc_softc *sc = ifp->if_softc; 3362 struct ifreq *ifr = (struct ifreq *) data; 3363 struct mii_data *mii; 3364 int error = 0; 3365 3366 DC_LOCK(sc); 3367 3368 switch(command) { 3369 case SIOCSIFADDR: 3370 case SIOCGIFADDR: 3371 case SIOCSIFMTU: 3372 error = ether_ioctl(ifp, command, data); 3373 break; 3374 case SIOCSIFFLAGS: 3375 if (ifp->if_flags & IFF_UP) { 3376 if (ifp->if_flags & IFF_RUNNING && 3377 ifp->if_flags & IFF_PROMISC && 3378 !(sc->dc_if_flags & IFF_PROMISC)) { 3379 dc_setfilt(sc); 3380 } else if (ifp->if_flags & IFF_RUNNING && 3381 !(ifp->if_flags & IFF_PROMISC) && 3382 sc->dc_if_flags & IFF_PROMISC) { 3383 dc_setfilt(sc); 3384 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3385 sc->dc_txthresh = 0; 3386 dc_init(sc); 3387 } 3388 } else { 3389 if (ifp->if_flags & IFF_RUNNING) 3390 dc_stop(sc); 3391 } 3392 sc->dc_if_flags = ifp->if_flags; 3393 error = 0; 3394 break; 3395 case SIOCADDMULTI: 3396 case SIOCDELMULTI: 3397 dc_setfilt(sc); 3398 error = 0; 3399 break; 3400 case SIOCGIFMEDIA: 3401 case SIOCSIFMEDIA: 3402 mii = device_get_softc(sc->dc_miibus); 3403 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3404#ifdef SRM_MEDIA 3405 if (sc->dc_srm_media) 3406 sc->dc_srm_media = 0; 3407#endif 3408 break; 3409 default: 3410 error = EINVAL; 3411 break; 3412 } 3413 3414 DC_UNLOCK(sc); 3415 3416 return(error); 3417} 3418 3419static void dc_watchdog(ifp) 3420 struct ifnet *ifp; 3421{ 3422 struct dc_softc *sc; 3423 3424 sc = ifp->if_softc; 3425 3426 DC_LOCK(sc); 3427 3428 ifp->if_oerrors++; 3429 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3430 3431 dc_stop(sc); 3432 dc_reset(sc); 3433 dc_init(sc); 3434 3435 if (ifp->if_snd.ifq_head != NULL) 3436 dc_start(ifp); 3437 3438 DC_UNLOCK(sc); 3439 3440 return; 3441} 3442 3443/* 3444 * Stop the adapter and free any mbufs allocated to the 3445 * RX and TX lists. 3446 */ 3447static void dc_stop(sc) 3448 struct dc_softc *sc; 3449{ 3450 register int i; 3451 struct ifnet *ifp; 3452 3453 DC_LOCK(sc); 3454 3455 ifp = &sc->arpcom.ac_if; 3456 ifp->if_timer = 0; 3457 3458 callout_stop(&sc->dc_stat_ch); 3459 3460 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3461#ifdef DEVICE_POLLING 3462 ether_poll_deregister(ifp); 3463#endif 3464 3465 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3466 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3467 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3468 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3469 sc->dc_link = 0; 3470 3471 /* 3472 * Free data in the RX lists. 3473 */ 3474 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3475 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3476 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3477 sc->dc_cdata.dc_rx_chain[i] = NULL; 3478 } 3479 } 3480 bzero((char *)&sc->dc_ldata->dc_rx_list, 3481 sizeof(sc->dc_ldata->dc_rx_list)); 3482 3483 /* 3484 * Free the TX list buffers. 3485 */ 3486 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3487 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3488 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3489 DC_TXCTL_SETUP) { 3490 sc->dc_cdata.dc_tx_chain[i] = NULL; 3491 continue; 3492 } 3493 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3494 sc->dc_cdata.dc_tx_chain[i] = NULL; 3495 } 3496 } 3497 3498 bzero((char *)&sc->dc_ldata->dc_tx_list, 3499 sizeof(sc->dc_ldata->dc_tx_list)); 3500 3501 DC_UNLOCK(sc); 3502 3503 return; 3504} 3505 3506/* 3507 * Stop all chip I/O so that the kernel's probe routines don't 3508 * get confused by errant DMAs when rebooting. 3509 */ 3510static void dc_shutdown(dev) 3511 device_t dev; 3512{ 3513 struct dc_softc *sc; 3514 3515 sc = device_get_softc(dev); 3516 3517 dc_stop(sc); 3518 3519 return; 3520} 3521