if_dc.c revision 72813
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/dc/if_dc.c 72813 2001-02-21 20:54:22Z wpaul $ 33 */ 34 35/* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63/* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91#include <sys/param.h> 92#include <sys/systm.h> 93#include <sys/sockio.h> 94#include <sys/mbuf.h> 95#include <sys/malloc.h> 96#include <sys/kernel.h> 97#include <sys/socket.h> 98 99#include <net/if.h> 100#include <net/if_arp.h> 101#include <net/ethernet.h> 102#include <net/if_dl.h> 103#include <net/if_media.h> 104 105#include <net/bpf.h> 106 107#include <vm/vm.h> /* for vtophys */ 108#include <vm/pmap.h> /* for vtophys */ 109#include <machine/bus_pio.h> 110#include <machine/bus_memio.h> 111#include <machine/bus.h> 112#include <machine/resource.h> 113#include <sys/bus.h> 114#include <sys/rman.h> 115 116#include <dev/mii/mii.h> 117#include <dev/mii/miivar.h> 118 119#include <pci/pcireg.h> 120#include <pci/pcivar.h> 121 122#define DC_USEIOSPACE 123#ifdef __alpha__ 124#define SRM_MEDIA 125#endif 126 127#include <pci/if_dcreg.h> 128 129MODULE_DEPEND(dc, miibus, 1, 1, 1); 130 131/* "controller miibus0" required. See GENERIC if you get errors here. */ 132#include "miibus_if.h" 133 134#ifndef lint 135static const char rcsid[] = 136 "$FreeBSD: head/sys/dev/dc/if_dc.c 72813 2001-02-21 20:54:22Z wpaul $"; 137#endif 138 139/* 140 * Various supported device vendors/types and their names. 141 */ 142static struct dc_type dc_devs[] = { 143 { DC_VENDORID_DEC, DC_DEVICEID_21143, 144 "Intel 21143 10/100BaseTX" }, 145 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 146 "Davicom DM9100 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 148 "Davicom DM9102 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 150 "Davicom DM9102A 10/100BaseTX" }, 151 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 152 "ADMtek AL981 10/100BaseTX" }, 153 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 154 "ADMtek AN985 10/100BaseTX" }, 155 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 156 "ASIX AX88140A 10/100BaseTX" }, 157 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 158 "ASIX AX88141 10/100BaseTX" }, 159 { DC_VENDORID_MX, DC_DEVICEID_98713, 160 "Macronix 98713 10/100BaseTX" }, 161 { DC_VENDORID_MX, DC_DEVICEID_98713, 162 "Macronix 98713A 10/100BaseTX" }, 163 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 164 "Compex RL100-TX 10/100BaseTX" }, 165 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 166 "Compex RL100-TX 10/100BaseTX" }, 167 { DC_VENDORID_MX, DC_DEVICEID_987x5, 168 "Macronix 98715/98715A 10/100BaseTX" }, 169 { DC_VENDORID_MX, DC_DEVICEID_987x5, 170 "Macronix 98715AEC-C 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98725 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_98727, 174 "Macronix 98727/98732 10/100BaseTX" }, 175 { DC_VENDORID_LO, DC_DEVICEID_82C115, 176 "LC82C115 PNIC II 10/100BaseTX" }, 177 { DC_VENDORID_LO, DC_DEVICEID_82C168, 178 "82c168 PNIC 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C168, 180 "82c169 PNIC 10/100BaseTX" }, 181 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 182 "Accton EN1217 10/100BaseTX" }, 183 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 184 "Accton EN2242 MiniPCI 10/100BaseTX" }, 185 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 186 "Xircom X3201 10/100BaseTX" }, 187 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 188 "Abocom FE2500 10/100BaseTX" }, 189 { 0, 0, NULL } 190}; 191 192static int dc_probe __P((device_t)); 193static int dc_attach __P((device_t)); 194static int dc_detach __P((device_t)); 195static void dc_acpi __P((device_t)); 196static struct dc_type *dc_devtype __P((device_t)); 197static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 198static int dc_encap __P((struct dc_softc *, struct mbuf *, 199 u_int32_t *)); 200static int dc_coal __P((struct dc_softc *, struct mbuf **)); 201static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 202static int dc_rx_resync __P((struct dc_softc *)); 203static void dc_rxeof __P((struct dc_softc *)); 204static void dc_txeof __P((struct dc_softc *)); 205static void dc_tick __P((void *)); 206static void dc_intr __P((void *)); 207static void dc_start __P((struct ifnet *)); 208static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 209static void dc_init __P((void *)); 210static void dc_stop __P((struct dc_softc *)); 211static void dc_watchdog __P((struct ifnet *)); 212static void dc_shutdown __P((device_t)); 213static int dc_ifmedia_upd __P((struct ifnet *)); 214static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 215 216static void dc_delay __P((struct dc_softc *)); 217static void dc_eeprom_idle __P((struct dc_softc *)); 218static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 219static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 220static void dc_eeprom_getword_pnic 221 __P((struct dc_softc *, int, u_int16_t *)); 222static void dc_eeprom_getword_xircom 223 __P((struct dc_softc *, int, u_int16_t *)); 224static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 225 int, int)); 226 227static void dc_mii_writebit __P((struct dc_softc *, int)); 228static int dc_mii_readbit __P((struct dc_softc *)); 229static void dc_mii_sync __P((struct dc_softc *)); 230static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 231static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 232static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 233static int dc_miibus_readreg __P((device_t, int, int)); 234static int dc_miibus_writereg __P((device_t, int, int, int)); 235static void dc_miibus_statchg __P((device_t)); 236static void dc_miibus_mediainit __P((device_t)); 237 238static void dc_setcfg __P((struct dc_softc *, int)); 239static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 240static u_int32_t dc_crc_be __P((caddr_t)); 241static void dc_setfilt_21143 __P((struct dc_softc *)); 242static void dc_setfilt_asix __P((struct dc_softc *)); 243static void dc_setfilt_admtek __P((struct dc_softc *)); 244static void dc_setfilt_xircom __P((struct dc_softc *)); 245 246static void dc_setfilt __P((struct dc_softc *)); 247 248static void dc_reset __P((struct dc_softc *)); 249static int dc_list_rx_init __P((struct dc_softc *)); 250static int dc_list_tx_init __P((struct dc_softc *)); 251 252static void dc_parse_21143_srom __P((struct dc_softc *)); 253static void dc_decode_leaf_sia __P((struct dc_softc *, 254 struct dc_eblock_sia *)); 255static void dc_decode_leaf_mii __P((struct dc_softc *, 256 struct dc_eblock_mii *)); 257static void dc_decode_leaf_sym __P((struct dc_softc *, 258 struct dc_eblock_sym *)); 259static void dc_apply_fixup __P((struct dc_softc *, int)); 260 261#ifdef DC_USEIOSPACE 262#define DC_RES SYS_RES_IOPORT 263#define DC_RID DC_PCI_CFBIO 264#else 265#define DC_RES SYS_RES_MEMORY 266#define DC_RID DC_PCI_CFBMA 267#endif 268 269static device_method_t dc_methods[] = { 270 /* Device interface */ 271 DEVMETHOD(device_probe, dc_probe), 272 DEVMETHOD(device_attach, dc_attach), 273 DEVMETHOD(device_detach, dc_detach), 274 DEVMETHOD(device_shutdown, dc_shutdown), 275 276 /* bus interface */ 277 DEVMETHOD(bus_print_child, bus_generic_print_child), 278 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 279 280 /* MII interface */ 281 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 282 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 283 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 284 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 285 286 { 0, 0 } 287}; 288 289static driver_t dc_driver = { 290 "dc", 291 dc_methods, 292 sizeof(struct dc_softc) 293}; 294 295static devclass_t dc_devclass; 296 297DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 298DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 299DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 300 301#define DC_SETBIT(sc, reg, x) \ 302 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 303 304#define DC_CLRBIT(sc, reg, x) \ 305 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 306 307#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 308#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 309 310#define IS_MPSAFE 0 311 312static void dc_delay(sc) 313 struct dc_softc *sc; 314{ 315 int idx; 316 317 for (idx = (300 / 33) + 1; idx > 0; idx--) 318 CSR_READ_4(sc, DC_BUSCTL); 319} 320 321static void dc_eeprom_idle(sc) 322 struct dc_softc *sc; 323{ 324 register int i; 325 326 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 327 dc_delay(sc); 328 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 329 dc_delay(sc); 330 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 331 dc_delay(sc); 332 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 333 dc_delay(sc); 334 335 for (i = 0; i < 25; i++) { 336 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 337 dc_delay(sc); 338 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 339 dc_delay(sc); 340 } 341 342 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 343 dc_delay(sc); 344 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 345 dc_delay(sc); 346 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 347 348 return; 349} 350 351/* 352 * Send a read command and address to the EEPROM, check for ACK. 353 */ 354static void dc_eeprom_putbyte(sc, addr) 355 struct dc_softc *sc; 356 int addr; 357{ 358 register int d, i; 359 360 /* 361 * The AN985 has a 93C66 EEPROM on it instead of 362 * a 93C46. It uses a different bit sequence for 363 * specifying the "read" opcode. 364 */ 365 if (DC_IS_CENTAUR(sc)) 366 d = addr | (DC_EECMD_READ << 2); 367 else 368 d = addr | DC_EECMD_READ; 369 370 /* 371 * Feed in each bit and strobe the clock. 372 */ 373 for (i = 0x400; i; i >>= 1) { 374 if (d & i) { 375 SIO_SET(DC_SIO_EE_DATAIN); 376 } else { 377 SIO_CLR(DC_SIO_EE_DATAIN); 378 } 379 dc_delay(sc); 380 SIO_SET(DC_SIO_EE_CLK); 381 dc_delay(sc); 382 SIO_CLR(DC_SIO_EE_CLK); 383 dc_delay(sc); 384 } 385 386 return; 387} 388 389/* 390 * Read a word of data stored in the EEPROM at address 'addr.' 391 * The PNIC 82c168/82c169 has its own non-standard way to read 392 * the EEPROM. 393 */ 394static void dc_eeprom_getword_pnic(sc, addr, dest) 395 struct dc_softc *sc; 396 int addr; 397 u_int16_t *dest; 398{ 399 register int i; 400 u_int32_t r; 401 402 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 403 404 for (i = 0; i < DC_TIMEOUT; i++) { 405 DELAY(1); 406 r = CSR_READ_4(sc, DC_SIO); 407 if (!(r & DC_PN_SIOCTL_BUSY)) { 408 *dest = (u_int16_t)(r & 0xFFFF); 409 return; 410 } 411 } 412 413 return; 414} 415 416/* 417 * Read a word of data stored in the EEPROM at address 'addr.' 418 * The Xircom X3201 has its own non-standard way to read 419 * the EEPROM, too. 420 */ 421static void dc_eeprom_getword_xircom(sc, addr, dest) 422 struct dc_softc *sc; 423 int addr; 424 u_int16_t *dest; 425{ 426 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 427 428 addr *= 2; 429 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 430 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 431 addr += 1; 432 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 433 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 434 435 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 436 return; 437} 438 439/* 440 * Read a word of data stored in the EEPROM at address 'addr.' 441 */ 442static void dc_eeprom_getword(sc, addr, dest) 443 struct dc_softc *sc; 444 int addr; 445 u_int16_t *dest; 446{ 447 register int i; 448 u_int16_t word = 0; 449 450 /* Force EEPROM to idle state. */ 451 dc_eeprom_idle(sc); 452 453 /* Enter EEPROM access mode. */ 454 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 455 dc_delay(sc); 456 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 457 dc_delay(sc); 458 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 459 dc_delay(sc); 460 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 461 dc_delay(sc); 462 463 /* 464 * Send address of word we want to read. 465 */ 466 dc_eeprom_putbyte(sc, addr); 467 468 /* 469 * Start reading bits from EEPROM. 470 */ 471 for (i = 0x8000; i; i >>= 1) { 472 SIO_SET(DC_SIO_EE_CLK); 473 dc_delay(sc); 474 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 475 word |= i; 476 dc_delay(sc); 477 SIO_CLR(DC_SIO_EE_CLK); 478 dc_delay(sc); 479 } 480 481 /* Turn off EEPROM access mode. */ 482 dc_eeprom_idle(sc); 483 484 *dest = word; 485 486 return; 487} 488 489/* 490 * Read a sequence of words from the EEPROM. 491 */ 492static void dc_read_eeprom(sc, dest, off, cnt, swap) 493 struct dc_softc *sc; 494 caddr_t dest; 495 int off; 496 int cnt; 497 int swap; 498{ 499 int i; 500 u_int16_t word = 0, *ptr; 501 502 for (i = 0; i < cnt; i++) { 503 if (DC_IS_PNIC(sc)) 504 dc_eeprom_getword_pnic(sc, off + i, &word); 505 else if (DC_IS_XIRCOM(sc)) 506 dc_eeprom_getword_xircom(sc, off + i, &word); 507 else 508 dc_eeprom_getword(sc, off + i, &word); 509 ptr = (u_int16_t *)(dest + (i * 2)); 510 if (swap) 511 *ptr = ntohs(word); 512 else 513 *ptr = word; 514 } 515 516 return; 517} 518 519/* 520 * The following two routines are taken from the Macronix 98713 521 * Application Notes pp.19-21. 522 */ 523/* 524 * Write a bit to the MII bus. 525 */ 526static void dc_mii_writebit(sc, bit) 527 struct dc_softc *sc; 528 int bit; 529{ 530 if (bit) 531 CSR_WRITE_4(sc, DC_SIO, 532 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 533 else 534 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 535 536 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 537 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 538 539 return; 540} 541 542/* 543 * Read a bit from the MII bus. 544 */ 545static int dc_mii_readbit(sc) 546 struct dc_softc *sc; 547{ 548 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 549 CSR_READ_4(sc, DC_SIO); 550 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 551 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 552 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 553 return(1); 554 555 return(0); 556} 557 558/* 559 * Sync the PHYs by setting data bit and strobing the clock 32 times. 560 */ 561static void dc_mii_sync(sc) 562 struct dc_softc *sc; 563{ 564 register int i; 565 566 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 567 568 for (i = 0; i < 32; i++) 569 dc_mii_writebit(sc, 1); 570 571 return; 572} 573 574/* 575 * Clock a series of bits through the MII. 576 */ 577static void dc_mii_send(sc, bits, cnt) 578 struct dc_softc *sc; 579 u_int32_t bits; 580 int cnt; 581{ 582 int i; 583 584 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 585 dc_mii_writebit(sc, bits & i); 586} 587 588/* 589 * Read an PHY register through the MII. 590 */ 591static int dc_mii_readreg(sc, frame) 592 struct dc_softc *sc; 593 struct dc_mii_frame *frame; 594 595{ 596 int i, ack; 597 598 DC_LOCK(sc); 599 600 /* 601 * Set up frame for RX. 602 */ 603 frame->mii_stdelim = DC_MII_STARTDELIM; 604 frame->mii_opcode = DC_MII_READOP; 605 frame->mii_turnaround = 0; 606 frame->mii_data = 0; 607 608 /* 609 * Sync the PHYs. 610 */ 611 dc_mii_sync(sc); 612 613 /* 614 * Send command/address info. 615 */ 616 dc_mii_send(sc, frame->mii_stdelim, 2); 617 dc_mii_send(sc, frame->mii_opcode, 2); 618 dc_mii_send(sc, frame->mii_phyaddr, 5); 619 dc_mii_send(sc, frame->mii_regaddr, 5); 620 621#ifdef notdef 622 /* Idle bit */ 623 dc_mii_writebit(sc, 1); 624 dc_mii_writebit(sc, 0); 625#endif 626 627 /* Check for ack */ 628 ack = dc_mii_readbit(sc); 629 630 /* 631 * Now try reading data bits. If the ack failed, we still 632 * need to clock through 16 cycles to keep the PHY(s) in sync. 633 */ 634 if (ack) { 635 for(i = 0; i < 16; i++) { 636 dc_mii_readbit(sc); 637 } 638 goto fail; 639 } 640 641 for (i = 0x8000; i; i >>= 1) { 642 if (!ack) { 643 if (dc_mii_readbit(sc)) 644 frame->mii_data |= i; 645 } 646 } 647 648fail: 649 650 dc_mii_writebit(sc, 0); 651 dc_mii_writebit(sc, 0); 652 653 DC_UNLOCK(sc); 654 655 if (ack) 656 return(1); 657 return(0); 658} 659 660/* 661 * Write to a PHY register through the MII. 662 */ 663static int dc_mii_writereg(sc, frame) 664 struct dc_softc *sc; 665 struct dc_mii_frame *frame; 666 667{ 668 DC_LOCK(sc); 669 /* 670 * Set up frame for TX. 671 */ 672 673 frame->mii_stdelim = DC_MII_STARTDELIM; 674 frame->mii_opcode = DC_MII_WRITEOP; 675 frame->mii_turnaround = DC_MII_TURNAROUND; 676 677 /* 678 * Sync the PHYs. 679 */ 680 dc_mii_sync(sc); 681 682 dc_mii_send(sc, frame->mii_stdelim, 2); 683 dc_mii_send(sc, frame->mii_opcode, 2); 684 dc_mii_send(sc, frame->mii_phyaddr, 5); 685 dc_mii_send(sc, frame->mii_regaddr, 5); 686 dc_mii_send(sc, frame->mii_turnaround, 2); 687 dc_mii_send(sc, frame->mii_data, 16); 688 689 /* Idle bit. */ 690 dc_mii_writebit(sc, 0); 691 dc_mii_writebit(sc, 0); 692 693 DC_UNLOCK(sc); 694 695 return(0); 696} 697 698static int dc_miibus_readreg(dev, phy, reg) 699 device_t dev; 700 int phy, reg; 701{ 702 struct dc_mii_frame frame; 703 struct dc_softc *sc; 704 int i, rval, phy_reg = 0; 705 706 sc = device_get_softc(dev); 707 bzero((char *)&frame, sizeof(frame)); 708 709 /* 710 * Note: both the AL981 and AN985 have internal PHYs, 711 * however the AL981 provides direct access to the PHY 712 * registers while the AN985 uses a serial MII interface. 713 * The AN985's MII interface is also buggy in that you 714 * can read from any MII address (0 to 31), but only address 1 715 * behaves normally. To deal with both cases, we pretend 716 * that the PHY is at MII address 1. 717 */ 718 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 719 return(0); 720 721 if (sc->dc_pmode != DC_PMODE_MII) { 722 if (phy == (MII_NPHY - 1)) { 723 switch(reg) { 724 case MII_BMSR: 725 /* 726 * Fake something to make the probe 727 * code think there's a PHY here. 728 */ 729 return(BMSR_MEDIAMASK); 730 break; 731 case MII_PHYIDR1: 732 if (DC_IS_PNIC(sc)) 733 return(DC_VENDORID_LO); 734 return(DC_VENDORID_DEC); 735 break; 736 case MII_PHYIDR2: 737 if (DC_IS_PNIC(sc)) 738 return(DC_DEVICEID_82C168); 739 return(DC_DEVICEID_21143); 740 break; 741 default: 742 return(0); 743 break; 744 } 745 } else 746 return(0); 747 } 748 749 if (DC_IS_PNIC(sc)) { 750 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 751 (phy << 23) | (reg << 18)); 752 for (i = 0; i < DC_TIMEOUT; i++) { 753 DELAY(1); 754 rval = CSR_READ_4(sc, DC_PN_MII); 755 if (!(rval & DC_PN_MII_BUSY)) { 756 rval &= 0xFFFF; 757 return(rval == 0xFFFF ? 0 : rval); 758 } 759 } 760 return(0); 761 } 762 763 if (DC_IS_COMET(sc)) { 764 switch(reg) { 765 case MII_BMCR: 766 phy_reg = DC_AL_BMCR; 767 break; 768 case MII_BMSR: 769 phy_reg = DC_AL_BMSR; 770 break; 771 case MII_PHYIDR1: 772 phy_reg = DC_AL_VENID; 773 break; 774 case MII_PHYIDR2: 775 phy_reg = DC_AL_DEVID; 776 break; 777 case MII_ANAR: 778 phy_reg = DC_AL_ANAR; 779 break; 780 case MII_ANLPAR: 781 phy_reg = DC_AL_LPAR; 782 break; 783 case MII_ANER: 784 phy_reg = DC_AL_ANER; 785 break; 786 default: 787 printf("dc%d: phy_read: bad phy register %x\n", 788 sc->dc_unit, reg); 789 return(0); 790 break; 791 } 792 793 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 794 795 if (rval == 0xFFFF) 796 return(0); 797 return(rval); 798 } 799 800 frame.mii_phyaddr = phy; 801 frame.mii_regaddr = reg; 802 if (sc->dc_type == DC_TYPE_98713) { 803 phy_reg = CSR_READ_4(sc, DC_NETCFG); 804 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 805 } 806 dc_mii_readreg(sc, &frame); 807 if (sc->dc_type == DC_TYPE_98713) 808 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 809 810 return(frame.mii_data); 811} 812 813static int dc_miibus_writereg(dev, phy, reg, data) 814 device_t dev; 815 int phy, reg, data; 816{ 817 struct dc_softc *sc; 818 struct dc_mii_frame frame; 819 int i, phy_reg = 0; 820 821 sc = device_get_softc(dev); 822 bzero((char *)&frame, sizeof(frame)); 823 824 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 825 return(0); 826 827 if (DC_IS_PNIC(sc)) { 828 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 829 (phy << 23) | (reg << 10) | data); 830 for (i = 0; i < DC_TIMEOUT; i++) { 831 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 832 break; 833 } 834 return(0); 835 } 836 837 if (DC_IS_COMET(sc)) { 838 switch(reg) { 839 case MII_BMCR: 840 phy_reg = DC_AL_BMCR; 841 break; 842 case MII_BMSR: 843 phy_reg = DC_AL_BMSR; 844 break; 845 case MII_PHYIDR1: 846 phy_reg = DC_AL_VENID; 847 break; 848 case MII_PHYIDR2: 849 phy_reg = DC_AL_DEVID; 850 break; 851 case MII_ANAR: 852 phy_reg = DC_AL_ANAR; 853 break; 854 case MII_ANLPAR: 855 phy_reg = DC_AL_LPAR; 856 break; 857 case MII_ANER: 858 phy_reg = DC_AL_ANER; 859 break; 860 default: 861 printf("dc%d: phy_write: bad phy register %x\n", 862 sc->dc_unit, reg); 863 return(0); 864 break; 865 } 866 867 CSR_WRITE_4(sc, phy_reg, data); 868 return(0); 869 } 870 871 frame.mii_phyaddr = phy; 872 frame.mii_regaddr = reg; 873 frame.mii_data = data; 874 875 if (sc->dc_type == DC_TYPE_98713) { 876 phy_reg = CSR_READ_4(sc, DC_NETCFG); 877 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 878 } 879 dc_mii_writereg(sc, &frame); 880 if (sc->dc_type == DC_TYPE_98713) 881 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 882 883 return(0); 884} 885 886static void dc_miibus_statchg(dev) 887 device_t dev; 888{ 889 struct dc_softc *sc; 890 struct mii_data *mii; 891 struct ifmedia *ifm; 892 893 sc = device_get_softc(dev); 894 if (DC_IS_ADMTEK(sc)) 895 return; 896 897 mii = device_get_softc(sc->dc_miibus); 898 ifm = &mii->mii_media; 899 if (DC_IS_DAVICOM(sc) && 900 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 901 dc_setcfg(sc, ifm->ifm_media); 902 sc->dc_if_media = ifm->ifm_media; 903 } else { 904 dc_setcfg(sc, mii->mii_media_active); 905 sc->dc_if_media = mii->mii_media_active; 906 } 907 908 return; 909} 910 911/* 912 * Special support for DM9102A cards with HomePNA PHYs. Note: 913 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 914 * to be impossible to talk to the management interface of the DM9801 915 * PHY (its MDIO pin is not connected to anything). Consequently, 916 * the driver has to just 'know' about the additional mode and deal 917 * with it itself. *sigh* 918 */ 919static void dc_miibus_mediainit(dev) 920 device_t dev; 921{ 922 struct dc_softc *sc; 923 struct mii_data *mii; 924 struct ifmedia *ifm; 925 int rev; 926 927 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 928 929 sc = device_get_softc(dev); 930 mii = device_get_softc(sc->dc_miibus); 931 ifm = &mii->mii_media; 932 933 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 934 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 935 936 return; 937} 938 939#define DC_POLY 0xEDB88320 940#define DC_BITS_512 9 941#define DC_BITS_128 7 942#define DC_BITS_64 6 943 944static u_int32_t dc_crc_le(sc, addr) 945 struct dc_softc *sc; 946 caddr_t addr; 947{ 948 u_int32_t idx, bit, data, crc; 949 950 /* Compute CRC for the address value. */ 951 crc = 0xFFFFFFFF; /* initial value */ 952 953 for (idx = 0; idx < 6; idx++) { 954 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 955 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 956 } 957 958 /* 959 * The hash table on the PNIC II and the MX98715AEC-C/D/E 960 * chips is only 128 bits wide. 961 */ 962 if (sc->dc_flags & DC_128BIT_HASH) 963 return (crc & ((1 << DC_BITS_128) - 1)); 964 965 /* The hash table on the MX98715BEC is only 64 bits wide. */ 966 if (sc->dc_flags & DC_64BIT_HASH) 967 return (crc & ((1 << DC_BITS_64) - 1)); 968 969 /* Xircom's hash filtering table is different (read: weird) */ 970 /* Xircom uses the LEAST significant bits */ 971 if (DC_IS_XIRCOM(sc)) { 972 if ((crc & 0x180) == 0x180) 973 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 974 else 975 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 976 } 977 978 return (crc & ((1 << DC_BITS_512) - 1)); 979} 980 981/* 982 * Calculate CRC of a multicast group address, return the lower 6 bits. 983 */ 984static u_int32_t dc_crc_be(addr) 985 caddr_t addr; 986{ 987 u_int32_t crc, carry; 988 int i, j; 989 u_int8_t c; 990 991 /* Compute CRC for the address value. */ 992 crc = 0xFFFFFFFF; /* initial value */ 993 994 for (i = 0; i < 6; i++) { 995 c = *(addr + i); 996 for (j = 0; j < 8; j++) { 997 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 998 crc <<= 1; 999 c >>= 1; 1000 if (carry) 1001 crc = (crc ^ 0x04c11db6) | carry; 1002 } 1003 } 1004 1005 /* return the filter bit position */ 1006 return((crc >> 26) & 0x0000003F); 1007} 1008 1009/* 1010 * 21143-style RX filter setup routine. Filter programming is done by 1011 * downloading a special setup frame into the TX engine. 21143, Macronix, 1012 * PNIC, PNIC II and Davicom chips are programmed this way. 1013 * 1014 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1015 * address (our node address) and a 512-bit hash filter for multicast 1016 * frames. We also sneak the broadcast address into the hash filter since 1017 * we need that too. 1018 */ 1019void dc_setfilt_21143(sc) 1020 struct dc_softc *sc; 1021{ 1022 struct dc_desc *sframe; 1023 u_int32_t h, *sp; 1024 struct ifmultiaddr *ifma; 1025 struct ifnet *ifp; 1026 int i; 1027 1028 ifp = &sc->arpcom.ac_if; 1029 1030 i = sc->dc_cdata.dc_tx_prod; 1031 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1032 sc->dc_cdata.dc_tx_cnt++; 1033 sframe = &sc->dc_ldata->dc_tx_list[i]; 1034 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1035 bzero((char *)sp, DC_SFRAME_LEN); 1036 1037 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1038 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1039 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1040 1041 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1042 1043 /* If we want promiscuous mode, set the allframes bit. */ 1044 if (ifp->if_flags & IFF_PROMISC) 1045 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1046 else 1047 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1048 1049 if (ifp->if_flags & IFF_ALLMULTI) 1050 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1051 else 1052 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1053 1054 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1055 if (ifma->ifma_addr->sa_family != AF_LINK) 1056 continue; 1057 h = dc_crc_le(sc, 1058 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1059 sp[h >> 4] |= 1 << (h & 0xF); 1060 } 1061 1062 if (ifp->if_flags & IFF_BROADCAST) { 1063 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1064 sp[h >> 4] |= 1 << (h & 0xF); 1065 } 1066 1067 /* Set our MAC address */ 1068 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1069 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1070 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1071 1072 sframe->dc_status = DC_TXSTAT_OWN; 1073 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1074 1075 /* 1076 * The PNIC takes an exceedingly long time to process its 1077 * setup frame; wait 10ms after posting the setup frame 1078 * before proceeding, just so it has time to swallow its 1079 * medicine. 1080 */ 1081 DELAY(10000); 1082 1083 ifp->if_timer = 5; 1084 1085 return; 1086} 1087 1088void dc_setfilt_admtek(sc) 1089 struct dc_softc *sc; 1090{ 1091 struct ifnet *ifp; 1092 int h = 0; 1093 u_int32_t hashes[2] = { 0, 0 }; 1094 struct ifmultiaddr *ifma; 1095 1096 ifp = &sc->arpcom.ac_if; 1097 1098 /* Init our MAC address */ 1099 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1100 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1101 1102 /* If we want promiscuous mode, set the allframes bit. */ 1103 if (ifp->if_flags & IFF_PROMISC) 1104 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1105 else 1106 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1107 1108 if (ifp->if_flags & IFF_ALLMULTI) 1109 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1110 else 1111 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1112 1113 /* first, zot all the existing hash bits */ 1114 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1115 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1116 1117 /* 1118 * If we're already in promisc or allmulti mode, we 1119 * don't have to bother programming the multicast filter. 1120 */ 1121 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1122 return; 1123 1124 /* now program new ones */ 1125 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1126 if (ifma->ifma_addr->sa_family != AF_LINK) 1127 continue; 1128 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1129 if (h < 32) 1130 hashes[0] |= (1 << h); 1131 else 1132 hashes[1] |= (1 << (h - 32)); 1133 } 1134 1135 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1136 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1137 1138 return; 1139} 1140 1141void dc_setfilt_asix(sc) 1142 struct dc_softc *sc; 1143{ 1144 struct ifnet *ifp; 1145 int h = 0; 1146 u_int32_t hashes[2] = { 0, 0 }; 1147 struct ifmultiaddr *ifma; 1148 1149 ifp = &sc->arpcom.ac_if; 1150 1151 /* Init our MAC address */ 1152 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1153 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1154 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1155 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1156 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1157 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1158 1159 /* If we want promiscuous mode, set the allframes bit. */ 1160 if (ifp->if_flags & IFF_PROMISC) 1161 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1162 else 1163 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1164 1165 if (ifp->if_flags & IFF_ALLMULTI) 1166 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1167 else 1168 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1169 1170 /* 1171 * The ASIX chip has a special bit to enable reception 1172 * of broadcast frames. 1173 */ 1174 if (ifp->if_flags & IFF_BROADCAST) 1175 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1176 else 1177 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1178 1179 /* first, zot all the existing hash bits */ 1180 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1181 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1182 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1183 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1184 1185 /* 1186 * If we're already in promisc or allmulti mode, we 1187 * don't have to bother programming the multicast filter. 1188 */ 1189 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1190 return; 1191 1192 /* now program new ones */ 1193 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1194 if (ifma->ifma_addr->sa_family != AF_LINK) 1195 continue; 1196 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1197 if (h < 32) 1198 hashes[0] |= (1 << h); 1199 else 1200 hashes[1] |= (1 << (h - 32)); 1201 } 1202 1203 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1204 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1205 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1206 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1207 1208 return; 1209} 1210 1211void dc_setfilt_xircom(sc) 1212 struct dc_softc *sc; 1213{ 1214 struct dc_desc *sframe; 1215 u_int32_t h, *sp; 1216 struct ifmultiaddr *ifma; 1217 struct ifnet *ifp; 1218 int i; 1219 1220 ifp = &sc->arpcom.ac_if; 1221 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1222 1223 i = sc->dc_cdata.dc_tx_prod; 1224 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1225 sc->dc_cdata.dc_tx_cnt++; 1226 sframe = &sc->dc_ldata->dc_tx_list[i]; 1227 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1228 bzero((char *)sp, DC_SFRAME_LEN); 1229 1230 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1231 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1232 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1233 1234 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1235 1236 /* If we want promiscuous mode, set the allframes bit. */ 1237 if (ifp->if_flags & IFF_PROMISC) 1238 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1239 else 1240 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1241 1242 if (ifp->if_flags & IFF_ALLMULTI) 1243 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1244 else 1245 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1246 1247 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1248 if (ifma->ifma_addr->sa_family != AF_LINK) 1249 continue; 1250 h = dc_crc_le(sc, 1251 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1252 sp[h >> 4] |= 1 << (h & 0xF); 1253 } 1254 1255 if (ifp->if_flags & IFF_BROADCAST) { 1256 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1257 sp[h >> 4] |= 1 << (h & 0xF); 1258 } 1259 1260 /* Set our MAC address */ 1261 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1262 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1263 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1264 1265 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1266 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1267 ifp->if_flags |= IFF_RUNNING; 1268 sframe->dc_status = DC_TXSTAT_OWN; 1269 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1270 1271 /* 1272 * wait some time... 1273 */ 1274 DELAY(1000); 1275 1276 ifp->if_timer = 5; 1277 1278 return; 1279} 1280 1281static void dc_setfilt(sc) 1282 struct dc_softc *sc; 1283{ 1284 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1285 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1286 dc_setfilt_21143(sc); 1287 1288 if (DC_IS_ASIX(sc)) 1289 dc_setfilt_asix(sc); 1290 1291 if (DC_IS_ADMTEK(sc)) 1292 dc_setfilt_admtek(sc); 1293 1294 if (DC_IS_XIRCOM(sc)) 1295 dc_setfilt_xircom(sc); 1296 1297 return; 1298} 1299 1300/* 1301 * In order to fiddle with the 1302 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1303 * first have to put the transmit and/or receive logic in the idle state. 1304 */ 1305static void dc_setcfg(sc, media) 1306 struct dc_softc *sc; 1307 int media; 1308{ 1309 int i, restart = 0; 1310 u_int32_t isr; 1311 1312 if (IFM_SUBTYPE(media) == IFM_NONE) 1313 return; 1314 1315 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1316 restart = 1; 1317 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1318 1319 for (i = 0; i < DC_TIMEOUT; i++) { 1320 DELAY(10); 1321 isr = CSR_READ_4(sc, DC_ISR); 1322 if (isr & DC_ISR_TX_IDLE || 1323 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1324 break; 1325 } 1326 1327 if (i == DC_TIMEOUT) 1328 printf("dc%d: failed to force tx and " 1329 "rx to idle state\n", sc->dc_unit); 1330 1331 } 1332 1333 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1334 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1335 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1336 if (sc->dc_pmode == DC_PMODE_MII) { 1337 int watchdogreg; 1338 1339 if (DC_IS_INTEL(sc)) { 1340 /* there's a write enable bit here that reads as 1 */ 1341 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1342 watchdogreg &= ~DC_WDOG_CTLWREN; 1343 watchdogreg |= DC_WDOG_JABBERDIS; 1344 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1345 } else { 1346 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1347 } 1348 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1349 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1350 if (sc->dc_type == DC_TYPE_98713) 1351 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1352 DC_NETCFG_SCRAMBLER)); 1353 if (!DC_IS_DAVICOM(sc)) 1354 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1355 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1356 if (DC_IS_INTEL(sc)) 1357 dc_apply_fixup(sc, IFM_AUTO); 1358 } else { 1359 if (DC_IS_PNIC(sc)) { 1360 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1361 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1362 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1363 } 1364 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1365 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1366 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1367 if (DC_IS_INTEL(sc)) 1368 dc_apply_fixup(sc, 1369 (media & IFM_GMASK) == IFM_FDX ? 1370 IFM_100_TX|IFM_FDX : IFM_100_TX); 1371 } 1372 } 1373 1374 if (IFM_SUBTYPE(media) == IFM_10_T) { 1375 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1376 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1377 if (sc->dc_pmode == DC_PMODE_MII) { 1378 int watchdogreg; 1379 1380 /* there's a write enable bit here that reads as 1 */ 1381 if (DC_IS_INTEL(sc)) { 1382 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1383 watchdogreg &= ~DC_WDOG_CTLWREN; 1384 watchdogreg |= DC_WDOG_JABBERDIS; 1385 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1386 } else { 1387 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1388 } 1389 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1390 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1391 if (sc->dc_type == DC_TYPE_98713) 1392 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1393 if (!DC_IS_DAVICOM(sc)) 1394 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1395 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1396 if (DC_IS_INTEL(sc)) 1397 dc_apply_fixup(sc, IFM_AUTO); 1398 } else { 1399 if (DC_IS_PNIC(sc)) { 1400 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1401 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1402 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1403 } 1404 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1405 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1406 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1407 if (DC_IS_INTEL(sc)) { 1408 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1409 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1410 if ((media & IFM_GMASK) == IFM_FDX) 1411 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1412 else 1413 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1414 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1415 DC_CLRBIT(sc, DC_10BTCTRL, 1416 DC_TCTL_AUTONEGENBL); 1417 dc_apply_fixup(sc, 1418 (media & IFM_GMASK) == IFM_FDX ? 1419 IFM_10_T|IFM_FDX : IFM_10_T); 1420 DELAY(20000); 1421 } 1422 } 1423 } 1424 1425 /* 1426 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1427 * PHY and we want HomePNA mode, set the portsel bit to turn 1428 * on the external MII port. 1429 */ 1430 if (DC_IS_DAVICOM(sc)) { 1431 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1432 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1433 sc->dc_link = 1; 1434 } else { 1435 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1436 } 1437 } 1438 1439 if ((media & IFM_GMASK) == IFM_FDX) { 1440 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1441 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1442 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1443 } else { 1444 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1445 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1446 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1447 } 1448 1449 if (restart) 1450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1451 1452 return; 1453} 1454 1455static void dc_reset(sc) 1456 struct dc_softc *sc; 1457{ 1458 register int i; 1459 1460 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1461 1462 for (i = 0; i < DC_TIMEOUT; i++) { 1463 DELAY(10); 1464 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1465 break; 1466 } 1467 1468 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || 1469 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1470 DELAY(10000); 1471 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1472 i = 0; 1473 } 1474 1475 if (i == DC_TIMEOUT) 1476 printf("dc%d: reset never completed!\n", sc->dc_unit); 1477 1478 /* Wait a little while for the chip to get its brains in order. */ 1479 DELAY(1000); 1480 1481 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1482 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1483 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1484 1485 /* 1486 * Bring the SIA out of reset. In some cases, it looks 1487 * like failing to unreset the SIA soon enough gets it 1488 * into a state where it will never come out of reset 1489 * until we reset the whole chip again. 1490 */ 1491 if (DC_IS_INTEL(sc)) { 1492 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1493 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1494 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1495 } 1496 1497 return; 1498} 1499 1500static struct dc_type *dc_devtype(dev) 1501 device_t dev; 1502{ 1503 struct dc_type *t; 1504 u_int32_t rev; 1505 1506 t = dc_devs; 1507 1508 while(t->dc_name != NULL) { 1509 if ((pci_get_vendor(dev) == t->dc_vid) && 1510 (pci_get_device(dev) == t->dc_did)) { 1511 /* Check the PCI revision */ 1512 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1513 if (t->dc_did == DC_DEVICEID_98713 && 1514 rev >= DC_REVISION_98713A) 1515 t++; 1516 if (t->dc_did == DC_DEVICEID_98713_CP && 1517 rev >= DC_REVISION_98713A) 1518 t++; 1519 if (t->dc_did == DC_DEVICEID_987x5 && 1520 rev >= DC_REVISION_98715AEC_C) 1521 t++; 1522 if (t->dc_did == DC_DEVICEID_987x5 && 1523 rev >= DC_REVISION_98725) 1524 t++; 1525 if (t->dc_did == DC_DEVICEID_AX88140A && 1526 rev >= DC_REVISION_88141) 1527 t++; 1528 if (t->dc_did == DC_DEVICEID_82C168 && 1529 rev >= DC_REVISION_82C169) 1530 t++; 1531 if (t->dc_did == DC_DEVICEID_DM9102 && 1532 rev >= DC_REVISION_DM9102A) 1533 t++; 1534 return(t); 1535 } 1536 t++; 1537 } 1538 1539 return(NULL); 1540} 1541 1542/* 1543 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1544 * IDs against our list and return a device name if we find a match. 1545 * We do a little bit of extra work to identify the exact type of 1546 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1547 * but different revision IDs. The same is true for 98715/98715A 1548 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1549 * cases, the exact chip revision affects driver behavior. 1550 */ 1551static int dc_probe(dev) 1552 device_t dev; 1553{ 1554 struct dc_type *t; 1555 1556 t = dc_devtype(dev); 1557 1558 if (t != NULL) { 1559 device_set_desc(dev, t->dc_name); 1560 return(0); 1561 } 1562 1563 return(ENXIO); 1564} 1565 1566static void dc_acpi(dev) 1567 device_t dev; 1568{ 1569 int unit; 1570 1571 unit = device_get_unit(dev); 1572 1573 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1574 u_int32_t iobase, membase, irq; 1575 1576 /* Save important PCI config data. */ 1577 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1578 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1579 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1580 1581 /* Reset the power state. */ 1582 printf("dc%d: chip is in D%d power mode " 1583 "-- setting to D0\n", unit, 1584 pci_get_powerstate(dev)); 1585 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1586 1587 /* Restore PCI config data. */ 1588 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1589 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1590 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1591 } 1592 1593 return; 1594} 1595 1596static void dc_apply_fixup(sc, media) 1597 struct dc_softc *sc; 1598 int media; 1599{ 1600 struct dc_mediainfo *m; 1601 u_int8_t *p; 1602 int i; 1603 u_int32_t reg; 1604 1605 m = sc->dc_mi; 1606 1607 while (m != NULL) { 1608 if (m->dc_media == media) 1609 break; 1610 m = m->dc_next; 1611 } 1612 1613 if (m == NULL) 1614 return; 1615 1616 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1617 reg = (p[0] | (p[1] << 8)) << 16; 1618 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1619 } 1620 1621 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1622 reg = (p[0] | (p[1] << 8)) << 16; 1623 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1624 } 1625 1626 return; 1627} 1628 1629static void dc_decode_leaf_sia(sc, l) 1630 struct dc_softc *sc; 1631 struct dc_eblock_sia *l; 1632{ 1633 struct dc_mediainfo *m; 1634 1635 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1636 bzero(m, sizeof(struct dc_mediainfo)); 1637 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1638 m->dc_media = IFM_10_T; 1639 1640 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1641 m->dc_media = IFM_10_T|IFM_FDX; 1642 1643 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1644 m->dc_media = IFM_10_2; 1645 1646 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1647 m->dc_media = IFM_10_5; 1648 1649 m->dc_gp_len = 2; 1650 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1651 1652 m->dc_next = sc->dc_mi; 1653 sc->dc_mi = m; 1654 1655 sc->dc_pmode = DC_PMODE_SIA; 1656 1657 return; 1658} 1659 1660static void dc_decode_leaf_sym(sc, l) 1661 struct dc_softc *sc; 1662 struct dc_eblock_sym *l; 1663{ 1664 struct dc_mediainfo *m; 1665 1666 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1667 bzero(m, sizeof(struct dc_mediainfo)); 1668 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1669 m->dc_media = IFM_100_TX; 1670 1671 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1672 m->dc_media = IFM_100_TX|IFM_FDX; 1673 1674 m->dc_gp_len = 2; 1675 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1676 1677 m->dc_next = sc->dc_mi; 1678 sc->dc_mi = m; 1679 1680 sc->dc_pmode = DC_PMODE_SYM; 1681 1682 return; 1683} 1684 1685static void dc_decode_leaf_mii(sc, l) 1686 struct dc_softc *sc; 1687 struct dc_eblock_mii *l; 1688{ 1689 u_int8_t *p; 1690 struct dc_mediainfo *m; 1691 1692 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1693 bzero(m, sizeof(struct dc_mediainfo)); 1694 /* We abuse IFM_AUTO to represent MII. */ 1695 m->dc_media = IFM_AUTO; 1696 m->dc_gp_len = l->dc_gpr_len; 1697 1698 p = (u_int8_t *)l; 1699 p += sizeof(struct dc_eblock_mii); 1700 m->dc_gp_ptr = p; 1701 p += 2 * l->dc_gpr_len; 1702 m->dc_reset_len = *p; 1703 p++; 1704 m->dc_reset_ptr = p; 1705 1706 m->dc_next = sc->dc_mi; 1707 sc->dc_mi = m; 1708 1709 return; 1710} 1711 1712static void dc_parse_21143_srom(sc) 1713 struct dc_softc *sc; 1714{ 1715 struct dc_leaf_hdr *lhdr; 1716 struct dc_eblock_hdr *hdr; 1717 int i, loff; 1718 char *ptr; 1719 1720 loff = sc->dc_srom[27]; 1721 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1722 1723 ptr = (char *)lhdr; 1724 ptr += sizeof(struct dc_leaf_hdr) - 1; 1725 for (i = 0; i < lhdr->dc_mcnt; i++) { 1726 hdr = (struct dc_eblock_hdr *)ptr; 1727 switch(hdr->dc_type) { 1728 case DC_EBLOCK_MII: 1729 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1730 break; 1731 case DC_EBLOCK_SIA: 1732 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1733 break; 1734 case DC_EBLOCK_SYM: 1735 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1736 break; 1737 default: 1738 /* Don't care. Yet. */ 1739 break; 1740 } 1741 ptr += (hdr->dc_len & 0x7F); 1742 ptr++; 1743 } 1744 1745 return; 1746} 1747 1748/* 1749 * Attach the interface. Allocate softc structures, do ifmedia 1750 * setup and ethernet/BPF attach. 1751 */ 1752static int dc_attach(dev) 1753 device_t dev; 1754{ 1755 int tmp = 0; 1756 u_char eaddr[ETHER_ADDR_LEN]; 1757 u_int32_t command; 1758 struct dc_softc *sc; 1759 struct ifnet *ifp; 1760 u_int32_t revision; 1761 int unit, error = 0, rid, mac_offset; 1762 1763 sc = device_get_softc(dev); 1764 unit = device_get_unit(dev); 1765 bzero(sc, sizeof(struct dc_softc)); 1766 1767 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1768 DC_LOCK(sc); 1769 1770 /* 1771 * Handle power management nonsense. 1772 */ 1773 dc_acpi(dev); 1774 1775 /* 1776 * Map control/status registers. 1777 */ 1778 pci_enable_busmaster(dev); 1779 pci_enable_io(dev, PCIM_CMD_PORTEN); 1780 pci_enable_io(dev, PCIM_CMD_MEMEN); 1781 command = pci_read_config(dev, PCIR_COMMAND, 4); 1782 1783#ifdef DC_USEIOSPACE 1784 if (!(command & PCIM_CMD_PORTEN)) { 1785 printf("dc%d: failed to enable I/O ports!\n", unit); 1786 error = ENXIO; 1787 goto fail; 1788 } 1789#else 1790 if (!(command & PCIM_CMD_MEMEN)) { 1791 printf("dc%d: failed to enable memory mapping!\n", unit); 1792 error = ENXIO; 1793 goto fail; 1794 } 1795#endif 1796 1797 rid = DC_RID; 1798 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1799 0, ~0, 1, RF_ACTIVE); 1800 1801 if (sc->dc_res == NULL) { 1802 printf("dc%d: couldn't map ports/memory\n", unit); 1803 error = ENXIO; 1804 goto fail; 1805 } 1806 1807 sc->dc_btag = rman_get_bustag(sc->dc_res); 1808 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1809 1810 /* Allocate interrupt */ 1811 rid = 0; 1812 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1813 RF_SHAREABLE | RF_ACTIVE); 1814 1815 if (sc->dc_irq == NULL) { 1816 printf("dc%d: couldn't map interrupt\n", unit); 1817 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1818 error = ENXIO; 1819 goto fail; 1820 } 1821 1822 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 1823 (IS_MPSAFE ? INTR_MPSAFE : 0), 1824 dc_intr, sc, &sc->dc_intrhand); 1825 1826 if (error) { 1827 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1828 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1829 printf("dc%d: couldn't set up irq\n", unit); 1830 goto fail; 1831 } 1832 1833 /* Need this info to decide on a chip type. */ 1834 sc->dc_info = dc_devtype(dev); 1835 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1836 1837 switch(sc->dc_info->dc_did) { 1838 case DC_DEVICEID_21143: 1839 sc->dc_type = DC_TYPE_21143; 1840 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1841 sc->dc_flags |= DC_REDUCED_MII_POLL; 1842 /* Save EEPROM contents so we can parse them later. */ 1843 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1844 break; 1845 case DC_DEVICEID_DM9100: 1846 case DC_DEVICEID_DM9102: 1847 sc->dc_type = DC_TYPE_DM9102; 1848 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1849 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1850 sc->dc_pmode = DC_PMODE_MII; 1851 /* Increase the latency timer value. */ 1852 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1853 command &= 0xFFFF00FF; 1854 command |= 0x00008000; 1855 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1856 break; 1857 case DC_DEVICEID_AL981: 1858 sc->dc_type = DC_TYPE_AL981; 1859 sc->dc_flags |= DC_TX_USE_TX_INTR; 1860 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1861 sc->dc_pmode = DC_PMODE_MII; 1862 break; 1863 case DC_DEVICEID_AN985: 1864 case DC_DEVICEID_FE2500: 1865 case DC_DEVICEID_EN2242: 1866 sc->dc_type = DC_TYPE_AN985; 1867 sc->dc_flags |= DC_TX_USE_TX_INTR; 1868 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1869 sc->dc_pmode = DC_PMODE_MII; 1870 break; 1871 case DC_DEVICEID_98713: 1872 case DC_DEVICEID_98713_CP: 1873 if (revision < DC_REVISION_98713A) { 1874 sc->dc_type = DC_TYPE_98713; 1875 } 1876 if (revision >= DC_REVISION_98713A) { 1877 sc->dc_type = DC_TYPE_98713A; 1878 sc->dc_flags |= DC_21143_NWAY; 1879 } 1880 sc->dc_flags |= DC_REDUCED_MII_POLL; 1881 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1882 break; 1883 case DC_DEVICEID_987x5: 1884 case DC_DEVICEID_EN1217: 1885 /* 1886 * Macronix MX98715AEC-C/D/E parts have only a 1887 * 128-bit hash table. We need to deal with these 1888 * in the same manner as the PNIC II so that we 1889 * get the right number of bits out of the 1890 * CRC routine. 1891 */ 1892 if (revision >= DC_REVISION_98715AEC_C && 1893 revision < DC_REVISION_98725) 1894 sc->dc_flags |= DC_128BIT_HASH; 1895 sc->dc_type = DC_TYPE_987x5; 1896 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1897 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1898 break; 1899 case DC_DEVICEID_98727: 1900 sc->dc_type = DC_TYPE_987x5; 1901 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1902 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1903 break; 1904 case DC_DEVICEID_82C115: 1905 sc->dc_type = DC_TYPE_PNICII; 1906 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1907 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1908 break; 1909 case DC_DEVICEID_82C168: 1910 sc->dc_type = DC_TYPE_PNIC; 1911 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1912 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1913 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1914 if (revision < DC_REVISION_82C169) 1915 sc->dc_pmode = DC_PMODE_SYM; 1916 break; 1917 case DC_DEVICEID_AX88140A: 1918 sc->dc_type = DC_TYPE_ASIX; 1919 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1920 sc->dc_flags |= DC_REDUCED_MII_POLL; 1921 sc->dc_pmode = DC_PMODE_MII; 1922 break; 1923 case DC_DEVICEID_X3201: 1924 sc->dc_type = DC_TYPE_XIRCOM; 1925 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE; 1926 /* 1927 * We don't actually need to coalesce, but we're doing 1928 * it to obtain a double word aligned buffer. 1929 */ 1930 break; 1931 default: 1932 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1933 sc->dc_info->dc_did); 1934 break; 1935 } 1936 1937 /* Save the cache line size. */ 1938 if (DC_IS_DAVICOM(sc)) 1939 sc->dc_cachesize = 0; 1940 else 1941 sc->dc_cachesize = pci_read_config(dev, 1942 DC_PCI_CFLT, 4) & 0xFF; 1943 1944 /* Reset the adapter. */ 1945 dc_reset(sc); 1946 1947 /* Take 21143 out of snooze mode */ 1948 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1949 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1950 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1951 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1952 } 1953 1954 /* 1955 * Try to learn something about the supported media. 1956 * We know that ASIX and ADMtek and Davicom devices 1957 * will *always* be using MII media, so that's a no-brainer. 1958 * The tricky ones are the Macronix/PNIC II and the 1959 * Intel 21143. 1960 */ 1961 if (DC_IS_INTEL(sc)) 1962 dc_parse_21143_srom(sc); 1963 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1964 if (sc->dc_type == DC_TYPE_98713) 1965 sc->dc_pmode = DC_PMODE_MII; 1966 else 1967 sc->dc_pmode = DC_PMODE_SYM; 1968 } else if (!sc->dc_pmode) 1969 sc->dc_pmode = DC_PMODE_MII; 1970 1971 /* 1972 * Get station address from the EEPROM. 1973 */ 1974 switch(sc->dc_type) { 1975 case DC_TYPE_98713: 1976 case DC_TYPE_98713A: 1977 case DC_TYPE_987x5: 1978 case DC_TYPE_PNICII: 1979 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1980 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1981 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1982 break; 1983 case DC_TYPE_PNIC: 1984 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1985 break; 1986 case DC_TYPE_DM9102: 1987 case DC_TYPE_21143: 1988 case DC_TYPE_ASIX: 1989 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1990 break; 1991 case DC_TYPE_AL981: 1992 case DC_TYPE_AN985: 1993 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1994 break; 1995 case DC_TYPE_XIRCOM: 1996 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 1997 break; 1998 default: 1999 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2000 break; 2001 } 2002 2003 /* 2004 * A 21143 or clone chip was detected. Inform the world. 2005 */ 2006 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2007 2008 sc->dc_unit = unit; 2009 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2010 2011 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2012 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2013 2014 if (sc->dc_ldata == NULL) { 2015 printf("dc%d: no memory for list buffers!\n", unit); 2016 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2017 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2018 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2019 error = ENXIO; 2020 goto fail; 2021 } 2022 2023 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2024 2025 ifp = &sc->arpcom.ac_if; 2026 ifp->if_softc = sc; 2027 ifp->if_unit = unit; 2028 ifp->if_name = "dc"; 2029 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2030 ifp->if_mtu = ETHERMTU; 2031 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2032 ifp->if_ioctl = dc_ioctl; 2033 ifp->if_output = ether_output; 2034 ifp->if_start = dc_start; 2035 ifp->if_watchdog = dc_watchdog; 2036 ifp->if_init = dc_init; 2037 ifp->if_baudrate = 10000000; 2038 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2039 ifp->if_mpsafe = IS_MPSAFE; 2040 2041 /* 2042 * Do MII setup. If this is a 21143, check for a PHY on the 2043 * MII bus after applying any necessary fixups to twiddle the 2044 * GPIO bits. If we don't end up finding a PHY, restore the 2045 * old selection (SIA only or SIA/SYM) and attach the dcphy 2046 * driver instead. 2047 */ 2048 if (DC_IS_INTEL(sc)) { 2049 dc_apply_fixup(sc, IFM_AUTO); 2050 tmp = sc->dc_pmode; 2051 sc->dc_pmode = DC_PMODE_MII; 2052 } 2053 2054 error = mii_phy_probe(dev, &sc->dc_miibus, 2055 dc_ifmedia_upd, dc_ifmedia_sts); 2056 2057 if (error && DC_IS_INTEL(sc)) { 2058 sc->dc_pmode = tmp; 2059 if (sc->dc_pmode != DC_PMODE_SIA) 2060 sc->dc_pmode = DC_PMODE_SYM; 2061 sc->dc_flags |= DC_21143_NWAY; 2062 mii_phy_probe(dev, &sc->dc_miibus, 2063 dc_ifmedia_upd, dc_ifmedia_sts); 2064 /* 2065 * For non-MII cards, we need to have the 21143 2066 * drive the LEDs. Except there are some systems 2067 * like the NEC VersaPro NoteBook PC which have no 2068 * LEDs, and twiddling these bits has adverse effects 2069 * on them. (I.e. you suddenly can't get a link.) 2070 */ 2071 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2072 sc->dc_flags |= DC_TULIP_LEDS; 2073 error = 0; 2074 } 2075 2076 if (error) { 2077 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2078 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2079 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2080 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2081 error = ENXIO; 2082 goto fail; 2083 } 2084 2085 if (DC_IS_XIRCOM(sc)) { 2086 /* 2087 * setup General Purpose Port mode and data so the tulip 2088 * can talk to the MII. 2089 */ 2090 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2091 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2092 DELAY(10); 2093 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2094 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2095 DELAY(10); 2096 } 2097 2098 /* 2099 * Call MI attach routine. 2100 */ 2101 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2102 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2103 2104#ifdef SRM_MEDIA 2105 sc->dc_srm_media = 0; 2106 2107 /* Remember the SRM console media setting */ 2108 if (DC_IS_INTEL(sc)) { 2109 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2110 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2111 switch ((command >> 8) & 0xff) { 2112 case 3: 2113 sc->dc_srm_media = IFM_10_T; 2114 break; 2115 case 4: 2116 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2117 break; 2118 case 5: 2119 sc->dc_srm_media = IFM_100_TX; 2120 break; 2121 case 6: 2122 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2123 break; 2124 } 2125 if (sc->dc_srm_media) 2126 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2127 } 2128#endif 2129 2130 DC_UNLOCK(sc); 2131 return(0); 2132 2133fail: 2134 DC_UNLOCK(sc); 2135 mtx_destroy(&sc->dc_mtx); 2136 return(error); 2137} 2138 2139static int dc_detach(dev) 2140 device_t dev; 2141{ 2142 struct dc_softc *sc; 2143 struct ifnet *ifp; 2144 struct dc_mediainfo *m; 2145 2146 sc = device_get_softc(dev); 2147 2148 DC_LOCK(sc); 2149 2150 ifp = &sc->arpcom.ac_if; 2151 2152 dc_stop(sc); 2153 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2154 2155 bus_generic_detach(dev); 2156 device_delete_child(dev, sc->dc_miibus); 2157 2158 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2159 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2160 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2161 2162 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2163 if (sc->dc_pnic_rx_buf != NULL) 2164 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2165 2166 while(sc->dc_mi != NULL) { 2167 m = sc->dc_mi->dc_next; 2168 free(sc->dc_mi, M_DEVBUF); 2169 sc->dc_mi = m; 2170 } 2171 2172 DC_UNLOCK(sc); 2173 mtx_destroy(&sc->dc_mtx); 2174 2175 return(0); 2176} 2177 2178/* 2179 * Initialize the transmit descriptors. 2180 */ 2181static int dc_list_tx_init(sc) 2182 struct dc_softc *sc; 2183{ 2184 struct dc_chain_data *cd; 2185 struct dc_list_data *ld; 2186 int i; 2187 2188 cd = &sc->dc_cdata; 2189 ld = sc->dc_ldata; 2190 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2191 if (i == (DC_TX_LIST_CNT - 1)) { 2192 ld->dc_tx_list[i].dc_next = 2193 vtophys(&ld->dc_tx_list[0]); 2194 } else { 2195 ld->dc_tx_list[i].dc_next = 2196 vtophys(&ld->dc_tx_list[i + 1]); 2197 } 2198 cd->dc_tx_chain[i] = NULL; 2199 ld->dc_tx_list[i].dc_data = 0; 2200 ld->dc_tx_list[i].dc_ctl = 0; 2201 } 2202 2203 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2204 2205 return(0); 2206} 2207 2208 2209/* 2210 * Initialize the RX descriptors and allocate mbufs for them. Note that 2211 * we arrange the descriptors in a closed ring, so that the last descriptor 2212 * points back to the first. 2213 */ 2214static int dc_list_rx_init(sc) 2215 struct dc_softc *sc; 2216{ 2217 struct dc_chain_data *cd; 2218 struct dc_list_data *ld; 2219 int i; 2220 2221 cd = &sc->dc_cdata; 2222 ld = sc->dc_ldata; 2223 2224 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2225 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2226 return(ENOBUFS); 2227 if (i == (DC_RX_LIST_CNT - 1)) { 2228 ld->dc_rx_list[i].dc_next = 2229 vtophys(&ld->dc_rx_list[0]); 2230 } else { 2231 ld->dc_rx_list[i].dc_next = 2232 vtophys(&ld->dc_rx_list[i + 1]); 2233 } 2234 } 2235 2236 cd->dc_rx_prod = 0; 2237 2238 return(0); 2239} 2240 2241/* 2242 * Initialize an RX descriptor and attach an MBUF cluster. 2243 */ 2244static int dc_newbuf(sc, i, m) 2245 struct dc_softc *sc; 2246 int i; 2247 struct mbuf *m; 2248{ 2249 struct mbuf *m_new = NULL; 2250 struct dc_desc *c; 2251 2252 c = &sc->dc_ldata->dc_rx_list[i]; 2253 2254 if (m == NULL) { 2255 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2256 if (m_new == NULL) { 2257 printf("dc%d: no memory for rx list " 2258 "-- packet dropped!\n", sc->dc_unit); 2259 return(ENOBUFS); 2260 } 2261 2262 MCLGET(m_new, M_DONTWAIT); 2263 if (!(m_new->m_flags & M_EXT)) { 2264 printf("dc%d: no memory for rx list " 2265 "-- packet dropped!\n", sc->dc_unit); 2266 m_freem(m_new); 2267 return(ENOBUFS); 2268 } 2269 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2270 } else { 2271 m_new = m; 2272 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2273 m_new->m_data = m_new->m_ext.ext_buf; 2274 } 2275 2276 m_adj(m_new, sizeof(u_int64_t)); 2277 2278 /* 2279 * If this is a PNIC chip, zero the buffer. This is part 2280 * of the workaround for the receive bug in the 82c168 and 2281 * 82c169 chips. 2282 */ 2283 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2284 bzero((char *)mtod(m_new, char *), m_new->m_len); 2285 2286 sc->dc_cdata.dc_rx_chain[i] = m_new; 2287 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2288 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2289 c->dc_status = DC_RXSTAT_OWN; 2290 2291 return(0); 2292} 2293 2294/* 2295 * Grrrrr. 2296 * The PNIC chip has a terrible bug in it that manifests itself during 2297 * periods of heavy activity. The exact mode of failure if difficult to 2298 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2299 * will happen on slow machines. The bug is that sometimes instead of 2300 * uploading one complete frame during reception, it uploads what looks 2301 * like the entire contents of its FIFO memory. The frame we want is at 2302 * the end of the whole mess, but we never know exactly how much data has 2303 * been uploaded, so salvaging the frame is hard. 2304 * 2305 * There is only one way to do it reliably, and it's disgusting. 2306 * Here's what we know: 2307 * 2308 * - We know there will always be somewhere between one and three extra 2309 * descriptors uploaded. 2310 * 2311 * - We know the desired received frame will always be at the end of the 2312 * total data upload. 2313 * 2314 * - We know the size of the desired received frame because it will be 2315 * provided in the length field of the status word in the last descriptor. 2316 * 2317 * Here's what we do: 2318 * 2319 * - When we allocate buffers for the receive ring, we bzero() them. 2320 * This means that we know that the buffer contents should be all 2321 * zeros, except for data uploaded by the chip. 2322 * 2323 * - We also force the PNIC chip to upload frames that include the 2324 * ethernet CRC at the end. 2325 * 2326 * - We gather all of the bogus frame data into a single buffer. 2327 * 2328 * - We then position a pointer at the end of this buffer and scan 2329 * backwards until we encounter the first non-zero byte of data. 2330 * This is the end of the received frame. We know we will encounter 2331 * some data at the end of the frame because the CRC will always be 2332 * there, so even if the sender transmits a packet of all zeros, 2333 * we won't be fooled. 2334 * 2335 * - We know the size of the actual received frame, so we subtract 2336 * that value from the current pointer location. This brings us 2337 * to the start of the actual received packet. 2338 * 2339 * - We copy this into an mbuf and pass it on, along with the actual 2340 * frame length. 2341 * 2342 * The performance hit is tremendous, but it beats dropping frames all 2343 * the time. 2344 */ 2345 2346#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2347static void dc_pnic_rx_bug_war(sc, idx) 2348 struct dc_softc *sc; 2349 int idx; 2350{ 2351 struct dc_desc *cur_rx; 2352 struct dc_desc *c = NULL; 2353 struct mbuf *m = NULL; 2354 unsigned char *ptr; 2355 int i, total_len; 2356 u_int32_t rxstat = 0; 2357 2358 i = sc->dc_pnic_rx_bug_save; 2359 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2360 ptr = sc->dc_pnic_rx_buf; 2361 bzero(ptr, sizeof(DC_RXLEN * 5)); 2362 2363 /* Copy all the bytes from the bogus buffers. */ 2364 while (1) { 2365 c = &sc->dc_ldata->dc_rx_list[i]; 2366 rxstat = c->dc_status; 2367 m = sc->dc_cdata.dc_rx_chain[i]; 2368 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2369 ptr += DC_RXLEN; 2370 /* If this is the last buffer, break out. */ 2371 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2372 break; 2373 dc_newbuf(sc, i, m); 2374 DC_INC(i, DC_RX_LIST_CNT); 2375 } 2376 2377 /* Find the length of the actual receive frame. */ 2378 total_len = DC_RXBYTES(rxstat); 2379 2380 /* Scan backwards until we hit a non-zero byte. */ 2381 while(*ptr == 0x00) 2382 ptr--; 2383 2384 /* Round off. */ 2385 if ((uintptr_t)(ptr) & 0x3) 2386 ptr -= 1; 2387 2388 /* Now find the start of the frame. */ 2389 ptr -= total_len; 2390 if (ptr < sc->dc_pnic_rx_buf) 2391 ptr = sc->dc_pnic_rx_buf; 2392 2393 /* 2394 * Now copy the salvaged frame to the last mbuf and fake up 2395 * the status word to make it look like a successful 2396 * frame reception. 2397 */ 2398 dc_newbuf(sc, i, m); 2399 bcopy(ptr, mtod(m, char *), total_len); 2400 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2401 2402 return; 2403} 2404 2405/* 2406 * This routine searches the RX ring for dirty descriptors in the 2407 * event that the rxeof routine falls out of sync with the chip's 2408 * current descriptor pointer. This may happen sometimes as a result 2409 * of a "no RX buffer available" condition that happens when the chip 2410 * consumes all of the RX buffers before the driver has a chance to 2411 * process the RX ring. This routine may need to be called more than 2412 * once to bring the driver back in sync with the chip, however we 2413 * should still be getting RX DONE interrupts to drive the search 2414 * for new packets in the RX ring, so we should catch up eventually. 2415 */ 2416static int dc_rx_resync(sc) 2417 struct dc_softc *sc; 2418{ 2419 int i, pos; 2420 struct dc_desc *cur_rx; 2421 2422 pos = sc->dc_cdata.dc_rx_prod; 2423 2424 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2425 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2426 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2427 break; 2428 DC_INC(pos, DC_RX_LIST_CNT); 2429 } 2430 2431 /* If the ring really is empty, then just return. */ 2432 if (i == DC_RX_LIST_CNT) 2433 return(0); 2434 2435 /* We've fallen behing the chip: catch it. */ 2436 sc->dc_cdata.dc_rx_prod = pos; 2437 2438 return(EAGAIN); 2439} 2440 2441/* 2442 * A frame has been uploaded: pass the resulting mbuf chain up to 2443 * the higher level protocols. 2444 */ 2445static void dc_rxeof(sc) 2446 struct dc_softc *sc; 2447{ 2448 struct ether_header *eh; 2449 struct mbuf *m; 2450 struct ifnet *ifp; 2451 struct dc_desc *cur_rx; 2452 int i, total_len = 0; 2453 u_int32_t rxstat; 2454 2455 ifp = &sc->arpcom.ac_if; 2456 i = sc->dc_cdata.dc_rx_prod; 2457 2458 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2459 struct mbuf *m0 = NULL; 2460 2461 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2462 rxstat = cur_rx->dc_status; 2463 m = sc->dc_cdata.dc_rx_chain[i]; 2464 total_len = DC_RXBYTES(rxstat); 2465 2466 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2467 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2468 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2469 sc->dc_pnic_rx_bug_save = i; 2470 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2471 DC_INC(i, DC_RX_LIST_CNT); 2472 continue; 2473 } 2474 dc_pnic_rx_bug_war(sc, i); 2475 rxstat = cur_rx->dc_status; 2476 total_len = DC_RXBYTES(rxstat); 2477 } 2478 } 2479 2480 sc->dc_cdata.dc_rx_chain[i] = NULL; 2481 2482 /* 2483 * If an error occurs, update stats, clear the 2484 * status word and leave the mbuf cluster in place: 2485 * it should simply get re-used next time this descriptor 2486 * comes up in the ring. 2487 */ 2488 if (rxstat & DC_RXSTAT_RXERR) { 2489 ifp->if_ierrors++; 2490 if (rxstat & DC_RXSTAT_COLLSEEN) 2491 ifp->if_collisions++; 2492 dc_newbuf(sc, i, m); 2493 if (rxstat & DC_RXSTAT_CRCERR) { 2494 DC_INC(i, DC_RX_LIST_CNT); 2495 continue; 2496 } else { 2497 dc_init(sc); 2498 return; 2499 } 2500 } 2501 2502 /* No errors; receive the packet. */ 2503 total_len -= ETHER_CRC_LEN; 2504 2505 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2506 total_len + ETHER_ALIGN, 0, ifp, NULL); 2507 dc_newbuf(sc, i, m); 2508 DC_INC(i, DC_RX_LIST_CNT); 2509 if (m0 == NULL) { 2510 ifp->if_ierrors++; 2511 continue; 2512 } 2513 m_adj(m0, ETHER_ALIGN); 2514 m = m0; 2515 2516 ifp->if_ipackets++; 2517 eh = mtod(m, struct ether_header *); 2518 2519 /* Remove header from mbuf and pass it on. */ 2520 m_adj(m, sizeof(struct ether_header)); 2521 ether_input(ifp, eh, m); 2522 } 2523 2524 sc->dc_cdata.dc_rx_prod = i; 2525} 2526 2527/* 2528 * A frame was downloaded to the chip. It's safe for us to clean up 2529 * the list buffers. 2530 */ 2531 2532static void dc_txeof(sc) 2533 struct dc_softc *sc; 2534{ 2535 struct dc_desc *cur_tx = NULL; 2536 struct ifnet *ifp; 2537 int idx; 2538 2539 ifp = &sc->arpcom.ac_if; 2540 2541 /* Clear the timeout timer. */ 2542 ifp->if_timer = 0; 2543 2544 /* 2545 * Go through our tx list and free mbufs for those 2546 * frames that have been transmitted. 2547 */ 2548 idx = sc->dc_cdata.dc_tx_cons; 2549 while(idx != sc->dc_cdata.dc_tx_prod) { 2550 u_int32_t txstat; 2551 2552 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2553 txstat = cur_tx->dc_status; 2554 2555 if (txstat & DC_TXSTAT_OWN) 2556 break; 2557 2558 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2559 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2560 sc->dc_cdata.dc_tx_cnt--; 2561 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2562 /* 2563 * Yes, the PNIC is so brain damaged 2564 * that it will sometimes generate a TX 2565 * underrun error while DMAing the RX 2566 * filter setup frame. If we detect this, 2567 * we have to send the setup frame again, 2568 * or else the filter won't be programmed 2569 * correctly. 2570 */ 2571 if (DC_IS_PNIC(sc)) { 2572 if (txstat & DC_TXSTAT_ERRSUM) 2573 dc_setfilt(sc); 2574 } 2575 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2576 } 2577 DC_INC(idx, DC_TX_LIST_CNT); 2578 continue; 2579 } 2580 2581 if (DC_IS_XIRCOM(sc)) { 2582 /* 2583 * XXX: Why does my Xircom taunt me so? 2584 * For some reason it likes setting the CARRLOST flag 2585 * even when the carrier is there. wtf?!? */ 2586 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2587 sc->dc_pmode == DC_PMODE_MII && 2588 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2589 DC_TXSTAT_NOCARRIER))) 2590 txstat &= ~DC_TXSTAT_ERRSUM; 2591 } else { 2592 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2593 sc->dc_pmode == DC_PMODE_MII && 2594 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2595 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2596 txstat &= ~DC_TXSTAT_ERRSUM; 2597 } 2598 2599 if (txstat & DC_TXSTAT_ERRSUM) { 2600 ifp->if_oerrors++; 2601 if (txstat & DC_TXSTAT_EXCESSCOLL) 2602 ifp->if_collisions++; 2603 if (txstat & DC_TXSTAT_LATECOLL) 2604 ifp->if_collisions++; 2605 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2606 dc_init(sc); 2607 return; 2608 } 2609 } 2610 2611 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2612 2613 ifp->if_opackets++; 2614 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2615 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2616 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2617 } 2618 2619 sc->dc_cdata.dc_tx_cnt--; 2620 DC_INC(idx, DC_TX_LIST_CNT); 2621 } 2622 2623 sc->dc_cdata.dc_tx_cons = idx; 2624 if (cur_tx != NULL) 2625 ifp->if_flags &= ~IFF_OACTIVE; 2626 2627 return; 2628} 2629 2630static void dc_tick(xsc) 2631 void *xsc; 2632{ 2633 struct dc_softc *sc; 2634 struct mii_data *mii; 2635 struct ifnet *ifp; 2636 u_int32_t r; 2637 2638 sc = xsc; 2639 DC_LOCK(sc); 2640 ifp = &sc->arpcom.ac_if; 2641 mii = device_get_softc(sc->dc_miibus); 2642 2643 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2644 if (sc->dc_flags & DC_21143_NWAY) { 2645 r = CSR_READ_4(sc, DC_10BTSTAT); 2646 if (IFM_SUBTYPE(mii->mii_media_active) == 2647 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2648 sc->dc_link = 0; 2649 mii_mediachg(mii); 2650 } 2651 if (IFM_SUBTYPE(mii->mii_media_active) == 2652 IFM_10_T && (r & DC_TSTAT_LS10)) { 2653 sc->dc_link = 0; 2654 mii_mediachg(mii); 2655 } 2656 if (sc->dc_link == 0) 2657 mii_tick(mii); 2658 } else { 2659 r = CSR_READ_4(sc, DC_ISR); 2660 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2661 sc->dc_cdata.dc_tx_cnt == 0) 2662 mii_tick(mii); 2663 if (!(mii->mii_media_status & IFM_ACTIVE)) 2664 sc->dc_link = 0; 2665 } 2666 } else 2667 mii_tick(mii); 2668 2669 /* 2670 * When the init routine completes, we expect to be able to send 2671 * packets right away, and in fact the network code will send a 2672 * gratuitous ARP the moment the init routine marks the interface 2673 * as running. However, even though the MAC may have been initialized, 2674 * there may be a delay of a few seconds before the PHY completes 2675 * autonegotiation and the link is brought up. Any transmissions 2676 * made during that delay will be lost. Dealing with this is tricky: 2677 * we can't just pause in the init routine while waiting for the 2678 * PHY to come ready since that would bring the whole system to 2679 * a screeching halt for several seconds. 2680 * 2681 * What we do here is prevent the TX start routine from sending 2682 * any packets until a link has been established. After the 2683 * interface has been initialized, the tick routine will poll 2684 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2685 * that time, packets will stay in the send queue, and once the 2686 * link comes up, they will be flushed out to the wire. 2687 */ 2688 if (!sc->dc_link) { 2689 mii_pollstat(mii); 2690 if (mii->mii_media_status & IFM_ACTIVE && 2691 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2692 sc->dc_link++; 2693 if (ifp->if_snd.ifq_head != NULL) 2694 dc_start(ifp); 2695 } 2696 } 2697 2698 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2699 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2700 else 2701 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2702 2703 DC_UNLOCK(sc); 2704 2705 return; 2706} 2707 2708static void dc_intr(arg) 2709 void *arg; 2710{ 2711 struct dc_softc *sc; 2712 struct ifnet *ifp; 2713 u_int32_t status; 2714 2715 sc = arg; 2716 2717 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2718 return ; 2719 2720 DC_LOCK(sc); 2721 ifp = &sc->arpcom.ac_if; 2722 2723 /* Suppress unwanted interrupts */ 2724 if (!(ifp->if_flags & IFF_UP)) { 2725 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2726 dc_stop(sc); 2727 DC_UNLOCK(sc); 2728 return; 2729 } 2730 2731 /* Disable interrupts. */ 2732 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2733 2734 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2735 && status != 0xFFFFFFFF) { 2736 2737 CSR_WRITE_4(sc, DC_ISR, status); 2738 2739 if (status & DC_ISR_RX_OK) { 2740 int curpkts; 2741 curpkts = ifp->if_ipackets; 2742 dc_rxeof(sc); 2743 if (curpkts == ifp->if_ipackets) { 2744 while(dc_rx_resync(sc)) 2745 dc_rxeof(sc); 2746 } 2747 } 2748 2749 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2750 dc_txeof(sc); 2751 2752 if (status & DC_ISR_TX_IDLE) { 2753 dc_txeof(sc); 2754 if (sc->dc_cdata.dc_tx_cnt) { 2755 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2756 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2757 } 2758 } 2759 2760 if (status & DC_ISR_TX_UNDERRUN) { 2761 u_int32_t cfg; 2762 2763 printf("dc%d: TX underrun -- ", sc->dc_unit); 2764 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2765 dc_init(sc); 2766 cfg = CSR_READ_4(sc, DC_NETCFG); 2767 cfg &= ~DC_NETCFG_TX_THRESH; 2768 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2769 printf("using store and forward mode\n"); 2770 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2771 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2772 printf("resetting\n"); 2773 } else { 2774 sc->dc_txthresh += 0x4000; 2775 printf("increasing TX threshold\n"); 2776 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2777 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2778 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2779 } 2780 } 2781 2782 if ((status & DC_ISR_RX_WATDOGTIMEO) 2783 || (status & DC_ISR_RX_NOBUF)) { 2784 int curpkts; 2785 curpkts = ifp->if_ipackets; 2786 dc_rxeof(sc); 2787 if (curpkts == ifp->if_ipackets) { 2788 while(dc_rx_resync(sc)) 2789 dc_rxeof(sc); 2790 } 2791 } 2792 2793 if (status & DC_ISR_BUS_ERR) { 2794 dc_reset(sc); 2795 dc_init(sc); 2796 } 2797 } 2798 2799 /* Re-enable interrupts. */ 2800 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2801 2802 if (ifp->if_snd.ifq_head != NULL) 2803 dc_start(ifp); 2804 2805 DC_UNLOCK(sc); 2806 2807 return; 2808} 2809 2810/* 2811 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2812 * pointers to the fragment pointers. 2813 */ 2814static int dc_encap(sc, m_head, txidx) 2815 struct dc_softc *sc; 2816 struct mbuf *m_head; 2817 u_int32_t *txidx; 2818{ 2819 struct dc_desc *f = NULL; 2820 struct mbuf *m; 2821 int frag, cur, cnt = 0; 2822 2823 /* 2824 * Start packing the mbufs in this chain into 2825 * the fragment pointers. Stop when we run out 2826 * of fragments or hit the end of the mbuf chain. 2827 */ 2828 m = m_head; 2829 cur = frag = *txidx; 2830 2831 for (m = m_head; m != NULL; m = m->m_next) { 2832 if (m->m_len != 0) { 2833 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2834 if (*txidx != sc->dc_cdata.dc_tx_prod && 2835 frag == (DC_TX_LIST_CNT - 1)) 2836 return(ENOBUFS); 2837 } 2838 if ((DC_TX_LIST_CNT - 2839 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2840 return(ENOBUFS); 2841 2842 f = &sc->dc_ldata->dc_tx_list[frag]; 2843 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2844 if (cnt == 0) { 2845 f->dc_status = 0; 2846 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2847 } else 2848 f->dc_status = DC_TXSTAT_OWN; 2849 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2850 cur = frag; 2851 DC_INC(frag, DC_TX_LIST_CNT); 2852 cnt++; 2853 } 2854 } 2855 2856 if (m != NULL) 2857 return(ENOBUFS); 2858 2859 sc->dc_cdata.dc_tx_cnt += cnt; 2860 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2861 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2862 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2863 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2864 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2865 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2866 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2867 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2868 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2869 *txidx = frag; 2870 2871 return(0); 2872} 2873 2874/* 2875 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2876 * Needed for some really badly behaved chips that just can't 2877 * do scatter/gather correctly. 2878 */ 2879static int dc_coal(sc, m_head) 2880 struct dc_softc *sc; 2881 struct mbuf **m_head; 2882{ 2883 struct mbuf *m_new, *m; 2884 2885 m = *m_head; 2886 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2887 if (m_new == NULL) { 2888 printf("dc%d: no memory for tx list", sc->dc_unit); 2889 return(ENOBUFS); 2890 } 2891 if (m->m_pkthdr.len > MHLEN) { 2892 MCLGET(m_new, M_DONTWAIT); 2893 if (!(m_new->m_flags & M_EXT)) { 2894 m_freem(m_new); 2895 printf("dc%d: no memory for tx list", sc->dc_unit); 2896 return(ENOBUFS); 2897 } 2898 } 2899 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2900 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2901 m_freem(m); 2902 *m_head = m_new; 2903 2904 return(0); 2905} 2906 2907/* 2908 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2909 * to the mbuf data regions directly in the transmit lists. We also save a 2910 * copy of the pointers since the transmit list fragment pointers are 2911 * physical addresses. 2912 */ 2913 2914static void dc_start(ifp) 2915 struct ifnet *ifp; 2916{ 2917 struct dc_softc *sc; 2918 struct mbuf *m_head = NULL; 2919 int idx; 2920 2921 sc = ifp->if_softc; 2922 2923 DC_LOCK(sc); 2924 2925 if (!sc->dc_link) { 2926 DC_UNLOCK(sc); 2927 return; 2928 } 2929 2930 if (ifp->if_flags & IFF_OACTIVE) { 2931 DC_UNLOCK(sc); 2932 return; 2933 } 2934 2935 idx = sc->dc_cdata.dc_tx_prod; 2936 2937 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2938 IF_DEQUEUE(&ifp->if_snd, m_head); 2939 if (m_head == NULL) 2940 break; 2941 2942 if (sc->dc_flags & DC_TX_COALESCE) { 2943 if (dc_coal(sc, &m_head)) { 2944 IF_PREPEND(&ifp->if_snd, m_head); 2945 ifp->if_flags |= IFF_OACTIVE; 2946 break; 2947 } 2948 } 2949 2950 if (dc_encap(sc, m_head, &idx)) { 2951 IF_PREPEND(&ifp->if_snd, m_head); 2952 ifp->if_flags |= IFF_OACTIVE; 2953 break; 2954 } 2955 2956 /* 2957 * If there's a BPF listener, bounce a copy of this frame 2958 * to him. 2959 */ 2960 if (ifp->if_bpf) 2961 bpf_mtap(ifp, m_head); 2962 2963 if (sc->dc_flags & DC_TX_ONE) { 2964 ifp->if_flags |= IFF_OACTIVE; 2965 break; 2966 } 2967 } 2968 2969 /* Transmit */ 2970 sc->dc_cdata.dc_tx_prod = idx; 2971 if (!(sc->dc_flags & DC_TX_POLL)) 2972 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2973 2974 /* 2975 * Set a timeout in case the chip goes out to lunch. 2976 */ 2977 ifp->if_timer = 5; 2978 2979 DC_UNLOCK(sc); 2980 2981 return; 2982} 2983 2984static void dc_init(xsc) 2985 void *xsc; 2986{ 2987 struct dc_softc *sc = xsc; 2988 struct ifnet *ifp = &sc->arpcom.ac_if; 2989 struct mii_data *mii; 2990 2991 DC_LOCK(sc); 2992 2993 mii = device_get_softc(sc->dc_miibus); 2994 2995 /* 2996 * Cancel pending I/O and free all RX/TX buffers. 2997 */ 2998 dc_stop(sc); 2999 dc_reset(sc); 3000 3001 /* 3002 * Set cache alignment and burst length. 3003 */ 3004 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3005 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3006 else 3007 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3008 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3009 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3010 } else { 3011 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3012 } 3013 if (sc->dc_flags & DC_TX_POLL) 3014 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3015 switch(sc->dc_cachesize) { 3016 case 32: 3017 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3018 break; 3019 case 16: 3020 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3021 break; 3022 case 8: 3023 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3024 break; 3025 case 0: 3026 default: 3027 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3028 break; 3029 } 3030 3031 if (sc->dc_flags & DC_TX_STORENFWD) 3032 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3033 else { 3034 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 3035 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3036 } else { 3037 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3038 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3039 } 3040 } 3041 3042 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3043 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3044 3045 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3046 /* 3047 * The app notes for the 98713 and 98715A say that 3048 * in order to have the chips operate properly, a magic 3049 * number must be written to CSR16. Macronix does not 3050 * document the meaning of these bits so there's no way 3051 * to know exactly what they do. The 98713 has a magic 3052 * number all its own; the rest all use a different one. 3053 */ 3054 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3055 if (sc->dc_type == DC_TYPE_98713) 3056 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3057 else 3058 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3059 } 3060 3061 if (DC_IS_XIRCOM(sc)) { 3062 /* 3063 * setup General Purpose Port mode and data so the tulip 3064 * can talk to the MII. 3065 */ 3066 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3067 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3068 DELAY(10); 3069 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3070 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3071 DELAY(10); 3072 } 3073 3074 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3075 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 3076 3077 /* Init circular RX list. */ 3078 if (dc_list_rx_init(sc) == ENOBUFS) { 3079 printf("dc%d: initialization failed: no " 3080 "memory for rx buffers\n", sc->dc_unit); 3081 dc_stop(sc); 3082 DC_UNLOCK(sc); 3083 return; 3084 } 3085 3086 /* 3087 * Init tx descriptors. 3088 */ 3089 dc_list_tx_init(sc); 3090 3091 /* 3092 * Load the address of the RX list. 3093 */ 3094 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3095 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3096 3097 /* 3098 * Enable interrupts. 3099 */ 3100 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3101 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3102 3103 /* Enable transmitter. */ 3104 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3105 3106 /* 3107 * If this is an Intel 21143 and we're not using the 3108 * MII port, program the LED control pins so we get 3109 * link and activity indications. 3110 */ 3111 if (sc->dc_flags & DC_TULIP_LEDS) { 3112 CSR_WRITE_4(sc, DC_WATCHDOG, 3113 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3114 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3115 } 3116 3117 /* 3118 * Load the RX/multicast filter. We do this sort of late 3119 * because the filter programming scheme on the 21143 and 3120 * some clones requires DMAing a setup frame via the TX 3121 * engine, and we need the transmitter enabled for that. 3122 */ 3123 dc_setfilt(sc); 3124 3125 /* Enable receiver. */ 3126 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3127 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3128 3129 mii_mediachg(mii); 3130 dc_setcfg(sc, sc->dc_if_media); 3131 3132 ifp->if_flags |= IFF_RUNNING; 3133 ifp->if_flags &= ~IFF_OACTIVE; 3134 3135 /* Don't start the ticker if this is a homePNA link. */ 3136 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3137 sc->dc_link = 1; 3138 else { 3139 if (sc->dc_flags & DC_21143_NWAY) 3140 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3141 else 3142 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3143 } 3144 3145#ifdef SRM_MEDIA 3146 if(sc->dc_srm_media) { 3147 struct ifreq ifr; 3148 3149 ifr.ifr_media = sc->dc_srm_media; 3150 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3151 sc->dc_srm_media = 0; 3152 } 3153#endif 3154 DC_UNLOCK(sc); 3155 return; 3156} 3157 3158/* 3159 * Set media options. 3160 */ 3161static int dc_ifmedia_upd(ifp) 3162 struct ifnet *ifp; 3163{ 3164 struct dc_softc *sc; 3165 struct mii_data *mii; 3166 struct ifmedia *ifm; 3167 3168 sc = ifp->if_softc; 3169 mii = device_get_softc(sc->dc_miibus); 3170 mii_mediachg(mii); 3171 ifm = &mii->mii_media; 3172 3173 if (DC_IS_DAVICOM(sc) && 3174 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3175 dc_setcfg(sc, ifm->ifm_media); 3176 else 3177 sc->dc_link = 0; 3178 3179 return(0); 3180} 3181 3182/* 3183 * Report current media status. 3184 */ 3185static void dc_ifmedia_sts(ifp, ifmr) 3186 struct ifnet *ifp; 3187 struct ifmediareq *ifmr; 3188{ 3189 struct dc_softc *sc; 3190 struct mii_data *mii; 3191 struct ifmedia *ifm; 3192 3193 sc = ifp->if_softc; 3194 mii = device_get_softc(sc->dc_miibus); 3195 mii_pollstat(mii); 3196 ifm = &mii->mii_media; 3197 if (DC_IS_DAVICOM(sc)) { 3198 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3199 ifmr->ifm_active = ifm->ifm_media; 3200 ifmr->ifm_status = 0; 3201 return; 3202 } 3203 } 3204 ifmr->ifm_active = mii->mii_media_active; 3205 ifmr->ifm_status = mii->mii_media_status; 3206 3207 return; 3208} 3209 3210static int dc_ioctl(ifp, command, data) 3211 struct ifnet *ifp; 3212 u_long command; 3213 caddr_t data; 3214{ 3215 struct dc_softc *sc = ifp->if_softc; 3216 struct ifreq *ifr = (struct ifreq *) data; 3217 struct mii_data *mii; 3218 int error = 0; 3219 3220 DC_LOCK(sc); 3221 3222 switch(command) { 3223 case SIOCSIFADDR: 3224 case SIOCGIFADDR: 3225 case SIOCSIFMTU: 3226 error = ether_ioctl(ifp, command, data); 3227 break; 3228 case SIOCSIFFLAGS: 3229 if (ifp->if_flags & IFF_UP) { 3230 if (ifp->if_flags & IFF_RUNNING && 3231 ifp->if_flags & IFF_PROMISC && 3232 !(sc->dc_if_flags & IFF_PROMISC)) { 3233 dc_setfilt(sc); 3234 } else if (ifp->if_flags & IFF_RUNNING && 3235 !(ifp->if_flags & IFF_PROMISC) && 3236 sc->dc_if_flags & IFF_PROMISC) { 3237 dc_setfilt(sc); 3238 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3239 sc->dc_txthresh = 0; 3240 dc_init(sc); 3241 } 3242 } else { 3243 if (ifp->if_flags & IFF_RUNNING) 3244 dc_stop(sc); 3245 } 3246 sc->dc_if_flags = ifp->if_flags; 3247 error = 0; 3248 break; 3249 case SIOCADDMULTI: 3250 case SIOCDELMULTI: 3251 dc_setfilt(sc); 3252 error = 0; 3253 break; 3254 case SIOCGIFMEDIA: 3255 case SIOCSIFMEDIA: 3256 mii = device_get_softc(sc->dc_miibus); 3257 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3258#ifdef SRM_MEDIA 3259 if (sc->dc_srm_media) 3260 sc->dc_srm_media = 0; 3261#endif 3262 break; 3263 default: 3264 error = EINVAL; 3265 break; 3266 } 3267 3268 DC_UNLOCK(sc); 3269 3270 return(error); 3271} 3272 3273static void dc_watchdog(ifp) 3274 struct ifnet *ifp; 3275{ 3276 struct dc_softc *sc; 3277 3278 sc = ifp->if_softc; 3279 3280 DC_LOCK(sc); 3281 3282 ifp->if_oerrors++; 3283 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3284 3285 dc_stop(sc); 3286 dc_reset(sc); 3287 dc_init(sc); 3288 3289 if (ifp->if_snd.ifq_head != NULL) 3290 dc_start(ifp); 3291 3292 DC_UNLOCK(sc); 3293 3294 return; 3295} 3296 3297/* 3298 * Stop the adapter and free any mbufs allocated to the 3299 * RX and TX lists. 3300 */ 3301static void dc_stop(sc) 3302 struct dc_softc *sc; 3303{ 3304 register int i; 3305 struct ifnet *ifp; 3306 3307 DC_LOCK(sc); 3308 3309 ifp = &sc->arpcom.ac_if; 3310 ifp->if_timer = 0; 3311 3312 callout_stop(&sc->dc_stat_ch); 3313 3314 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3315 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3316 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3317 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3318 sc->dc_link = 0; 3319 3320 /* 3321 * Free data in the RX lists. 3322 */ 3323 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3324 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3325 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3326 sc->dc_cdata.dc_rx_chain[i] = NULL; 3327 } 3328 } 3329 bzero((char *)&sc->dc_ldata->dc_rx_list, 3330 sizeof(sc->dc_ldata->dc_rx_list)); 3331 3332 /* 3333 * Free the TX list buffers. 3334 */ 3335 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3336 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3337 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3338 DC_TXCTL_SETUP) { 3339 sc->dc_cdata.dc_tx_chain[i] = NULL; 3340 continue; 3341 } 3342 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3343 sc->dc_cdata.dc_tx_chain[i] = NULL; 3344 } 3345 } 3346 3347 bzero((char *)&sc->dc_ldata->dc_tx_list, 3348 sizeof(sc->dc_ldata->dc_tx_list)); 3349 3350 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3351 3352 DC_UNLOCK(sc); 3353 3354 return; 3355} 3356 3357/* 3358 * Stop all chip I/O so that the kernel's probe routines don't 3359 * get confused by errant DMAs when rebooting. 3360 */ 3361static void dc_shutdown(dev) 3362 device_t dev; 3363{ 3364 struct dc_softc *sc; 3365 3366 sc = device_get_softc(dev); 3367 3368 dc_stop(sc); 3369 3370 return; 3371} 3372