if_dc.c revision 68725
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/dc/if_dc.c 68725 2000-11-14 19:35:22Z wpaul $ 33 */ 34 35/* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * 51 * Datasheets for the 21143 are available at developer.intel.com. 52 * Datasheets for the clone parts can be found at their respective sites. 53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 54 * The PNIC II is essentially a Macronix 98715A chip; the only difference 55 * worth noting is that its multicast hash table is only 128 bits wide 56 * instead of 512. 57 * 58 * Written by Bill Paul <wpaul@ee.columbia.edu> 59 * Electrical Engineering Department 60 * Columbia University, New York City 61 */ 62 63/* 64 * The Intel 21143 is the successor to the DEC 21140. It is basically 65 * the same as the 21140 but with a few new features. The 21143 supports 66 * three kinds of media attachments: 67 * 68 * o MII port, for 10Mbps and 100Mbps support and NWAY 69 * autonegotiation provided by an external PHY. 70 * o SYM port, for symbol mode 100Mbps support. 71 * o 10baseT port. 72 * o AUI/BNC port. 73 * 74 * The 100Mbps SYM port and 10baseT port can be used together in 75 * combination with the internal NWAY support to create a 10/100 76 * autosensing configuration. 77 * 78 * Note that not all tulip workalikes are handled in this driver: we only 79 * deal with those which are relatively well behaved. The Winbond is 80 * handled separately due to its different register offsets and the 81 * special handling needed for its various bugs. The PNIC is handled 82 * here, but I'm not thrilled about it. 83 * 84 * All of the workalike chips use some form of MII transceiver support 85 * with the exception of the Macronix chips, which also have a SYM port. 86 * The ASIX AX88140A is also documented to have a SYM port, but all 87 * the cards I've seen use an MII transceiver, probably because the 88 * AX88140A doesn't support internal NWAY. 89 */ 90 91#include <sys/param.h> 92#include <sys/systm.h> 93#include <sys/sockio.h> 94#include <sys/mbuf.h> 95#include <sys/malloc.h> 96#include <sys/kernel.h> 97#include <sys/socket.h> 98 99#include <net/if.h> 100#include <net/if_arp.h> 101#include <net/ethernet.h> 102#include <net/if_dl.h> 103#include <net/if_media.h> 104 105#include <net/bpf.h> 106 107#include <vm/vm.h> /* for vtophys */ 108#include <vm/pmap.h> /* for vtophys */ 109#include <machine/bus_pio.h> 110#include <machine/bus_memio.h> 111#include <machine/bus.h> 112#include <machine/resource.h> 113#include <sys/bus.h> 114#include <sys/rman.h> 115 116#include <dev/mii/mii.h> 117#include <dev/mii/miivar.h> 118 119#include <pci/pcireg.h> 120#include <pci/pcivar.h> 121 122#define DC_USEIOSPACE 123#ifdef __alpha__ 124#define SRM_MEDIA 125#endif 126 127#include <pci/if_dcreg.h> 128 129MODULE_DEPEND(dc, miibus, 1, 1, 1); 130 131/* "controller miibus0" required. See GENERIC if you get errors here. */ 132#include "miibus_if.h" 133 134#ifndef lint 135static const char rcsid[] = 136 "$FreeBSD: head/sys/dev/dc/if_dc.c 68725 2000-11-14 19:35:22Z wpaul $"; 137#endif 138 139/* 140 * Various supported device vendors/types and their names. 141 */ 142static struct dc_type dc_devs[] = { 143 { DC_VENDORID_DEC, DC_DEVICEID_21143, 144 "Intel 21143 10/100BaseTX" }, 145 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 146 "Davicom DM9100 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 148 "Davicom DM9102 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 150 "Davicom DM9102A 10/100BaseTX" }, 151 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 152 "ADMtek AL981 10/100BaseTX" }, 153 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 154 "ADMtek AN985 10/100BaseTX" }, 155 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 156 "ASIX AX88140A 10/100BaseTX" }, 157 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 158 "ASIX AX88141 10/100BaseTX" }, 159 { DC_VENDORID_MX, DC_DEVICEID_98713, 160 "Macronix 98713 10/100BaseTX" }, 161 { DC_VENDORID_MX, DC_DEVICEID_98713, 162 "Macronix 98713A 10/100BaseTX" }, 163 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 164 "Compex RL100-TX 10/100BaseTX" }, 165 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 166 "Compex RL100-TX 10/100BaseTX" }, 167 { DC_VENDORID_MX, DC_DEVICEID_987x5, 168 "Macronix 98715/98715A 10/100BaseTX" }, 169 { DC_VENDORID_MX, DC_DEVICEID_987x5, 170 "Macronix 98715AEC-C 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98725 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_98727, 174 "Macronix 98727/98732 10/100BaseTX" }, 175 { DC_VENDORID_LO, DC_DEVICEID_82C115, 176 "LC82C115 PNIC II 10/100BaseTX" }, 177 { DC_VENDORID_LO, DC_DEVICEID_82C168, 178 "82c168 PNIC 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C168, 180 "82c169 PNIC 10/100BaseTX" }, 181 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 182 "Accton EN1217 10/100BaseTX" }, 183 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 184 "Accton EN2242 MiniPCI 10/100BaseTX" }, 185 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 186 "Xircom X3201 10/100BaseTX" }, 187 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 188 "Abocom FE2500 10/100BaseTX" }, 189 { 0, 0, NULL } 190}; 191 192static int dc_probe __P((device_t)); 193static int dc_attach __P((device_t)); 194static int dc_detach __P((device_t)); 195static void dc_acpi __P((device_t)); 196static struct dc_type *dc_devtype __P((device_t)); 197static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 198static int dc_encap __P((struct dc_softc *, struct mbuf *, 199 u_int32_t *)); 200static int dc_coal __P((struct dc_softc *, struct mbuf **)); 201static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 202static int dc_rx_resync __P((struct dc_softc *)); 203static void dc_rxeof __P((struct dc_softc *)); 204static void dc_txeof __P((struct dc_softc *)); 205static void dc_tick __P((void *)); 206static void dc_intr __P((void *)); 207static void dc_start __P((struct ifnet *)); 208static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 209static void dc_init __P((void *)); 210static void dc_stop __P((struct dc_softc *)); 211static void dc_watchdog __P((struct ifnet *)); 212static void dc_shutdown __P((device_t)); 213static int dc_ifmedia_upd __P((struct ifnet *)); 214static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 215 216static void dc_delay __P((struct dc_softc *)); 217static void dc_eeprom_idle __P((struct dc_softc *)); 218static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 219static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 220static void dc_eeprom_getword_pnic 221 __P((struct dc_softc *, int, u_int16_t *)); 222static void dc_eeprom_getword_xircom 223 __P((struct dc_softc *, int, u_int16_t *)); 224static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 225 int, int)); 226 227static void dc_mii_writebit __P((struct dc_softc *, int)); 228static int dc_mii_readbit __P((struct dc_softc *)); 229static void dc_mii_sync __P((struct dc_softc *)); 230static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 231static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 232static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 233static int dc_miibus_readreg __P((device_t, int, int)); 234static int dc_miibus_writereg __P((device_t, int, int, int)); 235static void dc_miibus_statchg __P((device_t)); 236static void dc_miibus_mediainit __P((device_t)); 237 238static void dc_setcfg __P((struct dc_softc *, int)); 239static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 240static u_int32_t dc_crc_be __P((caddr_t)); 241static void dc_setfilt_21143 __P((struct dc_softc *)); 242static void dc_setfilt_asix __P((struct dc_softc *)); 243static void dc_setfilt_admtek __P((struct dc_softc *)); 244static void dc_setfilt_xircom __P((struct dc_softc *)); 245 246static void dc_setfilt __P((struct dc_softc *)); 247 248static void dc_reset __P((struct dc_softc *)); 249static int dc_list_rx_init __P((struct dc_softc *)); 250static int dc_list_tx_init __P((struct dc_softc *)); 251 252static void dc_parse_21143_srom __P((struct dc_softc *)); 253static void dc_decode_leaf_sia __P((struct dc_softc *, 254 struct dc_eblock_sia *)); 255static void dc_decode_leaf_mii __P((struct dc_softc *, 256 struct dc_eblock_mii *)); 257static void dc_decode_leaf_sym __P((struct dc_softc *, 258 struct dc_eblock_sym *)); 259static void dc_apply_fixup __P((struct dc_softc *, int)); 260 261#ifdef DC_USEIOSPACE 262#define DC_RES SYS_RES_IOPORT 263#define DC_RID DC_PCI_CFBIO 264#else 265#define DC_RES SYS_RES_MEMORY 266#define DC_RID DC_PCI_CFBMA 267#endif 268 269static device_method_t dc_methods[] = { 270 /* Device interface */ 271 DEVMETHOD(device_probe, dc_probe), 272 DEVMETHOD(device_attach, dc_attach), 273 DEVMETHOD(device_detach, dc_detach), 274 DEVMETHOD(device_shutdown, dc_shutdown), 275 276 /* bus interface */ 277 DEVMETHOD(bus_print_child, bus_generic_print_child), 278 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 279 280 /* MII interface */ 281 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 282 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 283 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 284 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 285 286 { 0, 0 } 287}; 288 289static driver_t dc_driver = { 290 "dc", 291 dc_methods, 292 sizeof(struct dc_softc) 293}; 294 295static devclass_t dc_devclass; 296 297DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 298DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 299DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 300 301#define DC_SETBIT(sc, reg, x) \ 302 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 303 304#define DC_CLRBIT(sc, reg, x) \ 305 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 306 307#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 308#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 309 310static void dc_delay(sc) 311 struct dc_softc *sc; 312{ 313 int idx; 314 315 for (idx = (300 / 33) + 1; idx > 0; idx--) 316 CSR_READ_4(sc, DC_BUSCTL); 317} 318 319static void dc_eeprom_idle(sc) 320 struct dc_softc *sc; 321{ 322 register int i; 323 324 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 325 dc_delay(sc); 326 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 327 dc_delay(sc); 328 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 329 dc_delay(sc); 330 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 331 dc_delay(sc); 332 333 for (i = 0; i < 25; i++) { 334 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 335 dc_delay(sc); 336 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 337 dc_delay(sc); 338 } 339 340 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 341 dc_delay(sc); 342 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 343 dc_delay(sc); 344 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 345 346 return; 347} 348 349/* 350 * Send a read command and address to the EEPROM, check for ACK. 351 */ 352static void dc_eeprom_putbyte(sc, addr) 353 struct dc_softc *sc; 354 int addr; 355{ 356 register int d, i; 357 358 /* 359 * The AN985 has a 93C66 EEPROM on it instead of 360 * a 93C46. It uses a different bit sequence for 361 * specifying the "read" opcode. 362 */ 363 if (DC_IS_CENTAUR(sc)) 364 d = addr | (DC_EECMD_READ << 2); 365 else 366 d = addr | DC_EECMD_READ; 367 368 /* 369 * Feed in each bit and strobe the clock. 370 */ 371 for (i = 0x400; i; i >>= 1) { 372 if (d & i) { 373 SIO_SET(DC_SIO_EE_DATAIN); 374 } else { 375 SIO_CLR(DC_SIO_EE_DATAIN); 376 } 377 dc_delay(sc); 378 SIO_SET(DC_SIO_EE_CLK); 379 dc_delay(sc); 380 SIO_CLR(DC_SIO_EE_CLK); 381 dc_delay(sc); 382 } 383 384 return; 385} 386 387/* 388 * Read a word of data stored in the EEPROM at address 'addr.' 389 * The PNIC 82c168/82c169 has its own non-standard way to read 390 * the EEPROM. 391 */ 392static void dc_eeprom_getword_pnic(sc, addr, dest) 393 struct dc_softc *sc; 394 int addr; 395 u_int16_t *dest; 396{ 397 register int i; 398 u_int32_t r; 399 400 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 401 402 for (i = 0; i < DC_TIMEOUT; i++) { 403 DELAY(1); 404 r = CSR_READ_4(sc, DC_SIO); 405 if (!(r & DC_PN_SIOCTL_BUSY)) { 406 *dest = (u_int16_t)(r & 0xFFFF); 407 return; 408 } 409 } 410 411 return; 412} 413 414/* 415 * Read a word of data stored in the EEPROM at address 'addr.' 416 * The Xircom X3201 has its own non-standard way to read 417 * the EEPROM, too. 418 */ 419static void dc_eeprom_getword_xircom(sc, addr, dest) 420 struct dc_softc *sc; 421 int addr; 422 u_int16_t *dest; 423{ 424 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 425 426 addr *= 2; 427 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 428 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 429 addr += 1; 430 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 431 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 432 433 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 434 return; 435} 436 437/* 438 * Read a word of data stored in the EEPROM at address 'addr.' 439 */ 440static void dc_eeprom_getword(sc, addr, dest) 441 struct dc_softc *sc; 442 int addr; 443 u_int16_t *dest; 444{ 445 register int i; 446 u_int16_t word = 0; 447 448 /* Force EEPROM to idle state. */ 449 dc_eeprom_idle(sc); 450 451 /* Enter EEPROM access mode. */ 452 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 453 dc_delay(sc); 454 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 455 dc_delay(sc); 456 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 457 dc_delay(sc); 458 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 459 dc_delay(sc); 460 461 /* 462 * Send address of word we want to read. 463 */ 464 dc_eeprom_putbyte(sc, addr); 465 466 /* 467 * Start reading bits from EEPROM. 468 */ 469 for (i = 0x8000; i; i >>= 1) { 470 SIO_SET(DC_SIO_EE_CLK); 471 dc_delay(sc); 472 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 473 word |= i; 474 dc_delay(sc); 475 SIO_CLR(DC_SIO_EE_CLK); 476 dc_delay(sc); 477 } 478 479 /* Turn off EEPROM access mode. */ 480 dc_eeprom_idle(sc); 481 482 *dest = word; 483 484 return; 485} 486 487/* 488 * Read a sequence of words from the EEPROM. 489 */ 490static void dc_read_eeprom(sc, dest, off, cnt, swap) 491 struct dc_softc *sc; 492 caddr_t dest; 493 int off; 494 int cnt; 495 int swap; 496{ 497 int i; 498 u_int16_t word = 0, *ptr; 499 500 for (i = 0; i < cnt; i++) { 501 if (DC_IS_PNIC(sc)) 502 dc_eeprom_getword_pnic(sc, off + i, &word); 503 else if (DC_IS_XIRCOM(sc)) 504 dc_eeprom_getword_xircom(sc, off + i, &word); 505 else 506 dc_eeprom_getword(sc, off + i, &word); 507 ptr = (u_int16_t *)(dest + (i * 2)); 508 if (swap) 509 *ptr = ntohs(word); 510 else 511 *ptr = word; 512 } 513 514 return; 515} 516 517/* 518 * The following two routines are taken from the Macronix 98713 519 * Application Notes pp.19-21. 520 */ 521/* 522 * Write a bit to the MII bus. 523 */ 524static void dc_mii_writebit(sc, bit) 525 struct dc_softc *sc; 526 int bit; 527{ 528 if (bit) 529 CSR_WRITE_4(sc, DC_SIO, 530 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 531 else 532 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 533 534 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 535 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 536 537 return; 538} 539 540/* 541 * Read a bit from the MII bus. 542 */ 543static int dc_mii_readbit(sc) 544 struct dc_softc *sc; 545{ 546 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 547 CSR_READ_4(sc, DC_SIO); 548 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 549 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 550 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 551 return(1); 552 553 return(0); 554} 555 556/* 557 * Sync the PHYs by setting data bit and strobing the clock 32 times. 558 */ 559static void dc_mii_sync(sc) 560 struct dc_softc *sc; 561{ 562 register int i; 563 564 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 565 566 for (i = 0; i < 32; i++) 567 dc_mii_writebit(sc, 1); 568 569 return; 570} 571 572/* 573 * Clock a series of bits through the MII. 574 */ 575static void dc_mii_send(sc, bits, cnt) 576 struct dc_softc *sc; 577 u_int32_t bits; 578 int cnt; 579{ 580 int i; 581 582 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 583 dc_mii_writebit(sc, bits & i); 584} 585 586/* 587 * Read an PHY register through the MII. 588 */ 589static int dc_mii_readreg(sc, frame) 590 struct dc_softc *sc; 591 struct dc_mii_frame *frame; 592 593{ 594 int i, ack; 595 596 DC_LOCK(sc); 597 598 /* 599 * Set up frame for RX. 600 */ 601 frame->mii_stdelim = DC_MII_STARTDELIM; 602 frame->mii_opcode = DC_MII_READOP; 603 frame->mii_turnaround = 0; 604 frame->mii_data = 0; 605 606 /* 607 * Sync the PHYs. 608 */ 609 dc_mii_sync(sc); 610 611 /* 612 * Send command/address info. 613 */ 614 dc_mii_send(sc, frame->mii_stdelim, 2); 615 dc_mii_send(sc, frame->mii_opcode, 2); 616 dc_mii_send(sc, frame->mii_phyaddr, 5); 617 dc_mii_send(sc, frame->mii_regaddr, 5); 618 619#ifdef notdef 620 /* Idle bit */ 621 dc_mii_writebit(sc, 1); 622 dc_mii_writebit(sc, 0); 623#endif 624 625 /* Check for ack */ 626 ack = dc_mii_readbit(sc); 627 628 /* 629 * Now try reading data bits. If the ack failed, we still 630 * need to clock through 16 cycles to keep the PHY(s) in sync. 631 */ 632 if (ack) { 633 for(i = 0; i < 16; i++) { 634 dc_mii_readbit(sc); 635 } 636 goto fail; 637 } 638 639 for (i = 0x8000; i; i >>= 1) { 640 if (!ack) { 641 if (dc_mii_readbit(sc)) 642 frame->mii_data |= i; 643 } 644 } 645 646fail: 647 648 dc_mii_writebit(sc, 0); 649 dc_mii_writebit(sc, 0); 650 651 DC_UNLOCK(sc); 652 653 if (ack) 654 return(1); 655 return(0); 656} 657 658/* 659 * Write to a PHY register through the MII. 660 */ 661static int dc_mii_writereg(sc, frame) 662 struct dc_softc *sc; 663 struct dc_mii_frame *frame; 664 665{ 666 DC_LOCK(sc); 667 /* 668 * Set up frame for TX. 669 */ 670 671 frame->mii_stdelim = DC_MII_STARTDELIM; 672 frame->mii_opcode = DC_MII_WRITEOP; 673 frame->mii_turnaround = DC_MII_TURNAROUND; 674 675 /* 676 * Sync the PHYs. 677 */ 678 dc_mii_sync(sc); 679 680 dc_mii_send(sc, frame->mii_stdelim, 2); 681 dc_mii_send(sc, frame->mii_opcode, 2); 682 dc_mii_send(sc, frame->mii_phyaddr, 5); 683 dc_mii_send(sc, frame->mii_regaddr, 5); 684 dc_mii_send(sc, frame->mii_turnaround, 2); 685 dc_mii_send(sc, frame->mii_data, 16); 686 687 /* Idle bit. */ 688 dc_mii_writebit(sc, 0); 689 dc_mii_writebit(sc, 0); 690 691 DC_UNLOCK(sc); 692 693 return(0); 694} 695 696static int dc_miibus_readreg(dev, phy, reg) 697 device_t dev; 698 int phy, reg; 699{ 700 struct dc_mii_frame frame; 701 struct dc_softc *sc; 702 int i, rval, phy_reg; 703 704 sc = device_get_softc(dev); 705 bzero((char *)&frame, sizeof(frame)); 706 707 /* 708 * Note: both the AL981 and AN985 have internal PHYs, 709 * however the AL981 provides direct access to the PHY 710 * registers while the AN985 uses a serial MII interface. 711 * The AN985's MII interface is also buggy in that you 712 * can read from any MII address (0 to 31), but only address 1 713 * behaves normally. To deal with both cases, we pretend 714 * that the PHY is at MII address 1. 715 */ 716 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 717 return(0); 718 719 if (sc->dc_pmode != DC_PMODE_MII) { 720 if (phy == (MII_NPHY - 1)) { 721 switch(reg) { 722 case MII_BMSR: 723 /* 724 * Fake something to make the probe 725 * code think there's a PHY here. 726 */ 727 return(BMSR_MEDIAMASK); 728 break; 729 case MII_PHYIDR1: 730 if (DC_IS_PNIC(sc)) 731 return(DC_VENDORID_LO); 732 return(DC_VENDORID_DEC); 733 break; 734 case MII_PHYIDR2: 735 if (DC_IS_PNIC(sc)) 736 return(DC_DEVICEID_82C168); 737 return(DC_DEVICEID_21143); 738 break; 739 default: 740 return(0); 741 break; 742 } 743 } else 744 return(0); 745 } 746 747 if (DC_IS_PNIC(sc)) { 748 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 749 (phy << 23) | (reg << 18)); 750 for (i = 0; i < DC_TIMEOUT; i++) { 751 DELAY(1); 752 rval = CSR_READ_4(sc, DC_PN_MII); 753 if (!(rval & DC_PN_MII_BUSY)) { 754 rval &= 0xFFFF; 755 return(rval == 0xFFFF ? 0 : rval); 756 } 757 } 758 return(0); 759 } 760 761 if (DC_IS_COMET(sc)) { 762 switch(reg) { 763 case MII_BMCR: 764 phy_reg = DC_AL_BMCR; 765 break; 766 case MII_BMSR: 767 phy_reg = DC_AL_BMSR; 768 break; 769 case MII_PHYIDR1: 770 phy_reg = DC_AL_VENID; 771 break; 772 case MII_PHYIDR2: 773 phy_reg = DC_AL_DEVID; 774 break; 775 case MII_ANAR: 776 phy_reg = DC_AL_ANAR; 777 break; 778 case MII_ANLPAR: 779 phy_reg = DC_AL_LPAR; 780 break; 781 case MII_ANER: 782 phy_reg = DC_AL_ANER; 783 break; 784 default: 785 printf("dc%d: phy_read: bad phy register %x\n", 786 sc->dc_unit, reg); 787 return(0); 788 break; 789 } 790 791 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 792 793 if (rval == 0xFFFF) 794 return(0); 795 return(rval); 796 } 797 798 frame.mii_phyaddr = phy; 799 frame.mii_regaddr = reg; 800 phy_reg = CSR_READ_4(sc, DC_NETCFG); 801 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 802 dc_mii_readreg(sc, &frame); 803 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 804 805 return(frame.mii_data); 806} 807 808static int dc_miibus_writereg(dev, phy, reg, data) 809 device_t dev; 810 int phy, reg, data; 811{ 812 struct dc_softc *sc; 813 struct dc_mii_frame frame; 814 int i, phy_reg; 815 816 sc = device_get_softc(dev); 817 bzero((char *)&frame, sizeof(frame)); 818 819 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 820 return(0); 821 822 if (DC_IS_PNIC(sc)) { 823 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 824 (phy << 23) | (reg << 10) | data); 825 for (i = 0; i < DC_TIMEOUT; i++) { 826 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 827 break; 828 } 829 return(0); 830 } 831 832 if (DC_IS_COMET(sc)) { 833 switch(reg) { 834 case MII_BMCR: 835 phy_reg = DC_AL_BMCR; 836 break; 837 case MII_BMSR: 838 phy_reg = DC_AL_BMSR; 839 break; 840 case MII_PHYIDR1: 841 phy_reg = DC_AL_VENID; 842 break; 843 case MII_PHYIDR2: 844 phy_reg = DC_AL_DEVID; 845 break; 846 case MII_ANAR: 847 phy_reg = DC_AL_ANAR; 848 break; 849 case MII_ANLPAR: 850 phy_reg = DC_AL_LPAR; 851 break; 852 case MII_ANER: 853 phy_reg = DC_AL_ANER; 854 break; 855 default: 856 printf("dc%d: phy_write: bad phy register %x\n", 857 sc->dc_unit, reg); 858 return(0); 859 break; 860 } 861 862 CSR_WRITE_4(sc, phy_reg, data); 863 return(0); 864 } 865 866 frame.mii_phyaddr = phy; 867 frame.mii_regaddr = reg; 868 frame.mii_data = data; 869 870 phy_reg = CSR_READ_4(sc, DC_NETCFG); 871 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 872 dc_mii_writereg(sc, &frame); 873 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 874 875 return(0); 876} 877 878static void dc_miibus_statchg(dev) 879 device_t dev; 880{ 881 struct dc_softc *sc; 882 struct mii_data *mii; 883 struct ifmedia *ifm; 884 885 sc = device_get_softc(dev); 886 if (DC_IS_ADMTEK(sc)) 887 return; 888 889 mii = device_get_softc(sc->dc_miibus); 890 ifm = &mii->mii_media; 891 if (DC_IS_DAVICOM(sc) && 892 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 893 dc_setcfg(sc, ifm->ifm_media); 894 sc->dc_if_media = ifm->ifm_media; 895 } else { 896 dc_setcfg(sc, mii->mii_media_active); 897 sc->dc_if_media = mii->mii_media_active; 898 } 899 900 return; 901} 902 903/* 904 * Special support for DM9102A cards with HomePNA PHYs. Note: 905 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 906 * to be impossible to talk to the management interface of the DM9801 907 * PHY (its MDIO pin is not connected to anything). Consequently, 908 * the driver has to just 'know' about the additional mode and deal 909 * with it itself. *sigh* 910 */ 911static void dc_miibus_mediainit(dev) 912 device_t dev; 913{ 914 struct dc_softc *sc; 915 struct mii_data *mii; 916 struct ifmedia *ifm; 917 int rev; 918 919 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 920 921 sc = device_get_softc(dev); 922 mii = device_get_softc(sc->dc_miibus); 923 ifm = &mii->mii_media; 924 925 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 926 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 927 928 return; 929} 930 931#define DC_POLY 0xEDB88320 932#define DC_BITS_512 9 933#define DC_BITS_128 7 934#define DC_BITS_64 6 935 936static u_int32_t dc_crc_le(sc, addr) 937 struct dc_softc *sc; 938 caddr_t addr; 939{ 940 u_int32_t idx, bit, data, crc; 941 942 /* Compute CRC for the address value. */ 943 crc = 0xFFFFFFFF; /* initial value */ 944 945 for (idx = 0; idx < 6; idx++) { 946 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 947 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 948 } 949 950 /* 951 * The hash table on the PNIC II and the MX98715AEC-C/D/E 952 * chips is only 128 bits wide. 953 */ 954 if (sc->dc_flags & DC_128BIT_HASH) 955 return (crc & ((1 << DC_BITS_128) - 1)); 956 957 /* The hash table on the MX98715BEC is only 64 bits wide. */ 958 if (sc->dc_flags & DC_64BIT_HASH) 959 return (crc & ((1 << DC_BITS_64) - 1)); 960 961 /* Xircom's hash filtering table is different (read: weird) */ 962 /* Xircom uses the LEAST significant bits */ 963 if (DC_IS_XIRCOM(sc)) { 964 if ((crc & 0x180) == 0x180) 965 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 966 else 967 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 968 } 969 970 return (crc & ((1 << DC_BITS_512) - 1)); 971} 972 973/* 974 * Calculate CRC of a multicast group address, return the lower 6 bits. 975 */ 976static u_int32_t dc_crc_be(addr) 977 caddr_t addr; 978{ 979 u_int32_t crc, carry; 980 int i, j; 981 u_int8_t c; 982 983 /* Compute CRC for the address value. */ 984 crc = 0xFFFFFFFF; /* initial value */ 985 986 for (i = 0; i < 6; i++) { 987 c = *(addr + i); 988 for (j = 0; j < 8; j++) { 989 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 990 crc <<= 1; 991 c >>= 1; 992 if (carry) 993 crc = (crc ^ 0x04c11db6) | carry; 994 } 995 } 996 997 /* return the filter bit position */ 998 return((crc >> 26) & 0x0000003F); 999} 1000 1001/* 1002 * 21143-style RX filter setup routine. Filter programming is done by 1003 * downloading a special setup frame into the TX engine. 21143, Macronix, 1004 * PNIC, PNIC II and Davicom chips are programmed this way. 1005 * 1006 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1007 * address (our node address) and a 512-bit hash filter for multicast 1008 * frames. We also sneak the broadcast address into the hash filter since 1009 * we need that too. 1010 */ 1011void dc_setfilt_21143(sc) 1012 struct dc_softc *sc; 1013{ 1014 struct dc_desc *sframe; 1015 u_int32_t h, *sp; 1016 struct ifmultiaddr *ifma; 1017 struct ifnet *ifp; 1018 int i; 1019 1020 ifp = &sc->arpcom.ac_if; 1021 1022 i = sc->dc_cdata.dc_tx_prod; 1023 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1024 sc->dc_cdata.dc_tx_cnt++; 1025 sframe = &sc->dc_ldata->dc_tx_list[i]; 1026 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1027 bzero((char *)sp, DC_SFRAME_LEN); 1028 1029 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1030 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1031 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1032 1033 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1034 1035 /* If we want promiscuous mode, set the allframes bit. */ 1036 if (ifp->if_flags & IFF_PROMISC) 1037 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1038 else 1039 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1040 1041 if (ifp->if_flags & IFF_ALLMULTI) 1042 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1043 else 1044 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1045 1046 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1047 ifma = ifma->ifma_link.le_next) { 1048 if (ifma->ifma_addr->sa_family != AF_LINK) 1049 continue; 1050 h = dc_crc_le(sc, 1051 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1052 sp[h >> 4] |= 1 << (h & 0xF); 1053 } 1054 1055 if (ifp->if_flags & IFF_BROADCAST) { 1056 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1057 sp[h >> 4] |= 1 << (h & 0xF); 1058 } 1059 1060 /* Set our MAC address */ 1061 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1062 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1063 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1064 1065 sframe->dc_status = DC_TXSTAT_OWN; 1066 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1067 1068 /* 1069 * The PNIC takes an exceedingly long time to process its 1070 * setup frame; wait 10ms after posting the setup frame 1071 * before proceeding, just so it has time to swallow its 1072 * medicine. 1073 */ 1074 DELAY(10000); 1075 1076 ifp->if_timer = 5; 1077 1078 return; 1079} 1080 1081void dc_setfilt_admtek(sc) 1082 struct dc_softc *sc; 1083{ 1084 struct ifnet *ifp; 1085 int h = 0; 1086 u_int32_t hashes[2] = { 0, 0 }; 1087 struct ifmultiaddr *ifma; 1088 1089 ifp = &sc->arpcom.ac_if; 1090 1091 /* Init our MAC address */ 1092 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1093 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1094 1095 /* If we want promiscuous mode, set the allframes bit. */ 1096 if (ifp->if_flags & IFF_PROMISC) 1097 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1098 else 1099 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1100 1101 if (ifp->if_flags & IFF_ALLMULTI) 1102 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1103 else 1104 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1105 1106 /* first, zot all the existing hash bits */ 1107 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1108 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1109 1110 /* 1111 * If we're already in promisc or allmulti mode, we 1112 * don't have to bother programming the multicast filter. 1113 */ 1114 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1115 return; 1116 1117 /* now program new ones */ 1118 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1119 ifma = ifma->ifma_link.le_next) { 1120 if (ifma->ifma_addr->sa_family != AF_LINK) 1121 continue; 1122 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1123 if (h < 32) 1124 hashes[0] |= (1 << h); 1125 else 1126 hashes[1] |= (1 << (h - 32)); 1127 } 1128 1129 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1130 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1131 1132 return; 1133} 1134 1135void dc_setfilt_asix(sc) 1136 struct dc_softc *sc; 1137{ 1138 struct ifnet *ifp; 1139 int h = 0; 1140 u_int32_t hashes[2] = { 0, 0 }; 1141 struct ifmultiaddr *ifma; 1142 1143 ifp = &sc->arpcom.ac_if; 1144 1145 /* Init our MAC address */ 1146 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1147 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1148 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1149 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1150 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1151 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1152 1153 /* If we want promiscuous mode, set the allframes bit. */ 1154 if (ifp->if_flags & IFF_PROMISC) 1155 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1156 else 1157 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1158 1159 if (ifp->if_flags & IFF_ALLMULTI) 1160 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1161 else 1162 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1163 1164 /* 1165 * The ASIX chip has a special bit to enable reception 1166 * of broadcast frames. 1167 */ 1168 if (ifp->if_flags & IFF_BROADCAST) 1169 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1170 else 1171 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1172 1173 /* first, zot all the existing hash bits */ 1174 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1175 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1176 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1177 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1178 1179 /* 1180 * If we're already in promisc or allmulti mode, we 1181 * don't have to bother programming the multicast filter. 1182 */ 1183 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1184 return; 1185 1186 /* now program new ones */ 1187 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1188 ifma = ifma->ifma_link.le_next) { 1189 if (ifma->ifma_addr->sa_family != AF_LINK) 1190 continue; 1191 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1192 if (h < 32) 1193 hashes[0] |= (1 << h); 1194 else 1195 hashes[1] |= (1 << (h - 32)); 1196 } 1197 1198 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1199 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1200 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1201 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1202 1203 return; 1204} 1205 1206void dc_setfilt_xircom(sc) 1207 struct dc_softc *sc; 1208{ 1209 struct dc_desc *sframe; 1210 u_int32_t h, *sp; 1211 struct ifmultiaddr *ifma; 1212 struct ifnet *ifp; 1213 int i; 1214 1215 ifp = &sc->arpcom.ac_if; 1216 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1217 1218 i = sc->dc_cdata.dc_tx_prod; 1219 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1220 sc->dc_cdata.dc_tx_cnt++; 1221 sframe = &sc->dc_ldata->dc_tx_list[i]; 1222 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1223 bzero((char *)sp, DC_SFRAME_LEN); 1224 1225 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1226 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1227 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1228 1229 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1230 1231 /* If we want promiscuous mode, set the allframes bit. */ 1232 if (ifp->if_flags & IFF_PROMISC) 1233 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1234 else 1235 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1236 1237 if (ifp->if_flags & IFF_ALLMULTI) 1238 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1239 else 1240 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1241 1242 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1243 ifma = ifma->ifma_link.le_next) { 1244 if (ifma->ifma_addr->sa_family != AF_LINK) 1245 continue; 1246 h = dc_crc_le(sc, 1247 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1248 sp[h >> 4] |= 1 << (h & 0xF); 1249 } 1250 1251 if (ifp->if_flags & IFF_BROADCAST) { 1252 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1253 sp[h >> 4] |= 1 << (h & 0xF); 1254 } 1255 1256 /* Set our MAC address */ 1257 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1258 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1259 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1260 1261 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1262 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1263 ifp->if_flags |= IFF_RUNNING; 1264 sframe->dc_status = DC_TXSTAT_OWN; 1265 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1266 1267 /* 1268 * wait some time... 1269 */ 1270 DELAY(1000); 1271 1272 ifp->if_timer = 5; 1273 1274 return; 1275} 1276 1277static void dc_setfilt(sc) 1278 struct dc_softc *sc; 1279{ 1280 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1281 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1282 dc_setfilt_21143(sc); 1283 1284 if (DC_IS_ASIX(sc)) 1285 dc_setfilt_asix(sc); 1286 1287 if (DC_IS_ADMTEK(sc)) 1288 dc_setfilt_admtek(sc); 1289 1290 if (DC_IS_XIRCOM(sc)) 1291 dc_setfilt_xircom(sc); 1292 1293 return; 1294} 1295 1296/* 1297 * In order to fiddle with the 1298 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1299 * first have to put the transmit and/or receive logic in the idle state. 1300 */ 1301static void dc_setcfg(sc, media) 1302 struct dc_softc *sc; 1303 int media; 1304{ 1305 int i, restart = 0; 1306 u_int32_t isr; 1307 1308 if (IFM_SUBTYPE(media) == IFM_NONE) 1309 return; 1310 1311 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1312 restart = 1; 1313 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1314 1315 for (i = 0; i < DC_TIMEOUT; i++) { 1316 DELAY(10); 1317 isr = CSR_READ_4(sc, DC_ISR); 1318 if (isr & DC_ISR_TX_IDLE || 1319 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1320 break; 1321 } 1322 1323 if (i == DC_TIMEOUT) 1324 printf("dc%d: failed to force tx and " 1325 "rx to idle state\n", sc->dc_unit); 1326 1327 } 1328 1329 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1330 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1331 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1332 if (sc->dc_pmode == DC_PMODE_MII) { 1333 int watchdogreg; 1334 1335 if (DC_IS_INTEL(sc)) { 1336 /* there's a write enable bit here that reads as 1 */ 1337 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1338 watchdogreg &= ~DC_WDOG_CTLWREN; 1339 watchdogreg |= DC_WDOG_JABBERDIS; 1340 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1341 } else { 1342 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1343 } 1344 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1345 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1346 if (sc->dc_type == DC_TYPE_98713) 1347 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1348 DC_NETCFG_SCRAMBLER)); 1349 if (!DC_IS_DAVICOM(sc)) 1350 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1351 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1352 if (DC_IS_INTEL(sc)) 1353 dc_apply_fixup(sc, IFM_AUTO); 1354 } else { 1355 if (DC_IS_PNIC(sc)) { 1356 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1357 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1358 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1359 } 1360 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1361 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1362 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1363 if (DC_IS_INTEL(sc)) 1364 dc_apply_fixup(sc, 1365 (media & IFM_GMASK) == IFM_FDX ? 1366 IFM_100_TX|IFM_FDX : IFM_100_TX); 1367 } 1368 } 1369 1370 if (IFM_SUBTYPE(media) == IFM_10_T) { 1371 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1372 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1373 if (sc->dc_pmode == DC_PMODE_MII) { 1374 int watchdogreg; 1375 1376 /* there's a write enable bit here that reads as 1 */ 1377 if (DC_IS_INTEL(sc)) { 1378 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1379 watchdogreg &= ~DC_WDOG_CTLWREN; 1380 watchdogreg |= DC_WDOG_JABBERDIS; 1381 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1382 } else { 1383 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1384 } 1385 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1386 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1387 if (sc->dc_type == DC_TYPE_98713) 1388 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1389 if (!DC_IS_DAVICOM(sc)) 1390 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1391 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1392 if (DC_IS_INTEL(sc)) 1393 dc_apply_fixup(sc, IFM_AUTO); 1394 } else { 1395 if (DC_IS_PNIC(sc)) { 1396 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1397 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1398 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1399 } 1400 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1401 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1402 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1403 if (DC_IS_INTEL(sc)) { 1404 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1405 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1406 if ((media & IFM_GMASK) == IFM_FDX) 1407 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1408 else 1409 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1410 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1411 DC_CLRBIT(sc, DC_10BTCTRL, 1412 DC_TCTL_AUTONEGENBL); 1413 dc_apply_fixup(sc, 1414 (media & IFM_GMASK) == IFM_FDX ? 1415 IFM_10_T|IFM_FDX : IFM_10_T); 1416 DELAY(20000); 1417 } 1418 } 1419 } 1420 1421 /* 1422 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1423 * PHY and we want HomePNA mode, set the portsel bit to turn 1424 * on the external MII port. 1425 */ 1426 if (DC_IS_DAVICOM(sc)) { 1427 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1428 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1429 sc->dc_link = 1; 1430 } else { 1431 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1432 } 1433 } 1434 1435 if ((media & IFM_GMASK) == IFM_FDX) { 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1437 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1438 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1439 } else { 1440 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1441 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1442 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1443 } 1444 1445 if (restart) 1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1447 1448 return; 1449} 1450 1451static void dc_reset(sc) 1452 struct dc_softc *sc; 1453{ 1454 register int i; 1455 1456 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1457 1458 for (i = 0; i < DC_TIMEOUT; i++) { 1459 DELAY(10); 1460 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1461 break; 1462 } 1463 1464 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || 1465 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1466 DELAY(10000); 1467 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1468 i = 0; 1469 } 1470 1471 if (i == DC_TIMEOUT) 1472 printf("dc%d: reset never completed!\n", sc->dc_unit); 1473 1474 /* Wait a little while for the chip to get its brains in order. */ 1475 DELAY(1000); 1476 1477 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1478 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1479 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1480 1481 /* 1482 * Bring the SIA out of reset. In some cases, it looks 1483 * like failing to unreset the SIA soon enough gets it 1484 * into a state where it will never come out of reset 1485 * until we reset the whole chip again. 1486 */ 1487 if (DC_IS_INTEL(sc)) { 1488 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1489 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1490 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1491 } 1492 1493 return; 1494} 1495 1496static struct dc_type *dc_devtype(dev) 1497 device_t dev; 1498{ 1499 struct dc_type *t; 1500 u_int32_t rev; 1501 1502 t = dc_devs; 1503 1504 while(t->dc_name != NULL) { 1505 if ((pci_get_vendor(dev) == t->dc_vid) && 1506 (pci_get_device(dev) == t->dc_did)) { 1507 /* Check the PCI revision */ 1508 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1509 if (t->dc_did == DC_DEVICEID_98713 && 1510 rev >= DC_REVISION_98713A) 1511 t++; 1512 if (t->dc_did == DC_DEVICEID_98713_CP && 1513 rev >= DC_REVISION_98713A) 1514 t++; 1515 if (t->dc_did == DC_DEVICEID_987x5 && 1516 rev >= DC_REVISION_98715AEC_C) 1517 t++; 1518 if (t->dc_did == DC_DEVICEID_987x5 && 1519 rev >= DC_REVISION_98725) 1520 t++; 1521 if (t->dc_did == DC_DEVICEID_AX88140A && 1522 rev >= DC_REVISION_88141) 1523 t++; 1524 if (t->dc_did == DC_DEVICEID_82C168 && 1525 rev >= DC_REVISION_82C169) 1526 t++; 1527 if (t->dc_did == DC_DEVICEID_DM9102 && 1528 rev >= DC_REVISION_DM9102A) 1529 t++; 1530 return(t); 1531 } 1532 t++; 1533 } 1534 1535 return(NULL); 1536} 1537 1538/* 1539 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1540 * IDs against our list and return a device name if we find a match. 1541 * We do a little bit of extra work to identify the exact type of 1542 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1543 * but different revision IDs. The same is true for 98715/98715A 1544 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1545 * cases, the exact chip revision affects driver behavior. 1546 */ 1547static int dc_probe(dev) 1548 device_t dev; 1549{ 1550 struct dc_type *t; 1551 1552 t = dc_devtype(dev); 1553 1554 if (t != NULL) { 1555 device_set_desc(dev, t->dc_name); 1556 return(0); 1557 } 1558 1559 return(ENXIO); 1560} 1561 1562static void dc_acpi(dev) 1563 device_t dev; 1564{ 1565 u_int32_t r, cptr; 1566 int unit; 1567 1568 unit = device_get_unit(dev); 1569 1570 /* Find the location of the capabilities block */ 1571 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1572 1573 r = pci_read_config(dev, cptr, 4) & 0xFF; 1574 if (r == 0x01) { 1575 1576 r = pci_read_config(dev, cptr + 4, 4); 1577 if (r & DC_PSTATE_D3) { 1578 u_int32_t iobase, membase, irq; 1579 1580 /* Save important PCI config data. */ 1581 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1582 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1583 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1584 1585 /* Reset the power state. */ 1586 printf("dc%d: chip is in D%d power mode " 1587 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1588 r &= 0xFFFFFFFC; 1589 pci_write_config(dev, cptr + 4, r, 4); 1590 1591 /* Restore PCI config data. */ 1592 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1593 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1594 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1595 } 1596 } 1597 return; 1598} 1599 1600static void dc_apply_fixup(sc, media) 1601 struct dc_softc *sc; 1602 int media; 1603{ 1604 struct dc_mediainfo *m; 1605 u_int8_t *p; 1606 int i; 1607 u_int32_t reg; 1608 1609 m = sc->dc_mi; 1610 1611 while (m != NULL) { 1612 if (m->dc_media == media) 1613 break; 1614 m = m->dc_next; 1615 } 1616 1617 if (m == NULL) 1618 return; 1619 1620 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1621 reg = (p[0] | (p[1] << 8)) << 16; 1622 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1623 } 1624 1625 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1626 reg = (p[0] | (p[1] << 8)) << 16; 1627 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1628 } 1629 1630 return; 1631} 1632 1633static void dc_decode_leaf_sia(sc, l) 1634 struct dc_softc *sc; 1635 struct dc_eblock_sia *l; 1636{ 1637 struct dc_mediainfo *m; 1638 1639 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1640 bzero(m, sizeof(struct dc_mediainfo)); 1641 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1642 m->dc_media = IFM_10_T; 1643 1644 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1645 m->dc_media = IFM_10_T|IFM_FDX; 1646 1647 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1648 m->dc_media = IFM_10_2; 1649 1650 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1651 m->dc_media = IFM_10_5; 1652 1653 m->dc_gp_len = 2; 1654 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1655 1656 m->dc_next = sc->dc_mi; 1657 sc->dc_mi = m; 1658 1659 sc->dc_pmode = DC_PMODE_SIA; 1660 1661 return; 1662} 1663 1664static void dc_decode_leaf_sym(sc, l) 1665 struct dc_softc *sc; 1666 struct dc_eblock_sym *l; 1667{ 1668 struct dc_mediainfo *m; 1669 1670 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1671 bzero(m, sizeof(struct dc_mediainfo)); 1672 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1673 m->dc_media = IFM_100_TX; 1674 1675 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1676 m->dc_media = IFM_100_TX|IFM_FDX; 1677 1678 m->dc_gp_len = 2; 1679 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1680 1681 m->dc_next = sc->dc_mi; 1682 sc->dc_mi = m; 1683 1684 sc->dc_pmode = DC_PMODE_SYM; 1685 1686 return; 1687} 1688 1689static void dc_decode_leaf_mii(sc, l) 1690 struct dc_softc *sc; 1691 struct dc_eblock_mii *l; 1692{ 1693 u_int8_t *p; 1694 struct dc_mediainfo *m; 1695 1696 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1697 bzero(m, sizeof(struct dc_mediainfo)); 1698 /* We abuse IFM_AUTO to represent MII. */ 1699 m->dc_media = IFM_AUTO; 1700 m->dc_gp_len = l->dc_gpr_len; 1701 1702 p = (u_int8_t *)l; 1703 p += sizeof(struct dc_eblock_mii); 1704 m->dc_gp_ptr = p; 1705 p += 2 * l->dc_gpr_len; 1706 m->dc_reset_len = *p; 1707 p++; 1708 m->dc_reset_ptr = p; 1709 1710 m->dc_next = sc->dc_mi; 1711 sc->dc_mi = m; 1712 1713 return; 1714} 1715 1716static void dc_parse_21143_srom(sc) 1717 struct dc_softc *sc; 1718{ 1719 struct dc_leaf_hdr *lhdr; 1720 struct dc_eblock_hdr *hdr; 1721 int i, loff; 1722 char *ptr; 1723 1724 loff = sc->dc_srom[27]; 1725 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1726 1727 ptr = (char *)lhdr; 1728 ptr += sizeof(struct dc_leaf_hdr) - 1; 1729 for (i = 0; i < lhdr->dc_mcnt; i++) { 1730 hdr = (struct dc_eblock_hdr *)ptr; 1731 switch(hdr->dc_type) { 1732 case DC_EBLOCK_MII: 1733 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1734 break; 1735 case DC_EBLOCK_SIA: 1736 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1737 break; 1738 case DC_EBLOCK_SYM: 1739 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1740 break; 1741 default: 1742 /* Don't care. Yet. */ 1743 break; 1744 } 1745 ptr += (hdr->dc_len & 0x7F); 1746 ptr++; 1747 } 1748 1749 return; 1750} 1751 1752/* 1753 * Attach the interface. Allocate softc structures, do ifmedia 1754 * setup and ethernet/BPF attach. 1755 */ 1756static int dc_attach(dev) 1757 device_t dev; 1758{ 1759 int tmp = 0; 1760 u_char eaddr[ETHER_ADDR_LEN]; 1761 u_int32_t command; 1762 struct dc_softc *sc; 1763 struct ifnet *ifp; 1764 u_int32_t revision; 1765 int unit, error = 0, rid, mac_offset; 1766 1767 sc = device_get_softc(dev); 1768 unit = device_get_unit(dev); 1769 bzero(sc, sizeof(struct dc_softc)); 1770 1771 /* 1772 * Handle power management nonsense. 1773 */ 1774 dc_acpi(dev); 1775 1776 /* 1777 * Map control/status registers. 1778 */ 1779 command = pci_read_config(dev, PCIR_COMMAND, 4); 1780 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1781 pci_write_config(dev, PCIR_COMMAND, command, 4); 1782 command = pci_read_config(dev, PCIR_COMMAND, 4); 1783 1784#ifdef DC_USEIOSPACE 1785 if (!(command & PCIM_CMD_PORTEN)) { 1786 printf("dc%d: failed to enable I/O ports!\n", unit); 1787 error = ENXIO; 1788 goto fail; 1789 } 1790#else 1791 if (!(command & PCIM_CMD_MEMEN)) { 1792 printf("dc%d: failed to enable memory mapping!\n", unit); 1793 error = ENXIO; 1794 goto fail; 1795 } 1796#endif 1797 1798 rid = DC_RID; 1799 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1800 0, ~0, 1, RF_ACTIVE); 1801 1802 if (sc->dc_res == NULL) { 1803 printf("dc%d: couldn't map ports/memory\n", unit); 1804 error = ENXIO; 1805 goto fail; 1806 } 1807 1808 sc->dc_btag = rman_get_bustag(sc->dc_res); 1809 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1810 1811 /* Allocate interrupt */ 1812 rid = 0; 1813 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1814 RF_SHAREABLE | RF_ACTIVE); 1815 1816 if (sc->dc_irq == NULL) { 1817 printf("dc%d: couldn't map interrupt\n", unit); 1818 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1819 error = ENXIO; 1820 goto fail; 1821 } 1822 1823 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1824 dc_intr, sc, &sc->dc_intrhand); 1825 1826 if (error) { 1827 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1828 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1829 printf("dc%d: couldn't set up irq\n", unit); 1830 goto fail; 1831 } 1832 1833 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_DEF); 1834 DC_LOCK(sc); 1835 /* Need this info to decide on a chip type. */ 1836 sc->dc_info = dc_devtype(dev); 1837 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1838 1839 switch(sc->dc_info->dc_did) { 1840 case DC_DEVICEID_21143: 1841 sc->dc_type = DC_TYPE_21143; 1842 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1843 sc->dc_flags |= DC_REDUCED_MII_POLL; 1844 /* Save EEPROM contents so we can parse them later. */ 1845 dc_read_eeprom(sc, (caddr_t)&sc->dc_srom, 0, 512, 0); 1846 break; 1847 case DC_DEVICEID_DM9100: 1848 case DC_DEVICEID_DM9102: 1849 sc->dc_type = DC_TYPE_DM9102; 1850 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1851 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1852 sc->dc_pmode = DC_PMODE_MII; 1853 /* Increase the latency timer value. */ 1854 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1855 command &= 0xFFFF00FF; 1856 command |= 0x00008000; 1857 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1858 break; 1859 case DC_DEVICEID_AL981: 1860 sc->dc_type = DC_TYPE_AL981; 1861 sc->dc_flags |= DC_TX_USE_TX_INTR; 1862 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1863 sc->dc_pmode = DC_PMODE_MII; 1864 break; 1865 case DC_DEVICEID_AN985: 1866 case DC_DEVICEID_FE2500: 1867 case DC_DEVICEID_EN2242: 1868 sc->dc_type = DC_TYPE_AN985; 1869 sc->dc_flags |= DC_TX_USE_TX_INTR; 1870 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1871 sc->dc_pmode = DC_PMODE_MII; 1872 break; 1873 case DC_DEVICEID_98713: 1874 case DC_DEVICEID_98713_CP: 1875 if (revision < DC_REVISION_98713A) { 1876 sc->dc_type = DC_TYPE_98713; 1877 } 1878 if (revision >= DC_REVISION_98713A) { 1879 sc->dc_type = DC_TYPE_98713A; 1880 sc->dc_flags |= DC_21143_NWAY; 1881 } 1882 sc->dc_flags |= DC_REDUCED_MII_POLL; 1883 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1884 break; 1885 case DC_DEVICEID_987x5: 1886 case DC_DEVICEID_EN1217: 1887 /* 1888 * Macronix MX98715AEC-C/D/E parts have only a 1889 * 128-bit hash table. We need to deal with these 1890 * in the same manner as the PNIC II so that we 1891 * get the right number of bits out of the 1892 * CRC routine. 1893 */ 1894 if (revision >= DC_REVISION_98715AEC_C && 1895 revision < DC_REVISION_98725) 1896 sc->dc_flags |= DC_128BIT_HASH; 1897 sc->dc_type = DC_TYPE_987x5; 1898 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1899 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1900 break; 1901 case DC_DEVICEID_98727: 1902 sc->dc_type = DC_TYPE_987x5; 1903 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1904 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1905 break; 1906 case DC_DEVICEID_82C115: 1907 sc->dc_type = DC_TYPE_PNICII; 1908 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1909 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1910 break; 1911 case DC_DEVICEID_82C168: 1912 sc->dc_type = DC_TYPE_PNIC; 1913 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1914 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1915 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1916 if (revision < DC_REVISION_82C169) 1917 sc->dc_pmode = DC_PMODE_SYM; 1918 break; 1919 case DC_DEVICEID_AX88140A: 1920 sc->dc_type = DC_TYPE_ASIX; 1921 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1922 sc->dc_flags |= DC_REDUCED_MII_POLL; 1923 sc->dc_pmode = DC_PMODE_MII; 1924 break; 1925 case DC_DEVICEID_X3201: 1926 sc->dc_type = DC_TYPE_XIRCOM; 1927 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE; 1928 /* 1929 * We don't actually need to coalesce, but we're doing 1930 * it to obtain a double word aligned buffer. 1931 */ 1932 break; 1933 default: 1934 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1935 sc->dc_info->dc_did); 1936 break; 1937 } 1938 1939 /* Save the cache line size. */ 1940 if (DC_IS_DAVICOM(sc)) 1941 sc->dc_cachesize = 0; 1942 else 1943 sc->dc_cachesize = pci_read_config(dev, 1944 DC_PCI_CFLT, 4) & 0xFF; 1945 1946 /* Reset the adapter. */ 1947 dc_reset(sc); 1948 1949 /* Take 21143 out of snooze mode */ 1950 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 1951 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1952 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1953 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1954 } 1955 1956 /* 1957 * Try to learn something about the supported media. 1958 * We know that ASIX and ADMtek and Davicom devices 1959 * will *always* be using MII media, so that's a no-brainer. 1960 * The tricky ones are the Macronix/PNIC II and the 1961 * Intel 21143. 1962 */ 1963 if (DC_IS_INTEL(sc)) 1964 dc_parse_21143_srom(sc); 1965 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1966 if (sc->dc_type == DC_TYPE_98713) 1967 sc->dc_pmode = DC_PMODE_MII; 1968 else 1969 sc->dc_pmode = DC_PMODE_SYM; 1970 } else if (!sc->dc_pmode) 1971 sc->dc_pmode = DC_PMODE_MII; 1972 1973 /* 1974 * Get station address from the EEPROM. 1975 */ 1976 switch(sc->dc_type) { 1977 case DC_TYPE_98713: 1978 case DC_TYPE_98713A: 1979 case DC_TYPE_987x5: 1980 case DC_TYPE_PNICII: 1981 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1982 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1983 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1984 break; 1985 case DC_TYPE_PNIC: 1986 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1987 break; 1988 case DC_TYPE_DM9102: 1989 case DC_TYPE_21143: 1990 case DC_TYPE_ASIX: 1991 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1992 break; 1993 case DC_TYPE_AL981: 1994 case DC_TYPE_AN985: 1995 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1996 break; 1997 case DC_TYPE_XIRCOM: 1998 dc_read_eeprom(sc, (caddr_t)&eaddr, 3, 3, 0); 1999 break; 2000 default: 2001 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2002 break; 2003 } 2004 2005 /* 2006 * A 21143 or clone chip was detected. Inform the world. 2007 */ 2008 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2009 2010 sc->dc_unit = unit; 2011 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2012 2013 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2014 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2015 2016 if (sc->dc_ldata == NULL) { 2017 printf("dc%d: no memory for list buffers!\n", unit); 2018 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2019 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2020 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2021 error = ENXIO; 2022 goto fail; 2023 } 2024 2025 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2026 2027 ifp = &sc->arpcom.ac_if; 2028 ifp->if_softc = sc; 2029 ifp->if_unit = unit; 2030 ifp->if_name = "dc"; 2031 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2032 ifp->if_mtu = ETHERMTU; 2033 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2034 ifp->if_ioctl = dc_ioctl; 2035 ifp->if_output = ether_output; 2036 ifp->if_start = dc_start; 2037 ifp->if_watchdog = dc_watchdog; 2038 ifp->if_init = dc_init; 2039 ifp->if_baudrate = 10000000; 2040 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2041 2042 /* 2043 * Do MII setup. If this is a 21143, check for a PHY on the 2044 * MII bus after applying any necessary fixups to twiddle the 2045 * GPIO bits. If we don't end up finding a PHY, restore the 2046 * old selection (SIA only or SIA/SYM) and attach the dcphy 2047 * driver instead. 2048 */ 2049 if (DC_IS_INTEL(sc)) { 2050 dc_apply_fixup(sc, IFM_AUTO); 2051 tmp = sc->dc_pmode; 2052 sc->dc_pmode = DC_PMODE_MII; 2053 } 2054 2055 error = mii_phy_probe(dev, &sc->dc_miibus, 2056 dc_ifmedia_upd, dc_ifmedia_sts); 2057 2058 if (error && DC_IS_INTEL(sc)) { 2059 sc->dc_pmode = tmp; 2060 if (sc->dc_pmode != DC_PMODE_SIA) 2061 sc->dc_pmode = DC_PMODE_SYM; 2062 sc->dc_flags |= DC_21143_NWAY; 2063 mii_phy_probe(dev, &sc->dc_miibus, 2064 dc_ifmedia_upd, dc_ifmedia_sts); 2065 /* 2066 * For non-MII cards, we need to have the 21143 2067 * drive the LEDs. Except there are some systems 2068 * like the NEC VersaPro NoteBook PC which have no 2069 * LEDs, and twiddling these bits has adverse effects 2070 * on them. (I.e. you suddenly can't get a link.) 2071 */ 2072 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2073 sc->dc_flags |= DC_TULIP_LEDS; 2074 error = 0; 2075 } 2076 2077 if (error) { 2078 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2079 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2080 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2081 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2082 error = ENXIO; 2083 goto fail; 2084 } 2085 2086 if (DC_IS_XIRCOM(sc)) { 2087 /* 2088 * setup General Purpose Port mode and data so the tulip 2089 * can talk to the MII. 2090 */ 2091 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2092 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2093 DELAY(10); 2094 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2095 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2096 DELAY(10); 2097 } 2098 2099 /* 2100 * Call MI attach routine. 2101 */ 2102 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2103 callout_handle_init(&sc->dc_stat_ch); 2104 2105#ifdef SRM_MEDIA 2106 sc->dc_srm_media = 0; 2107 2108 /* Remember the SRM console media setting */ 2109 if (DC_IS_INTEL(sc)) { 2110 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2111 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2112 switch ((command >> 8) & 0xff) { 2113 case 3: 2114 sc->dc_srm_media = IFM_10_T; 2115 break; 2116 case 4: 2117 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2118 break; 2119 case 5: 2120 sc->dc_srm_media = IFM_100_TX; 2121 break; 2122 case 6: 2123 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2124 break; 2125 } 2126 if (sc->dc_srm_media) 2127 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2128 } 2129#endif 2130 2131 DC_UNLOCK(sc); 2132 return(0); 2133 2134fail: 2135 DC_UNLOCK(sc); 2136 mtx_destroy(&sc->dc_mtx); 2137 return(error); 2138} 2139 2140static int dc_detach(dev) 2141 device_t dev; 2142{ 2143 struct dc_softc *sc; 2144 struct ifnet *ifp; 2145 struct dc_mediainfo *m; 2146 2147 sc = device_get_softc(dev); 2148 2149 DC_LOCK(sc); 2150 2151 ifp = &sc->arpcom.ac_if; 2152 2153 dc_stop(sc); 2154 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2155 2156 bus_generic_detach(dev); 2157 device_delete_child(dev, sc->dc_miibus); 2158 2159 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2160 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2161 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2162 2163 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2164 if (sc->dc_pnic_rx_buf != NULL) 2165 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2166 2167 while(sc->dc_mi != NULL) { 2168 m = sc->dc_mi->dc_next; 2169 free(sc->dc_mi, M_DEVBUF); 2170 sc->dc_mi = m; 2171 } 2172 2173 DC_UNLOCK(sc); 2174 mtx_destroy(&sc->dc_mtx); 2175 2176 return(0); 2177} 2178 2179/* 2180 * Initialize the transmit descriptors. 2181 */ 2182static int dc_list_tx_init(sc) 2183 struct dc_softc *sc; 2184{ 2185 struct dc_chain_data *cd; 2186 struct dc_list_data *ld; 2187 int i; 2188 2189 cd = &sc->dc_cdata; 2190 ld = sc->dc_ldata; 2191 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2192 if (i == (DC_TX_LIST_CNT - 1)) { 2193 ld->dc_tx_list[i].dc_next = 2194 vtophys(&ld->dc_tx_list[0]); 2195 } else { 2196 ld->dc_tx_list[i].dc_next = 2197 vtophys(&ld->dc_tx_list[i + 1]); 2198 } 2199 cd->dc_tx_chain[i] = NULL; 2200 ld->dc_tx_list[i].dc_data = 0; 2201 ld->dc_tx_list[i].dc_ctl = 0; 2202 } 2203 2204 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2205 2206 return(0); 2207} 2208 2209 2210/* 2211 * Initialize the RX descriptors and allocate mbufs for them. Note that 2212 * we arrange the descriptors in a closed ring, so that the last descriptor 2213 * points back to the first. 2214 */ 2215static int dc_list_rx_init(sc) 2216 struct dc_softc *sc; 2217{ 2218 struct dc_chain_data *cd; 2219 struct dc_list_data *ld; 2220 int i; 2221 2222 cd = &sc->dc_cdata; 2223 ld = sc->dc_ldata; 2224 2225 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2226 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2227 return(ENOBUFS); 2228 if (i == (DC_RX_LIST_CNT - 1)) { 2229 ld->dc_rx_list[i].dc_next = 2230 vtophys(&ld->dc_rx_list[0]); 2231 } else { 2232 ld->dc_rx_list[i].dc_next = 2233 vtophys(&ld->dc_rx_list[i + 1]); 2234 } 2235 } 2236 2237 cd->dc_rx_prod = 0; 2238 2239 return(0); 2240} 2241 2242/* 2243 * Initialize an RX descriptor and attach an MBUF cluster. 2244 */ 2245static int dc_newbuf(sc, i, m) 2246 struct dc_softc *sc; 2247 int i; 2248 struct mbuf *m; 2249{ 2250 struct mbuf *m_new = NULL; 2251 struct dc_desc *c; 2252 2253 c = &sc->dc_ldata->dc_rx_list[i]; 2254 2255 if (m == NULL) { 2256 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2257 if (m_new == NULL) { 2258 printf("dc%d: no memory for rx list " 2259 "-- packet dropped!\n", sc->dc_unit); 2260 return(ENOBUFS); 2261 } 2262 2263 MCLGET(m_new, M_DONTWAIT); 2264 if (!(m_new->m_flags & M_EXT)) { 2265 printf("dc%d: no memory for rx list " 2266 "-- packet dropped!\n", sc->dc_unit); 2267 m_freem(m_new); 2268 return(ENOBUFS); 2269 } 2270 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2271 } else { 2272 m_new = m; 2273 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2274 m_new->m_data = m_new->m_ext.ext_buf; 2275 } 2276 2277 m_adj(m_new, sizeof(u_int64_t)); 2278 2279 /* 2280 * If this is a PNIC chip, zero the buffer. This is part 2281 * of the workaround for the receive bug in the 82c168 and 2282 * 82c169 chips. 2283 */ 2284 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2285 bzero((char *)mtod(m_new, char *), m_new->m_len); 2286 2287 sc->dc_cdata.dc_rx_chain[i] = m_new; 2288 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2289 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2290 c->dc_status = DC_RXSTAT_OWN; 2291 2292 return(0); 2293} 2294 2295/* 2296 * Grrrrr. 2297 * The PNIC chip has a terrible bug in it that manifests itself during 2298 * periods of heavy activity. The exact mode of failure if difficult to 2299 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2300 * will happen on slow machines. The bug is that sometimes instead of 2301 * uploading one complete frame during reception, it uploads what looks 2302 * like the entire contents of its FIFO memory. The frame we want is at 2303 * the end of the whole mess, but we never know exactly how much data has 2304 * been uploaded, so salvaging the frame is hard. 2305 * 2306 * There is only one way to do it reliably, and it's disgusting. 2307 * Here's what we know: 2308 * 2309 * - We know there will always be somewhere between one and three extra 2310 * descriptors uploaded. 2311 * 2312 * - We know the desired received frame will always be at the end of the 2313 * total data upload. 2314 * 2315 * - We know the size of the desired received frame because it will be 2316 * provided in the length field of the status word in the last descriptor. 2317 * 2318 * Here's what we do: 2319 * 2320 * - When we allocate buffers for the receive ring, we bzero() them. 2321 * This means that we know that the buffer contents should be all 2322 * zeros, except for data uploaded by the chip. 2323 * 2324 * - We also force the PNIC chip to upload frames that include the 2325 * ethernet CRC at the end. 2326 * 2327 * - We gather all of the bogus frame data into a single buffer. 2328 * 2329 * - We then position a pointer at the end of this buffer and scan 2330 * backwards until we encounter the first non-zero byte of data. 2331 * This is the end of the received frame. We know we will encounter 2332 * some data at the end of the frame because the CRC will always be 2333 * there, so even if the sender transmits a packet of all zeros, 2334 * we won't be fooled. 2335 * 2336 * - We know the size of the actual received frame, so we subtract 2337 * that value from the current pointer location. This brings us 2338 * to the start of the actual received packet. 2339 * 2340 * - We copy this into an mbuf and pass it on, along with the actual 2341 * frame length. 2342 * 2343 * The performance hit is tremendous, but it beats dropping frames all 2344 * the time. 2345 */ 2346 2347#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2348static void dc_pnic_rx_bug_war(sc, idx) 2349 struct dc_softc *sc; 2350 int idx; 2351{ 2352 struct dc_desc *cur_rx; 2353 struct dc_desc *c = NULL; 2354 struct mbuf *m = NULL; 2355 unsigned char *ptr; 2356 int i, total_len; 2357 u_int32_t rxstat = 0; 2358 2359 i = sc->dc_pnic_rx_bug_save; 2360 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2361 ptr = sc->dc_pnic_rx_buf; 2362 bzero(ptr, sizeof(DC_RXLEN * 5)); 2363 2364 /* Copy all the bytes from the bogus buffers. */ 2365 while (1) { 2366 c = &sc->dc_ldata->dc_rx_list[i]; 2367 rxstat = c->dc_status; 2368 m = sc->dc_cdata.dc_rx_chain[i]; 2369 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2370 ptr += DC_RXLEN; 2371 /* If this is the last buffer, break out. */ 2372 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2373 break; 2374 dc_newbuf(sc, i, m); 2375 DC_INC(i, DC_RX_LIST_CNT); 2376 } 2377 2378 /* Find the length of the actual receive frame. */ 2379 total_len = DC_RXBYTES(rxstat); 2380 2381 /* Scan backwards until we hit a non-zero byte. */ 2382 while(*ptr == 0x00) 2383 ptr--; 2384 2385 /* Round off. */ 2386 if ((uintptr_t)(ptr) & 0x3) 2387 ptr -= 1; 2388 2389 /* Now find the start of the frame. */ 2390 ptr -= total_len; 2391 if (ptr < sc->dc_pnic_rx_buf) 2392 ptr = sc->dc_pnic_rx_buf; 2393 2394 /* 2395 * Now copy the salvaged frame to the last mbuf and fake up 2396 * the status word to make it look like a successful 2397 * frame reception. 2398 */ 2399 dc_newbuf(sc, i, m); 2400 bcopy(ptr, mtod(m, char *), total_len); 2401 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2402 2403 return; 2404} 2405 2406/* 2407 * This routine searches the RX ring for dirty descriptors in the 2408 * event that the rxeof routine falls out of sync with the chip's 2409 * current descriptor pointer. This may happen sometimes as a result 2410 * of a "no RX buffer available" condition that happens when the chip 2411 * consumes all of the RX buffers before the driver has a chance to 2412 * process the RX ring. This routine may need to be called more than 2413 * once to bring the driver back in sync with the chip, however we 2414 * should still be getting RX DONE interrupts to drive the search 2415 * for new packets in the RX ring, so we should catch up eventually. 2416 */ 2417static int dc_rx_resync(sc) 2418 struct dc_softc *sc; 2419{ 2420 int i, pos; 2421 struct dc_desc *cur_rx; 2422 2423 pos = sc->dc_cdata.dc_rx_prod; 2424 2425 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2426 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2427 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2428 break; 2429 DC_INC(pos, DC_RX_LIST_CNT); 2430 } 2431 2432 /* If the ring really is empty, then just return. */ 2433 if (i == DC_RX_LIST_CNT) 2434 return(0); 2435 2436 /* We've fallen behing the chip: catch it. */ 2437 sc->dc_cdata.dc_rx_prod = pos; 2438 2439 return(EAGAIN); 2440} 2441 2442/* 2443 * A frame has been uploaded: pass the resulting mbuf chain up to 2444 * the higher level protocols. 2445 */ 2446static void dc_rxeof(sc) 2447 struct dc_softc *sc; 2448{ 2449 struct ether_header *eh; 2450 struct mbuf *m; 2451 struct ifnet *ifp; 2452 struct dc_desc *cur_rx; 2453 int i, total_len = 0; 2454 u_int32_t rxstat; 2455 2456 ifp = &sc->arpcom.ac_if; 2457 i = sc->dc_cdata.dc_rx_prod; 2458 2459 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2460 struct mbuf *m0 = NULL; 2461 2462 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2463 rxstat = cur_rx->dc_status; 2464 m = sc->dc_cdata.dc_rx_chain[i]; 2465 total_len = DC_RXBYTES(rxstat); 2466 2467 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2468 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2469 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2470 sc->dc_pnic_rx_bug_save = i; 2471 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2472 DC_INC(i, DC_RX_LIST_CNT); 2473 continue; 2474 } 2475 dc_pnic_rx_bug_war(sc, i); 2476 rxstat = cur_rx->dc_status; 2477 total_len = DC_RXBYTES(rxstat); 2478 } 2479 } 2480 2481 sc->dc_cdata.dc_rx_chain[i] = NULL; 2482 2483 /* 2484 * If an error occurs, update stats, clear the 2485 * status word and leave the mbuf cluster in place: 2486 * it should simply get re-used next time this descriptor 2487 * comes up in the ring. 2488 */ 2489 if (rxstat & DC_RXSTAT_RXERR) { 2490 ifp->if_ierrors++; 2491 if (rxstat & DC_RXSTAT_COLLSEEN) 2492 ifp->if_collisions++; 2493 dc_newbuf(sc, i, m); 2494 if (rxstat & DC_RXSTAT_CRCERR) { 2495 DC_INC(i, DC_RX_LIST_CNT); 2496 continue; 2497 } else { 2498 dc_init(sc); 2499 return; 2500 } 2501 } 2502 2503 /* No errors; receive the packet. */ 2504 total_len -= ETHER_CRC_LEN; 2505 2506 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2507 total_len + ETHER_ALIGN, 0, ifp, NULL); 2508 dc_newbuf(sc, i, m); 2509 DC_INC(i, DC_RX_LIST_CNT); 2510 if (m0 == NULL) { 2511 ifp->if_ierrors++; 2512 continue; 2513 } 2514 m_adj(m0, ETHER_ALIGN); 2515 m = m0; 2516 2517 ifp->if_ipackets++; 2518 eh = mtod(m, struct ether_header *); 2519 2520 /* Remove header from mbuf and pass it on. */ 2521 m_adj(m, sizeof(struct ether_header)); 2522 ether_input(ifp, eh, m); 2523 } 2524 2525 sc->dc_cdata.dc_rx_prod = i; 2526} 2527 2528/* 2529 * A frame was downloaded to the chip. It's safe for us to clean up 2530 * the list buffers. 2531 */ 2532 2533static void dc_txeof(sc) 2534 struct dc_softc *sc; 2535{ 2536 struct dc_desc *cur_tx = NULL; 2537 struct ifnet *ifp; 2538 int idx; 2539 2540 ifp = &sc->arpcom.ac_if; 2541 2542 /* Clear the timeout timer. */ 2543 ifp->if_timer = 0; 2544 2545 /* 2546 * Go through our tx list and free mbufs for those 2547 * frames that have been transmitted. 2548 */ 2549 idx = sc->dc_cdata.dc_tx_cons; 2550 while(idx != sc->dc_cdata.dc_tx_prod) { 2551 u_int32_t txstat; 2552 2553 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2554 txstat = cur_tx->dc_status; 2555 2556 if (txstat & DC_TXSTAT_OWN) 2557 break; 2558 2559 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2560 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2561 sc->dc_cdata.dc_tx_cnt--; 2562 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2563 /* 2564 * Yes, the PNIC is so brain damaged 2565 * that it will sometimes generate a TX 2566 * underrun error while DMAing the RX 2567 * filter setup frame. If we detect this, 2568 * we have to send the setup frame again, 2569 * or else the filter won't be programmed 2570 * correctly. 2571 */ 2572 if (DC_IS_PNIC(sc)) { 2573 if (txstat & DC_TXSTAT_ERRSUM) 2574 dc_setfilt(sc); 2575 } 2576 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2577 } 2578 DC_INC(idx, DC_TX_LIST_CNT); 2579 continue; 2580 } 2581 2582 if (DC_IS_XIRCOM(sc)) { 2583 /* 2584 * XXX: Why does my Xircom taunt me so? 2585 * For some reason it likes setting the CARRLOST flag 2586 * even when the carrier is there. wtf?!? */ 2587 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2588 sc->dc_pmode == DC_PMODE_MII && 2589 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2590 DC_TXSTAT_NOCARRIER))) 2591 txstat &= ~DC_TXSTAT_ERRSUM; 2592 } else { 2593 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2594 sc->dc_pmode == DC_PMODE_MII && 2595 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2596 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2597 txstat &= ~DC_TXSTAT_ERRSUM; 2598 } 2599 2600 if (txstat & DC_TXSTAT_ERRSUM) { 2601 ifp->if_oerrors++; 2602 if (txstat & DC_TXSTAT_EXCESSCOLL) 2603 ifp->if_collisions++; 2604 if (txstat & DC_TXSTAT_LATECOLL) 2605 ifp->if_collisions++; 2606 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2607 dc_init(sc); 2608 return; 2609 } 2610 } 2611 2612 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2613 2614 ifp->if_opackets++; 2615 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2616 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2617 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2618 } 2619 2620 sc->dc_cdata.dc_tx_cnt--; 2621 DC_INC(idx, DC_TX_LIST_CNT); 2622 } 2623 2624 sc->dc_cdata.dc_tx_cons = idx; 2625 if (cur_tx != NULL) 2626 ifp->if_flags &= ~IFF_OACTIVE; 2627 2628 return; 2629} 2630 2631static void dc_tick(xsc) 2632 void *xsc; 2633{ 2634 struct dc_softc *sc; 2635 struct mii_data *mii; 2636 struct ifnet *ifp; 2637 u_int32_t r; 2638 2639 sc = xsc; 2640 DC_LOCK(sc); 2641 ifp = &sc->arpcom.ac_if; 2642 mii = device_get_softc(sc->dc_miibus); 2643 2644 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2645 if (sc->dc_flags & DC_21143_NWAY) { 2646 r = CSR_READ_4(sc, DC_10BTSTAT); 2647 if (IFM_SUBTYPE(mii->mii_media_active) == 2648 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2649 sc->dc_link = 0; 2650 mii_mediachg(mii); 2651 } 2652 if (IFM_SUBTYPE(mii->mii_media_active) == 2653 IFM_10_T && (r & DC_TSTAT_LS10)) { 2654 sc->dc_link = 0; 2655 mii_mediachg(mii); 2656 } 2657 if (sc->dc_link == 0) 2658 mii_tick(mii); 2659 } else { 2660 r = CSR_READ_4(sc, DC_ISR); 2661 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2662 sc->dc_cdata.dc_tx_cnt == 0) 2663 mii_tick(mii); 2664 if (!(mii->mii_media_status & IFM_ACTIVE)) 2665 sc->dc_link = 0; 2666 } 2667 } else 2668 mii_tick(mii); 2669 2670 /* 2671 * When the init routine completes, we expect to be able to send 2672 * packets right away, and in fact the network code will send a 2673 * gratuitous ARP the moment the init routine marks the interface 2674 * as running. However, even though the MAC may have been initialized, 2675 * there may be a delay of a few seconds before the PHY completes 2676 * autonegotiation and the link is brought up. Any transmissions 2677 * made during that delay will be lost. Dealing with this is tricky: 2678 * we can't just pause in the init routine while waiting for the 2679 * PHY to come ready since that would bring the whole system to 2680 * a screeching halt for several seconds. 2681 * 2682 * What we do here is prevent the TX start routine from sending 2683 * any packets until a link has been established. After the 2684 * interface has been initialized, the tick routine will poll 2685 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2686 * that time, packets will stay in the send queue, and once the 2687 * link comes up, they will be flushed out to the wire. 2688 */ 2689 if (!sc->dc_link) { 2690 mii_pollstat(mii); 2691 if (mii->mii_media_status & IFM_ACTIVE && 2692 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2693 sc->dc_link++; 2694 if (ifp->if_snd.ifq_head != NULL) 2695 dc_start(ifp); 2696 } 2697 } 2698 2699 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2700 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2701 else 2702 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2703 2704 DC_UNLOCK(sc); 2705 2706 return; 2707} 2708 2709static void dc_intr(arg) 2710 void *arg; 2711{ 2712 struct dc_softc *sc; 2713 struct ifnet *ifp; 2714 u_int32_t status; 2715 2716 sc = arg; 2717 DC_LOCK(sc); 2718 ifp = &sc->arpcom.ac_if; 2719 2720 /* Supress unwanted interrupts */ 2721 if (!(ifp->if_flags & IFF_UP)) { 2722 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2723 dc_stop(sc); 2724 DC_UNLOCK(sc); 2725 return; 2726 } 2727 2728 /* Disable interrupts. */ 2729 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2730 2731 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 2732 && status != 0xFFFFFFFF) { 2733 2734 CSR_WRITE_4(sc, DC_ISR, status); 2735 2736 if (status & DC_ISR_RX_OK) { 2737 int curpkts; 2738 curpkts = ifp->if_ipackets; 2739 dc_rxeof(sc); 2740 if (curpkts == ifp->if_ipackets) { 2741 while(dc_rx_resync(sc)) 2742 dc_rxeof(sc); 2743 } 2744 } 2745 2746 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2747 dc_txeof(sc); 2748 2749 if (status & DC_ISR_TX_IDLE) { 2750 dc_txeof(sc); 2751 if (sc->dc_cdata.dc_tx_cnt) { 2752 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2753 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2754 } 2755 } 2756 2757 if (status & DC_ISR_TX_UNDERRUN) { 2758 u_int32_t cfg; 2759 2760 printf("dc%d: TX underrun -- ", sc->dc_unit); 2761 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2762 dc_init(sc); 2763 cfg = CSR_READ_4(sc, DC_NETCFG); 2764 cfg &= ~DC_NETCFG_TX_THRESH; 2765 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2766 printf("using store and forward mode\n"); 2767 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2768 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2769 printf("resetting\n"); 2770 } else { 2771 sc->dc_txthresh += 0x4000; 2772 printf("increasing TX threshold\n"); 2773 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2774 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2775 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2776 } 2777 } 2778 2779 if ((status & DC_ISR_RX_WATDOGTIMEO) 2780 || (status & DC_ISR_RX_NOBUF)) { 2781 int curpkts; 2782 curpkts = ifp->if_ipackets; 2783 dc_rxeof(sc); 2784 if (curpkts == ifp->if_ipackets) { 2785 while(dc_rx_resync(sc)) 2786 dc_rxeof(sc); 2787 } 2788 } 2789 2790 if (status & DC_ISR_BUS_ERR) { 2791 dc_reset(sc); 2792 dc_init(sc); 2793 } 2794 } 2795 2796 /* Re-enable interrupts. */ 2797 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2798 2799 if (ifp->if_snd.ifq_head != NULL) 2800 dc_start(ifp); 2801 2802 DC_UNLOCK(sc); 2803 2804 return; 2805} 2806 2807/* 2808 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2809 * pointers to the fragment pointers. 2810 */ 2811static int dc_encap(sc, m_head, txidx) 2812 struct dc_softc *sc; 2813 struct mbuf *m_head; 2814 u_int32_t *txidx; 2815{ 2816 struct dc_desc *f = NULL; 2817 struct mbuf *m; 2818 int frag, cur, cnt = 0; 2819 2820 /* 2821 * Start packing the mbufs in this chain into 2822 * the fragment pointers. Stop when we run out 2823 * of fragments or hit the end of the mbuf chain. 2824 */ 2825 m = m_head; 2826 cur = frag = *txidx; 2827 2828 for (m = m_head; m != NULL; m = m->m_next) { 2829 if (m->m_len != 0) { 2830 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2831 if (*txidx != sc->dc_cdata.dc_tx_prod && 2832 frag == (DC_TX_LIST_CNT - 1)) 2833 return(ENOBUFS); 2834 } 2835 if ((DC_TX_LIST_CNT - 2836 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2837 return(ENOBUFS); 2838 2839 f = &sc->dc_ldata->dc_tx_list[frag]; 2840 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2841 if (cnt == 0) { 2842 f->dc_status = 0; 2843 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2844 } else 2845 f->dc_status = DC_TXSTAT_OWN; 2846 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2847 cur = frag; 2848 DC_INC(frag, DC_TX_LIST_CNT); 2849 cnt++; 2850 } 2851 } 2852 2853 if (m != NULL) 2854 return(ENOBUFS); 2855 2856 sc->dc_cdata.dc_tx_cnt += cnt; 2857 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2858 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2859 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2860 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2861 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2862 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2863 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2864 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2865 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2866 *txidx = frag; 2867 2868 return(0); 2869} 2870 2871/* 2872 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2873 * Needed for some really badly behaved chips that just can't 2874 * do scatter/gather correctly. 2875 */ 2876static int dc_coal(sc, m_head) 2877 struct dc_softc *sc; 2878 struct mbuf **m_head; 2879{ 2880 struct mbuf *m_new, *m; 2881 2882 m = *m_head; 2883 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2884 if (m_new == NULL) { 2885 printf("dc%d: no memory for tx list", sc->dc_unit); 2886 return(ENOBUFS); 2887 } 2888 if (m->m_pkthdr.len > MHLEN) { 2889 MCLGET(m_new, M_DONTWAIT); 2890 if (!(m_new->m_flags & M_EXT)) { 2891 m_freem(m_new); 2892 printf("dc%d: no memory for tx list", sc->dc_unit); 2893 return(ENOBUFS); 2894 } 2895 } 2896 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2897 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2898 m_freem(m); 2899 *m_head = m_new; 2900 2901 return(0); 2902} 2903 2904/* 2905 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2906 * to the mbuf data regions directly in the transmit lists. We also save a 2907 * copy of the pointers since the transmit list fragment pointers are 2908 * physical addresses. 2909 */ 2910 2911static void dc_start(ifp) 2912 struct ifnet *ifp; 2913{ 2914 struct dc_softc *sc; 2915 struct mbuf *m_head = NULL; 2916 int idx; 2917 2918 sc = ifp->if_softc; 2919 2920 DC_LOCK(sc); 2921 2922 if (!sc->dc_link) { 2923 DC_UNLOCK(sc); 2924 return; 2925 } 2926 2927 if (ifp->if_flags & IFF_OACTIVE) { 2928 DC_UNLOCK(sc); 2929 return; 2930 } 2931 2932 idx = sc->dc_cdata.dc_tx_prod; 2933 2934 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2935 IF_DEQUEUE(&ifp->if_snd, m_head); 2936 if (m_head == NULL) 2937 break; 2938 2939 if (sc->dc_flags & DC_TX_COALESCE) { 2940 if (dc_coal(sc, &m_head)) { 2941 IF_PREPEND(&ifp->if_snd, m_head); 2942 ifp->if_flags |= IFF_OACTIVE; 2943 break; 2944 } 2945 } 2946 2947 if (dc_encap(sc, m_head, &idx)) { 2948 IF_PREPEND(&ifp->if_snd, m_head); 2949 ifp->if_flags |= IFF_OACTIVE; 2950 break; 2951 } 2952 2953 /* 2954 * If there's a BPF listener, bounce a copy of this frame 2955 * to him. 2956 */ 2957 if (ifp->if_bpf) 2958 bpf_mtap(ifp, m_head); 2959 2960 if (sc->dc_flags & DC_TX_ONE) { 2961 ifp->if_flags |= IFF_OACTIVE; 2962 break; 2963 } 2964 } 2965 2966 /* Transmit */ 2967 sc->dc_cdata.dc_tx_prod = idx; 2968 if (!(sc->dc_flags & DC_TX_POLL)) 2969 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2970 2971 /* 2972 * Set a timeout in case the chip goes out to lunch. 2973 */ 2974 ifp->if_timer = 5; 2975 2976 DC_UNLOCK(sc); 2977 2978 return; 2979} 2980 2981static void dc_init(xsc) 2982 void *xsc; 2983{ 2984 struct dc_softc *sc = xsc; 2985 struct ifnet *ifp = &sc->arpcom.ac_if; 2986 struct mii_data *mii; 2987 2988 DC_LOCK(sc); 2989 2990 mii = device_get_softc(sc->dc_miibus); 2991 2992 /* 2993 * Cancel pending I/O and free all RX/TX buffers. 2994 */ 2995 dc_stop(sc); 2996 dc_reset(sc); 2997 2998 /* 2999 * Set cache alignment and burst length. 3000 */ 3001 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3002 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3003 else 3004 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3005 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3006 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3007 } else { 3008 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3009 } 3010 if (sc->dc_flags & DC_TX_POLL) 3011 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3012 switch(sc->dc_cachesize) { 3013 case 32: 3014 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3015 break; 3016 case 16: 3017 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3018 break; 3019 case 8: 3020 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3021 break; 3022 case 0: 3023 default: 3024 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3025 break; 3026 } 3027 3028 if (sc->dc_flags & DC_TX_STORENFWD) 3029 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3030 else { 3031 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 3032 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3033 } else { 3034 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3035 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3036 } 3037 } 3038 3039 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3040 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3041 3042 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3043 /* 3044 * The app notes for the 98713 and 98715A say that 3045 * in order to have the chips operate properly, a magic 3046 * number must be written to CSR16. Macronix does not 3047 * document the meaning of these bits so there's no way 3048 * to know exactly what they do. The 98713 has a magic 3049 * number all its own; the rest all use a different one. 3050 */ 3051 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3052 if (sc->dc_type == DC_TYPE_98713) 3053 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3054 else 3055 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3056 } 3057 3058 if (DC_IS_XIRCOM(sc)) { 3059 /* 3060 * setup General Purpose Port mode and data so the tulip 3061 * can talk to the MII. 3062 */ 3063 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3064 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3065 DELAY(10); 3066 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3067 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3068 DELAY(10); 3069 } 3070 3071 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3072 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 3073 3074 /* Init circular RX list. */ 3075 if (dc_list_rx_init(sc) == ENOBUFS) { 3076 printf("dc%d: initialization failed: no " 3077 "memory for rx buffers\n", sc->dc_unit); 3078 dc_stop(sc); 3079 DC_UNLOCK(sc); 3080 return; 3081 } 3082 3083 /* 3084 * Init tx descriptors. 3085 */ 3086 dc_list_tx_init(sc); 3087 3088 /* 3089 * Load the address of the RX list. 3090 */ 3091 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3092 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3093 3094 /* 3095 * Enable interrupts. 3096 */ 3097 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3098 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3099 3100 /* Enable transmitter. */ 3101 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3102 3103 /* 3104 * If this is an Intel 21143 and we're not using the 3105 * MII port, program the LED control pins so we get 3106 * link and activity indications. 3107 */ 3108 if (sc->dc_flags & DC_TULIP_LEDS) { 3109 CSR_WRITE_4(sc, DC_WATCHDOG, 3110 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3111 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3112 } 3113 3114 /* 3115 * Load the RX/multicast filter. We do this sort of late 3116 * because the filter programming scheme on the 21143 and 3117 * some clones requires DMAing a setup frame via the TX 3118 * engine, and we need the transmitter enabled for that. 3119 */ 3120 dc_setfilt(sc); 3121 3122 /* Enable receiver. */ 3123 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3124 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3125 3126 mii_mediachg(mii); 3127 dc_setcfg(sc, sc->dc_if_media); 3128 3129 ifp->if_flags |= IFF_RUNNING; 3130 ifp->if_flags &= ~IFF_OACTIVE; 3131 3132 /* Don't start the ticker if this is a homePNA link. */ 3133 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_homePNA) 3134 sc->dc_link = 1; 3135 else { 3136 if (sc->dc_flags & DC_21143_NWAY) 3137 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 3138 else 3139 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 3140 } 3141 3142#ifdef SRM_MEDIA 3143 if(sc->dc_srm_media) { 3144 struct ifreq ifr; 3145 3146 ifr.ifr_media = sc->dc_srm_media; 3147 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3148 sc->dc_srm_media = 0; 3149 } 3150#endif 3151 DC_UNLOCK(sc); 3152 return; 3153} 3154 3155/* 3156 * Set media options. 3157 */ 3158static int dc_ifmedia_upd(ifp) 3159 struct ifnet *ifp; 3160{ 3161 struct dc_softc *sc; 3162 struct mii_data *mii; 3163 struct ifmedia *ifm; 3164 3165 sc = ifp->if_softc; 3166 mii = device_get_softc(sc->dc_miibus); 3167 mii_mediachg(mii); 3168 ifm = &mii->mii_media; 3169 3170 if (DC_IS_DAVICOM(sc) && 3171 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 3172 dc_setcfg(sc, ifm->ifm_media); 3173 else 3174 sc->dc_link = 0; 3175 3176 return(0); 3177} 3178 3179/* 3180 * Report current media status. 3181 */ 3182static void dc_ifmedia_sts(ifp, ifmr) 3183 struct ifnet *ifp; 3184 struct ifmediareq *ifmr; 3185{ 3186 struct dc_softc *sc; 3187 struct mii_data *mii; 3188 struct ifmedia *ifm; 3189 3190 sc = ifp->if_softc; 3191 mii = device_get_softc(sc->dc_miibus); 3192 mii_pollstat(mii); 3193 ifm = &mii->mii_media; 3194 if (DC_IS_DAVICOM(sc)) { 3195 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 3196 ifmr->ifm_active = ifm->ifm_media; 3197 ifmr->ifm_status = 0; 3198 return; 3199 } 3200 } 3201 ifmr->ifm_active = mii->mii_media_active; 3202 ifmr->ifm_status = mii->mii_media_status; 3203 3204 return; 3205} 3206 3207static int dc_ioctl(ifp, command, data) 3208 struct ifnet *ifp; 3209 u_long command; 3210 caddr_t data; 3211{ 3212 struct dc_softc *sc = ifp->if_softc; 3213 struct ifreq *ifr = (struct ifreq *) data; 3214 struct mii_data *mii; 3215 int error = 0; 3216 3217 DC_LOCK(sc); 3218 3219 switch(command) { 3220 case SIOCSIFADDR: 3221 case SIOCGIFADDR: 3222 case SIOCSIFMTU: 3223 error = ether_ioctl(ifp, command, data); 3224 break; 3225 case SIOCSIFFLAGS: 3226 if (ifp->if_flags & IFF_UP) { 3227 if (ifp->if_flags & IFF_RUNNING && 3228 ifp->if_flags & IFF_PROMISC && 3229 !(sc->dc_if_flags & IFF_PROMISC)) { 3230 dc_setfilt(sc); 3231 } else if (ifp->if_flags & IFF_RUNNING && 3232 !(ifp->if_flags & IFF_PROMISC) && 3233 sc->dc_if_flags & IFF_PROMISC) { 3234 dc_setfilt(sc); 3235 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3236 sc->dc_txthresh = 0; 3237 dc_init(sc); 3238 } 3239 } else { 3240 if (ifp->if_flags & IFF_RUNNING) 3241 dc_stop(sc); 3242 } 3243 sc->dc_if_flags = ifp->if_flags; 3244 error = 0; 3245 break; 3246 case SIOCADDMULTI: 3247 case SIOCDELMULTI: 3248 dc_setfilt(sc); 3249 error = 0; 3250 break; 3251 case SIOCGIFMEDIA: 3252 case SIOCSIFMEDIA: 3253 mii = device_get_softc(sc->dc_miibus); 3254 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3255#ifdef SRM_MEDIA 3256 if (sc->dc_srm_media) 3257 sc->dc_srm_media = 0; 3258#endif 3259 break; 3260 default: 3261 error = EINVAL; 3262 break; 3263 } 3264 3265 DC_UNLOCK(sc); 3266 3267 return(error); 3268} 3269 3270static void dc_watchdog(ifp) 3271 struct ifnet *ifp; 3272{ 3273 struct dc_softc *sc; 3274 3275 sc = ifp->if_softc; 3276 3277 DC_LOCK(sc); 3278 3279 ifp->if_oerrors++; 3280 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3281 3282 dc_stop(sc); 3283 dc_reset(sc); 3284 dc_init(sc); 3285 3286 if (ifp->if_snd.ifq_head != NULL) 3287 dc_start(ifp); 3288 3289 DC_UNLOCK(sc); 3290 3291 return; 3292} 3293 3294/* 3295 * Stop the adapter and free any mbufs allocated to the 3296 * RX and TX lists. 3297 */ 3298static void dc_stop(sc) 3299 struct dc_softc *sc; 3300{ 3301 register int i; 3302 struct ifnet *ifp; 3303 3304 DC_LOCK(sc); 3305 3306 ifp = &sc->arpcom.ac_if; 3307 ifp->if_timer = 0; 3308 3309 untimeout(dc_tick, sc, sc->dc_stat_ch); 3310 3311 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3312 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3313 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3314 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3315 sc->dc_link = 0; 3316 3317 /* 3318 * Free data in the RX lists. 3319 */ 3320 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3321 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3322 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3323 sc->dc_cdata.dc_rx_chain[i] = NULL; 3324 } 3325 } 3326 bzero((char *)&sc->dc_ldata->dc_rx_list, 3327 sizeof(sc->dc_ldata->dc_rx_list)); 3328 3329 /* 3330 * Free the TX list buffers. 3331 */ 3332 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3333 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3334 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3335 DC_TXCTL_SETUP) { 3336 sc->dc_cdata.dc_tx_chain[i] = NULL; 3337 continue; 3338 } 3339 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3340 sc->dc_cdata.dc_tx_chain[i] = NULL; 3341 } 3342 } 3343 3344 bzero((char *)&sc->dc_ldata->dc_tx_list, 3345 sizeof(sc->dc_ldata->dc_tx_list)); 3346 3347 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3348 3349 DC_UNLOCK(sc); 3350 3351 return; 3352} 3353 3354/* 3355 * Stop all chip I/O so that the kernel's probe routines don't 3356 * get confused by errant DMAs when rebooting. 3357 */ 3358static void dc_shutdown(dev) 3359 device_t dev; 3360{ 3361 struct dc_softc *sc; 3362 3363 sc = device_get_softc(dev); 3364 3365 dc_stop(sc); 3366 3367 return; 3368} 3369