if_dc.c revision 61363
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/dc/if_dc.c 61363 2000-06-07 17:07:44Z wpaul $ 33 */ 34 35/* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * 48 * Datasheets for the 21143 are available at developer.intel.com. 49 * Datasheets for the clone parts can be found at their respective sites. 50 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 51 * The PNIC II is essentially a Macronix 98715A chip; the only difference 52 * worth noting is that its multicast hash table is only 128 bits wide 53 * instead of 512. 54 * 55 * Written by Bill Paul <wpaul@ee.columbia.edu> 56 * Electrical Engineering Department 57 * Columbia University, New York City 58 */ 59 60/* 61 * The Intel 21143 is the successor to the DEC 21140. It is basically 62 * the same as the 21140 but with a few new features. The 21143 supports 63 * three kinds of media attachments: 64 * 65 * o MII port, for 10Mbps and 100Mbps support and NWAY 66 * autonegotiation provided by an external PHY. 67 * o SYM port, for symbol mode 100Mbps support. 68 * o 10baseT port. 69 * o AUI/BNC port. 70 * 71 * The 100Mbps SYM port and 10baseT port can be used together in 72 * combination with the internal NWAY support to create a 10/100 73 * autosensing configuration. 74 * 75 * Knowing which media is available on a given card is tough: you're 76 * supposed to go slogging through the EEPROM looking for media 77 * description structures. Unfortunately, some card vendors that use 78 * the 21143 don't obey the DEC SROM spec correctly, which means that 79 * what you find in the EEPROM may not agree with reality. Fortunately, 80 * the 21143 provides us a way to get around this issue: lurking in 81 * PCI configuration space is the Configuration Wake-Up Command Register. 82 * This register is loaded with a value from the EEPROM when wake on LAN 83 * mode is enabled; this value tells us quite clearly what kind of media 84 * is attached to the NIC. The main purpose of this register is to tell 85 * the NIC what media to scan when in wake on LAN mode, however by 86 * forcibly enabling wake on LAN mode, we can use to learn what kind of 87 * media a given NIC has available and adapt ourselves accordingly. 88 * 89 * Of course, if the media description blocks in the EEPROM are bogus. 90 * what are the odds that the CWUC aren't bogus as well, right? Well, 91 * the CWUC value is more likely to be correct since wake on LAN mode 92 * won't work correctly without it, and wake on LAN is a big selling 93 * point these days. It's also harder to screw up a single byte than 94 * a whole media descriptor block. 95 * 96 * Note that not all tulip workalikes are handled in this driver: we only 97 * deal with those which are relatively well behaved. The Winbond is 98 * handled separately due to its different register offsets and the 99 * special handling needed for its various bugs. The PNIC is handled 100 * here, but I'm not thrilled about it. 101 * 102 * All of the workalike chips use some form of MII transceiver support 103 * with the exception of the Macronix chips, which also have a SYM port. 104 * The ASIX AX88140A is also documented to have a SYM port, but all 105 * the cards I've seen use an MII transceiver, probably because the 106 * AX88140A doesn't support internal NWAY. 107 */ 108 109#include <sys/param.h> 110#include <sys/systm.h> 111#include <sys/sockio.h> 112#include <sys/mbuf.h> 113#include <sys/malloc.h> 114#include <sys/kernel.h> 115#include <sys/socket.h> 116 117#include <net/if.h> 118#include <net/if_arp.h> 119#include <net/ethernet.h> 120#include <net/if_dl.h> 121#include <net/if_media.h> 122 123#include <net/bpf.h> 124 125#include <vm/vm.h> /* for vtophys */ 126#include <vm/pmap.h> /* for vtophys */ 127#include <machine/clock.h> /* for DELAY */ 128#include <machine/bus_pio.h> 129#include <machine/bus_memio.h> 130#include <machine/bus.h> 131#include <machine/resource.h> 132#include <sys/bus.h> 133#include <sys/rman.h> 134 135#include <dev/mii/mii.h> 136#include <dev/mii/miivar.h> 137 138#include <pci/pcireg.h> 139#include <pci/pcivar.h> 140 141#define DC_USEIOSPACE 142 143#include <pci/if_dcreg.h> 144 145MODULE_DEPEND(dc, miibus, 1, 1, 1); 146 147/* "controller miibus0" required. See GENERIC if you get errors here. */ 148#include "miibus_if.h" 149 150#ifndef lint 151static const char rcsid[] = 152 "$FreeBSD: head/sys/dev/dc/if_dc.c 61363 2000-06-07 17:07:44Z wpaul $"; 153#endif 154 155/* 156 * Various supported device vendors/types and their names. 157 */ 158static struct dc_type dc_devs[] = { 159 { DC_VENDORID_DEC, DC_DEVICEID_21143, 160 "Intel 21143 10/100BaseTX" }, 161 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 162 "Davicom DM9100 10/100BaseTX" }, 163 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 164 "Davicom DM9102 10/100BaseTX" }, 165 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 166 "Davicom DM9102A 10/100BaseTX" }, 167 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 168 "ADMtek AL981 10/100BaseTX" }, 169 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 170 "ADMtek AN985 10/100BaseTX" }, 171 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 172 "ASIX AX88140A 10/100BaseTX" }, 173 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 174 "ASIX AX88141 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_98713, 176 "Macronix 98713 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98713, 178 "Macronix 98713A 10/100BaseTX" }, 179 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 180 "Compex RL100-TX 10/100BaseTX" }, 181 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_VENDORID_MX, DC_DEVICEID_987x5, 184 "Macronix 98715/98715A 10/100BaseTX" }, 185 { DC_VENDORID_MX, DC_DEVICEID_987x5, 186 "Macronix 98725 10/100BaseTX" }, 187 { DC_VENDORID_LO, DC_DEVICEID_82C115, 188 "LC82C115 PNIC II 10/100BaseTX" }, 189 { DC_VENDORID_LO, DC_DEVICEID_82C168, 190 "82c168 PNIC 10/100BaseTX" }, 191 { DC_VENDORID_LO, DC_DEVICEID_82C168, 192 "82c169 PNIC 10/100BaseTX" }, 193 { 0, 0, NULL } 194}; 195 196static int dc_probe __P((device_t)); 197static int dc_attach __P((device_t)); 198static int dc_detach __P((device_t)); 199static void dc_acpi __P((device_t)); 200static struct dc_type *dc_devtype __P((device_t)); 201static int dc_newbuf __P((struct dc_softc *, int, struct mbuf *)); 202static int dc_encap __P((struct dc_softc *, struct mbuf *, 203 u_int32_t *)); 204static int dc_coal __P((struct dc_softc *, struct mbuf **)); 205static void dc_pnic_rx_bug_war __P((struct dc_softc *, int)); 206static int dc_rx_resync __P((struct dc_softc *)); 207static void dc_rxeof __P((struct dc_softc *)); 208static void dc_txeof __P((struct dc_softc *)); 209static void dc_tick __P((void *)); 210static void dc_intr __P((void *)); 211static void dc_start __P((struct ifnet *)); 212static int dc_ioctl __P((struct ifnet *, u_long, caddr_t)); 213static void dc_init __P((void *)); 214static void dc_stop __P((struct dc_softc *)); 215static void dc_watchdog __P((struct ifnet *)); 216static void dc_shutdown __P((device_t)); 217static int dc_ifmedia_upd __P((struct ifnet *)); 218static void dc_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 219 220static void dc_delay __P((struct dc_softc *)); 221static void dc_eeprom_idle __P((struct dc_softc *)); 222static void dc_eeprom_putbyte __P((struct dc_softc *, int)); 223static void dc_eeprom_getword __P((struct dc_softc *, int, u_int16_t *)); 224static void dc_eeprom_getword_pnic 225 __P((struct dc_softc *, int, u_int16_t *)); 226static void dc_read_eeprom __P((struct dc_softc *, caddr_t, int, 227 int, int)); 228 229static void dc_mii_writebit __P((struct dc_softc *, int)); 230static int dc_mii_readbit __P((struct dc_softc *)); 231static void dc_mii_sync __P((struct dc_softc *)); 232static void dc_mii_send __P((struct dc_softc *, u_int32_t, int)); 233static int dc_mii_readreg __P((struct dc_softc *, struct dc_mii_frame *)); 234static int dc_mii_writereg __P((struct dc_softc *, struct dc_mii_frame *)); 235static int dc_miibus_readreg __P((device_t, int, int)); 236static int dc_miibus_writereg __P((device_t, int, int, int)); 237static void dc_miibus_statchg __P((device_t)); 238static void dc_miibus_mediainit __P((device_t)); 239 240static void dc_setcfg __P((struct dc_softc *, int)); 241static u_int32_t dc_crc_le __P((struct dc_softc *, caddr_t)); 242static u_int32_t dc_crc_be __P((caddr_t)); 243static void dc_setfilt_21143 __P((struct dc_softc *)); 244static void dc_setfilt_asix __P((struct dc_softc *)); 245static void dc_setfilt_admtek __P((struct dc_softc *)); 246 247static void dc_setfilt __P((struct dc_softc *)); 248 249static void dc_reset __P((struct dc_softc *)); 250static int dc_list_rx_init __P((struct dc_softc *)); 251static int dc_list_tx_init __P((struct dc_softc *)); 252 253#ifdef DC_USEIOSPACE 254#define DC_RES SYS_RES_IOPORT 255#define DC_RID DC_PCI_CFBIO 256#else 257#define DC_RES SYS_RES_MEMORY 258#define DC_RID DC_PCI_CFBMA 259#endif 260 261static device_method_t dc_methods[] = { 262 /* Device interface */ 263 DEVMETHOD(device_probe, dc_probe), 264 DEVMETHOD(device_attach, dc_attach), 265 DEVMETHOD(device_detach, dc_detach), 266 DEVMETHOD(device_shutdown, dc_shutdown), 267 268 /* bus interface */ 269 DEVMETHOD(bus_print_child, bus_generic_print_child), 270 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 271 272 /* MII interface */ 273 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 274 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 275 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 276 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 277 278 { 0, 0 } 279}; 280 281static driver_t dc_driver = { 282 "dc", 283 dc_methods, 284 sizeof(struct dc_softc) 285}; 286 287static devclass_t dc_devclass; 288 289DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 290DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 291 292#define DC_SETBIT(sc, reg, x) \ 293 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 294 295#define DC_CLRBIT(sc, reg, x) \ 296 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 297 298#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 299#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 300 301static void dc_delay(sc) 302 struct dc_softc *sc; 303{ 304 int idx; 305 306 for (idx = (300 / 33) + 1; idx > 0; idx--) 307 CSR_READ_4(sc, DC_BUSCTL); 308} 309 310static void dc_eeprom_idle(sc) 311 struct dc_softc *sc; 312{ 313 register int i; 314 315 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 316 dc_delay(sc); 317 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 318 dc_delay(sc); 319 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 320 dc_delay(sc); 321 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 322 dc_delay(sc); 323 324 for (i = 0; i < 25; i++) { 325 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 326 dc_delay(sc); 327 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 328 dc_delay(sc); 329 } 330 331 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 332 dc_delay(sc); 333 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 334 dc_delay(sc); 335 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 336 337 return; 338} 339 340/* 341 * Send a read command and address to the EEPROM, check for ACK. 342 */ 343static void dc_eeprom_putbyte(sc, addr) 344 struct dc_softc *sc; 345 int addr; 346{ 347 register int d, i; 348 349 /* 350 * The AN985 has a 93C66 EEPROM on it instead of 351 * a 93C46. It uses a different bit sequence for 352 * specifying the "read" opcode. 353 */ 354 if (DC_IS_CENTAUR(sc)) 355 d = addr | (DC_EECMD_READ << 2); 356 else 357 d = addr | DC_EECMD_READ; 358 359 /* 360 * Feed in each bit and strobe the clock. 361 */ 362 for (i = 0x400; i; i >>= 1) { 363 if (d & i) { 364 SIO_SET(DC_SIO_EE_DATAIN); 365 } else { 366 SIO_CLR(DC_SIO_EE_DATAIN); 367 } 368 dc_delay(sc); 369 SIO_SET(DC_SIO_EE_CLK); 370 dc_delay(sc); 371 SIO_CLR(DC_SIO_EE_CLK); 372 dc_delay(sc); 373 } 374 375 return; 376} 377 378/* 379 * Read a word of data stored in the EEPROM at address 'addr.' 380 * The PNIC 82c168/82c169 has its own non-standard way to read 381 * the EEPROM. 382 */ 383static void dc_eeprom_getword_pnic(sc, addr, dest) 384 struct dc_softc *sc; 385 int addr; 386 u_int16_t *dest; 387{ 388 register int i; 389 u_int32_t r; 390 391 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 392 393 for (i = 0; i < DC_TIMEOUT; i++) { 394 DELAY(1); 395 r = CSR_READ_4(sc, DC_SIO); 396 if (!(r & DC_PN_SIOCTL_BUSY)) { 397 *dest = (u_int16_t)(r & 0xFFFF); 398 return; 399 } 400 } 401 402 return; 403} 404 405/* 406 * Read a word of data stored in the EEPROM at address 'addr.' 407 */ 408static void dc_eeprom_getword(sc, addr, dest) 409 struct dc_softc *sc; 410 int addr; 411 u_int16_t *dest; 412{ 413 register int i; 414 u_int16_t word = 0; 415 416 /* Force EEPROM to idle state. */ 417 dc_eeprom_idle(sc); 418 419 /* Enter EEPROM access mode. */ 420 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 421 dc_delay(sc); 422 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 423 dc_delay(sc); 424 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 425 dc_delay(sc); 426 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 427 dc_delay(sc); 428 429 /* 430 * Send address of word we want to read. 431 */ 432 dc_eeprom_putbyte(sc, addr); 433 434 /* 435 * Start reading bits from EEPROM. 436 */ 437 for (i = 0x8000; i; i >>= 1) { 438 SIO_SET(DC_SIO_EE_CLK); 439 dc_delay(sc); 440 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 441 word |= i; 442 dc_delay(sc); 443 SIO_CLR(DC_SIO_EE_CLK); 444 dc_delay(sc); 445 } 446 447 /* Turn off EEPROM access mode. */ 448 dc_eeprom_idle(sc); 449 450 *dest = word; 451 452 return; 453} 454 455/* 456 * Read a sequence of words from the EEPROM. 457 */ 458static void dc_read_eeprom(sc, dest, off, cnt, swap) 459 struct dc_softc *sc; 460 caddr_t dest; 461 int off; 462 int cnt; 463 int swap; 464{ 465 int i; 466 u_int16_t word = 0, *ptr; 467 468 for (i = 0; i < cnt; i++) { 469 if (DC_IS_PNIC(sc)) 470 dc_eeprom_getword_pnic(sc, off + i, &word); 471 else 472 dc_eeprom_getword(sc, off + i, &word); 473 ptr = (u_int16_t *)(dest + (i * 2)); 474 if (swap) 475 *ptr = ntohs(word); 476 else 477 *ptr = word; 478 } 479 480 return; 481} 482 483/* 484 * The following two routines are taken from the Macronix 98713 485 * Application Notes pp.19-21. 486 */ 487/* 488 * Write a bit to the MII bus. 489 */ 490static void dc_mii_writebit(sc, bit) 491 struct dc_softc *sc; 492 int bit; 493{ 494 if (bit) 495 CSR_WRITE_4(sc, DC_SIO, 496 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 497 else 498 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 499 500 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 501 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 502 503 return; 504} 505 506/* 507 * Read a bit from the MII bus. 508 */ 509static int dc_mii_readbit(sc) 510 struct dc_softc *sc; 511{ 512 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 513 CSR_READ_4(sc, DC_SIO); 514 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 515 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 516 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 517 return(1); 518 519 return(0); 520} 521 522/* 523 * Sync the PHYs by setting data bit and strobing the clock 32 times. 524 */ 525static void dc_mii_sync(sc) 526 struct dc_softc *sc; 527{ 528 register int i; 529 530 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 531 532 for (i = 0; i < 32; i++) 533 dc_mii_writebit(sc, 1); 534 535 return; 536} 537 538/* 539 * Clock a series of bits through the MII. 540 */ 541static void dc_mii_send(sc, bits, cnt) 542 struct dc_softc *sc; 543 u_int32_t bits; 544 int cnt; 545{ 546 int i; 547 548 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 549 dc_mii_writebit(sc, bits & i); 550} 551 552/* 553 * Read an PHY register through the MII. 554 */ 555static int dc_mii_readreg(sc, frame) 556 struct dc_softc *sc; 557 struct dc_mii_frame *frame; 558 559{ 560 int i, ack, s; 561 562 s = splimp(); 563 564 /* 565 * Set up frame for RX. 566 */ 567 frame->mii_stdelim = DC_MII_STARTDELIM; 568 frame->mii_opcode = DC_MII_READOP; 569 frame->mii_turnaround = 0; 570 frame->mii_data = 0; 571 572 /* 573 * Sync the PHYs. 574 */ 575 dc_mii_sync(sc); 576 577 /* 578 * Send command/address info. 579 */ 580 dc_mii_send(sc, frame->mii_stdelim, 2); 581 dc_mii_send(sc, frame->mii_opcode, 2); 582 dc_mii_send(sc, frame->mii_phyaddr, 5); 583 dc_mii_send(sc, frame->mii_regaddr, 5); 584 585#ifdef notdef 586 /* Idle bit */ 587 dc_mii_writebit(sc, 1); 588 dc_mii_writebit(sc, 0); 589#endif 590 591 /* Check for ack */ 592 ack = dc_mii_readbit(sc); 593 594 /* 595 * Now try reading data bits. If the ack failed, we still 596 * need to clock through 16 cycles to keep the PHY(s) in sync. 597 */ 598 if (ack) { 599 for(i = 0; i < 16; i++) { 600 dc_mii_readbit(sc); 601 } 602 goto fail; 603 } 604 605 for (i = 0x8000; i; i >>= 1) { 606 if (!ack) { 607 if (dc_mii_readbit(sc)) 608 frame->mii_data |= i; 609 } 610 } 611 612fail: 613 614 dc_mii_writebit(sc, 0); 615 dc_mii_writebit(sc, 0); 616 617 splx(s); 618 619 if (ack) 620 return(1); 621 return(0); 622} 623 624/* 625 * Write to a PHY register through the MII. 626 */ 627static int dc_mii_writereg(sc, frame) 628 struct dc_softc *sc; 629 struct dc_mii_frame *frame; 630 631{ 632 int s; 633 634 s = splimp(); 635 /* 636 * Set up frame for TX. 637 */ 638 639 frame->mii_stdelim = DC_MII_STARTDELIM; 640 frame->mii_opcode = DC_MII_WRITEOP; 641 frame->mii_turnaround = DC_MII_TURNAROUND; 642 643 /* 644 * Sync the PHYs. 645 */ 646 dc_mii_sync(sc); 647 648 dc_mii_send(sc, frame->mii_stdelim, 2); 649 dc_mii_send(sc, frame->mii_opcode, 2); 650 dc_mii_send(sc, frame->mii_phyaddr, 5); 651 dc_mii_send(sc, frame->mii_regaddr, 5); 652 dc_mii_send(sc, frame->mii_turnaround, 2); 653 dc_mii_send(sc, frame->mii_data, 16); 654 655 /* Idle bit. */ 656 dc_mii_writebit(sc, 0); 657 dc_mii_writebit(sc, 0); 658 659 splx(s); 660 661 return(0); 662} 663 664static int dc_miibus_readreg(dev, phy, reg) 665 device_t dev; 666 int phy, reg; 667{ 668 struct dc_mii_frame frame; 669 struct dc_softc *sc; 670 int i, rval, phy_reg; 671 672 sc = device_get_softc(dev); 673 bzero((char *)&frame, sizeof(frame)); 674 675 /* 676 * Note: both the AL981 and AN985 have internal PHYs, 677 * however the AL981 provides direct access to the PHY 678 * registers while the AN985 uses a serial MII interface. 679 * The AN985's MII interface is also buggy in that you 680 * can read from any MII address (0 to 31), but only address 1 681 * behaves normally. To deal with both cases, we pretend 682 * that the PHY is at MII address 1. 683 */ 684 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 685 return(0); 686 687 if (sc->dc_pmode == DC_PMODE_SYM) { 688 if (phy == (MII_NPHY - 1)) { 689 switch(reg) { 690 case MII_BMSR: 691 /* 692 * Fake something to make the probe 693 * code think there's a PHY here. 694 */ 695 return(BMSR_MEDIAMASK); 696 break; 697 case MII_PHYIDR1: 698 if (DC_IS_PNIC(sc)) 699 return(DC_VENDORID_LO); 700 return(DC_VENDORID_DEC); 701 break; 702 case MII_PHYIDR2: 703 if (DC_IS_PNIC(sc)) 704 return(DC_DEVICEID_82C168); 705 return(DC_DEVICEID_21143); 706 break; 707 default: 708 return(0); 709 break; 710 } 711 } else 712 return(0); 713 } 714 715 if (DC_IS_PNIC(sc)) { 716 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 717 (phy << 23) | (reg << 18)); 718 for (i = 0; i < DC_TIMEOUT; i++) { 719 DELAY(1); 720 rval = CSR_READ_4(sc, DC_PN_MII); 721 if (!(rval & DC_PN_MII_BUSY)) { 722 rval &= 0xFFFF; 723 return(rval == 0xFFFF ? 0 : rval); 724 } 725 } 726 return(0); 727 } 728 729 if (DC_IS_COMET(sc)) { 730 switch(reg) { 731 case MII_BMCR: 732 phy_reg = DC_AL_BMCR; 733 break; 734 case MII_BMSR: 735 phy_reg = DC_AL_BMSR; 736 break; 737 case MII_PHYIDR1: 738 phy_reg = DC_AL_VENID; 739 break; 740 case MII_PHYIDR2: 741 phy_reg = DC_AL_DEVID; 742 break; 743 case MII_ANAR: 744 phy_reg = DC_AL_ANAR; 745 break; 746 case MII_ANLPAR: 747 phy_reg = DC_AL_LPAR; 748 break; 749 case MII_ANER: 750 phy_reg = DC_AL_ANER; 751 break; 752 default: 753 printf("dc%d: phy_read: bad phy register %x\n", 754 sc->dc_unit, reg); 755 return(0); 756 break; 757 } 758 759 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 760 761 if (rval == 0xFFFF) 762 return(0); 763 return(rval); 764 } 765 766 frame.mii_phyaddr = phy; 767 frame.mii_regaddr = reg; 768 phy_reg = CSR_READ_4(sc, DC_NETCFG); 769 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 770 dc_mii_readreg(sc, &frame); 771 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 772 773 return(frame.mii_data); 774} 775 776static int dc_miibus_writereg(dev, phy, reg, data) 777 device_t dev; 778 int phy, reg, data; 779{ 780 struct dc_softc *sc; 781 struct dc_mii_frame frame; 782 int i, phy_reg; 783 784 sc = device_get_softc(dev); 785 bzero((char *)&frame, sizeof(frame)); 786 787 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 788 return(0); 789 790 if (DC_IS_PNIC(sc)) { 791 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 792 (phy << 23) | (reg << 10) | data); 793 for (i = 0; i < DC_TIMEOUT; i++) { 794 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 795 break; 796 } 797 return(0); 798 } 799 800 if (DC_IS_COMET(sc)) { 801 switch(reg) { 802 case MII_BMCR: 803 phy_reg = DC_AL_BMCR; 804 break; 805 case MII_BMSR: 806 phy_reg = DC_AL_BMSR; 807 break; 808 case MII_PHYIDR1: 809 phy_reg = DC_AL_VENID; 810 break; 811 case MII_PHYIDR2: 812 phy_reg = DC_AL_DEVID; 813 break; 814 case MII_ANAR: 815 phy_reg = DC_AL_ANAR; 816 break; 817 case MII_ANLPAR: 818 phy_reg = DC_AL_LPAR; 819 break; 820 case MII_ANER: 821 phy_reg = DC_AL_ANER; 822 break; 823 default: 824 printf("dc%d: phy_write: bad phy register %x\n", 825 sc->dc_unit, reg); 826 return(0); 827 break; 828 } 829 830 CSR_WRITE_4(sc, phy_reg, data); 831 return(0); 832 } 833 834 frame.mii_phyaddr = phy; 835 frame.mii_regaddr = reg; 836 frame.mii_data = data; 837 838 phy_reg = CSR_READ_4(sc, DC_NETCFG); 839 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 840 dc_mii_writereg(sc, &frame); 841 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 842 843 return(0); 844} 845 846static void dc_miibus_statchg(dev) 847 device_t dev; 848{ 849 struct dc_softc *sc; 850 struct mii_data *mii; 851 struct ifmedia *ifm; 852 853 sc = device_get_softc(dev); 854 if (DC_IS_ADMTEK(sc)) 855 return; 856 mii = device_get_softc(sc->dc_miibus); 857 ifm = &mii->mii_media; 858 if (DC_IS_DAVICOM(sc) && 859 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 860 dc_setcfg(sc, ifm->ifm_media); 861 sc->dc_if_media = ifm->ifm_media; 862 } else { 863 dc_setcfg(sc, mii->mii_media_active); 864 sc->dc_if_media = mii->mii_media_active; 865 } 866 867 return; 868} 869 870/* 871 * Special support for DM9102A cards with HomePNA PHYs. Note: 872 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 873 * to be impossible to talk to the management interface of the DM9801 874 * PHY (its MDIO pin is not connected to anything). Consequently, 875 * the driver has to just 'know' about the additional mode and deal 876 * with it itself. *sigh* 877 */ 878static void dc_miibus_mediainit(dev) 879 device_t dev; 880{ 881 struct dc_softc *sc; 882 struct mii_data *mii; 883 struct ifmedia *ifm; 884 int rev; 885 886 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 887 888 sc = device_get_softc(dev); 889 mii = device_get_softc(sc->dc_miibus); 890 ifm = &mii->mii_media; 891 892 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 893 ifmedia_add(ifm, IFM_ETHER|IFM_homePNA, 0, NULL); 894 895 return; 896} 897 898#define DC_POLY 0xEDB88320 899#define DC_BITS 9 900#define DC_BITS_PNIC_II 7 901 902static u_int32_t dc_crc_le(sc, addr) 903 struct dc_softc *sc; 904 caddr_t addr; 905{ 906 u_int32_t idx, bit, data, crc; 907 908 /* Compute CRC for the address value. */ 909 crc = 0xFFFFFFFF; /* initial value */ 910 911 for (idx = 0; idx < 6; idx++) { 912 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 913 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 914 } 915 916 /* The hash table on the PNIC II is only 128 bits wide. */ 917 if (DC_IS_PNICII(sc)) 918 return (crc & ((1 << DC_BITS_PNIC_II) - 1)); 919 920 return (crc & ((1 << DC_BITS) - 1)); 921} 922 923/* 924 * Calculate CRC of a multicast group address, return the lower 6 bits. 925 */ 926static u_int32_t dc_crc_be(addr) 927 caddr_t addr; 928{ 929 u_int32_t crc, carry; 930 int i, j; 931 u_int8_t c; 932 933 /* Compute CRC for the address value. */ 934 crc = 0xFFFFFFFF; /* initial value */ 935 936 for (i = 0; i < 6; i++) { 937 c = *(addr + i); 938 for (j = 0; j < 8; j++) { 939 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 940 crc <<= 1; 941 c >>= 1; 942 if (carry) 943 crc = (crc ^ 0x04c11db6) | carry; 944 } 945 } 946 947 /* return the filter bit position */ 948 return((crc >> 26) & 0x0000003F); 949} 950 951/* 952 * 21143-style RX filter setup routine. Filter programming is done by 953 * downloading a special setup frame into the TX engine. 21143, Macronix, 954 * PNIC, PNIC II and Davicom chips are programmed this way. 955 * 956 * We always program the chip using 'hash perfect' mode, i.e. one perfect 957 * address (our node address) and a 512-bit hash filter for multicast 958 * frames. We also sneak the broadcast address into the hash filter since 959 * we need that too. 960 */ 961void dc_setfilt_21143(sc) 962 struct dc_softc *sc; 963{ 964 struct dc_desc *sframe; 965 u_int32_t h, *sp; 966 struct ifmultiaddr *ifma; 967 struct ifnet *ifp; 968 int i; 969 970 ifp = &sc->arpcom.ac_if; 971 972 i = sc->dc_cdata.dc_tx_prod; 973 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 974 sc->dc_cdata.dc_tx_cnt++; 975 sframe = &sc->dc_ldata->dc_tx_list[i]; 976 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 977 bzero((char *)sp, DC_SFRAME_LEN); 978 979 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 980 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 981 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 982 983 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 984 985 /* If we want promiscuous mode, set the allframes bit. */ 986 if (ifp->if_flags & IFF_PROMISC) 987 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 988 else 989 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 990 991 if (ifp->if_flags & IFF_ALLMULTI) 992 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 993 else 994 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 995 996 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 997 ifma = ifma->ifma_link.le_next) { 998 if (ifma->ifma_addr->sa_family != AF_LINK) 999 continue; 1000 h = dc_crc_le(sc, 1001 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1002 sp[h >> 4] |= 1 << (h & 0xF); 1003 } 1004 1005 if (ifp->if_flags & IFF_BROADCAST) { 1006 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1007 sp[h >> 4] |= 1 << (h & 0xF); 1008 } 1009 1010 /* Set our MAC address */ 1011 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1012 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1013 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1014 1015 sframe->dc_status = DC_TXSTAT_OWN; 1016 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1017 1018 /* 1019 * The PNIC takes an exceedingly long time to process its 1020 * setup frame; wait 10ms after posting the setup frame 1021 * before proceeding, just so it has time to swallow its 1022 * medicine. 1023 */ 1024 DELAY(10000); 1025 1026 ifp->if_timer = 5; 1027 1028 return; 1029} 1030 1031void dc_setfilt_admtek(sc) 1032 struct dc_softc *sc; 1033{ 1034 struct ifnet *ifp; 1035 int h = 0; 1036 u_int32_t hashes[2] = { 0, 0 }; 1037 struct ifmultiaddr *ifma; 1038 1039 ifp = &sc->arpcom.ac_if; 1040 1041 /* Init our MAC address */ 1042 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1043 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1044 1045 /* If we want promiscuous mode, set the allframes bit. */ 1046 if (ifp->if_flags & IFF_PROMISC) 1047 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1048 else 1049 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1050 1051 if (ifp->if_flags & IFF_ALLMULTI) 1052 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1053 else 1054 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1055 1056 /* first, zot all the existing hash bits */ 1057 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1058 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1059 1060 /* 1061 * If we're already in promisc or allmulti mode, we 1062 * don't have to bother programming the multicast filter. 1063 */ 1064 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1065 return; 1066 1067 /* now program new ones */ 1068 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1069 ifma = ifma->ifma_link.le_next) { 1070 if (ifma->ifma_addr->sa_family != AF_LINK) 1071 continue; 1072 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1073 if (h < 32) 1074 hashes[0] |= (1 << h); 1075 else 1076 hashes[1] |= (1 << (h - 32)); 1077 } 1078 1079 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1080 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1081 1082 return; 1083} 1084 1085void dc_setfilt_asix(sc) 1086 struct dc_softc *sc; 1087{ 1088 struct ifnet *ifp; 1089 int h = 0; 1090 u_int32_t hashes[2] = { 0, 0 }; 1091 struct ifmultiaddr *ifma; 1092 1093 ifp = &sc->arpcom.ac_if; 1094 1095 /* Init our MAC address */ 1096 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1097 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1098 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1099 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1100 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1101 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1102 1103 /* If we want promiscuous mode, set the allframes bit. */ 1104 if (ifp->if_flags & IFF_PROMISC) 1105 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1106 else 1107 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1108 1109 if (ifp->if_flags & IFF_ALLMULTI) 1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1111 else 1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1113 1114 /* 1115 * The ASIX chip has a special bit to enable reception 1116 * of broadcast frames. 1117 */ 1118 if (ifp->if_flags & IFF_BROADCAST) 1119 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1120 else 1121 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1122 1123 /* first, zot all the existing hash bits */ 1124 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1125 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1126 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1127 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1128 1129 /* 1130 * If we're already in promisc or allmulti mode, we 1131 * don't have to bother programming the multicast filter. 1132 */ 1133 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1134 return; 1135 1136 /* now program new ones */ 1137 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1138 ifma = ifma->ifma_link.le_next) { 1139 if (ifma->ifma_addr->sa_family != AF_LINK) 1140 continue; 1141 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1142 if (h < 32) 1143 hashes[0] |= (1 << h); 1144 else 1145 hashes[1] |= (1 << (h - 32)); 1146 } 1147 1148 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1149 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1150 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1151 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1152 1153 return; 1154} 1155 1156static void dc_setfilt(sc) 1157 struct dc_softc *sc; 1158{ 1159 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1160 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc)) 1161 dc_setfilt_21143(sc); 1162 1163 if (DC_IS_ASIX(sc)) 1164 dc_setfilt_asix(sc); 1165 1166 if (DC_IS_ADMTEK(sc)) 1167 dc_setfilt_admtek(sc); 1168 1169 return; 1170} 1171 1172/* 1173 * In order to fiddle with the 1174 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1175 * first have to put the transmit and/or receive logic in the idle state. 1176 */ 1177static void dc_setcfg(sc, media) 1178 struct dc_softc *sc; 1179 int media; 1180{ 1181 int i, restart = 0; 1182 u_int32_t isr; 1183 1184 if (IFM_SUBTYPE(media) == IFM_NONE) 1185 return; 1186 1187 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1188 restart = 1; 1189 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1190 1191 for (i = 0; i < DC_TIMEOUT; i++) { 1192 DELAY(10); 1193 isr = CSR_READ_4(sc, DC_ISR); 1194 if (isr & DC_ISR_TX_IDLE || 1195 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED) 1196 break; 1197 } 1198 1199 if (i == DC_TIMEOUT) 1200 printf("dc%d: failed to force tx and " 1201 "rx to idle state\n", sc->dc_unit); 1202 1203 } 1204 1205 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1206 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1207 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1208 if (sc->dc_pmode == DC_PMODE_MII) { 1209 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1210 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1211 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1212 if (sc->dc_type == DC_TYPE_98713) 1213 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1214 DC_NETCFG_SCRAMBLER)); 1215 if (!DC_IS_DAVICOM(sc)) 1216 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1217 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1218 } else { 1219 if (DC_IS_PNIC(sc)) { 1220 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1221 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1222 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1223 } 1224 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1225 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1226 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1227 } 1228 } 1229 1230 if (IFM_SUBTYPE(media) == IFM_10_T) { 1231 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1232 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1233 if (sc->dc_pmode == DC_PMODE_MII) { 1234 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1235 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1236 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1237 if (sc->dc_type == DC_TYPE_98713) 1238 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1239 if (!DC_IS_DAVICOM(sc)) 1240 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1241 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1242 } else { 1243 if (DC_IS_PNIC(sc)) { 1244 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1245 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1246 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1247 } 1248 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1249 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1250 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1251 } 1252 } 1253 1254 /* 1255 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1256 * PHY and we want HomePNA mode, set the portsel bit to turn 1257 * on the external MII port. 1258 */ 1259 if (DC_IS_DAVICOM(sc)) { 1260 if (IFM_SUBTYPE(media) == IFM_homePNA) { 1261 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1262 sc->dc_link = 1; 1263 } else { 1264 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1265 } 1266 } 1267 1268 if ((media & IFM_GMASK) == IFM_FDX) { 1269 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1270 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1271 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1272 } else { 1273 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1274 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1275 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1276 } 1277 1278 if (restart) 1279 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1280 1281 return; 1282} 1283 1284static void dc_reset(sc) 1285 struct dc_softc *sc; 1286{ 1287 register int i; 1288 1289 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1290 1291 for (i = 0; i < DC_TIMEOUT; i++) { 1292 DELAY(10); 1293 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1294 break; 1295 } 1296 1297 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc)) { 1298 DELAY(10000); 1299 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1300 i = 0; 1301 } 1302 1303 if (i == DC_TIMEOUT) 1304 printf("dc%d: reset never completed!\n", sc->dc_unit); 1305 1306 /* Wait a little while for the chip to get its brains in order. */ 1307 DELAY(1000); 1308 1309 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1310 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1311 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1312 1313 /* 1314 * Bring the SIA out of reset. In some cases, it looks 1315 * like failing to unreset the SIA soon enough gets it 1316 * into a state where it will never come out of reset 1317 * until we reset the whole chip again. 1318 */ 1319 if (DC_IS_INTEL(sc)) 1320 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1321 1322 return; 1323} 1324 1325static struct dc_type *dc_devtype(dev) 1326 device_t dev; 1327{ 1328 struct dc_type *t; 1329 u_int32_t rev; 1330 1331 t = dc_devs; 1332 1333 while(t->dc_name != NULL) { 1334 if ((pci_get_vendor(dev) == t->dc_vid) && 1335 (pci_get_device(dev) == t->dc_did)) { 1336 /* Check the PCI revision */ 1337 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1338 if (t->dc_did == DC_DEVICEID_98713 && 1339 rev >= DC_REVISION_98713A) 1340 t++; 1341 if (t->dc_did == DC_DEVICEID_98713_CP && 1342 rev >= DC_REVISION_98713A) 1343 t++; 1344 if (t->dc_did == DC_DEVICEID_987x5 && 1345 rev >= DC_REVISION_98725) 1346 t++; 1347 if (t->dc_did == DC_DEVICEID_AX88140A && 1348 rev >= DC_REVISION_88141) 1349 t++; 1350 if (t->dc_did == DC_DEVICEID_82C168 && 1351 rev >= DC_REVISION_82C169) 1352 t++; 1353 if (t->dc_did == DC_DEVICEID_DM9102 && 1354 rev >= DC_REVISION_DM9102A) 1355 t++; 1356 return(t); 1357 } 1358 t++; 1359 } 1360 1361 return(NULL); 1362} 1363 1364/* 1365 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1366 * IDs against our list and return a device name if we find a match. 1367 * We do a little bit of extra work to identify the exact type of 1368 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1369 * but different revision IDs. The same is true for 98715/98715A 1370 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1371 * cases, the exact chip revision affects driver behavior. 1372 */ 1373static int dc_probe(dev) 1374 device_t dev; 1375{ 1376 struct dc_type *t; 1377 1378 t = dc_devtype(dev); 1379 1380 if (t != NULL) { 1381 device_set_desc(dev, t->dc_name); 1382 return(0); 1383 } 1384 1385 return(ENXIO); 1386} 1387 1388static void dc_acpi(dev) 1389 device_t dev; 1390{ 1391 u_int32_t r, cptr; 1392 int unit; 1393 1394 unit = device_get_unit(dev); 1395 1396 /* Find the location of the capabilities block */ 1397 cptr = pci_read_config(dev, DC_PCI_CCAP, 4) & 0xFF; 1398 1399 r = pci_read_config(dev, cptr, 4) & 0xFF; 1400 if (r == 0x01) { 1401 1402 r = pci_read_config(dev, cptr + 4, 4); 1403 if (r & DC_PSTATE_D3) { 1404 u_int32_t iobase, membase, irq; 1405 1406 /* Save important PCI config data. */ 1407 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1408 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1409 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1410 1411 /* Reset the power state. */ 1412 printf("dc%d: chip is in D%d power mode " 1413 "-- setting to D0\n", unit, r & DC_PSTATE_D3); 1414 r &= 0xFFFFFFFC; 1415 pci_write_config(dev, cptr + 4, r, 4); 1416 1417 /* Restore PCI config data. */ 1418 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1419 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1420 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1421 } 1422 } 1423 return; 1424} 1425 1426/* 1427 * Attach the interface. Allocate softc structures, do ifmedia 1428 * setup and ethernet/BPF attach. 1429 */ 1430static int dc_attach(dev) 1431 device_t dev; 1432{ 1433 int s; 1434 u_char eaddr[ETHER_ADDR_LEN]; 1435 u_int32_t command; 1436 struct dc_softc *sc; 1437 struct ifnet *ifp; 1438 u_int32_t revision; 1439 int unit, error = 0, rid, mac_offset; 1440 1441 s = splimp(); 1442 1443 sc = device_get_softc(dev); 1444 unit = device_get_unit(dev); 1445 bzero(sc, sizeof(struct dc_softc)); 1446 1447 /* 1448 * Handle power management nonsense. 1449 */ 1450 dc_acpi(dev); 1451 1452 /* 1453 * Map control/status registers. 1454 */ 1455 command = pci_read_config(dev, PCIR_COMMAND, 4); 1456 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1457 pci_write_config(dev, PCIR_COMMAND, command, 4); 1458 command = pci_read_config(dev, PCIR_COMMAND, 4); 1459 1460#ifdef DC_USEIOSPACE 1461 if (!(command & PCIM_CMD_PORTEN)) { 1462 printf("dc%d: failed to enable I/O ports!\n", unit); 1463 error = ENXIO; 1464 goto fail; 1465 } 1466#else 1467 if (!(command & PCIM_CMD_MEMEN)) { 1468 printf("dc%d: failed to enable memory mapping!\n", unit); 1469 error = ENXIO; 1470 goto fail; 1471 } 1472#endif 1473 1474 rid = DC_RID; 1475 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1476 0, ~0, 1, RF_ACTIVE); 1477 1478 if (sc->dc_res == NULL) { 1479 printf("dc%d: couldn't map ports/memory\n", unit); 1480 error = ENXIO; 1481 goto fail; 1482 } 1483 1484 sc->dc_btag = rman_get_bustag(sc->dc_res); 1485 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1486 1487 /* Allocate interrupt */ 1488 rid = 0; 1489 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1490 RF_SHAREABLE | RF_ACTIVE); 1491 1492 if (sc->dc_irq == NULL) { 1493 printf("dc%d: couldn't map interrupt\n", unit); 1494 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1495 error = ENXIO; 1496 goto fail; 1497 } 1498 1499 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET, 1500 dc_intr, sc, &sc->dc_intrhand); 1501 1502 if (error) { 1503 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1504 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1505 printf("dc%d: couldn't set up irq\n", unit); 1506 goto fail; 1507 } 1508 1509 /* Need this info to decide on a chip type. */ 1510 sc->dc_info = dc_devtype(dev); 1511 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1512 1513 switch(sc->dc_info->dc_did) { 1514 case DC_DEVICEID_21143: 1515 sc->dc_type = DC_TYPE_21143; 1516 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1517 sc->dc_flags |= DC_REDUCED_MII_POLL; 1518 break; 1519 case DC_DEVICEID_DM9100: 1520 case DC_DEVICEID_DM9102: 1521 sc->dc_type = DC_TYPE_DM9102; 1522 sc->dc_flags |= DC_TX_COALESCE|DC_TX_USE_TX_INTR; 1523 sc->dc_flags |= DC_REDUCED_MII_POLL; 1524 sc->dc_pmode = DC_PMODE_MII; 1525 break; 1526 case DC_DEVICEID_AL981: 1527 sc->dc_type = DC_TYPE_AL981; 1528 sc->dc_flags |= DC_TX_USE_TX_INTR; 1529 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1530 sc->dc_pmode = DC_PMODE_MII; 1531 break; 1532 case DC_DEVICEID_AN985: 1533 sc->dc_type = DC_TYPE_AN985; 1534 sc->dc_flags |= DC_TX_USE_TX_INTR; 1535 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1536 sc->dc_pmode = DC_PMODE_MII; 1537 break; 1538 case DC_DEVICEID_98713: 1539 case DC_DEVICEID_98713_CP: 1540 if (revision < DC_REVISION_98713A) { 1541 sc->dc_type = DC_TYPE_98713; 1542 } 1543 if (revision >= DC_REVISION_98713A) { 1544 sc->dc_type = DC_TYPE_98713A; 1545 sc->dc_flags |= DC_21143_NWAY; 1546 } 1547 sc->dc_flags |= DC_REDUCED_MII_POLL; 1548 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1549 break; 1550 case DC_DEVICEID_987x5: 1551 sc->dc_type = DC_TYPE_987x5; 1552 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1553 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1554 break; 1555 case DC_DEVICEID_82C115: 1556 sc->dc_type = DC_TYPE_PNICII; 1557 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1558 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1559 break; 1560 case DC_DEVICEID_82C168: 1561 sc->dc_type = DC_TYPE_PNIC; 1562 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1563 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1564 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1565 if (revision < DC_REVISION_82C169) 1566 sc->dc_pmode = DC_PMODE_SYM; 1567 break; 1568 case DC_DEVICEID_AX88140A: 1569 sc->dc_type = DC_TYPE_ASIX; 1570 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1571 sc->dc_flags |= DC_REDUCED_MII_POLL; 1572 sc->dc_pmode = DC_PMODE_MII; 1573 break; 1574 default: 1575 printf("dc%d: unknown device: %x\n", sc->dc_unit, 1576 sc->dc_info->dc_did); 1577 break; 1578 } 1579 1580 /* Save the cache line size. */ 1581 if (DC_IS_DAVICOM(sc)) 1582 sc->dc_cachesize = 0; 1583 else 1584 sc->dc_cachesize = pci_read_config(dev, 1585 DC_PCI_CFLT, 4) & 0xFF; 1586 1587 /* Reset the adapter. */ 1588 dc_reset(sc); 1589 1590 /* Take 21143 out of snooze mode */ 1591 if (DC_IS_INTEL(sc)) { 1592 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1593 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1594 pci_write_config(dev, DC_PCI_CFDD, command, 4); 1595 } 1596 1597 /* 1598 * Try to learn something about the supported media. 1599 * We know that ASIX and ADMtek and Davicom devices 1600 * will *always* be using MII media, so that's a no-brainer. 1601 * The tricky ones are the Macronix/PNIC II and the 1602 * Intel 21143. 1603 */ 1604 if (DC_IS_INTEL(sc)) { 1605 u_int32_t media, cwuc; 1606 cwuc = pci_read_config(dev, DC_PCI_CWUC, 4); 1607 cwuc |= DC_CWUC_FORCE_WUL; 1608 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1609 DELAY(10000); 1610 media = pci_read_config(dev, DC_PCI_CWUC, 4); 1611 cwuc &= ~DC_CWUC_FORCE_WUL; 1612 pci_write_config(dev, DC_PCI_CWUC, cwuc, 4); 1613 DELAY(10000); 1614 if (media & DC_CWUC_MII_ABILITY) 1615 sc->dc_pmode = DC_PMODE_MII; 1616 if (media & DC_CWUC_SYM_ABILITY) { 1617 sc->dc_pmode = DC_PMODE_SYM; 1618 sc->dc_flags |= DC_21143_NWAY; 1619 } 1620 /* 1621 * If none of the bits are set, then this NIC 1622 * isn't meant to support 'wake up LAN' mode. 1623 * This is usually only the case on multiport 1624 * cards, and these cards almost always have 1625 * MII transceivers. 1626 */ 1627 if (media == 0) 1628 sc->dc_pmode = DC_PMODE_MII; 1629 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 1630 if (sc->dc_type == DC_TYPE_98713) 1631 sc->dc_pmode = DC_PMODE_MII; 1632 else 1633 sc->dc_pmode = DC_PMODE_SYM; 1634 } else if (!sc->dc_pmode) 1635 sc->dc_pmode = DC_PMODE_MII; 1636 1637 /* 1638 * Get station address from the EEPROM. 1639 */ 1640 switch(sc->dc_type) { 1641 case DC_TYPE_98713: 1642 case DC_TYPE_98713A: 1643 case DC_TYPE_987x5: 1644 case DC_TYPE_PNICII: 1645 dc_read_eeprom(sc, (caddr_t)&mac_offset, 1646 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 1647 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 1648 break; 1649 case DC_TYPE_PNIC: 1650 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 1651 break; 1652 case DC_TYPE_DM9102: 1653 case DC_TYPE_21143: 1654 case DC_TYPE_ASIX: 1655 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1656 break; 1657 case DC_TYPE_AL981: 1658 case DC_TYPE_AN985: 1659 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 1660 break; 1661 default: 1662 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 1663 break; 1664 } 1665 1666 /* 1667 * A 21143 or clone chip was detected. Inform the world. 1668 */ 1669 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1670 1671 sc->dc_unit = unit; 1672 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1673 1674 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 1675 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1676 1677 if (sc->dc_ldata == NULL) { 1678 printf("dc%d: no memory for list buffers!\n", unit); 1679 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1680 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1681 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1682 error = ENXIO; 1683 goto fail; 1684 } 1685 1686 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 1687 1688 ifp = &sc->arpcom.ac_if; 1689 ifp->if_softc = sc; 1690 ifp->if_unit = unit; 1691 ifp->if_name = "dc"; 1692 ifp->if_mtu = ETHERMTU; 1693 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1694 ifp->if_ioctl = dc_ioctl; 1695 ifp->if_output = ether_output; 1696 ifp->if_start = dc_start; 1697 ifp->if_watchdog = dc_watchdog; 1698 ifp->if_init = dc_init; 1699 ifp->if_baudrate = 10000000; 1700 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 1701 1702 /* 1703 * Do MII setup. 1704 */ 1705 error = mii_phy_probe(dev, &sc->dc_miibus, 1706 dc_ifmedia_upd, dc_ifmedia_sts); 1707 1708 if (error && DC_IS_INTEL(sc)) { 1709 sc->dc_pmode = DC_PMODE_SYM; 1710 sc->dc_flags |= DC_21143_NWAY; 1711 mii_phy_probe(dev, &sc->dc_miibus, 1712 dc_ifmedia_upd, dc_ifmedia_sts); 1713 error = 0; 1714 } 1715 1716 if (error) { 1717 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 1718 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1719 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1720 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1721 error = ENXIO; 1722 goto fail; 1723 } 1724 1725 /* 1726 * Call MI attach routines. 1727 */ 1728 if_attach(ifp); 1729 ether_ifattach(ifp); 1730 callout_handle_init(&sc->dc_stat_ch); 1731 1732 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1733 1734#ifdef __alpha__ 1735 sc->dc_srm_media = 0; 1736 1737 /* Remember the SRM console media setting */ 1738 if (DC_IS_INTEL(sc)) { 1739 command = pci_read_config(dev, DC_PCI_CFDD, 4); 1740 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 1741 switch ((command >> 8) & 0xff) { 1742 case 3: 1743 sc->dc_srm_media = IFM_10_T; 1744 break; 1745 case 4: 1746 sc->dc_srm_media = IFM_10_T | IFM_FDX; 1747 break; 1748 case 5: 1749 sc->dc_srm_media = IFM_100_TX; 1750 break; 1751 case 6: 1752 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 1753 break; 1754 } 1755 if (sc->dc_srm_media) 1756 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 1757 } 1758#endif 1759 1760 1761fail: 1762 splx(s); 1763 1764 return(error); 1765} 1766 1767static int dc_detach(dev) 1768 device_t dev; 1769{ 1770 struct dc_softc *sc; 1771 struct ifnet *ifp; 1772 int s; 1773 1774 s = splimp(); 1775 1776 sc = device_get_softc(dev); 1777 ifp = &sc->arpcom.ac_if; 1778 1779 dc_stop(sc); 1780 if_detach(ifp); 1781 1782 bus_generic_detach(dev); 1783 device_delete_child(dev, sc->dc_miibus); 1784 1785 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 1786 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1787 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1788 1789 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 1790 if (sc->dc_pnic_rx_buf != NULL) 1791 free(sc->dc_pnic_rx_buf, M_DEVBUF); 1792 1793 splx(s); 1794 1795 return(0); 1796} 1797 1798/* 1799 * Initialize the transmit descriptors. 1800 */ 1801static int dc_list_tx_init(sc) 1802 struct dc_softc *sc; 1803{ 1804 struct dc_chain_data *cd; 1805 struct dc_list_data *ld; 1806 int i; 1807 1808 cd = &sc->dc_cdata; 1809 ld = sc->dc_ldata; 1810 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1811 if (i == (DC_TX_LIST_CNT - 1)) { 1812 ld->dc_tx_list[i].dc_next = 1813 vtophys(&ld->dc_tx_list[0]); 1814 } else { 1815 ld->dc_tx_list[i].dc_next = 1816 vtophys(&ld->dc_tx_list[i + 1]); 1817 } 1818 cd->dc_tx_chain[i] = NULL; 1819 ld->dc_tx_list[i].dc_data = 0; 1820 ld->dc_tx_list[i].dc_ctl = 0; 1821 } 1822 1823 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 1824 1825 return(0); 1826} 1827 1828 1829/* 1830 * Initialize the RX descriptors and allocate mbufs for them. Note that 1831 * we arrange the descriptors in a closed ring, so that the last descriptor 1832 * points back to the first. 1833 */ 1834static int dc_list_rx_init(sc) 1835 struct dc_softc *sc; 1836{ 1837 struct dc_chain_data *cd; 1838 struct dc_list_data *ld; 1839 int i; 1840 1841 cd = &sc->dc_cdata; 1842 ld = sc->dc_ldata; 1843 1844 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1845 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 1846 return(ENOBUFS); 1847 if (i == (DC_RX_LIST_CNT - 1)) { 1848 ld->dc_rx_list[i].dc_next = 1849 vtophys(&ld->dc_rx_list[0]); 1850 } else { 1851 ld->dc_rx_list[i].dc_next = 1852 vtophys(&ld->dc_rx_list[i + 1]); 1853 } 1854 } 1855 1856 cd->dc_rx_prod = 0; 1857 1858 return(0); 1859} 1860 1861/* 1862 * Initialize an RX descriptor and attach an MBUF cluster. 1863 */ 1864static int dc_newbuf(sc, i, m) 1865 struct dc_softc *sc; 1866 int i; 1867 struct mbuf *m; 1868{ 1869 struct mbuf *m_new = NULL; 1870 struct dc_desc *c; 1871 1872 c = &sc->dc_ldata->dc_rx_list[i]; 1873 1874 if (m == NULL) { 1875 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1876 if (m_new == NULL) { 1877 printf("dc%d: no memory for rx list " 1878 "-- packet dropped!\n", sc->dc_unit); 1879 return(ENOBUFS); 1880 } 1881 1882 MCLGET(m_new, M_DONTWAIT); 1883 if (!(m_new->m_flags & M_EXT)) { 1884 printf("dc%d: no memory for rx list " 1885 "-- packet dropped!\n", sc->dc_unit); 1886 m_freem(m_new); 1887 return(ENOBUFS); 1888 } 1889 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1890 } else { 1891 m_new = m; 1892 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1893 m_new->m_data = m_new->m_ext.ext_buf; 1894 } 1895 1896 m_adj(m_new, sizeof(u_int64_t)); 1897 1898 /* 1899 * If this is a PNIC chip, zero the buffer. This is part 1900 * of the workaround for the receive bug in the 82c168 and 1901 * 82c169 chips. 1902 */ 1903 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 1904 bzero((char *)mtod(m_new, char *), m_new->m_len); 1905 1906 sc->dc_cdata.dc_rx_chain[i] = m_new; 1907 c->dc_data = vtophys(mtod(m_new, caddr_t)); 1908 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 1909 c->dc_status = DC_RXSTAT_OWN; 1910 1911 return(0); 1912} 1913 1914/* 1915 * Grrrrr. 1916 * The PNIC chip has a terrible bug in it that manifests itself during 1917 * periods of heavy activity. The exact mode of failure if difficult to 1918 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 1919 * will happen on slow machines. The bug is that sometimes instead of 1920 * uploading one complete frame during reception, it uploads what looks 1921 * like the entire contents of its FIFO memory. The frame we want is at 1922 * the end of the whole mess, but we never know exactly how much data has 1923 * been uploaded, so salvaging the frame is hard. 1924 * 1925 * There is only one way to do it reliably, and it's disgusting. 1926 * Here's what we know: 1927 * 1928 * - We know there will always be somewhere between one and three extra 1929 * descriptors uploaded. 1930 * 1931 * - We know the desired received frame will always be at the end of the 1932 * total data upload. 1933 * 1934 * - We know the size of the desired received frame because it will be 1935 * provided in the length field of the status word in the last descriptor. 1936 * 1937 * Here's what we do: 1938 * 1939 * - When we allocate buffers for the receive ring, we bzero() them. 1940 * This means that we know that the buffer contents should be all 1941 * zeros, except for data uploaded by the chip. 1942 * 1943 * - We also force the PNIC chip to upload frames that include the 1944 * ethernet CRC at the end. 1945 * 1946 * - We gather all of the bogus frame data into a single buffer. 1947 * 1948 * - We then position a pointer at the end of this buffer and scan 1949 * backwards until we encounter the first non-zero byte of data. 1950 * This is the end of the received frame. We know we will encounter 1951 * some data at the end of the frame because the CRC will always be 1952 * there, so even if the sender transmits a packet of all zeros, 1953 * we won't be fooled. 1954 * 1955 * - We know the size of the actual received frame, so we subtract 1956 * that value from the current pointer location. This brings us 1957 * to the start of the actual received packet. 1958 * 1959 * - We copy this into an mbuf and pass it on, along with the actual 1960 * frame length. 1961 * 1962 * The performance hit is tremendous, but it beats dropping frames all 1963 * the time. 1964 */ 1965 1966#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 1967static void dc_pnic_rx_bug_war(sc, idx) 1968 struct dc_softc *sc; 1969 int idx; 1970{ 1971 struct dc_desc *cur_rx; 1972 struct dc_desc *c = NULL; 1973 struct mbuf *m = NULL; 1974 unsigned char *ptr; 1975 int i, total_len; 1976 u_int32_t rxstat = 0; 1977 1978 i = sc->dc_pnic_rx_bug_save; 1979 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 1980 ptr = sc->dc_pnic_rx_buf; 1981 bzero(ptr, sizeof(DC_RXLEN * 5)); 1982 1983 /* Copy all the bytes from the bogus buffers. */ 1984 while (1) { 1985 c = &sc->dc_ldata->dc_rx_list[i]; 1986 rxstat = c->dc_status; 1987 m = sc->dc_cdata.dc_rx_chain[i]; 1988 bcopy(mtod(m, char *), ptr, DC_RXLEN); 1989 ptr += DC_RXLEN; 1990 /* If this is the last buffer, break out. */ 1991 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 1992 break; 1993 dc_newbuf(sc, i, m); 1994 DC_INC(i, DC_RX_LIST_CNT); 1995 } 1996 1997 /* Find the length of the actual receive frame. */ 1998 total_len = DC_RXBYTES(rxstat); 1999 2000 /* Scan backwards until we hit a non-zero byte. */ 2001 while(*ptr == 0x00) 2002 ptr--; 2003 2004 /* Round off. */ 2005 if ((uintptr_t)(ptr) & 0x3) 2006 ptr -= 1; 2007 2008 /* Now find the start of the frame. */ 2009 ptr -= total_len; 2010 if (ptr < sc->dc_pnic_rx_buf) 2011 ptr = sc->dc_pnic_rx_buf; 2012 2013 /* 2014 * Now copy the salvaged frame to the last mbuf and fake up 2015 * the status word to make it look like a successful 2016 * frame reception. 2017 */ 2018 dc_newbuf(sc, i, m); 2019 bcopy(ptr, mtod(m, char *), total_len); 2020 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2021 2022 return; 2023} 2024 2025/* 2026 * This routine searches the RX ring for dirty descriptors in the 2027 * event that the rxeof routine falls out of sync with the chip's 2028 * current descriptor pointer. This may happen sometimes as a result 2029 * of a "no RX buffer available" condition that happens when the chip 2030 * consumes all of the RX buffers before the driver has a chance to 2031 * process the RX ring. This routine may need to be called more than 2032 * once to bring the driver back in sync with the chip, however we 2033 * should still be getting RX DONE interrupts to drive the search 2034 * for new packets in the RX ring, so we should catch up eventually. 2035 */ 2036static int dc_rx_resync(sc) 2037 struct dc_softc *sc; 2038{ 2039 int i, pos; 2040 struct dc_desc *cur_rx; 2041 2042 pos = sc->dc_cdata.dc_rx_prod; 2043 2044 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2045 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2046 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2047 break; 2048 DC_INC(pos, DC_RX_LIST_CNT); 2049 } 2050 2051 /* If the ring really is empty, then just return. */ 2052 if (i == DC_RX_LIST_CNT) 2053 return(0); 2054 2055 /* We've fallen behing the chip: catch it. */ 2056 sc->dc_cdata.dc_rx_prod = pos; 2057 2058 return(EAGAIN); 2059} 2060 2061/* 2062 * A frame has been uploaded: pass the resulting mbuf chain up to 2063 * the higher level protocols. 2064 */ 2065static void dc_rxeof(sc) 2066 struct dc_softc *sc; 2067{ 2068 struct ether_header *eh; 2069 struct mbuf *m; 2070 struct ifnet *ifp; 2071 struct dc_desc *cur_rx; 2072 int i, total_len = 0; 2073 u_int32_t rxstat; 2074 2075 ifp = &sc->arpcom.ac_if; 2076 i = sc->dc_cdata.dc_rx_prod; 2077 2078 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2079 struct mbuf *m0 = NULL; 2080 2081 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2082 rxstat = cur_rx->dc_status; 2083 m = sc->dc_cdata.dc_rx_chain[i]; 2084 total_len = DC_RXBYTES(rxstat); 2085 2086 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2087 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2088 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2089 sc->dc_pnic_rx_bug_save = i; 2090 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2091 DC_INC(i, DC_RX_LIST_CNT); 2092 continue; 2093 } 2094 dc_pnic_rx_bug_war(sc, i); 2095 rxstat = cur_rx->dc_status; 2096 total_len = DC_RXBYTES(rxstat); 2097 } 2098 } 2099 2100 sc->dc_cdata.dc_rx_chain[i] = NULL; 2101 2102 /* 2103 * If an error occurs, update stats, clear the 2104 * status word and leave the mbuf cluster in place: 2105 * it should simply get re-used next time this descriptor 2106 * comes up in the ring. 2107 */ 2108 if (rxstat & DC_RXSTAT_RXERR) { 2109 ifp->if_ierrors++; 2110 if (rxstat & DC_RXSTAT_COLLSEEN) 2111 ifp->if_collisions++; 2112 dc_newbuf(sc, i, m); 2113 if (rxstat & DC_RXSTAT_CRCERR) { 2114 DC_INC(i, DC_RX_LIST_CNT); 2115 continue; 2116 } else { 2117 dc_init(sc); 2118 return; 2119 } 2120 } 2121 2122 /* No errors; receive the packet. */ 2123 total_len -= ETHER_CRC_LEN; 2124 2125 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2126 total_len + ETHER_ALIGN, 0, ifp, NULL); 2127 dc_newbuf(sc, i, m); 2128 DC_INC(i, DC_RX_LIST_CNT); 2129 if (m0 == NULL) { 2130 ifp->if_ierrors++; 2131 continue; 2132 } 2133 m_adj(m0, ETHER_ALIGN); 2134 m = m0; 2135 2136 ifp->if_ipackets++; 2137 eh = mtod(m, struct ether_header *); 2138 2139 /* Remove header from mbuf and pass it on. */ 2140 m_adj(m, sizeof(struct ether_header)); 2141 ether_input(ifp, eh, m); 2142 } 2143 2144 sc->dc_cdata.dc_rx_prod = i; 2145} 2146 2147/* 2148 * A frame was downloaded to the chip. It's safe for us to clean up 2149 * the list buffers. 2150 */ 2151 2152static void dc_txeof(sc) 2153 struct dc_softc *sc; 2154{ 2155 struct dc_desc *cur_tx = NULL; 2156 struct ifnet *ifp; 2157 int idx; 2158 2159 ifp = &sc->arpcom.ac_if; 2160 2161 /* Clear the timeout timer. */ 2162 ifp->if_timer = 0; 2163 2164 /* 2165 * Go through our tx list and free mbufs for those 2166 * frames that have been transmitted. 2167 */ 2168 idx = sc->dc_cdata.dc_tx_cons; 2169 while(idx != sc->dc_cdata.dc_tx_prod) { 2170 u_int32_t txstat; 2171 2172 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2173 txstat = cur_tx->dc_status; 2174 2175 if (txstat & DC_TXSTAT_OWN) 2176 break; 2177 2178 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2179 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2180 sc->dc_cdata.dc_tx_cnt--; 2181 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2182 /* 2183 * Yes, the PNIC is so brain damaged 2184 * that it will sometimes generate a TX 2185 * underrun error while DMAing the RX 2186 * filter setup frame. If we detect this, 2187 * we have to send the setup frame again, 2188 * or else the filter won't be programmed 2189 * correctly. 2190 */ 2191 if (DC_IS_PNIC(sc)) { 2192 if (txstat & DC_TXSTAT_ERRSUM) 2193 dc_setfilt(sc); 2194 } 2195 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2196 } 2197 DC_INC(idx, DC_TX_LIST_CNT); 2198 continue; 2199 } 2200 2201 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2202 sc->dc_pmode == DC_PMODE_MII && 2203 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2204 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2205 txstat &= ~DC_TXSTAT_ERRSUM; 2206 2207 if (txstat & DC_TXSTAT_ERRSUM) { 2208 ifp->if_oerrors++; 2209 if (txstat & DC_TXSTAT_EXCESSCOLL) 2210 ifp->if_collisions++; 2211 if (txstat & DC_TXSTAT_LATECOLL) 2212 ifp->if_collisions++; 2213 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2214 dc_init(sc); 2215 return; 2216 } 2217 } 2218 2219 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2220 2221 ifp->if_opackets++; 2222 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2223 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2224 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2225 } 2226 2227 sc->dc_cdata.dc_tx_cnt--; 2228 DC_INC(idx, DC_TX_LIST_CNT); 2229 } 2230 2231 sc->dc_cdata.dc_tx_cons = idx; 2232 if (cur_tx != NULL) 2233 ifp->if_flags &= ~IFF_OACTIVE; 2234 2235 return; 2236} 2237 2238static void dc_tick(xsc) 2239 void *xsc; 2240{ 2241 struct dc_softc *sc; 2242 struct mii_data *mii; 2243 struct ifnet *ifp; 2244 int s; 2245 u_int32_t r; 2246 2247 s = splimp(); 2248 2249 sc = xsc; 2250 ifp = &sc->arpcom.ac_if; 2251 mii = device_get_softc(sc->dc_miibus); 2252 2253 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2254 if (sc->dc_flags & DC_21143_NWAY) { 2255 r = CSR_READ_4(sc, DC_10BTSTAT); 2256 if (IFM_SUBTYPE(mii->mii_media_active) == 2257 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2258 sc->dc_link = 0; 2259 mii_mediachg(mii); 2260 } 2261 if (IFM_SUBTYPE(mii->mii_media_active) == 2262 IFM_10_T && (r & DC_TSTAT_LS10)) { 2263 sc->dc_link = 0; 2264 mii_mediachg(mii); 2265 } 2266 if (sc->dc_link == 0) 2267 mii_tick(mii); 2268 } else { 2269 r = CSR_READ_4(sc, DC_ISR); 2270 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2271 sc->dc_cdata.dc_tx_cnt == 0) 2272 mii_tick(mii); 2273 if (!(mii->mii_media_status & IFM_ACTIVE)) 2274 sc->dc_link = 0; 2275 } 2276 } else 2277 mii_tick(mii); 2278 2279 /* 2280 * When the init routine completes, we expect to be able to send 2281 * packets right away, and in fact the network code will send a 2282 * gratuitous ARP the moment the init routine marks the interface 2283 * as running. However, even though the MAC may have been initialized, 2284 * there may be a delay of a few seconds before the PHY completes 2285 * autonegotiation and the link is brought up. Any transmissions 2286 * made during that delay will be lost. Dealing with this is tricky: 2287 * we can't just pause in the init routine while waiting for the 2288 * PHY to come ready since that would bring the whole system to 2289 * a screeching halt for several seconds. 2290 * 2291 * What we do here is prevent the TX start routine from sending 2292 * any packets until a link has been established. After the 2293 * interface has been initialized, the tick routine will poll 2294 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2295 * that time, packets will stay in the send queue, and once the 2296 * link comes up, they will be flushed out to the wire. 2297 */ 2298 if (!sc->dc_link) { 2299 mii_pollstat(mii); 2300 if (mii->mii_media_status & IFM_ACTIVE && 2301 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2302 sc->dc_link++; 2303 if (ifp->if_snd.ifq_head != NULL) 2304 dc_start(ifp); 2305 } 2306 } 2307 2308 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2309 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2310 else 2311 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2312 2313 splx(s); 2314 2315 return; 2316} 2317 2318static void dc_intr(arg) 2319 void *arg; 2320{ 2321 struct dc_softc *sc; 2322 struct ifnet *ifp; 2323 u_int32_t status; 2324 2325 sc = arg; 2326 ifp = &sc->arpcom.ac_if; 2327 2328 /* Supress unwanted interrupts */ 2329 if (!(ifp->if_flags & IFF_UP)) { 2330 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2331 dc_stop(sc); 2332 return; 2333 } 2334 2335 /* Disable interrupts. */ 2336 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2337 2338 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) { 2339 2340 CSR_WRITE_4(sc, DC_ISR, status); 2341 2342 if (status & DC_ISR_RX_OK) { 2343 int curpkts; 2344 curpkts = ifp->if_ipackets; 2345 dc_rxeof(sc); 2346 if (curpkts == ifp->if_ipackets) { 2347 while(dc_rx_resync(sc)) 2348 dc_rxeof(sc); 2349 } 2350 } 2351 2352 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2353 dc_txeof(sc); 2354 2355 if (status & DC_ISR_TX_IDLE) { 2356 dc_txeof(sc); 2357 if (sc->dc_cdata.dc_tx_cnt) { 2358 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2359 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2360 } 2361 } 2362 2363 if (status & DC_ISR_TX_UNDERRUN) { 2364 u_int32_t cfg; 2365 2366 printf("dc%d: TX underrun -- ", sc->dc_unit); 2367 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) 2368 dc_init(sc); 2369 cfg = CSR_READ_4(sc, DC_NETCFG); 2370 cfg &= ~DC_NETCFG_TX_THRESH; 2371 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2372 printf("using store and forward mode\n"); 2373 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2374 } else if (sc->dc_flags & DC_TX_STORENFWD) { 2375 printf("resetting\n"); 2376 } else { 2377 sc->dc_txthresh += 0x4000; 2378 printf("increasing TX threshold\n"); 2379 CSR_WRITE_4(sc, DC_NETCFG, cfg); 2380 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2381 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2382 } 2383 } 2384 2385 if ((status & DC_ISR_RX_WATDOGTIMEO) 2386 || (status & DC_ISR_RX_NOBUF)) { 2387 int curpkts; 2388 curpkts = ifp->if_ipackets; 2389 dc_rxeof(sc); 2390 if (curpkts == ifp->if_ipackets) { 2391 while(dc_rx_resync(sc)) 2392 dc_rxeof(sc); 2393 } 2394 } 2395 2396 if (status & DC_ISR_BUS_ERR) { 2397 dc_reset(sc); 2398 dc_init(sc); 2399 } 2400 } 2401 2402 /* Re-enable interrupts. */ 2403 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2404 2405 if (ifp->if_snd.ifq_head != NULL) 2406 dc_start(ifp); 2407 2408 return; 2409} 2410 2411/* 2412 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2413 * pointers to the fragment pointers. 2414 */ 2415static int dc_encap(sc, m_head, txidx) 2416 struct dc_softc *sc; 2417 struct mbuf *m_head; 2418 u_int32_t *txidx; 2419{ 2420 struct dc_desc *f = NULL; 2421 struct mbuf *m; 2422 int frag, cur, cnt = 0; 2423 2424 /* 2425 * Start packing the mbufs in this chain into 2426 * the fragment pointers. Stop when we run out 2427 * of fragments or hit the end of the mbuf chain. 2428 */ 2429 m = m_head; 2430 cur = frag = *txidx; 2431 2432 for (m = m_head; m != NULL; m = m->m_next) { 2433 if (m->m_len != 0) { 2434 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 2435 if (*txidx != sc->dc_cdata.dc_tx_prod && 2436 frag == (DC_TX_LIST_CNT - 1)) 2437 return(ENOBUFS); 2438 } 2439 if ((DC_TX_LIST_CNT - 2440 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 2441 return(ENOBUFS); 2442 2443 f = &sc->dc_ldata->dc_tx_list[frag]; 2444 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 2445 if (cnt == 0) { 2446 f->dc_status = 0; 2447 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 2448 } else 2449 f->dc_status = DC_TXSTAT_OWN; 2450 f->dc_data = vtophys(mtod(m, vm_offset_t)); 2451 cur = frag; 2452 DC_INC(frag, DC_TX_LIST_CNT); 2453 cnt++; 2454 } 2455 } 2456 2457 if (m != NULL) 2458 return(ENOBUFS); 2459 2460 sc->dc_cdata.dc_tx_cnt += cnt; 2461 sc->dc_cdata.dc_tx_chain[cur] = m_head; 2462 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 2463 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 2464 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 2465 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 2466 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2467 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 2468 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 2469 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 2470 *txidx = frag; 2471 2472 return(0); 2473} 2474 2475/* 2476 * Coalesce an mbuf chain into a single mbuf cluster buffer. 2477 * Needed for some really badly behaved chips that just can't 2478 * do scatter/gather correctly. 2479 */ 2480static int dc_coal(sc, m_head) 2481 struct dc_softc *sc; 2482 struct mbuf **m_head; 2483{ 2484 struct mbuf *m_new, *m; 2485 2486 m = *m_head; 2487 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2488 if (m_new == NULL) { 2489 printf("dc%d: no memory for tx list", sc->dc_unit); 2490 return(ENOBUFS); 2491 } 2492 if (m->m_pkthdr.len > MHLEN) { 2493 MCLGET(m_new, M_DONTWAIT); 2494 if (!(m_new->m_flags & M_EXT)) { 2495 m_freem(m_new); 2496 printf("dc%d: no memory for tx list", sc->dc_unit); 2497 return(ENOBUFS); 2498 } 2499 } 2500 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 2501 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 2502 m_freem(m); 2503 *m_head = m_new; 2504 2505 return(0); 2506} 2507 2508/* 2509 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2510 * to the mbuf data regions directly in the transmit lists. We also save a 2511 * copy of the pointers since the transmit list fragment pointers are 2512 * physical addresses. 2513 */ 2514 2515static void dc_start(ifp) 2516 struct ifnet *ifp; 2517{ 2518 struct dc_softc *sc; 2519 struct mbuf *m_head = NULL; 2520 int idx; 2521 2522 sc = ifp->if_softc; 2523 2524 if (!sc->dc_link) 2525 return; 2526 2527 if (ifp->if_flags & IFF_OACTIVE) 2528 return; 2529 2530 idx = sc->dc_cdata.dc_tx_prod; 2531 2532 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 2533 IF_DEQUEUE(&ifp->if_snd, m_head); 2534 if (m_head == NULL) 2535 break; 2536 2537 if (sc->dc_flags & DC_TX_COALESCE) { 2538 if (dc_coal(sc, &m_head)) { 2539 IF_PREPEND(&ifp->if_snd, m_head); 2540 ifp->if_flags |= IFF_OACTIVE; 2541 break; 2542 } 2543 } 2544 2545 if (dc_encap(sc, m_head, &idx)) { 2546 IF_PREPEND(&ifp->if_snd, m_head); 2547 ifp->if_flags |= IFF_OACTIVE; 2548 break; 2549 } 2550 2551 /* 2552 * If there's a BPF listener, bounce a copy of this frame 2553 * to him. 2554 */ 2555 if (ifp->if_bpf) 2556 bpf_mtap(ifp, m_head); 2557 } 2558 2559 /* Transmit */ 2560 sc->dc_cdata.dc_tx_prod = idx; 2561 if (!(sc->dc_flags & DC_TX_POLL)) 2562 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2563 2564 /* 2565 * Set a timeout in case the chip goes out to lunch. 2566 */ 2567 ifp->if_timer = 5; 2568 2569 return; 2570} 2571 2572static void dc_init(xsc) 2573 void *xsc; 2574{ 2575 struct dc_softc *sc = xsc; 2576 struct ifnet *ifp = &sc->arpcom.ac_if; 2577 struct mii_data *mii; 2578 int s; 2579 2580 s = splimp(); 2581 2582 mii = device_get_softc(sc->dc_miibus); 2583 2584 /* 2585 * Cancel pending I/O and free all RX/TX buffers. 2586 */ 2587 dc_stop(sc); 2588 dc_reset(sc); 2589 2590 /* 2591 * Set cache alignment and burst length. 2592 */ 2593 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 2594 CSR_WRITE_4(sc, DC_BUSCTL, 0); 2595 else 2596 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 2597 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 2598 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 2599 } else { 2600 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 2601 } 2602 if (sc->dc_flags & DC_TX_POLL) 2603 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 2604 switch(sc->dc_cachesize) { 2605 case 32: 2606 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 2607 break; 2608 case 16: 2609 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 2610 break; 2611 case 8: 2612 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 2613 break; 2614 case 0: 2615 default: 2616 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 2617 break; 2618 } 2619 2620 if (sc->dc_flags & DC_TX_STORENFWD) 2621 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2622 else { 2623 if (sc->dc_txthresh == DC_TXTHRESH_160BYTES) { 2624 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2625 } else { 2626 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2627 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2628 } 2629 } 2630 2631 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 2632 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 2633 2634 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2635 /* 2636 * The app notes for the 98713 and 98715A say that 2637 * in order to have the chips operate properly, a magic 2638 * number must be written to CSR16. Macronix does not 2639 * document the meaning of these bits so there's no way 2640 * to know exactly what they do. The 98713 has a magic 2641 * number all its own; the rest all use a different one. 2642 */ 2643 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 2644 if (sc->dc_type == DC_TYPE_98713) 2645 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 2646 else 2647 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 2648 } 2649 2650 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2651 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_72BYTES); 2652 2653 /* Init circular RX list. */ 2654 if (dc_list_rx_init(sc) == ENOBUFS) { 2655 printf("dc%d: initialization failed: no " 2656 "memory for rx buffers\n", sc->dc_unit); 2657 dc_stop(sc); 2658 (void)splx(s); 2659 return; 2660 } 2661 2662 /* 2663 * Init tx descriptors. 2664 */ 2665 dc_list_tx_init(sc); 2666 2667 /* 2668 * Load the address of the RX list. 2669 */ 2670 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 2671 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 2672 2673 /* 2674 * Enable interrupts. 2675 */ 2676 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2677 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 2678 2679 /* Enable transmitter. */ 2680 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2681 2682 /* 2683 * Load the RX/multicast filter. We do this sort of late 2684 * because the filter programming scheme on the 21143 and 2685 * some clones requires DMAing a setup frame via the TX 2686 * engine, and we need the transmitter enabled for that. 2687 */ 2688 dc_setfilt(sc); 2689 2690 /* Enable receiver. */ 2691 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 2692 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 2693 2694 mii_mediachg(mii); 2695 dc_setcfg(sc, sc->dc_if_media); 2696 2697 ifp->if_flags |= IFF_RUNNING; 2698 ifp->if_flags &= ~IFF_OACTIVE; 2699 2700 (void)splx(s); 2701 2702 if (sc->dc_flags & DC_21143_NWAY) 2703 sc->dc_stat_ch = timeout(dc_tick, sc, hz/10); 2704 else 2705 sc->dc_stat_ch = timeout(dc_tick, sc, hz); 2706 2707#ifdef __alpha__ 2708 if(sc->dc_srm_media) { 2709 struct ifreq ifr; 2710 2711 ifr.ifr_media = sc->dc_srm_media; 2712 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 2713 sc->dc_srm_media = 0; 2714 } 2715#endif 2716 return; 2717} 2718 2719/* 2720 * Set media options. 2721 */ 2722static int dc_ifmedia_upd(ifp) 2723 struct ifnet *ifp; 2724{ 2725 struct dc_softc *sc; 2726 struct mii_data *mii; 2727 struct ifmedia *ifm; 2728 2729 sc = ifp->if_softc; 2730 mii = device_get_softc(sc->dc_miibus); 2731 mii_mediachg(mii); 2732 ifm = &mii->mii_media; 2733 2734 if (DC_IS_DAVICOM(sc) && 2735 IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) 2736 dc_setcfg(sc, ifm->ifm_media); 2737 else 2738 sc->dc_link = 0; 2739 2740 return(0); 2741} 2742 2743/* 2744 * Report current media status. 2745 */ 2746static void dc_ifmedia_sts(ifp, ifmr) 2747 struct ifnet *ifp; 2748 struct ifmediareq *ifmr; 2749{ 2750 struct dc_softc *sc; 2751 struct mii_data *mii; 2752 struct ifmedia *ifm; 2753 2754 sc = ifp->if_softc; 2755 mii = device_get_softc(sc->dc_miibus); 2756 mii_pollstat(mii); 2757 ifm = &mii->mii_media; 2758 if (DC_IS_DAVICOM(sc)) { 2759 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_homePNA) { 2760 ifmr->ifm_active = ifm->ifm_media; 2761 ifmr->ifm_status = 0; 2762 return; 2763 } 2764 } 2765 ifmr->ifm_active = mii->mii_media_active; 2766 ifmr->ifm_status = mii->mii_media_status; 2767 2768 return; 2769} 2770 2771static int dc_ioctl(ifp, command, data) 2772 struct ifnet *ifp; 2773 u_long command; 2774 caddr_t data; 2775{ 2776 struct dc_softc *sc = ifp->if_softc; 2777 struct ifreq *ifr = (struct ifreq *) data; 2778 struct mii_data *mii; 2779 int s, error = 0; 2780 2781 s = splimp(); 2782 2783 switch(command) { 2784 case SIOCSIFADDR: 2785 case SIOCGIFADDR: 2786 case SIOCSIFMTU: 2787 error = ether_ioctl(ifp, command, data); 2788 break; 2789 case SIOCSIFFLAGS: 2790 if (ifp->if_flags & IFF_UP) { 2791 if (ifp->if_flags & IFF_RUNNING && 2792 ifp->if_flags & IFF_PROMISC && 2793 !(sc->dc_if_flags & IFF_PROMISC)) { 2794 dc_setfilt(sc); 2795 } else if (ifp->if_flags & IFF_RUNNING && 2796 !(ifp->if_flags & IFF_PROMISC) && 2797 sc->dc_if_flags & IFF_PROMISC) { 2798 dc_setfilt(sc); 2799 } else if (!(ifp->if_flags & IFF_RUNNING)) { 2800 sc->dc_txthresh = 0; 2801 dc_init(sc); 2802 } 2803 } else { 2804 if (ifp->if_flags & IFF_RUNNING) 2805 dc_stop(sc); 2806 } 2807 sc->dc_if_flags = ifp->if_flags; 2808 error = 0; 2809 break; 2810 case SIOCADDMULTI: 2811 case SIOCDELMULTI: 2812 dc_setfilt(sc); 2813 error = 0; 2814 break; 2815 case SIOCGIFMEDIA: 2816 case SIOCSIFMEDIA: 2817 mii = device_get_softc(sc->dc_miibus); 2818 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2819#ifdef __alpha__ 2820 if (sc->dc_srm_media) 2821 sc->dc_srm_media = 0; 2822#endif 2823 break; 2824 default: 2825 error = EINVAL; 2826 break; 2827 } 2828 2829 (void)splx(s); 2830 2831 return(error); 2832} 2833 2834static void dc_watchdog(ifp) 2835 struct ifnet *ifp; 2836{ 2837 struct dc_softc *sc; 2838 2839 sc = ifp->if_softc; 2840 2841 ifp->if_oerrors++; 2842 printf("dc%d: watchdog timeout\n", sc->dc_unit); 2843 2844 dc_stop(sc); 2845 dc_reset(sc); 2846 dc_init(sc); 2847 2848 if (ifp->if_snd.ifq_head != NULL) 2849 dc_start(ifp); 2850 2851 return; 2852} 2853 2854/* 2855 * Stop the adapter and free any mbufs allocated to the 2856 * RX and TX lists. 2857 */ 2858static void dc_stop(sc) 2859 struct dc_softc *sc; 2860{ 2861 register int i; 2862 struct ifnet *ifp; 2863 2864 ifp = &sc->arpcom.ac_if; 2865 ifp->if_timer = 0; 2866 2867 untimeout(dc_tick, sc, sc->dc_stat_ch); 2868 2869 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 2870 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2871 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 2872 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 2873 sc->dc_link = 0; 2874 2875 /* 2876 * Free data in the RX lists. 2877 */ 2878 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2879 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 2880 m_freem(sc->dc_cdata.dc_rx_chain[i]); 2881 sc->dc_cdata.dc_rx_chain[i] = NULL; 2882 } 2883 } 2884 bzero((char *)&sc->dc_ldata->dc_rx_list, 2885 sizeof(sc->dc_ldata->dc_rx_list)); 2886 2887 /* 2888 * Free the TX list buffers. 2889 */ 2890 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2891 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 2892 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 2893 DC_TXCTL_SETUP) { 2894 sc->dc_cdata.dc_tx_chain[i] = NULL; 2895 continue; 2896 } 2897 m_freem(sc->dc_cdata.dc_tx_chain[i]); 2898 sc->dc_cdata.dc_tx_chain[i] = NULL; 2899 } 2900 } 2901 2902 bzero((char *)&sc->dc_ldata->dc_tx_list, 2903 sizeof(sc->dc_ldata->dc_tx_list)); 2904 2905 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2906 2907 return; 2908} 2909 2910/* 2911 * Stop all chip I/O so that the kernel's probe routines don't 2912 * get confused by errant DMAs when rebooting. 2913 */ 2914static void dc_shutdown(dev) 2915 device_t dev; 2916{ 2917 struct dc_softc *sc; 2918 2919 sc = device_get_softc(dev); 2920 2921 dc_stop(sc); 2922 2923 return; 2924} 2925