if_dc.c revision 227685
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/dc/if_dc.c 227685 2011-11-18 21:22:43Z marius $"); 35 36/* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN983 (www.admtek.com.tw) 47 * ADMtek CardBus AN985 (www.admtek.com.tw) 48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Xircom X3201 (www.xircom.com) 52 * Abocom FE2500 53 * Conexant LANfinity (www.conexant.com) 54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 55 * 56 * Datasheets for the 21143 are available at developer.intel.com. 57 * Datasheets for the clone parts can be found at their respective sites. 58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 59 * The PNIC II is essentially a Macronix 98715A chip; the only difference 60 * worth noting is that its multicast hash table is only 128 bits wide 61 * instead of 512. 62 * 63 * Written by Bill Paul <wpaul@ee.columbia.edu> 64 * Electrical Engineering Department 65 * Columbia University, New York City 66 */ 67/* 68 * The Intel 21143 is the successor to the DEC 21140. It is basically 69 * the same as the 21140 but with a few new features. The 21143 supports 70 * three kinds of media attachments: 71 * 72 * o MII port, for 10Mbps and 100Mbps support and NWAY 73 * autonegotiation provided by an external PHY. 74 * o SYM port, for symbol mode 100Mbps support. 75 * o 10baseT port. 76 * o AUI/BNC port. 77 * 78 * The 100Mbps SYM port and 10baseT port can be used together in 79 * combination with the internal NWAY support to create a 10/100 80 * autosensing configuration. 81 * 82 * Note that not all tulip workalikes are handled in this driver: we only 83 * deal with those which are relatively well behaved. The Winbond is 84 * handled separately due to its different register offsets and the 85 * special handling needed for its various bugs. The PNIC is handled 86 * here, but I'm not thrilled about it. 87 * 88 * All of the workalike chips use some form of MII transceiver support 89 * with the exception of the Macronix chips, which also have a SYM port. 90 * The ASIX AX88140A is also documented to have a SYM port, but all 91 * the cards I've seen use an MII transceiver, probably because the 92 * AX88140A doesn't support internal NWAY. 93 */ 94 95#ifdef HAVE_KERNEL_OPTION_HEADERS 96#include "opt_device_polling.h" 97#endif 98 99#include <sys/param.h> 100#include <sys/endian.h> 101#include <sys/systm.h> 102#include <sys/sockio.h> 103#include <sys/mbuf.h> 104#include <sys/malloc.h> 105#include <sys/kernel.h> 106#include <sys/module.h> 107#include <sys/socket.h> 108 109#include <net/if.h> 110#include <net/if_arp.h> 111#include <net/ethernet.h> 112#include <net/if_dl.h> 113#include <net/if_media.h> 114#include <net/if_types.h> 115#include <net/if_vlan_var.h> 116 117#include <net/bpf.h> 118 119#include <machine/bus.h> 120#include <machine/resource.h> 121#include <sys/bus.h> 122#include <sys/rman.h> 123 124#include <dev/mii/mii.h> 125#include <dev/mii/mii_bitbang.h> 126#include <dev/mii/miivar.h> 127 128#include <dev/pci/pcireg.h> 129#include <dev/pci/pcivar.h> 130 131#define DC_USEIOSPACE 132 133#include <dev/dc/if_dcreg.h> 134 135#ifdef __sparc64__ 136#include <dev/ofw/openfirm.h> 137#include <machine/ofw_machdep.h> 138#endif 139 140MODULE_DEPEND(dc, pci, 1, 1, 1); 141MODULE_DEPEND(dc, ether, 1, 1, 1); 142MODULE_DEPEND(dc, miibus, 1, 1, 1); 143 144/* 145 * "device miibus" is required in kernel config. See GENERIC if you get 146 * errors here. 147 */ 148#include "miibus_if.h" 149 150/* 151 * Various supported device vendors/types and their names. 152 */ 153static const struct dc_type const dc_devs[] = { 154 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 155 "Intel 21143 10/100BaseTX" }, 156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 157 "Davicom DM9009 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 159 "Davicom DM9100 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 161 "Davicom DM9102A 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 163 "Davicom DM9102 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 165 "ADMtek AL981 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 167 "ADMtek AN983 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 169 "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 171 "ADMtek ADM9511 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 173 "ADMtek ADM9513 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 175 "ASIX AX88141 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 177 "ASIX AX88140A 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 179 "Macronix 98713A 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 181 "Macronix 98713 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 185 "Compex RL100-TX 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 187 "Macronix 98725 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 189 "Macronix 98715AEC-C 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 191 "Macronix 98715/98715A 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 193 "Macronix 98727/98732 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 195 "LC82C115 PNIC II 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 197 "82c169 PNIC 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 199 "82c168 PNIC 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 201 "Accton EN1217 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 203 "Accton EN2242 MiniPCI 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 205 "Xircom X3201 10/100BaseTX" }, 206 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 207 "Neteasy DRP-32TXD Cardbus 10/100" }, 208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 209 "Abocom FE2500 10/100BaseTX" }, 210 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 211 "Abocom FE2500MX 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 213 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 214 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 215 "Hawking CB102 CardBus 10/100" }, 216 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 217 "PlaneX FNW-3602-T CardBus 10/100" }, 218 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 219 "3Com OfficeConnect 10/100B" }, 220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 221 "Microsoft MN-120 CardBus 10/100" }, 222 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 223 "Microsoft MN-130 10/100" }, 224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 225 "Linksys PCMPC200 CardBus 10/100" }, 226 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 227 "Linksys PCMPC200 CardBus 10/100" }, 228 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0, 229 "ULi M5261 FastEthernet" }, 230 { DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0, 231 "ULi M5263 FastEthernet" }, 232 { 0, 0, NULL } 233}; 234 235static int dc_probe(device_t); 236static int dc_attach(device_t); 237static int dc_detach(device_t); 238static int dc_suspend(device_t); 239static int dc_resume(device_t); 240static const struct dc_type *dc_devtype(device_t); 241static void dc_discard_rxbuf(struct dc_softc *, int); 242static int dc_newbuf(struct dc_softc *, int); 243static int dc_encap(struct dc_softc *, struct mbuf **); 244static void dc_pnic_rx_bug_war(struct dc_softc *, int); 245static int dc_rx_resync(struct dc_softc *); 246static int dc_rxeof(struct dc_softc *); 247static void dc_txeof(struct dc_softc *); 248static void dc_tick(void *); 249static void dc_tx_underrun(struct dc_softc *); 250static void dc_intr(void *); 251static void dc_start(struct ifnet *); 252static void dc_start_locked(struct ifnet *); 253static int dc_ioctl(struct ifnet *, u_long, caddr_t); 254static void dc_init(void *); 255static void dc_init_locked(struct dc_softc *); 256static void dc_stop(struct dc_softc *); 257static void dc_watchdog(void *); 258static int dc_shutdown(device_t); 259static int dc_ifmedia_upd(struct ifnet *); 260static int dc_ifmedia_upd_locked(struct dc_softc *); 261static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 262 263static int dc_dma_alloc(struct dc_softc *); 264static void dc_dma_free(struct dc_softc *); 265static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int); 266 267static void dc_delay(struct dc_softc *); 268static void dc_eeprom_idle(struct dc_softc *); 269static void dc_eeprom_putbyte(struct dc_softc *, int); 270static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *); 271static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *); 272static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *); 273static void dc_eeprom_width(struct dc_softc *); 274static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 275 276static int dc_miibus_readreg(device_t, int, int); 277static int dc_miibus_writereg(device_t, int, int, int); 278static void dc_miibus_statchg(device_t); 279static void dc_miibus_mediainit(device_t); 280 281static void dc_setcfg(struct dc_softc *, int); 282static void dc_netcfg_wait(struct dc_softc *); 283static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 284static uint32_t dc_mchash_be(const uint8_t *); 285static void dc_setfilt_21143(struct dc_softc *); 286static void dc_setfilt_asix(struct dc_softc *); 287static void dc_setfilt_admtek(struct dc_softc *); 288static void dc_setfilt_uli(struct dc_softc *); 289static void dc_setfilt_xircom(struct dc_softc *); 290 291static void dc_setfilt(struct dc_softc *); 292 293static void dc_reset(struct dc_softc *); 294static int dc_list_rx_init(struct dc_softc *); 295static int dc_list_tx_init(struct dc_softc *); 296 297static int dc_read_srom(struct dc_softc *, int); 298static int dc_parse_21143_srom(struct dc_softc *); 299static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 300static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 301static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 302static void dc_apply_fixup(struct dc_softc *, int); 303static int dc_check_multiport(struct dc_softc *); 304 305/* 306 * MII bit-bang glue 307 */ 308static uint32_t dc_mii_bitbang_read(device_t); 309static void dc_mii_bitbang_write(device_t, uint32_t); 310 311static const struct mii_bitbang_ops dc_mii_bitbang_ops = { 312 dc_mii_bitbang_read, 313 dc_mii_bitbang_write, 314 { 315 DC_SIO_MII_DATAOUT, /* MII_BIT_MDO */ 316 DC_SIO_MII_DATAIN, /* MII_BIT_MDI */ 317 DC_SIO_MII_CLK, /* MII_BIT_MDC */ 318 0, /* MII_BIT_DIR_HOST_PHY */ 319 DC_SIO_MII_DIR, /* MII_BIT_DIR_PHY_HOST */ 320 } 321}; 322 323#ifdef DC_USEIOSPACE 324#define DC_RES SYS_RES_IOPORT 325#define DC_RID DC_PCI_CFBIO 326#else 327#define DC_RES SYS_RES_MEMORY 328#define DC_RID DC_PCI_CFBMA 329#endif 330 331static device_method_t dc_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, dc_probe), 334 DEVMETHOD(device_attach, dc_attach), 335 DEVMETHOD(device_detach, dc_detach), 336 DEVMETHOD(device_suspend, dc_suspend), 337 DEVMETHOD(device_resume, dc_resume), 338 DEVMETHOD(device_shutdown, dc_shutdown), 339 340 /* bus interface */ 341 DEVMETHOD(bus_print_child, bus_generic_print_child), 342 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 343 344 /* MII interface */ 345 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 346 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 347 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 348 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 349 350 { 0, 0 } 351}; 352 353static driver_t dc_driver = { 354 "dc", 355 dc_methods, 356 sizeof(struct dc_softc) 357}; 358 359static devclass_t dc_devclass; 360 361DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 362DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 363 364#define DC_SETBIT(sc, reg, x) \ 365 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 366 367#define DC_CLRBIT(sc, reg, x) \ 368 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 369 370#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 371#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 372 373static void 374dc_delay(struct dc_softc *sc) 375{ 376 int idx; 377 378 for (idx = (300 / 33) + 1; idx > 0; idx--) 379 CSR_READ_4(sc, DC_BUSCTL); 380} 381 382static void 383dc_eeprom_width(struct dc_softc *sc) 384{ 385 int i; 386 387 /* Force EEPROM to idle state. */ 388 dc_eeprom_idle(sc); 389 390 /* Enter EEPROM access mode. */ 391 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 392 dc_delay(sc); 393 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 394 dc_delay(sc); 395 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 396 dc_delay(sc); 397 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 398 dc_delay(sc); 399 400 for (i = 3; i--;) { 401 if (6 & (1 << i)) 402 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 403 else 404 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 405 dc_delay(sc); 406 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 407 dc_delay(sc); 408 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 409 dc_delay(sc); 410 } 411 412 for (i = 1; i <= 12; i++) { 413 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 414 dc_delay(sc); 415 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 416 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 417 dc_delay(sc); 418 break; 419 } 420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 421 dc_delay(sc); 422 } 423 424 /* Turn off EEPROM access mode. */ 425 dc_eeprom_idle(sc); 426 427 if (i < 4 || i > 12) 428 sc->dc_romwidth = 6; 429 else 430 sc->dc_romwidth = i; 431 432 /* Enter EEPROM access mode. */ 433 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 434 dc_delay(sc); 435 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 436 dc_delay(sc); 437 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 438 dc_delay(sc); 439 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 440 dc_delay(sc); 441 442 /* Turn off EEPROM access mode. */ 443 dc_eeprom_idle(sc); 444} 445 446static void 447dc_eeprom_idle(struct dc_softc *sc) 448{ 449 int i; 450 451 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 452 dc_delay(sc); 453 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 454 dc_delay(sc); 455 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 456 dc_delay(sc); 457 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 458 dc_delay(sc); 459 460 for (i = 0; i < 25; i++) { 461 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 462 dc_delay(sc); 463 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 464 dc_delay(sc); 465 } 466 467 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 468 dc_delay(sc); 469 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 470 dc_delay(sc); 471 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 472} 473 474/* 475 * Send a read command and address to the EEPROM, check for ACK. 476 */ 477static void 478dc_eeprom_putbyte(struct dc_softc *sc, int addr) 479{ 480 int d, i; 481 482 d = DC_EECMD_READ >> 6; 483 for (i = 3; i--; ) { 484 if (d & (1 << i)) 485 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 486 else 487 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 488 dc_delay(sc); 489 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 490 dc_delay(sc); 491 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 492 dc_delay(sc); 493 } 494 495 /* 496 * Feed in each bit and strobe the clock. 497 */ 498 for (i = sc->dc_romwidth; i--;) { 499 if (addr & (1 << i)) { 500 SIO_SET(DC_SIO_EE_DATAIN); 501 } else { 502 SIO_CLR(DC_SIO_EE_DATAIN); 503 } 504 dc_delay(sc); 505 SIO_SET(DC_SIO_EE_CLK); 506 dc_delay(sc); 507 SIO_CLR(DC_SIO_EE_CLK); 508 dc_delay(sc); 509 } 510} 511 512/* 513 * Read a word of data stored in the EEPROM at address 'addr.' 514 * The PNIC 82c168/82c169 has its own non-standard way to read 515 * the EEPROM. 516 */ 517static void 518dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest) 519{ 520 int i; 521 uint32_t r; 522 523 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 524 525 for (i = 0; i < DC_TIMEOUT; i++) { 526 DELAY(1); 527 r = CSR_READ_4(sc, DC_SIO); 528 if (!(r & DC_PN_SIOCTL_BUSY)) { 529 *dest = (uint16_t)(r & 0xFFFF); 530 return; 531 } 532 } 533} 534 535/* 536 * Read a word of data stored in the EEPROM at address 'addr.' 537 * The Xircom X3201 has its own non-standard way to read 538 * the EEPROM, too. 539 */ 540static void 541dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest) 542{ 543 544 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 545 546 addr *= 2; 547 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 548 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 549 addr += 1; 550 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 551 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 552 553 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 554} 555 556/* 557 * Read a word of data stored in the EEPROM at address 'addr.' 558 */ 559static void 560dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest) 561{ 562 int i; 563 uint16_t word = 0; 564 565 /* Force EEPROM to idle state. */ 566 dc_eeprom_idle(sc); 567 568 /* Enter EEPROM access mode. */ 569 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 570 dc_delay(sc); 571 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 572 dc_delay(sc); 573 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 574 dc_delay(sc); 575 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 576 dc_delay(sc); 577 578 /* 579 * Send address of word we want to read. 580 */ 581 dc_eeprom_putbyte(sc, addr); 582 583 /* 584 * Start reading bits from EEPROM. 585 */ 586 for (i = 0x8000; i; i >>= 1) { 587 SIO_SET(DC_SIO_EE_CLK); 588 dc_delay(sc); 589 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 590 word |= i; 591 dc_delay(sc); 592 SIO_CLR(DC_SIO_EE_CLK); 593 dc_delay(sc); 594 } 595 596 /* Turn off EEPROM access mode. */ 597 dc_eeprom_idle(sc); 598 599 *dest = word; 600} 601 602/* 603 * Read a sequence of words from the EEPROM. 604 */ 605static void 606dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 607{ 608 int i; 609 uint16_t word = 0, *ptr; 610 611 for (i = 0; i < cnt; i++) { 612 if (DC_IS_PNIC(sc)) 613 dc_eeprom_getword_pnic(sc, off + i, &word); 614 else if (DC_IS_XIRCOM(sc)) 615 dc_eeprom_getword_xircom(sc, off + i, &word); 616 else 617 dc_eeprom_getword(sc, off + i, &word); 618 ptr = (uint16_t *)(dest + (i * 2)); 619 if (be) 620 *ptr = be16toh(word); 621 else 622 *ptr = le16toh(word); 623 } 624} 625 626/* 627 * Write the MII serial port for the MII bit-bang module. 628 */ 629static void 630dc_mii_bitbang_write(device_t dev, uint32_t val) 631{ 632 struct dc_softc *sc; 633 634 sc = device_get_softc(dev); 635 636 CSR_WRITE_4(sc, DC_SIO, val); 637 CSR_BARRIER_4(sc, DC_SIO, 638 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 639} 640 641/* 642 * Read the MII serial port for the MII bit-bang module. 643 */ 644static uint32_t 645dc_mii_bitbang_read(device_t dev) 646{ 647 struct dc_softc *sc; 648 uint32_t val; 649 650 sc = device_get_softc(dev); 651 652 val = CSR_READ_4(sc, DC_SIO); 653 CSR_BARRIER_4(sc, DC_SIO, 654 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 655 656 return (val); 657} 658 659static int 660dc_miibus_readreg(device_t dev, int phy, int reg) 661{ 662 struct dc_softc *sc; 663 int i, rval, phy_reg = 0; 664 665 sc = device_get_softc(dev); 666 667 if (sc->dc_pmode != DC_PMODE_MII) { 668 if (phy == (MII_NPHY - 1)) { 669 switch (reg) { 670 case MII_BMSR: 671 /* 672 * Fake something to make the probe 673 * code think there's a PHY here. 674 */ 675 return (BMSR_MEDIAMASK); 676 break; 677 case MII_PHYIDR1: 678 if (DC_IS_PNIC(sc)) 679 return (DC_VENDORID_LO); 680 return (DC_VENDORID_DEC); 681 break; 682 case MII_PHYIDR2: 683 if (DC_IS_PNIC(sc)) 684 return (DC_DEVICEID_82C168); 685 return (DC_DEVICEID_21143); 686 break; 687 default: 688 return (0); 689 break; 690 } 691 } else 692 return (0); 693 } 694 695 if (DC_IS_PNIC(sc)) { 696 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 697 (phy << 23) | (reg << 18)); 698 for (i = 0; i < DC_TIMEOUT; i++) { 699 DELAY(1); 700 rval = CSR_READ_4(sc, DC_PN_MII); 701 if (!(rval & DC_PN_MII_BUSY)) { 702 rval &= 0xFFFF; 703 return (rval == 0xFFFF ? 0 : rval); 704 } 705 } 706 return (0); 707 } 708 709 if (sc->dc_type == DC_TYPE_ULI_M5263) { 710 CSR_WRITE_4(sc, DC_ROM, 711 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 712 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 713 DC_ULI_PHY_OP_READ); 714 for (i = 0; i < DC_TIMEOUT; i++) { 715 DELAY(1); 716 rval = CSR_READ_4(sc, DC_ROM); 717 if ((rval & DC_ULI_PHY_OP_DONE) != 0) { 718 return (rval & DC_ULI_PHY_DATA_MASK); 719 } 720 } 721 if (i == DC_TIMEOUT) 722 device_printf(dev, "phy read timed out\n"); 723 return (0); 724 } 725 726 if (DC_IS_COMET(sc)) { 727 switch (reg) { 728 case MII_BMCR: 729 phy_reg = DC_AL_BMCR; 730 break; 731 case MII_BMSR: 732 phy_reg = DC_AL_BMSR; 733 break; 734 case MII_PHYIDR1: 735 phy_reg = DC_AL_VENID; 736 break; 737 case MII_PHYIDR2: 738 phy_reg = DC_AL_DEVID; 739 break; 740 case MII_ANAR: 741 phy_reg = DC_AL_ANAR; 742 break; 743 case MII_ANLPAR: 744 phy_reg = DC_AL_LPAR; 745 break; 746 case MII_ANER: 747 phy_reg = DC_AL_ANER; 748 break; 749 default: 750 device_printf(dev, "phy_read: bad phy register %x\n", 751 reg); 752 return (0); 753 break; 754 } 755 756 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 757 if (rval == 0xFFFF) 758 return (0); 759 return (rval); 760 } 761 762 if (sc->dc_type == DC_TYPE_98713) { 763 phy_reg = CSR_READ_4(sc, DC_NETCFG); 764 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 765 } 766 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg); 767 if (sc->dc_type == DC_TYPE_98713) 768 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 769 770 return (rval); 771} 772 773static int 774dc_miibus_writereg(device_t dev, int phy, int reg, int data) 775{ 776 struct dc_softc *sc; 777 int i, phy_reg = 0; 778 779 sc = device_get_softc(dev); 780 781 if (DC_IS_PNIC(sc)) { 782 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 783 (phy << 23) | (reg << 10) | data); 784 for (i = 0; i < DC_TIMEOUT; i++) { 785 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 786 break; 787 } 788 return (0); 789 } 790 791 if (sc->dc_type == DC_TYPE_ULI_M5263) { 792 CSR_WRITE_4(sc, DC_ROM, 793 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) | 794 ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) | 795 ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) | 796 DC_ULI_PHY_OP_WRITE); 797 DELAY(1); 798 return (0); 799 } 800 801 if (DC_IS_COMET(sc)) { 802 switch (reg) { 803 case MII_BMCR: 804 phy_reg = DC_AL_BMCR; 805 break; 806 case MII_BMSR: 807 phy_reg = DC_AL_BMSR; 808 break; 809 case MII_PHYIDR1: 810 phy_reg = DC_AL_VENID; 811 break; 812 case MII_PHYIDR2: 813 phy_reg = DC_AL_DEVID; 814 break; 815 case MII_ANAR: 816 phy_reg = DC_AL_ANAR; 817 break; 818 case MII_ANLPAR: 819 phy_reg = DC_AL_LPAR; 820 break; 821 case MII_ANER: 822 phy_reg = DC_AL_ANER; 823 break; 824 default: 825 device_printf(dev, "phy_write: bad phy register %x\n", 826 reg); 827 return (0); 828 break; 829 } 830 831 CSR_WRITE_4(sc, phy_reg, data); 832 return (0); 833 } 834 835 if (sc->dc_type == DC_TYPE_98713) { 836 phy_reg = CSR_READ_4(sc, DC_NETCFG); 837 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 838 } 839 mii_bitbang_writereg(dev, &dc_mii_bitbang_ops, phy, reg, data); 840 if (sc->dc_type == DC_TYPE_98713) 841 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 842 843 return (0); 844} 845 846static void 847dc_miibus_statchg(device_t dev) 848{ 849 struct dc_softc *sc; 850 struct ifnet *ifp; 851 struct mii_data *mii; 852 struct ifmedia *ifm; 853 854 sc = device_get_softc(dev); 855 856 mii = device_get_softc(sc->dc_miibus); 857 ifp = sc->dc_ifp; 858 if (mii == NULL || ifp == NULL || 859 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 860 return; 861 862 ifm = &mii->mii_media; 863 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 864 dc_setcfg(sc, ifm->ifm_media); 865 return; 866 } else if (!DC_IS_ADMTEK(sc)) 867 dc_setcfg(sc, mii->mii_media_active); 868 869 sc->dc_link = 0; 870 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 871 (IFM_ACTIVE | IFM_AVALID)) { 872 switch (IFM_SUBTYPE(mii->mii_media_active)) { 873 case IFM_10_T: 874 case IFM_100_TX: 875 sc->dc_link = 1; 876 break; 877 } 878 } 879} 880 881/* 882 * Special support for DM9102A cards with HomePNA PHYs. Note: 883 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 884 * to be impossible to talk to the management interface of the DM9801 885 * PHY (its MDIO pin is not connected to anything). Consequently, 886 * the driver has to just 'know' about the additional mode and deal 887 * with it itself. *sigh* 888 */ 889static void 890dc_miibus_mediainit(device_t dev) 891{ 892 struct dc_softc *sc; 893 struct mii_data *mii; 894 struct ifmedia *ifm; 895 int rev; 896 897 rev = pci_get_revid(dev); 898 899 sc = device_get_softc(dev); 900 mii = device_get_softc(sc->dc_miibus); 901 ifm = &mii->mii_media; 902 903 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 904 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 905} 906 907#define DC_BITS_512 9 908#define DC_BITS_128 7 909#define DC_BITS_64 6 910 911static uint32_t 912dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 913{ 914 uint32_t crc; 915 916 /* Compute CRC for the address value. */ 917 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 918 919 /* 920 * The hash table on the PNIC II and the MX98715AEC-C/D/E 921 * chips is only 128 bits wide. 922 */ 923 if (sc->dc_flags & DC_128BIT_HASH) 924 return (crc & ((1 << DC_BITS_128) - 1)); 925 926 /* The hash table on the MX98715BEC is only 64 bits wide. */ 927 if (sc->dc_flags & DC_64BIT_HASH) 928 return (crc & ((1 << DC_BITS_64) - 1)); 929 930 /* Xircom's hash filtering table is different (read: weird) */ 931 /* Xircom uses the LEAST significant bits */ 932 if (DC_IS_XIRCOM(sc)) { 933 if ((crc & 0x180) == 0x180) 934 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 935 else 936 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 937 (12 << 4)); 938 } 939 940 return (crc & ((1 << DC_BITS_512) - 1)); 941} 942 943/* 944 * Calculate CRC of a multicast group address, return the lower 6 bits. 945 */ 946static uint32_t 947dc_mchash_be(const uint8_t *addr) 948{ 949 uint32_t crc; 950 951 /* Compute CRC for the address value. */ 952 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 953 954 /* Return the filter bit position. */ 955 return ((crc >> 26) & 0x0000003F); 956} 957 958/* 959 * 21143-style RX filter setup routine. Filter programming is done by 960 * downloading a special setup frame into the TX engine. 21143, Macronix, 961 * PNIC, PNIC II and Davicom chips are programmed this way. 962 * 963 * We always program the chip using 'hash perfect' mode, i.e. one perfect 964 * address (our node address) and a 512-bit hash filter for multicast 965 * frames. We also sneak the broadcast address into the hash filter since 966 * we need that too. 967 */ 968static void 969dc_setfilt_21143(struct dc_softc *sc) 970{ 971 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 972 struct dc_desc *sframe; 973 uint32_t h, *sp; 974 struct ifmultiaddr *ifma; 975 struct ifnet *ifp; 976 int i; 977 978 ifp = sc->dc_ifp; 979 980 i = sc->dc_cdata.dc_tx_prod; 981 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 982 sc->dc_cdata.dc_tx_cnt++; 983 sframe = &sc->dc_ldata.dc_tx_list[i]; 984 sp = sc->dc_cdata.dc_sbuf; 985 bzero(sp, DC_SFRAME_LEN); 986 987 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 988 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 989 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 990 991 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 992 993 /* If we want promiscuous mode, set the allframes bit. */ 994 if (ifp->if_flags & IFF_PROMISC) 995 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 996 else 997 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 998 999 if (ifp->if_flags & IFF_ALLMULTI) 1000 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1001 else 1002 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1003 1004 if_maddr_rlock(ifp); 1005 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1006 if (ifma->ifma_addr->sa_family != AF_LINK) 1007 continue; 1008 h = dc_mchash_le(sc, 1009 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1010 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1011 } 1012 if_maddr_runlock(ifp); 1013 1014 if (ifp->if_flags & IFF_BROADCAST) { 1015 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1016 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1017 } 1018 1019 /* Set our MAC address. */ 1020 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1021 sp[39] = DC_SP_MAC(eaddr[0]); 1022 sp[40] = DC_SP_MAC(eaddr[1]); 1023 sp[41] = DC_SP_MAC(eaddr[2]); 1024 1025 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1026 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1027 BUS_DMASYNC_PREWRITE); 1028 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1029 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1030 1031 /* 1032 * The PNIC takes an exceedingly long time to process its 1033 * setup frame; wait 10ms after posting the setup frame 1034 * before proceeding, just so it has time to swallow its 1035 * medicine. 1036 */ 1037 DELAY(10000); 1038 1039 sc->dc_wdog_timer = 5; 1040} 1041 1042static void 1043dc_setfilt_admtek(struct dc_softc *sc) 1044{ 1045 uint8_t eaddr[ETHER_ADDR_LEN]; 1046 struct ifnet *ifp; 1047 struct ifmultiaddr *ifma; 1048 int h = 0; 1049 uint32_t hashes[2] = { 0, 0 }; 1050 1051 ifp = sc->dc_ifp; 1052 1053 /* Init our MAC address. */ 1054 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1055 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1056 eaddr[1] << 8 | eaddr[0]); 1057 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1058 1059 /* If we want promiscuous mode, set the allframes bit. */ 1060 if (ifp->if_flags & IFF_PROMISC) 1061 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1062 else 1063 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1064 1065 if (ifp->if_flags & IFF_ALLMULTI) 1066 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1067 else 1068 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1069 1070 /* First, zot all the existing hash bits. */ 1071 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1072 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1073 1074 /* 1075 * If we're already in promisc or allmulti mode, we 1076 * don't have to bother programming the multicast filter. 1077 */ 1078 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1079 return; 1080 1081 /* Now program new ones. */ 1082 if_maddr_rlock(ifp); 1083 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1084 if (ifma->ifma_addr->sa_family != AF_LINK) 1085 continue; 1086 if (DC_IS_CENTAUR(sc)) 1087 h = dc_mchash_le(sc, 1088 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1089 else 1090 h = dc_mchash_be( 1091 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1092 if (h < 32) 1093 hashes[0] |= (1 << h); 1094 else 1095 hashes[1] |= (1 << (h - 32)); 1096 } 1097 if_maddr_runlock(ifp); 1098 1099 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1100 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1101} 1102 1103static void 1104dc_setfilt_asix(struct dc_softc *sc) 1105{ 1106 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1107 struct ifnet *ifp; 1108 struct ifmultiaddr *ifma; 1109 int h = 0; 1110 uint32_t hashes[2] = { 0, 0 }; 1111 1112 ifp = sc->dc_ifp; 1113 1114 /* Init our MAC address. */ 1115 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1116 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1117 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1118 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1119 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1120 1121 /* If we want promiscuous mode, set the allframes bit. */ 1122 if (ifp->if_flags & IFF_PROMISC) 1123 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1124 else 1125 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1126 1127 if (ifp->if_flags & IFF_ALLMULTI) 1128 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1129 else 1130 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1131 1132 /* 1133 * The ASIX chip has a special bit to enable reception 1134 * of broadcast frames. 1135 */ 1136 if (ifp->if_flags & IFF_BROADCAST) 1137 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1138 else 1139 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1140 1141 /* first, zot all the existing hash bits */ 1142 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1143 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1144 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1145 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1146 1147 /* 1148 * If we're already in promisc or allmulti mode, we 1149 * don't have to bother programming the multicast filter. 1150 */ 1151 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1152 return; 1153 1154 /* now program new ones */ 1155 if_maddr_rlock(ifp); 1156 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1157 if (ifma->ifma_addr->sa_family != AF_LINK) 1158 continue; 1159 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1160 if (h < 32) 1161 hashes[0] |= (1 << h); 1162 else 1163 hashes[1] |= (1 << (h - 32)); 1164 } 1165 if_maddr_runlock(ifp); 1166 1167 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1168 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1169 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1170 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1171} 1172 1173static void 1174dc_setfilt_uli(struct dc_softc *sc) 1175{ 1176 uint8_t eaddr[ETHER_ADDR_LEN]; 1177 struct ifnet *ifp; 1178 struct ifmultiaddr *ifma; 1179 struct dc_desc *sframe; 1180 uint32_t filter, *sp; 1181 uint8_t *ma; 1182 int i, mcnt; 1183 1184 ifp = sc->dc_ifp; 1185 1186 i = sc->dc_cdata.dc_tx_prod; 1187 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1188 sc->dc_cdata.dc_tx_cnt++; 1189 sframe = &sc->dc_ldata.dc_tx_list[i]; 1190 sp = sc->dc_cdata.dc_sbuf; 1191 bzero(sp, DC_SFRAME_LEN); 1192 1193 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1194 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1195 DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT); 1196 1197 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1198 1199 /* Set station address. */ 1200 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1201 *sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]); 1202 *sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]); 1203 *sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]); 1204 1205 /* Set broadcast address. */ 1206 *sp++ = DC_SP_MAC(0xFFFF); 1207 *sp++ = DC_SP_MAC(0xFFFF); 1208 *sp++ = DC_SP_MAC(0xFFFF); 1209 1210 /* Extract current filter configuration. */ 1211 filter = CSR_READ_4(sc, DC_NETCFG); 1212 filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI); 1213 1214 /* Now build perfect filters. */ 1215 mcnt = 0; 1216 if_maddr_rlock(ifp); 1217 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1218 if (ifma->ifma_addr->sa_family != AF_LINK) 1219 continue; 1220 if (mcnt >= DC_ULI_FILTER_NPERF) { 1221 filter |= DC_NETCFG_RX_ALLMULTI; 1222 break; 1223 } 1224 ma = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1225 *sp++ = DC_SP_MAC(ma[1] << 8 | ma[0]); 1226 *sp++ = DC_SP_MAC(ma[3] << 8 | ma[2]); 1227 *sp++ = DC_SP_MAC(ma[5] << 8 | ma[4]); 1228 mcnt++; 1229 } 1230 if_maddr_runlock(ifp); 1231 1232 for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) { 1233 *sp++ = DC_SP_MAC(0xFFFF); 1234 *sp++ = DC_SP_MAC(0xFFFF); 1235 *sp++ = DC_SP_MAC(0xFFFF); 1236 } 1237 1238 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1239 CSR_WRITE_4(sc, DC_NETCFG, 1240 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1241 if (ifp->if_flags & IFF_PROMISC) 1242 filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI; 1243 if (ifp->if_flags & IFF_ALLMULTI) 1244 filter |= DC_NETCFG_RX_ALLMULTI; 1245 CSR_WRITE_4(sc, DC_NETCFG, 1246 filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1247 if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) 1248 CSR_WRITE_4(sc, DC_NETCFG, filter); 1249 1250 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1251 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1252 BUS_DMASYNC_PREWRITE); 1253 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1254 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1255 1256 /* 1257 * Wait some time... 1258 */ 1259 DELAY(1000); 1260 1261 sc->dc_wdog_timer = 5; 1262} 1263 1264static void 1265dc_setfilt_xircom(struct dc_softc *sc) 1266{ 1267 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1268 struct ifnet *ifp; 1269 struct ifmultiaddr *ifma; 1270 struct dc_desc *sframe; 1271 uint32_t h, *sp; 1272 int i; 1273 1274 ifp = sc->dc_ifp; 1275 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1276 1277 i = sc->dc_cdata.dc_tx_prod; 1278 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1279 sc->dc_cdata.dc_tx_cnt++; 1280 sframe = &sc->dc_ldata.dc_tx_list[i]; 1281 sp = sc->dc_cdata.dc_sbuf; 1282 bzero(sp, DC_SFRAME_LEN); 1283 1284 sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr)); 1285 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1286 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1287 1288 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1289 1290 /* If we want promiscuous mode, set the allframes bit. */ 1291 if (ifp->if_flags & IFF_PROMISC) 1292 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1293 else 1294 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1295 1296 if (ifp->if_flags & IFF_ALLMULTI) 1297 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1298 else 1299 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1300 1301 if_maddr_rlock(ifp); 1302 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1303 if (ifma->ifma_addr->sa_family != AF_LINK) 1304 continue; 1305 h = dc_mchash_le(sc, 1306 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1307 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1308 } 1309 if_maddr_runlock(ifp); 1310 1311 if (ifp->if_flags & IFF_BROADCAST) { 1312 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1313 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1314 } 1315 1316 /* Set our MAC address. */ 1317 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1318 sp[0] = DC_SP_MAC(eaddr[0]); 1319 sp[1] = DC_SP_MAC(eaddr[1]); 1320 sp[2] = DC_SP_MAC(eaddr[2]); 1321 1322 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1323 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1324 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1325 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD | 1326 BUS_DMASYNC_PREWRITE); 1327 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE); 1328 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1329 1330 /* 1331 * Wait some time... 1332 */ 1333 DELAY(1000); 1334 1335 sc->dc_wdog_timer = 5; 1336} 1337 1338static void 1339dc_setfilt(struct dc_softc *sc) 1340{ 1341 1342 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1343 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1344 dc_setfilt_21143(sc); 1345 1346 if (DC_IS_ASIX(sc)) 1347 dc_setfilt_asix(sc); 1348 1349 if (DC_IS_ADMTEK(sc)) 1350 dc_setfilt_admtek(sc); 1351 1352 if (DC_IS_ULI(sc)) 1353 dc_setfilt_uli(sc); 1354 1355 if (DC_IS_XIRCOM(sc)) 1356 dc_setfilt_xircom(sc); 1357} 1358 1359static void 1360dc_netcfg_wait(struct dc_softc *sc) 1361{ 1362 uint32_t isr; 1363 int i; 1364 1365 for (i = 0; i < DC_TIMEOUT; i++) { 1366 isr = CSR_READ_4(sc, DC_ISR); 1367 if (isr & DC_ISR_TX_IDLE && 1368 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1369 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1370 break; 1371 DELAY(10); 1372 } 1373 if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) { 1374 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1375 device_printf(sc->dc_dev, 1376 "%s: failed to force tx to idle state\n", __func__); 1377 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1378 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1379 !DC_HAS_BROKEN_RXSTATE(sc)) 1380 device_printf(sc->dc_dev, 1381 "%s: failed to force rx to idle state\n", __func__); 1382 } 1383} 1384 1385/* 1386 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1387 * the netconfig register, we first have to put the transmit and/or 1388 * receive logic in the idle state. 1389 */ 1390static void 1391dc_setcfg(struct dc_softc *sc, int media) 1392{ 1393 int restart = 0, watchdogreg; 1394 1395 if (IFM_SUBTYPE(media) == IFM_NONE) 1396 return; 1397 1398 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1399 restart = 1; 1400 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1401 dc_netcfg_wait(sc); 1402 } 1403 1404 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1405 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1406 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1407 if (sc->dc_pmode == DC_PMODE_MII) { 1408 if (DC_IS_INTEL(sc)) { 1409 /* There's a write enable bit here that reads as 1. */ 1410 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1411 watchdogreg &= ~DC_WDOG_CTLWREN; 1412 watchdogreg |= DC_WDOG_JABBERDIS; 1413 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1414 } else { 1415 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1416 } 1417 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1418 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1419 if (sc->dc_type == DC_TYPE_98713) 1420 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1421 DC_NETCFG_SCRAMBLER)); 1422 if (!DC_IS_DAVICOM(sc)) 1423 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1424 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1425 } else { 1426 if (DC_IS_PNIC(sc)) { 1427 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1428 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1429 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1430 } 1431 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1432 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1434 } 1435 } 1436 1437 if (IFM_SUBTYPE(media) == IFM_10_T) { 1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1439 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1440 if (sc->dc_pmode == DC_PMODE_MII) { 1441 /* There's a write enable bit here that reads as 1. */ 1442 if (DC_IS_INTEL(sc)) { 1443 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1444 watchdogreg &= ~DC_WDOG_CTLWREN; 1445 watchdogreg |= DC_WDOG_JABBERDIS; 1446 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1447 } else { 1448 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1449 } 1450 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1451 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1452 if (sc->dc_type == DC_TYPE_98713) 1453 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1454 if (!DC_IS_DAVICOM(sc)) 1455 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1456 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1457 } else { 1458 if (DC_IS_PNIC(sc)) { 1459 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1460 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1461 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1462 } 1463 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1464 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1465 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1466 if (DC_IS_INTEL(sc)) { 1467 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1468 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1469 if ((media & IFM_GMASK) == IFM_FDX) 1470 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1471 else 1472 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1473 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1474 DC_CLRBIT(sc, DC_10BTCTRL, 1475 DC_TCTL_AUTONEGENBL); 1476 DELAY(20000); 1477 } 1478 } 1479 } 1480 1481 /* 1482 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1483 * PHY and we want HomePNA mode, set the portsel bit to turn 1484 * on the external MII port. 1485 */ 1486 if (DC_IS_DAVICOM(sc)) { 1487 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1488 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1489 sc->dc_link = 1; 1490 } else { 1491 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1492 } 1493 } 1494 1495 if ((media & IFM_GMASK) == IFM_FDX) { 1496 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1497 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1498 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1499 } else { 1500 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1501 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1502 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1503 } 1504 1505 if (restart) 1506 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1507} 1508 1509static void 1510dc_reset(struct dc_softc *sc) 1511{ 1512 int i; 1513 1514 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1515 1516 for (i = 0; i < DC_TIMEOUT; i++) { 1517 DELAY(10); 1518 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1519 break; 1520 } 1521 1522 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1523 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) { 1524 DELAY(10000); 1525 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1526 i = 0; 1527 } 1528 1529 if (i == DC_TIMEOUT) 1530 device_printf(sc->dc_dev, "reset never completed!\n"); 1531 1532 /* Wait a little while for the chip to get its brains in order. */ 1533 DELAY(1000); 1534 1535 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1536 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1537 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1538 1539 /* 1540 * Bring the SIA out of reset. In some cases, it looks 1541 * like failing to unreset the SIA soon enough gets it 1542 * into a state where it will never come out of reset 1543 * until we reset the whole chip again. 1544 */ 1545 if (DC_IS_INTEL(sc)) { 1546 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1547 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF); 1548 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1549 } 1550} 1551 1552static const struct dc_type * 1553dc_devtype(device_t dev) 1554{ 1555 const struct dc_type *t; 1556 uint32_t devid; 1557 uint8_t rev; 1558 1559 t = dc_devs; 1560 devid = pci_get_devid(dev); 1561 rev = pci_get_revid(dev); 1562 1563 while (t->dc_name != NULL) { 1564 if (devid == t->dc_devid && rev >= t->dc_minrev) 1565 return (t); 1566 t++; 1567 } 1568 1569 return (NULL); 1570} 1571 1572/* 1573 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1574 * IDs against our list and return a device name if we find a match. 1575 * We do a little bit of extra work to identify the exact type of 1576 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1577 * but different revision IDs. The same is true for 98715/98715A 1578 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1579 * cases, the exact chip revision affects driver behavior. 1580 */ 1581static int 1582dc_probe(device_t dev) 1583{ 1584 const struct dc_type *t; 1585 1586 t = dc_devtype(dev); 1587 1588 if (t != NULL) { 1589 device_set_desc(dev, t->dc_name); 1590 return (BUS_PROBE_DEFAULT); 1591 } 1592 1593 return (ENXIO); 1594} 1595 1596static void 1597dc_apply_fixup(struct dc_softc *sc, int media) 1598{ 1599 struct dc_mediainfo *m; 1600 uint8_t *p; 1601 int i; 1602 uint32_t reg; 1603 1604 m = sc->dc_mi; 1605 1606 while (m != NULL) { 1607 if (m->dc_media == media) 1608 break; 1609 m = m->dc_next; 1610 } 1611 1612 if (m == NULL) 1613 return; 1614 1615 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1616 reg = (p[0] | (p[1] << 8)) << 16; 1617 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1618 } 1619 1620 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1621 reg = (p[0] | (p[1] << 8)) << 16; 1622 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1623 } 1624} 1625 1626static int 1627dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1628{ 1629 struct dc_mediainfo *m; 1630 1631 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1632 if (m == NULL) { 1633 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1634 return (ENOMEM); 1635 } 1636 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1637 case DC_SIA_CODE_10BT: 1638 m->dc_media = IFM_10_T; 1639 break; 1640 case DC_SIA_CODE_10BT_FDX: 1641 m->dc_media = IFM_10_T | IFM_FDX; 1642 break; 1643 case DC_SIA_CODE_10B2: 1644 m->dc_media = IFM_10_2; 1645 break; 1646 case DC_SIA_CODE_10B5: 1647 m->dc_media = IFM_10_5; 1648 break; 1649 default: 1650 break; 1651 } 1652 1653 /* 1654 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1655 * Things apparently already work for cards that do 1656 * supply Media Specific Data. 1657 */ 1658 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1659 m->dc_gp_len = 2; 1660 m->dc_gp_ptr = 1661 (uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1662 } else { 1663 m->dc_gp_len = 2; 1664 m->dc_gp_ptr = 1665 (uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1666 } 1667 1668 m->dc_next = sc->dc_mi; 1669 sc->dc_mi = m; 1670 1671 sc->dc_pmode = DC_PMODE_SIA; 1672 return (0); 1673} 1674 1675static int 1676dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1677{ 1678 struct dc_mediainfo *m; 1679 1680 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1681 if (m == NULL) { 1682 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1683 return (ENOMEM); 1684 } 1685 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1686 m->dc_media = IFM_100_TX; 1687 1688 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1689 m->dc_media = IFM_100_TX | IFM_FDX; 1690 1691 m->dc_gp_len = 2; 1692 m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl; 1693 1694 m->dc_next = sc->dc_mi; 1695 sc->dc_mi = m; 1696 1697 sc->dc_pmode = DC_PMODE_SYM; 1698 return (0); 1699} 1700 1701static int 1702dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1703{ 1704 struct dc_mediainfo *m; 1705 uint8_t *p; 1706 1707 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1708 if (m == NULL) { 1709 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1710 return (ENOMEM); 1711 } 1712 /* We abuse IFM_AUTO to represent MII. */ 1713 m->dc_media = IFM_AUTO; 1714 m->dc_gp_len = l->dc_gpr_len; 1715 1716 p = (uint8_t *)l; 1717 p += sizeof(struct dc_eblock_mii); 1718 m->dc_gp_ptr = p; 1719 p += 2 * l->dc_gpr_len; 1720 m->dc_reset_len = *p; 1721 p++; 1722 m->dc_reset_ptr = p; 1723 1724 m->dc_next = sc->dc_mi; 1725 sc->dc_mi = m; 1726 return (0); 1727} 1728 1729static int 1730dc_read_srom(struct dc_softc *sc, int bits) 1731{ 1732 int size; 1733 1734 size = DC_ROM_SIZE(bits); 1735 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 1736 if (sc->dc_srom == NULL) { 1737 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1738 return (ENOMEM); 1739 } 1740 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1741 return (0); 1742} 1743 1744static int 1745dc_parse_21143_srom(struct dc_softc *sc) 1746{ 1747 struct dc_leaf_hdr *lhdr; 1748 struct dc_eblock_hdr *hdr; 1749 int error, have_mii, i, loff; 1750 char *ptr; 1751 1752 have_mii = 0; 1753 loff = sc->dc_srom[27]; 1754 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1755 1756 ptr = (char *)lhdr; 1757 ptr += sizeof(struct dc_leaf_hdr) - 1; 1758 /* 1759 * Look if we got a MII media block. 1760 */ 1761 for (i = 0; i < lhdr->dc_mcnt; i++) { 1762 hdr = (struct dc_eblock_hdr *)ptr; 1763 if (hdr->dc_type == DC_EBLOCK_MII) 1764 have_mii++; 1765 1766 ptr += (hdr->dc_len & 0x7F); 1767 ptr++; 1768 } 1769 1770 /* 1771 * Do the same thing again. Only use SIA and SYM media 1772 * blocks if no MII media block is available. 1773 */ 1774 ptr = (char *)lhdr; 1775 ptr += sizeof(struct dc_leaf_hdr) - 1; 1776 error = 0; 1777 for (i = 0; i < lhdr->dc_mcnt; i++) { 1778 hdr = (struct dc_eblock_hdr *)ptr; 1779 switch (hdr->dc_type) { 1780 case DC_EBLOCK_MII: 1781 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1782 break; 1783 case DC_EBLOCK_SIA: 1784 if (! have_mii) 1785 error = dc_decode_leaf_sia(sc, 1786 (struct dc_eblock_sia *)hdr); 1787 break; 1788 case DC_EBLOCK_SYM: 1789 if (! have_mii) 1790 error = dc_decode_leaf_sym(sc, 1791 (struct dc_eblock_sym *)hdr); 1792 break; 1793 default: 1794 /* Don't care. Yet. */ 1795 break; 1796 } 1797 ptr += (hdr->dc_len & 0x7F); 1798 ptr++; 1799 } 1800 return (error); 1801} 1802 1803static void 1804dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1805{ 1806 bus_addr_t *paddr; 1807 1808 KASSERT(nseg == 1, 1809 ("%s: wrong number of segments (%d)", __func__, nseg)); 1810 paddr = arg; 1811 *paddr = segs->ds_addr; 1812} 1813 1814static int 1815dc_dma_alloc(struct dc_softc *sc) 1816{ 1817 int error, i; 1818 1819 error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0, 1820 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1821 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1822 NULL, NULL, &sc->dc_ptag); 1823 if (error) { 1824 device_printf(sc->dc_dev, 1825 "failed to allocate parent DMA tag\n"); 1826 goto fail; 1827 } 1828 1829 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1830 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1831 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1, 1832 DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag); 1833 if (error) { 1834 device_printf(sc->dc_dev, "failed to create RX list DMA tag\n"); 1835 goto fail; 1836 } 1837 1838 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1839 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1, 1840 DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag); 1841 if (error) { 1842 device_printf(sc->dc_dev, "failed to create TX list DMA tag\n"); 1843 goto fail; 1844 } 1845 1846 /* RX descriptor list. */ 1847 error = bus_dmamem_alloc(sc->dc_rx_ltag, 1848 (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT | 1849 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap); 1850 if (error) { 1851 device_printf(sc->dc_dev, 1852 "failed to allocate DMA'able memory for RX list\n"); 1853 goto fail; 1854 } 1855 error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap, 1856 sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr, 1857 &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT); 1858 if (error) { 1859 device_printf(sc->dc_dev, 1860 "failed to load DMA'able memory for RX list\n"); 1861 goto fail; 1862 } 1863 /* TX descriptor list. */ 1864 error = bus_dmamem_alloc(sc->dc_tx_ltag, 1865 (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT | 1866 BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap); 1867 if (error) { 1868 device_printf(sc->dc_dev, 1869 "failed to allocate DMA'able memory for TX list\n"); 1870 goto fail; 1871 } 1872 error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap, 1873 sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr, 1874 &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT); 1875 if (error) { 1876 device_printf(sc->dc_dev, 1877 "cannot load DMA'able memory for TX list\n"); 1878 goto fail; 1879 } 1880 1881 /* 1882 * Allocate a busdma tag and DMA safe memory for the multicast 1883 * setup frame. 1884 */ 1885 error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0, 1886 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1887 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1888 0, NULL, NULL, &sc->dc_stag); 1889 if (error) { 1890 device_printf(sc->dc_dev, 1891 "failed to create DMA tag for setup frame\n"); 1892 goto fail; 1893 } 1894 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 1895 BUS_DMA_NOWAIT, &sc->dc_smap); 1896 if (error) { 1897 device_printf(sc->dc_dev, 1898 "failed to allocate DMA'able memory for setup frame\n"); 1899 goto fail; 1900 } 1901 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 1902 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 1903 if (error) { 1904 device_printf(sc->dc_dev, 1905 "cannot load DMA'able memory for setup frame\n"); 1906 goto fail; 1907 } 1908 1909 /* Allocate a busdma tag for RX mbufs. */ 1910 error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0, 1911 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1912 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag); 1913 if (error) { 1914 device_printf(sc->dc_dev, "failed to create RX mbuf tag\n"); 1915 goto fail; 1916 } 1917 1918 /* Allocate a busdma tag for TX mbufs. */ 1919 error = bus_dma_tag_create(sc->dc_ptag, 1, 0, 1920 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1921 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 1922 0, NULL, NULL, &sc->dc_tx_mtag); 1923 if (error) { 1924 device_printf(sc->dc_dev, "failed to create TX mbuf tag\n"); 1925 goto fail; 1926 } 1927 1928 /* Create the TX/RX busdma maps. */ 1929 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1930 error = bus_dmamap_create(sc->dc_tx_mtag, 0, 1931 &sc->dc_cdata.dc_tx_map[i]); 1932 if (error) { 1933 device_printf(sc->dc_dev, 1934 "failed to create TX mbuf dmamap\n"); 1935 goto fail; 1936 } 1937 } 1938 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1939 error = bus_dmamap_create(sc->dc_rx_mtag, 0, 1940 &sc->dc_cdata.dc_rx_map[i]); 1941 if (error) { 1942 device_printf(sc->dc_dev, 1943 "failed to create RX mbuf dmamap\n"); 1944 goto fail; 1945 } 1946 } 1947 error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap); 1948 if (error) { 1949 device_printf(sc->dc_dev, 1950 "failed to create spare RX mbuf dmamap\n"); 1951 goto fail; 1952 } 1953 1954fail: 1955 return (error); 1956} 1957 1958static void 1959dc_dma_free(struct dc_softc *sc) 1960{ 1961 int i; 1962 1963 /* RX buffers. */ 1964 if (sc->dc_rx_mtag != NULL) { 1965 for (i = 0; i < DC_RX_LIST_CNT; i++) { 1966 if (sc->dc_cdata.dc_rx_map[i] != NULL) 1967 bus_dmamap_destroy(sc->dc_rx_mtag, 1968 sc->dc_cdata.dc_rx_map[i]); 1969 } 1970 if (sc->dc_sparemap != NULL) 1971 bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap); 1972 bus_dma_tag_destroy(sc->dc_rx_mtag); 1973 } 1974 1975 /* TX buffers. */ 1976 if (sc->dc_rx_mtag != NULL) { 1977 for (i = 0; i < DC_TX_LIST_CNT; i++) { 1978 if (sc->dc_cdata.dc_tx_map[i] != NULL) 1979 bus_dmamap_destroy(sc->dc_tx_mtag, 1980 sc->dc_cdata.dc_tx_map[i]); 1981 } 1982 bus_dma_tag_destroy(sc->dc_tx_mtag); 1983 } 1984 1985 /* RX descriptor list. */ 1986 if (sc->dc_rx_ltag) { 1987 if (sc->dc_rx_lmap != NULL) 1988 bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap); 1989 if (sc->dc_rx_lmap != NULL && sc->dc_ldata.dc_rx_list != NULL) 1990 bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list, 1991 sc->dc_rx_lmap); 1992 bus_dma_tag_destroy(sc->dc_rx_ltag); 1993 } 1994 1995 /* TX descriptor list. */ 1996 if (sc->dc_tx_ltag) { 1997 if (sc->dc_tx_lmap != NULL) 1998 bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap); 1999 if (sc->dc_tx_lmap != NULL && sc->dc_ldata.dc_tx_list != NULL) 2000 bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list, 2001 sc->dc_tx_lmap); 2002 bus_dma_tag_destroy(sc->dc_tx_ltag); 2003 } 2004 2005 /* multicast setup frame. */ 2006 if (sc->dc_stag) { 2007 if (sc->dc_smap != NULL) 2008 bus_dmamap_unload(sc->dc_stag, sc->dc_smap); 2009 if (sc->dc_smap != NULL && sc->dc_cdata.dc_sbuf != NULL) 2010 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, 2011 sc->dc_smap); 2012 bus_dma_tag_destroy(sc->dc_stag); 2013 } 2014} 2015 2016/* 2017 * Attach the interface. Allocate softc structures, do ifmedia 2018 * setup and ethernet/BPF attach. 2019 */ 2020static int 2021dc_attach(device_t dev) 2022{ 2023 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 2024 uint32_t command; 2025 struct dc_softc *sc; 2026 struct ifnet *ifp; 2027 struct dc_mediainfo *m; 2028 uint32_t reg, revision; 2029 uint16_t *srom; 2030 int error, mac_offset, n, phy, rid, tmp; 2031 uint8_t *mac; 2032 2033 sc = device_get_softc(dev); 2034 sc->dc_dev = dev; 2035 2036 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 2037 MTX_DEF); 2038 2039 /* 2040 * Map control/status registers. 2041 */ 2042 pci_enable_busmaster(dev); 2043 2044 rid = DC_RID; 2045 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 2046 2047 if (sc->dc_res == NULL) { 2048 device_printf(dev, "couldn't map ports/memory\n"); 2049 error = ENXIO; 2050 goto fail; 2051 } 2052 2053 sc->dc_btag = rman_get_bustag(sc->dc_res); 2054 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 2055 2056 /* Allocate interrupt. */ 2057 rid = 0; 2058 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2059 RF_SHAREABLE | RF_ACTIVE); 2060 2061 if (sc->dc_irq == NULL) { 2062 device_printf(dev, "couldn't map interrupt\n"); 2063 error = ENXIO; 2064 goto fail; 2065 } 2066 2067 /* Need this info to decide on a chip type. */ 2068 sc->dc_info = dc_devtype(dev); 2069 revision = pci_get_revid(dev); 2070 2071 error = 0; 2072 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 2073 if (sc->dc_info->dc_devid != 2074 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 2075 sc->dc_info->dc_devid != 2076 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 2077 dc_eeprom_width(sc); 2078 2079 switch (sc->dc_info->dc_devid) { 2080 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 2081 sc->dc_type = DC_TYPE_21143; 2082 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2083 sc->dc_flags |= DC_REDUCED_MII_POLL; 2084 /* Save EEPROM contents so we can parse them later. */ 2085 error = dc_read_srom(sc, sc->dc_romwidth); 2086 if (error != 0) 2087 goto fail; 2088 break; 2089 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 2090 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 2091 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 2092 sc->dc_type = DC_TYPE_DM9102; 2093 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 2094 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 2095 sc->dc_flags |= DC_TX_ALIGN; 2096 sc->dc_pmode = DC_PMODE_MII; 2097 2098 /* Increase the latency timer value. */ 2099 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 2100 break; 2101 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 2102 sc->dc_type = DC_TYPE_AL981; 2103 sc->dc_flags |= DC_TX_USE_TX_INTR; 2104 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2105 sc->dc_pmode = DC_PMODE_MII; 2106 error = dc_read_srom(sc, sc->dc_romwidth); 2107 if (error != 0) 2108 goto fail; 2109 break; 2110 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 2111 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 2112 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 2113 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 2114 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 2115 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 2116 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 2117 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 2118 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 2119 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 2120 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 2121 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 2122 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 2123 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 2124 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 2125 sc->dc_type = DC_TYPE_AN983; 2126 sc->dc_flags |= DC_64BIT_HASH; 2127 sc->dc_flags |= DC_TX_USE_TX_INTR; 2128 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2129 sc->dc_pmode = DC_PMODE_MII; 2130 /* Don't read SROM for - auto-loaded on reset */ 2131 break; 2132 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 2133 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 2134 if (revision < DC_REVISION_98713A) { 2135 sc->dc_type = DC_TYPE_98713; 2136 } 2137 if (revision >= DC_REVISION_98713A) { 2138 sc->dc_type = DC_TYPE_98713A; 2139 sc->dc_flags |= DC_21143_NWAY; 2140 } 2141 sc->dc_flags |= DC_REDUCED_MII_POLL; 2142 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2143 break; 2144 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 2145 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 2146 /* 2147 * Macronix MX98715AEC-C/D/E parts have only a 2148 * 128-bit hash table. We need to deal with these 2149 * in the same manner as the PNIC II so that we 2150 * get the right number of bits out of the 2151 * CRC routine. 2152 */ 2153 if (revision >= DC_REVISION_98715AEC_C && 2154 revision < DC_REVISION_98725) 2155 sc->dc_flags |= DC_128BIT_HASH; 2156 sc->dc_type = DC_TYPE_987x5; 2157 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2158 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2159 break; 2160 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 2161 sc->dc_type = DC_TYPE_987x5; 2162 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2163 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2164 break; 2165 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 2166 sc->dc_type = DC_TYPE_PNICII; 2167 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2168 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2169 break; 2170 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 2171 sc->dc_type = DC_TYPE_PNIC; 2172 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2173 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2174 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2175 if (sc->dc_pnic_rx_buf == NULL) { 2176 device_printf(sc->dc_dev, 2177 "Could not allocate PNIC RX buffer\n"); 2178 error = ENOMEM; 2179 goto fail; 2180 } 2181 if (revision < DC_REVISION_82C169) 2182 sc->dc_pmode = DC_PMODE_SYM; 2183 break; 2184 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 2185 sc->dc_type = DC_TYPE_ASIX; 2186 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2187 sc->dc_flags |= DC_REDUCED_MII_POLL; 2188 sc->dc_pmode = DC_PMODE_MII; 2189 break; 2190 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 2191 sc->dc_type = DC_TYPE_XIRCOM; 2192 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2193 DC_TX_ALIGN; 2194 /* 2195 * We don't actually need to coalesce, but we're doing 2196 * it to obtain a double word aligned buffer. 2197 * The DC_TX_COALESCE flag is required. 2198 */ 2199 sc->dc_pmode = DC_PMODE_MII; 2200 break; 2201 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 2202 sc->dc_type = DC_TYPE_CONEXANT; 2203 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2204 sc->dc_flags |= DC_REDUCED_MII_POLL; 2205 sc->dc_pmode = DC_PMODE_MII; 2206 error = dc_read_srom(sc, sc->dc_romwidth); 2207 if (error != 0) 2208 goto fail; 2209 break; 2210 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261): 2211 case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263): 2212 if (sc->dc_info->dc_devid == 2213 DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261)) 2214 sc->dc_type = DC_TYPE_ULI_M5261; 2215 else 2216 sc->dc_type = DC_TYPE_ULI_M5263; 2217 /* TX buffers should be aligned on 4 byte boundary. */ 2218 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2219 DC_TX_ALIGN; 2220 sc->dc_pmode = DC_PMODE_MII; 2221 error = dc_read_srom(sc, sc->dc_romwidth); 2222 if (error != 0) 2223 goto fail; 2224 break; 2225 default: 2226 device_printf(dev, "unknown device: %x\n", 2227 sc->dc_info->dc_devid); 2228 break; 2229 } 2230 2231 /* Save the cache line size. */ 2232 if (DC_IS_DAVICOM(sc)) 2233 sc->dc_cachesize = 0; 2234 else 2235 sc->dc_cachesize = pci_get_cachelnsz(dev); 2236 2237 /* Reset the adapter. */ 2238 dc_reset(sc); 2239 2240 /* Take 21143 out of snooze mode */ 2241 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2242 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2243 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2244 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2245 } 2246 2247 /* 2248 * Try to learn something about the supported media. 2249 * We know that ASIX and ADMtek and Davicom devices 2250 * will *always* be using MII media, so that's a no-brainer. 2251 * The tricky ones are the Macronix/PNIC II and the 2252 * Intel 21143. 2253 */ 2254 if (DC_IS_INTEL(sc)) { 2255 error = dc_parse_21143_srom(sc); 2256 if (error != 0) 2257 goto fail; 2258 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2259 if (sc->dc_type == DC_TYPE_98713) 2260 sc->dc_pmode = DC_PMODE_MII; 2261 else 2262 sc->dc_pmode = DC_PMODE_SYM; 2263 } else if (!sc->dc_pmode) 2264 sc->dc_pmode = DC_PMODE_MII; 2265 2266 /* 2267 * Get station address from the EEPROM. 2268 */ 2269 switch(sc->dc_type) { 2270 case DC_TYPE_98713: 2271 case DC_TYPE_98713A: 2272 case DC_TYPE_987x5: 2273 case DC_TYPE_PNICII: 2274 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2275 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2276 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2277 break; 2278 case DC_TYPE_PNIC: 2279 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2280 break; 2281 case DC_TYPE_DM9102: 2282 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2283#ifdef __sparc64__ 2284 /* 2285 * If this is an onboard dc(4) the station address read from 2286 * the EEPROM is all zero and we have to get it from the FCode. 2287 */ 2288 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2289 OF_getetheraddr(dev, (caddr_t)&eaddr); 2290#endif 2291 break; 2292 case DC_TYPE_21143: 2293 case DC_TYPE_ASIX: 2294 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2295 break; 2296 case DC_TYPE_AL981: 2297 case DC_TYPE_AN983: 2298 reg = CSR_READ_4(sc, DC_AL_PAR0); 2299 mac = (uint8_t *)&eaddr[0]; 2300 mac[0] = (reg >> 0) & 0xff; 2301 mac[1] = (reg >> 8) & 0xff; 2302 mac[2] = (reg >> 16) & 0xff; 2303 mac[3] = (reg >> 24) & 0xff; 2304 reg = CSR_READ_4(sc, DC_AL_PAR1); 2305 mac[4] = (reg >> 0) & 0xff; 2306 mac[5] = (reg >> 8) & 0xff; 2307 break; 2308 case DC_TYPE_CONEXANT: 2309 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2310 ETHER_ADDR_LEN); 2311 break; 2312 case DC_TYPE_XIRCOM: 2313 /* The MAC comes from the CIS. */ 2314 mac = pci_get_ether(dev); 2315 if (!mac) { 2316 device_printf(dev, "No station address in CIS!\n"); 2317 error = ENXIO; 2318 goto fail; 2319 } 2320 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2321 break; 2322 case DC_TYPE_ULI_M5261: 2323 case DC_TYPE_ULI_M5263: 2324 srom = (uint16_t *)sc->dc_srom; 2325 if (srom == NULL || *srom == 0xFFFF || *srom == 0) { 2326 /* 2327 * No valid SROM present, read station address 2328 * from ID Table. 2329 */ 2330 device_printf(dev, 2331 "Reading station address from ID Table.\n"); 2332 CSR_WRITE_4(sc, DC_BUSCTL, 0x10000); 2333 CSR_WRITE_4(sc, DC_SIARESET, 0x01C0); 2334 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2335 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010); 2336 CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000); 2337 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2338 CSR_WRITE_4(sc, DC_SIARESET, 0x01B0); 2339 mac = (uint8_t *)eaddr; 2340 for (n = 0; n < ETHER_ADDR_LEN; n++) 2341 mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL); 2342 CSR_WRITE_4(sc, DC_SIARESET, 0x0000); 2343 CSR_WRITE_4(sc, DC_BUSCTL, 0x0000); 2344 DELAY(10); 2345 } else 2346 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 2347 0); 2348 break; 2349 default: 2350 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2351 break; 2352 } 2353 2354 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 2355 /* 2356 * If we still have invalid station address, see whether we can 2357 * find station address for chip 0. Some multi-port controllers 2358 * just store station address for chip 0 if they have a shared 2359 * SROM. 2360 */ 2361 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 2362 (sc->dc_eaddr[0] == 0xffffffff && 2363 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2364 error = dc_check_multiport(sc); 2365 if (error == 0) { 2366 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2367 /* Extract media information. */ 2368 if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) { 2369 while (sc->dc_mi != NULL) { 2370 m = sc->dc_mi->dc_next; 2371 free(sc->dc_mi, M_DEVBUF); 2372 sc->dc_mi = m; 2373 } 2374 error = dc_parse_21143_srom(sc); 2375 if (error != 0) 2376 goto fail; 2377 } 2378 } else if (error == ENOMEM) 2379 goto fail; 2380 else 2381 error = 0; 2382 } 2383 2384 if ((error = dc_dma_alloc(sc)) != 0) 2385 goto fail; 2386 2387 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2388 if (ifp == NULL) { 2389 device_printf(dev, "can not if_alloc()\n"); 2390 error = ENOSPC; 2391 goto fail; 2392 } 2393 ifp->if_softc = sc; 2394 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2395 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2396 ifp->if_ioctl = dc_ioctl; 2397 ifp->if_start = dc_start; 2398 ifp->if_init = dc_init; 2399 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2400 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2401 IFQ_SET_READY(&ifp->if_snd); 2402 2403 /* 2404 * Do MII setup. If this is a 21143, check for a PHY on the 2405 * MII bus after applying any necessary fixups to twiddle the 2406 * GPIO bits. If we don't end up finding a PHY, restore the 2407 * old selection (SIA only or SIA/SYM) and attach the dcphy 2408 * driver instead. 2409 */ 2410 tmp = 0; 2411 if (DC_IS_INTEL(sc)) { 2412 dc_apply_fixup(sc, IFM_AUTO); 2413 tmp = sc->dc_pmode; 2414 sc->dc_pmode = DC_PMODE_MII; 2415 } 2416 2417 /* 2418 * Setup General Purpose port mode and data so the tulip can talk 2419 * to the MII. This needs to be done before mii_attach so that 2420 * we can actually see them. 2421 */ 2422 if (DC_IS_XIRCOM(sc)) { 2423 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2424 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2425 DELAY(10); 2426 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2427 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2428 DELAY(10); 2429 } 2430 2431 phy = MII_PHY_ANY; 2432 /* 2433 * Note: both the AL981 and AN983 have internal PHYs, however the 2434 * AL981 provides direct access to the PHY registers while the AN983 2435 * uses a serial MII interface. The AN983's MII interface is also 2436 * buggy in that you can read from any MII address (0 to 31), but 2437 * only address 1 behaves normally. To deal with both cases, we 2438 * pretend that the PHY is at MII address 1. 2439 */ 2440 if (DC_IS_ADMTEK(sc)) 2441 phy = DC_ADMTEK_PHYADDR; 2442 2443 /* 2444 * Note: the ukphy probes of the RS7112 report a PHY at MII address 2445 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 2446 * correct one. 2447 */ 2448 if (DC_IS_CONEXANT(sc)) 2449 phy = DC_CONEXANT_PHYADDR; 2450 2451 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2452 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 2453 2454 if (error && DC_IS_INTEL(sc)) { 2455 sc->dc_pmode = tmp; 2456 if (sc->dc_pmode != DC_PMODE_SIA) 2457 sc->dc_pmode = DC_PMODE_SYM; 2458 sc->dc_flags |= DC_21143_NWAY; 2459 /* 2460 * For non-MII cards, we need to have the 21143 2461 * drive the LEDs. Except there are some systems 2462 * like the NEC VersaPro NoteBook PC which have no 2463 * LEDs, and twiddling these bits has adverse effects 2464 * on them. (I.e. you suddenly can't get a link.) 2465 */ 2466 if (!(pci_get_subvendor(dev) == 0x1033 && 2467 pci_get_subdevice(dev) == 0x8028)) 2468 sc->dc_flags |= DC_TULIP_LEDS; 2469 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2470 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 2471 MII_OFFSET_ANY, 0); 2472 } 2473 2474 if (error) { 2475 device_printf(dev, "attaching PHYs failed\n"); 2476 goto fail; 2477 } 2478 2479 if (DC_IS_ADMTEK(sc)) { 2480 /* 2481 * Set automatic TX underrun recovery for the ADMtek chips 2482 */ 2483 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2484 } 2485 2486 /* 2487 * Tell the upper layer(s) we support long frames. 2488 */ 2489 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2490 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2491 ifp->if_capenable = ifp->if_capabilities; 2492#ifdef DEVICE_POLLING 2493 ifp->if_capabilities |= IFCAP_POLLING; 2494#endif 2495 2496 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2497 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2498 2499 /* 2500 * Call MI attach routine. 2501 */ 2502 ether_ifattach(ifp, (caddr_t)eaddr); 2503 2504 /* Hook interrupt last to avoid having to lock softc */ 2505 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2506 NULL, dc_intr, sc, &sc->dc_intrhand); 2507 2508 if (error) { 2509 device_printf(dev, "couldn't set up irq\n"); 2510 ether_ifdetach(ifp); 2511 goto fail; 2512 } 2513 2514fail: 2515 if (error) 2516 dc_detach(dev); 2517 return (error); 2518} 2519 2520/* 2521 * Shutdown hardware and free up resources. This can be called any 2522 * time after the mutex has been initialized. It is called in both 2523 * the error case in attach and the normal detach case so it needs 2524 * to be careful about only freeing resources that have actually been 2525 * allocated. 2526 */ 2527static int 2528dc_detach(device_t dev) 2529{ 2530 struct dc_softc *sc; 2531 struct ifnet *ifp; 2532 struct dc_mediainfo *m; 2533 2534 sc = device_get_softc(dev); 2535 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2536 2537 ifp = sc->dc_ifp; 2538 2539#ifdef DEVICE_POLLING 2540 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 2541 ether_poll_deregister(ifp); 2542#endif 2543 2544 /* These should only be active if attach succeeded */ 2545 if (device_is_attached(dev)) { 2546 DC_LOCK(sc); 2547 dc_stop(sc); 2548 DC_UNLOCK(sc); 2549 callout_drain(&sc->dc_stat_ch); 2550 callout_drain(&sc->dc_wdog_ch); 2551 ether_ifdetach(ifp); 2552 } 2553 if (sc->dc_miibus) 2554 device_delete_child(dev, sc->dc_miibus); 2555 bus_generic_detach(dev); 2556 2557 if (sc->dc_intrhand) 2558 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2559 if (sc->dc_irq) 2560 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2561 if (sc->dc_res) 2562 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2563 2564 if (ifp != NULL) 2565 if_free(ifp); 2566 2567 dc_dma_free(sc); 2568 2569 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2570 2571 while (sc->dc_mi != NULL) { 2572 m = sc->dc_mi->dc_next; 2573 free(sc->dc_mi, M_DEVBUF); 2574 sc->dc_mi = m; 2575 } 2576 free(sc->dc_srom, M_DEVBUF); 2577 2578 mtx_destroy(&sc->dc_mtx); 2579 2580 return (0); 2581} 2582 2583/* 2584 * Initialize the transmit descriptors. 2585 */ 2586static int 2587dc_list_tx_init(struct dc_softc *sc) 2588{ 2589 struct dc_chain_data *cd; 2590 struct dc_list_data *ld; 2591 int i, nexti; 2592 2593 cd = &sc->dc_cdata; 2594 ld = &sc->dc_ldata; 2595 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2596 if (i == DC_TX_LIST_CNT - 1) 2597 nexti = 0; 2598 else 2599 nexti = i + 1; 2600 ld->dc_tx_list[i].dc_status = 0; 2601 ld->dc_tx_list[i].dc_ctl = 0; 2602 ld->dc_tx_list[i].dc_data = 0; 2603 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2604 cd->dc_tx_chain[i] = NULL; 2605 } 2606 2607 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2608 cd->dc_tx_pkts = 0; 2609 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 2610 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2611 return (0); 2612} 2613 2614/* 2615 * Initialize the RX descriptors and allocate mbufs for them. Note that 2616 * we arrange the descriptors in a closed ring, so that the last descriptor 2617 * points back to the first. 2618 */ 2619static int 2620dc_list_rx_init(struct dc_softc *sc) 2621{ 2622 struct dc_chain_data *cd; 2623 struct dc_list_data *ld; 2624 int i, nexti; 2625 2626 cd = &sc->dc_cdata; 2627 ld = &sc->dc_ldata; 2628 2629 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2630 if (dc_newbuf(sc, i) != 0) 2631 return (ENOBUFS); 2632 if (i == DC_RX_LIST_CNT - 1) 2633 nexti = 0; 2634 else 2635 nexti = i + 1; 2636 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2637 } 2638 2639 cd->dc_rx_prod = 0; 2640 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2641 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2642 return (0); 2643} 2644 2645/* 2646 * Initialize an RX descriptor and attach an MBUF cluster. 2647 */ 2648static int 2649dc_newbuf(struct dc_softc *sc, int i) 2650{ 2651 struct mbuf *m; 2652 bus_dmamap_t map; 2653 bus_dma_segment_t segs[1]; 2654 int error, nseg; 2655 2656 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2657 if (m == NULL) 2658 return (ENOBUFS); 2659 m->m_len = m->m_pkthdr.len = MCLBYTES; 2660 m_adj(m, sizeof(u_int64_t)); 2661 2662 /* 2663 * If this is a PNIC chip, zero the buffer. This is part 2664 * of the workaround for the receive bug in the 82c168 and 2665 * 82c169 chips. 2666 */ 2667 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2668 bzero(mtod(m, char *), m->m_len); 2669 2670 error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap, 2671 m, segs, &nseg, 0); 2672 if (error) { 2673 m_freem(m); 2674 return (error); 2675 } 2676 KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__, 2677 nseg)); 2678 if (sc->dc_cdata.dc_rx_chain[i] != NULL) 2679 bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]); 2680 2681 map = sc->dc_cdata.dc_rx_map[i]; 2682 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2683 sc->dc_sparemap = map; 2684 sc->dc_cdata.dc_rx_chain[i] = m; 2685 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2686 BUS_DMASYNC_PREREAD); 2687 2688 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2689 sc->dc_ldata.dc_rx_list[i].dc_data = 2690 htole32(DC_ADDR_LO(segs[0].ds_addr)); 2691 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2692 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 2693 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2694 return (0); 2695} 2696 2697/* 2698 * Grrrrr. 2699 * The PNIC chip has a terrible bug in it that manifests itself during 2700 * periods of heavy activity. The exact mode of failure if difficult to 2701 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2702 * will happen on slow machines. The bug is that sometimes instead of 2703 * uploading one complete frame during reception, it uploads what looks 2704 * like the entire contents of its FIFO memory. The frame we want is at 2705 * the end of the whole mess, but we never know exactly how much data has 2706 * been uploaded, so salvaging the frame is hard. 2707 * 2708 * There is only one way to do it reliably, and it's disgusting. 2709 * Here's what we know: 2710 * 2711 * - We know there will always be somewhere between one and three extra 2712 * descriptors uploaded. 2713 * 2714 * - We know the desired received frame will always be at the end of the 2715 * total data upload. 2716 * 2717 * - We know the size of the desired received frame because it will be 2718 * provided in the length field of the status word in the last descriptor. 2719 * 2720 * Here's what we do: 2721 * 2722 * - When we allocate buffers for the receive ring, we bzero() them. 2723 * This means that we know that the buffer contents should be all 2724 * zeros, except for data uploaded by the chip. 2725 * 2726 * - We also force the PNIC chip to upload frames that include the 2727 * ethernet CRC at the end. 2728 * 2729 * - We gather all of the bogus frame data into a single buffer. 2730 * 2731 * - We then position a pointer at the end of this buffer and scan 2732 * backwards until we encounter the first non-zero byte of data. 2733 * This is the end of the received frame. We know we will encounter 2734 * some data at the end of the frame because the CRC will always be 2735 * there, so even if the sender transmits a packet of all zeros, 2736 * we won't be fooled. 2737 * 2738 * - We know the size of the actual received frame, so we subtract 2739 * that value from the current pointer location. This brings us 2740 * to the start of the actual received packet. 2741 * 2742 * - We copy this into an mbuf and pass it on, along with the actual 2743 * frame length. 2744 * 2745 * The performance hit is tremendous, but it beats dropping frames all 2746 * the time. 2747 */ 2748 2749#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2750static void 2751dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2752{ 2753 struct dc_desc *cur_rx; 2754 struct dc_desc *c = NULL; 2755 struct mbuf *m = NULL; 2756 unsigned char *ptr; 2757 int i, total_len; 2758 uint32_t rxstat = 0; 2759 2760 i = sc->dc_pnic_rx_bug_save; 2761 cur_rx = &sc->dc_ldata.dc_rx_list[idx]; 2762 ptr = sc->dc_pnic_rx_buf; 2763 bzero(ptr, DC_RXLEN * 5); 2764 2765 /* Copy all the bytes from the bogus buffers. */ 2766 while (1) { 2767 c = &sc->dc_ldata.dc_rx_list[i]; 2768 rxstat = le32toh(c->dc_status); 2769 m = sc->dc_cdata.dc_rx_chain[i]; 2770 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2771 ptr += DC_RXLEN; 2772 /* If this is the last buffer, break out. */ 2773 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2774 break; 2775 dc_discard_rxbuf(sc, i); 2776 DC_INC(i, DC_RX_LIST_CNT); 2777 } 2778 2779 /* Find the length of the actual receive frame. */ 2780 total_len = DC_RXBYTES(rxstat); 2781 2782 /* Scan backwards until we hit a non-zero byte. */ 2783 while (*ptr == 0x00) 2784 ptr--; 2785 2786 /* Round off. */ 2787 if ((uintptr_t)(ptr) & 0x3) 2788 ptr -= 1; 2789 2790 /* Now find the start of the frame. */ 2791 ptr -= total_len; 2792 if (ptr < sc->dc_pnic_rx_buf) 2793 ptr = sc->dc_pnic_rx_buf; 2794 2795 /* 2796 * Now copy the salvaged frame to the last mbuf and fake up 2797 * the status word to make it look like a successful 2798 * frame reception. 2799 */ 2800 bcopy(ptr, mtod(m, char *), total_len); 2801 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2802} 2803 2804/* 2805 * This routine searches the RX ring for dirty descriptors in the 2806 * event that the rxeof routine falls out of sync with the chip's 2807 * current descriptor pointer. This may happen sometimes as a result 2808 * of a "no RX buffer available" condition that happens when the chip 2809 * consumes all of the RX buffers before the driver has a chance to 2810 * process the RX ring. This routine may need to be called more than 2811 * once to bring the driver back in sync with the chip, however we 2812 * should still be getting RX DONE interrupts to drive the search 2813 * for new packets in the RX ring, so we should catch up eventually. 2814 */ 2815static int 2816dc_rx_resync(struct dc_softc *sc) 2817{ 2818 struct dc_desc *cur_rx; 2819 int i, pos; 2820 2821 pos = sc->dc_cdata.dc_rx_prod; 2822 2823 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2824 cur_rx = &sc->dc_ldata.dc_rx_list[pos]; 2825 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2826 break; 2827 DC_INC(pos, DC_RX_LIST_CNT); 2828 } 2829 2830 /* If the ring really is empty, then just return. */ 2831 if (i == DC_RX_LIST_CNT) 2832 return (0); 2833 2834 /* We've fallen behing the chip: catch it. */ 2835 sc->dc_cdata.dc_rx_prod = pos; 2836 2837 return (EAGAIN); 2838} 2839 2840static void 2841dc_discard_rxbuf(struct dc_softc *sc, int i) 2842{ 2843 struct mbuf *m; 2844 2845 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2846 m = sc->dc_cdata.dc_rx_chain[i]; 2847 bzero(mtod(m, char *), m->m_len); 2848 } 2849 2850 sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2851 sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2852 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD | 2853 BUS_DMASYNC_PREWRITE); 2854} 2855 2856/* 2857 * A frame has been uploaded: pass the resulting mbuf chain up to 2858 * the higher level protocols. 2859 */ 2860static int 2861dc_rxeof(struct dc_softc *sc) 2862{ 2863 struct mbuf *m; 2864 struct ifnet *ifp; 2865 struct dc_desc *cur_rx; 2866 int i, total_len, rx_npkts; 2867 uint32_t rxstat; 2868 2869 DC_LOCK_ASSERT(sc); 2870 2871 ifp = sc->dc_ifp; 2872 rx_npkts = 0; 2873 2874 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD | 2875 BUS_DMASYNC_POSTWRITE); 2876 for (i = sc->dc_cdata.dc_rx_prod; 2877 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2878 DC_INC(i, DC_RX_LIST_CNT)) { 2879#ifdef DEVICE_POLLING 2880 if (ifp->if_capenable & IFCAP_POLLING) { 2881 if (sc->rxcycles <= 0) 2882 break; 2883 sc->rxcycles--; 2884 } 2885#endif 2886 cur_rx = &sc->dc_ldata.dc_rx_list[i]; 2887 rxstat = le32toh(cur_rx->dc_status); 2888 if ((rxstat & DC_RXSTAT_OWN) != 0) 2889 break; 2890 m = sc->dc_cdata.dc_rx_chain[i]; 2891 bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i], 2892 BUS_DMASYNC_POSTREAD); 2893 total_len = DC_RXBYTES(rxstat); 2894 rx_npkts++; 2895 2896 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2897 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2898 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2899 sc->dc_pnic_rx_bug_save = i; 2900 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) 2901 continue; 2902 dc_pnic_rx_bug_war(sc, i); 2903 rxstat = le32toh(cur_rx->dc_status); 2904 total_len = DC_RXBYTES(rxstat); 2905 } 2906 } 2907 2908 /* 2909 * If an error occurs, update stats, clear the 2910 * status word and leave the mbuf cluster in place: 2911 * it should simply get re-used next time this descriptor 2912 * comes up in the ring. However, don't report long 2913 * frames as errors since they could be vlans. 2914 */ 2915 if ((rxstat & DC_RXSTAT_RXERR)) { 2916 if (!(rxstat & DC_RXSTAT_GIANT) || 2917 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2918 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2919 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2920 ifp->if_ierrors++; 2921 if (rxstat & DC_RXSTAT_COLLSEEN) 2922 ifp->if_collisions++; 2923 dc_discard_rxbuf(sc, i); 2924 if (rxstat & DC_RXSTAT_CRCERR) 2925 continue; 2926 else { 2927 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2928 dc_init_locked(sc); 2929 return (rx_npkts); 2930 } 2931 } 2932 } 2933 2934 /* No errors; receive the packet. */ 2935 total_len -= ETHER_CRC_LEN; 2936#ifdef __NO_STRICT_ALIGNMENT 2937 /* 2938 * On architectures without alignment problems we try to 2939 * allocate a new buffer for the receive ring, and pass up 2940 * the one where the packet is already, saving the expensive 2941 * copy done in m_devget(). 2942 * If we are on an architecture with alignment problems, or 2943 * if the allocation fails, then use m_devget and leave the 2944 * existing buffer in the receive ring. 2945 */ 2946 if (dc_newbuf(sc, i) != 0) { 2947 dc_discard_rxbuf(sc, i); 2948 ifp->if_iqdrops++; 2949 continue; 2950 } 2951 m->m_pkthdr.rcvif = ifp; 2952 m->m_pkthdr.len = m->m_len = total_len; 2953#else 2954 { 2955 struct mbuf *m0; 2956 2957 m0 = m_devget(mtod(m, char *), total_len, 2958 ETHER_ALIGN, ifp, NULL); 2959 dc_discard_rxbuf(sc, i); 2960 if (m0 == NULL) { 2961 ifp->if_iqdrops++; 2962 continue; 2963 } 2964 m = m0; 2965 } 2966#endif 2967 2968 ifp->if_ipackets++; 2969 DC_UNLOCK(sc); 2970 (*ifp->if_input)(ifp, m); 2971 DC_LOCK(sc); 2972 } 2973 2974 sc->dc_cdata.dc_rx_prod = i; 2975 return (rx_npkts); 2976} 2977 2978/* 2979 * A frame was downloaded to the chip. It's safe for us to clean up 2980 * the list buffers. 2981 */ 2982static void 2983dc_txeof(struct dc_softc *sc) 2984{ 2985 struct dc_desc *cur_tx; 2986 struct ifnet *ifp; 2987 int idx, setup; 2988 uint32_t ctl, txstat; 2989 2990 if (sc->dc_cdata.dc_tx_cnt == 0) 2991 return; 2992 2993 ifp = sc->dc_ifp; 2994 2995 /* 2996 * Go through our tx list and free mbufs for those 2997 * frames that have been transmitted. 2998 */ 2999 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD | 3000 BUS_DMASYNC_POSTWRITE); 3001 setup = 0; 3002 for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod; 3003 DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) { 3004 cur_tx = &sc->dc_ldata.dc_tx_list[idx]; 3005 txstat = le32toh(cur_tx->dc_status); 3006 ctl = le32toh(cur_tx->dc_ctl); 3007 3008 if (txstat & DC_TXSTAT_OWN) 3009 break; 3010 3011 if (sc->dc_cdata.dc_tx_chain[idx] == NULL) 3012 continue; 3013 3014 if (ctl & DC_TXCTL_SETUP) { 3015 cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP); 3016 setup++; 3017 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 3018 BUS_DMASYNC_POSTWRITE); 3019 /* 3020 * Yes, the PNIC is so brain damaged 3021 * that it will sometimes generate a TX 3022 * underrun error while DMAing the RX 3023 * filter setup frame. If we detect this, 3024 * we have to send the setup frame again, 3025 * or else the filter won't be programmed 3026 * correctly. 3027 */ 3028 if (DC_IS_PNIC(sc)) { 3029 if (txstat & DC_TXSTAT_ERRSUM) 3030 dc_setfilt(sc); 3031 } 3032 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3033 continue; 3034 } 3035 3036 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 3037 /* 3038 * XXX: Why does my Xircom taunt me so? 3039 * For some reason it likes setting the CARRLOST flag 3040 * even when the carrier is there. wtf?!? 3041 * Who knows, but Conexant chips have the 3042 * same problem. Maybe they took lessons 3043 * from Xircom. 3044 */ 3045 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3046 sc->dc_pmode == DC_PMODE_MII && 3047 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3048 DC_TXSTAT_NOCARRIER))) 3049 txstat &= ~DC_TXSTAT_ERRSUM; 3050 } else { 3051 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 3052 sc->dc_pmode == DC_PMODE_MII && 3053 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 3054 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 3055 txstat &= ~DC_TXSTAT_ERRSUM; 3056 } 3057 3058 if (txstat & DC_TXSTAT_ERRSUM) { 3059 ifp->if_oerrors++; 3060 if (txstat & DC_TXSTAT_EXCESSCOLL) 3061 ifp->if_collisions++; 3062 if (txstat & DC_TXSTAT_LATECOLL) 3063 ifp->if_collisions++; 3064 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 3065 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3066 dc_init_locked(sc); 3067 return; 3068 } 3069 } else 3070 ifp->if_opackets++; 3071 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 3072 3073 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3074 BUS_DMASYNC_POSTWRITE); 3075 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3076 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 3077 sc->dc_cdata.dc_tx_chain[idx] = NULL; 3078 } 3079 sc->dc_cdata.dc_tx_cons = idx; 3080 3081 if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3082 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3083 if (sc->dc_cdata.dc_tx_cnt == 0) 3084 sc->dc_wdog_timer = 0; 3085 } 3086 if (setup > 0) 3087 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3088 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3089} 3090 3091static void 3092dc_tick(void *xsc) 3093{ 3094 struct dc_softc *sc; 3095 struct mii_data *mii; 3096 struct ifnet *ifp; 3097 uint32_t r; 3098 3099 sc = xsc; 3100 DC_LOCK_ASSERT(sc); 3101 ifp = sc->dc_ifp; 3102 mii = device_get_softc(sc->dc_miibus); 3103 3104 /* 3105 * Reclaim transmitted frames for controllers that do 3106 * not generate TX completion interrupt for every frame. 3107 */ 3108 if (sc->dc_flags & DC_TX_USE_TX_INTR) 3109 dc_txeof(sc); 3110 3111 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 3112 if (sc->dc_flags & DC_21143_NWAY) { 3113 r = CSR_READ_4(sc, DC_10BTSTAT); 3114 if (IFM_SUBTYPE(mii->mii_media_active) == 3115 IFM_100_TX && (r & DC_TSTAT_LS100)) { 3116 sc->dc_link = 0; 3117 mii_mediachg(mii); 3118 } 3119 if (IFM_SUBTYPE(mii->mii_media_active) == 3120 IFM_10_T && (r & DC_TSTAT_LS10)) { 3121 sc->dc_link = 0; 3122 mii_mediachg(mii); 3123 } 3124 if (sc->dc_link == 0) 3125 mii_tick(mii); 3126 } else { 3127 /* 3128 * For NICs which never report DC_RXSTATE_WAIT, we 3129 * have to bite the bullet... 3130 */ 3131 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 3132 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 3133 sc->dc_cdata.dc_tx_cnt == 0) 3134 mii_tick(mii); 3135 } 3136 } else 3137 mii_tick(mii); 3138 3139 /* 3140 * When the init routine completes, we expect to be able to send 3141 * packets right away, and in fact the network code will send a 3142 * gratuitous ARP the moment the init routine marks the interface 3143 * as running. However, even though the MAC may have been initialized, 3144 * there may be a delay of a few seconds before the PHY completes 3145 * autonegotiation and the link is brought up. Any transmissions 3146 * made during that delay will be lost. Dealing with this is tricky: 3147 * we can't just pause in the init routine while waiting for the 3148 * PHY to come ready since that would bring the whole system to 3149 * a screeching halt for several seconds. 3150 * 3151 * What we do here is prevent the TX start routine from sending 3152 * any packets until a link has been established. After the 3153 * interface has been initialized, the tick routine will poll 3154 * the state of the PHY until the IFM_ACTIVE flag is set. Until 3155 * that time, packets will stay in the send queue, and once the 3156 * link comes up, they will be flushed out to the wire. 3157 */ 3158 if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3159 dc_start_locked(ifp); 3160 3161 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3162 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3163 else 3164 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3165} 3166 3167/* 3168 * A transmit underrun has occurred. Back off the transmit threshold, 3169 * or switch to store and forward mode if we have to. 3170 */ 3171static void 3172dc_tx_underrun(struct dc_softc *sc) 3173{ 3174 uint32_t netcfg, isr; 3175 int i, reinit; 3176 3177 reinit = 0; 3178 netcfg = CSR_READ_4(sc, DC_NETCFG); 3179 device_printf(sc->dc_dev, "TX underrun -- "); 3180 if ((sc->dc_flags & DC_TX_STORENFWD) == 0) { 3181 if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) { 3182 printf("using store and forward mode\n"); 3183 netcfg |= DC_NETCFG_STORENFWD; 3184 } else { 3185 printf("increasing TX threshold\n"); 3186 sc->dc_txthresh += DC_TXTHRESH_INC; 3187 netcfg &= ~DC_NETCFG_TX_THRESH; 3188 netcfg |= sc->dc_txthresh; 3189 } 3190 3191 if (DC_IS_INTEL(sc)) { 3192 /* 3193 * The real 21143 requires that the transmitter be idle 3194 * in order to change the transmit threshold or store 3195 * and forward state. 3196 */ 3197 CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON); 3198 3199 for (i = 0; i < DC_TIMEOUT; i++) { 3200 isr = CSR_READ_4(sc, DC_ISR); 3201 if (isr & DC_ISR_TX_IDLE) 3202 break; 3203 DELAY(10); 3204 } 3205 if (i == DC_TIMEOUT) { 3206 device_printf(sc->dc_dev, 3207 "%s: failed to force tx to idle state\n", 3208 __func__); 3209 reinit++; 3210 } 3211 } 3212 } else { 3213 printf("resetting\n"); 3214 reinit++; 3215 } 3216 3217 if (reinit == 0) { 3218 CSR_WRITE_4(sc, DC_NETCFG, netcfg); 3219 if (DC_IS_INTEL(sc)) 3220 CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON); 3221 } else { 3222 sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3223 dc_init_locked(sc); 3224 } 3225} 3226 3227#ifdef DEVICE_POLLING 3228static poll_handler_t dc_poll; 3229 3230static int 3231dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3232{ 3233 struct dc_softc *sc = ifp->if_softc; 3234 int rx_npkts = 0; 3235 3236 DC_LOCK(sc); 3237 3238 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3239 DC_UNLOCK(sc); 3240 return (rx_npkts); 3241 } 3242 3243 sc->rxcycles = count; 3244 rx_npkts = dc_rxeof(sc); 3245 dc_txeof(sc); 3246 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3247 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3248 dc_start_locked(ifp); 3249 3250 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3251 uint32_t status; 3252 3253 status = CSR_READ_4(sc, DC_ISR); 3254 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3255 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3256 DC_ISR_BUS_ERR); 3257 if (!status) { 3258 DC_UNLOCK(sc); 3259 return (rx_npkts); 3260 } 3261 /* ack what we have */ 3262 CSR_WRITE_4(sc, DC_ISR, status); 3263 3264 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3265 uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3266 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3267 3268 if (dc_rx_resync(sc)) 3269 dc_rxeof(sc); 3270 } 3271 /* restart transmit unit if necessary */ 3272 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3273 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3274 3275 if (status & DC_ISR_TX_UNDERRUN) 3276 dc_tx_underrun(sc); 3277 3278 if (status & DC_ISR_BUS_ERR) { 3279 if_printf(ifp, "%s: bus error\n", __func__); 3280 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3281 dc_init_locked(sc); 3282 } 3283 } 3284 DC_UNLOCK(sc); 3285 return (rx_npkts); 3286} 3287#endif /* DEVICE_POLLING */ 3288 3289static void 3290dc_intr(void *arg) 3291{ 3292 struct dc_softc *sc; 3293 struct ifnet *ifp; 3294 uint32_t r, status; 3295 int n; 3296 3297 sc = arg; 3298 3299 if (sc->suspended) 3300 return; 3301 3302 DC_LOCK(sc); 3303 status = CSR_READ_4(sc, DC_ISR); 3304 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) { 3305 DC_UNLOCK(sc); 3306 return; 3307 } 3308 ifp = sc->dc_ifp; 3309#ifdef DEVICE_POLLING 3310 if (ifp->if_capenable & IFCAP_POLLING) { 3311 DC_UNLOCK(sc); 3312 return; 3313 } 3314#endif 3315 /* Disable interrupts. */ 3316 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3317 3318 for (n = 16; n > 0; n--) { 3319 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3320 break; 3321 /* Ack interrupts. */ 3322 CSR_WRITE_4(sc, DC_ISR, status); 3323 3324 if (status & DC_ISR_RX_OK) { 3325 if (dc_rxeof(sc) == 0) { 3326 while (dc_rx_resync(sc)) 3327 dc_rxeof(sc); 3328 } 3329 } 3330 3331 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3332 dc_txeof(sc); 3333 3334 if (status & DC_ISR_TX_IDLE) { 3335 dc_txeof(sc); 3336 if (sc->dc_cdata.dc_tx_cnt) { 3337 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3338 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3339 } 3340 } 3341 3342 if (status & DC_ISR_TX_UNDERRUN) 3343 dc_tx_underrun(sc); 3344 3345 if ((status & DC_ISR_RX_WATDOGTIMEO) 3346 || (status & DC_ISR_RX_NOBUF)) { 3347 r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3348 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3349 if (dc_rxeof(sc) == 0) { 3350 while (dc_rx_resync(sc)) 3351 dc_rxeof(sc); 3352 } 3353 } 3354 3355 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3356 dc_start_locked(ifp); 3357 3358 if (status & DC_ISR_BUS_ERR) { 3359 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3360 dc_init_locked(sc); 3361 DC_UNLOCK(sc); 3362 return; 3363 } 3364 status = CSR_READ_4(sc, DC_ISR); 3365 if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) 3366 break; 3367 } 3368 3369 /* Re-enable interrupts. */ 3370 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3371 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3372 3373 DC_UNLOCK(sc); 3374} 3375 3376/* 3377 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3378 * pointers to the fragment pointers. 3379 */ 3380static int 3381dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3382{ 3383 bus_dma_segment_t segs[DC_MAXFRAGS]; 3384 bus_dmamap_t map; 3385 struct dc_desc *f; 3386 struct mbuf *m; 3387 int cur, defragged, error, first, frag, i, idx, nseg; 3388 3389 m = NULL; 3390 defragged = 0; 3391 if (sc->dc_flags & DC_TX_COALESCE && 3392 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3393 m = m_defrag(*m_head, M_DONTWAIT); 3394 defragged = 1; 3395 } else { 3396 /* 3397 * Count the number of frags in this chain to see if we 3398 * need to m_collapse. Since the descriptor list is shared 3399 * by all packets, we'll m_collapse long chains so that they 3400 * do not use up the entire list, even if they would fit. 3401 */ 3402 i = 0; 3403 for (m = *m_head; m != NULL; m = m->m_next) 3404 i++; 3405 if (i > DC_TX_LIST_CNT / 4 || 3406 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3407 DC_TX_LIST_RSVD) { 3408 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); 3409 defragged = 1; 3410 } 3411 } 3412 if (defragged != 0) { 3413 if (m == NULL) { 3414 m_freem(*m_head); 3415 *m_head = NULL; 3416 return (ENOBUFS); 3417 } 3418 *m_head = m; 3419 } 3420 3421 idx = sc->dc_cdata.dc_tx_prod; 3422 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3423 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3424 if (error == EFBIG) { 3425 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, 3426 DC_MAXFRAGS)) == NULL) { 3427 m_freem(*m_head); 3428 *m_head = NULL; 3429 return (defragged != 0 ? error : ENOBUFS); 3430 } 3431 *m_head = m; 3432 error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag, 3433 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3434 if (error != 0) { 3435 m_freem(*m_head); 3436 *m_head = NULL; 3437 return (error); 3438 } 3439 } else if (error != 0) 3440 return (error); 3441 KASSERT(nseg <= DC_MAXFRAGS, 3442 ("%s: wrong number of segments (%d)", __func__, nseg)); 3443 if (nseg == 0) { 3444 m_freem(*m_head); 3445 *m_head = NULL; 3446 return (EIO); 3447 } 3448 3449 /* Check descriptor overruns. */ 3450 if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3451 bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]); 3452 return (ENOBUFS); 3453 } 3454 bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx], 3455 BUS_DMASYNC_PREWRITE); 3456 3457 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3458 for (i = 0; i < nseg; i++) { 3459 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3460 (frag == (DC_TX_LIST_CNT - 1)) && 3461 (first != sc->dc_cdata.dc_tx_first)) { 3462 bus_dmamap_unload(sc->dc_tx_mtag, 3463 sc->dc_cdata.dc_tx_map[first]); 3464 m_freem(*m_head); 3465 *m_head = NULL; 3466 return (ENOBUFS); 3467 } 3468 3469 f = &sc->dc_ldata.dc_tx_list[frag]; 3470 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3471 if (i == 0) { 3472 f->dc_status = 0; 3473 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3474 } else 3475 f->dc_status = htole32(DC_TXSTAT_OWN); 3476 f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr)); 3477 cur = frag; 3478 DC_INC(frag, DC_TX_LIST_CNT); 3479 } 3480 3481 sc->dc_cdata.dc_tx_prod = frag; 3482 sc->dc_cdata.dc_tx_cnt += nseg; 3483 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3484 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3485 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3486 sc->dc_ldata.dc_tx_list[first].dc_ctl |= 3487 htole32(DC_TXCTL_FINT); 3488 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3489 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3490 if (sc->dc_flags & DC_TX_USE_TX_INTR && 3491 ++sc->dc_cdata.dc_tx_pkts >= 8) { 3492 sc->dc_cdata.dc_tx_pkts = 0; 3493 sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3494 } 3495 sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3496 3497 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 3498 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3499 3500 /* 3501 * Swap the last and the first dmamaps to ensure the map for 3502 * this transmission is placed at the last descriptor. 3503 */ 3504 map = sc->dc_cdata.dc_tx_map[cur]; 3505 sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first]; 3506 sc->dc_cdata.dc_tx_map[first] = map; 3507 3508 return (0); 3509} 3510 3511static void 3512dc_start(struct ifnet *ifp) 3513{ 3514 struct dc_softc *sc; 3515 3516 sc = ifp->if_softc; 3517 DC_LOCK(sc); 3518 dc_start_locked(ifp); 3519 DC_UNLOCK(sc); 3520} 3521 3522/* 3523 * Main transmit routine 3524 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3525 * regions directly in the transmit lists. We also save a copy of the 3526 * pointers since the transmit list fragment pointers are physical 3527 * addresses. 3528 */ 3529static void 3530dc_start_locked(struct ifnet *ifp) 3531{ 3532 struct dc_softc *sc; 3533 struct mbuf *m_head; 3534 int queued; 3535 3536 sc = ifp->if_softc; 3537 3538 DC_LOCK_ASSERT(sc); 3539 3540 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 3541 IFF_DRV_RUNNING || sc->dc_link == 0) 3542 return; 3543 3544 sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3545 3546 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 3547 /* 3548 * If there's no way we can send any packets, return now. 3549 */ 3550 if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) { 3551 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3552 break; 3553 } 3554 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3555 if (m_head == NULL) 3556 break; 3557 3558 if (dc_encap(sc, &m_head)) { 3559 if (m_head == NULL) 3560 break; 3561 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3562 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3563 break; 3564 } 3565 3566 queued++; 3567 /* 3568 * If there's a BPF listener, bounce a copy of this frame 3569 * to him. 3570 */ 3571 BPF_MTAP(ifp, m_head); 3572 } 3573 3574 if (queued > 0) { 3575 /* Transmit */ 3576 if (!(sc->dc_flags & DC_TX_POLL)) 3577 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3578 3579 /* 3580 * Set a timeout in case the chip goes out to lunch. 3581 */ 3582 sc->dc_wdog_timer = 5; 3583 } 3584} 3585 3586static void 3587dc_init(void *xsc) 3588{ 3589 struct dc_softc *sc = xsc; 3590 3591 DC_LOCK(sc); 3592 dc_init_locked(sc); 3593 DC_UNLOCK(sc); 3594} 3595 3596static void 3597dc_init_locked(struct dc_softc *sc) 3598{ 3599 struct ifnet *ifp = sc->dc_ifp; 3600 struct mii_data *mii; 3601 struct ifmedia *ifm; 3602 3603 DC_LOCK_ASSERT(sc); 3604 3605 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3606 return; 3607 3608 mii = device_get_softc(sc->dc_miibus); 3609 3610 /* 3611 * Cancel pending I/O and free all RX/TX buffers. 3612 */ 3613 dc_stop(sc); 3614 dc_reset(sc); 3615 if (DC_IS_INTEL(sc)) { 3616 ifm = &mii->mii_media; 3617 dc_apply_fixup(sc, ifm->ifm_media); 3618 } 3619 3620 /* 3621 * Set cache alignment and burst length. 3622 */ 3623 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc)) 3624 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3625 else 3626 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3627 /* 3628 * Evenly share the bus between receive and transmit process. 3629 */ 3630 if (DC_IS_INTEL(sc)) 3631 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3632 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3633 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3634 } else { 3635 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3636 } 3637 if (sc->dc_flags & DC_TX_POLL) 3638 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3639 switch(sc->dc_cachesize) { 3640 case 32: 3641 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3642 break; 3643 case 16: 3644 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3645 break; 3646 case 8: 3647 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3648 break; 3649 case 0: 3650 default: 3651 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3652 break; 3653 } 3654 3655 if (sc->dc_flags & DC_TX_STORENFWD) 3656 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3657 else { 3658 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3659 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3660 } else { 3661 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3662 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3663 } 3664 } 3665 3666 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3667 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3668 3669 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3670 /* 3671 * The app notes for the 98713 and 98715A say that 3672 * in order to have the chips operate properly, a magic 3673 * number must be written to CSR16. Macronix does not 3674 * document the meaning of these bits so there's no way 3675 * to know exactly what they do. The 98713 has a magic 3676 * number all its own; the rest all use a different one. 3677 */ 3678 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3679 if (sc->dc_type == DC_TYPE_98713) 3680 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3681 else 3682 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3683 } 3684 3685 if (DC_IS_XIRCOM(sc)) { 3686 /* 3687 * setup General Purpose Port mode and data so the tulip 3688 * can talk to the MII. 3689 */ 3690 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3691 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3692 DELAY(10); 3693 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3694 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3695 DELAY(10); 3696 } 3697 3698 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3699 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3700 3701 /* Init circular RX list. */ 3702 if (dc_list_rx_init(sc) == ENOBUFS) { 3703 device_printf(sc->dc_dev, 3704 "initialization failed: no memory for rx buffers\n"); 3705 dc_stop(sc); 3706 return; 3707 } 3708 3709 /* 3710 * Init TX descriptors. 3711 */ 3712 dc_list_tx_init(sc); 3713 3714 /* 3715 * Load the address of the RX list. 3716 */ 3717 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3718 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3719 3720 /* 3721 * Enable interrupts. 3722 */ 3723#ifdef DEVICE_POLLING 3724 /* 3725 * ... but only if we are not polling, and make sure they are off in 3726 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3727 * after a reset. 3728 */ 3729 if (ifp->if_capenable & IFCAP_POLLING) 3730 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3731 else 3732#endif 3733 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3734 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3735 3736 /* Initialize TX jabber and RX watchdog timer. */ 3737 if (DC_IS_ULI(sc)) 3738 CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK | 3739 DC_WDOG_HOSTUNJAB); 3740 3741 /* Enable transmitter. */ 3742 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3743 3744 /* 3745 * If this is an Intel 21143 and we're not using the 3746 * MII port, program the LED control pins so we get 3747 * link and activity indications. 3748 */ 3749 if (sc->dc_flags & DC_TULIP_LEDS) { 3750 CSR_WRITE_4(sc, DC_WATCHDOG, 3751 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3752 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3753 } 3754 3755 /* 3756 * Load the RX/multicast filter. We do this sort of late 3757 * because the filter programming scheme on the 21143 and 3758 * some clones requires DMAing a setup frame via the TX 3759 * engine, and we need the transmitter enabled for that. 3760 */ 3761 dc_setfilt(sc); 3762 3763 /* Enable receiver. */ 3764 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3765 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3766 3767 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3768 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3769 3770 dc_ifmedia_upd_locked(sc); 3771 3772 /* Clear missed frames and overflow counter. */ 3773 CSR_READ_4(sc, DC_FRAMESDISCARDED); 3774 3775 /* Don't start the ticker if this is a homePNA link. */ 3776 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3777 sc->dc_link = 1; 3778 else { 3779 if (sc->dc_flags & DC_21143_NWAY) 3780 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3781 else 3782 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3783 } 3784 3785 sc->dc_wdog_timer = 0; 3786 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3787} 3788 3789/* 3790 * Set media options. 3791 */ 3792static int 3793dc_ifmedia_upd(struct ifnet *ifp) 3794{ 3795 struct dc_softc *sc; 3796 int error; 3797 3798 sc = ifp->if_softc; 3799 DC_LOCK(sc); 3800 error = dc_ifmedia_upd_locked(sc); 3801 DC_UNLOCK(sc); 3802 return (error); 3803} 3804 3805static int 3806dc_ifmedia_upd_locked(struct dc_softc *sc) 3807{ 3808 struct mii_data *mii; 3809 struct ifmedia *ifm; 3810 int error; 3811 3812 DC_LOCK_ASSERT(sc); 3813 3814 sc->dc_link = 0; 3815 mii = device_get_softc(sc->dc_miibus); 3816 error = mii_mediachg(mii); 3817 if (error == 0) { 3818 ifm = &mii->mii_media; 3819 if (DC_IS_INTEL(sc)) 3820 dc_setcfg(sc, ifm->ifm_media); 3821 else if (DC_IS_DAVICOM(sc) && 3822 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3823 dc_setcfg(sc, ifm->ifm_media); 3824 } 3825 3826 return (error); 3827} 3828 3829/* 3830 * Report current media status. 3831 */ 3832static void 3833dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3834{ 3835 struct dc_softc *sc; 3836 struct mii_data *mii; 3837 struct ifmedia *ifm; 3838 3839 sc = ifp->if_softc; 3840 mii = device_get_softc(sc->dc_miibus); 3841 DC_LOCK(sc); 3842 mii_pollstat(mii); 3843 ifm = &mii->mii_media; 3844 if (DC_IS_DAVICOM(sc)) { 3845 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3846 ifmr->ifm_active = ifm->ifm_media; 3847 ifmr->ifm_status = 0; 3848 DC_UNLOCK(sc); 3849 return; 3850 } 3851 } 3852 ifmr->ifm_active = mii->mii_media_active; 3853 ifmr->ifm_status = mii->mii_media_status; 3854 DC_UNLOCK(sc); 3855} 3856 3857static int 3858dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3859{ 3860 struct dc_softc *sc = ifp->if_softc; 3861 struct ifreq *ifr = (struct ifreq *)data; 3862 struct mii_data *mii; 3863 int error = 0; 3864 3865 switch (command) { 3866 case SIOCSIFFLAGS: 3867 DC_LOCK(sc); 3868 if (ifp->if_flags & IFF_UP) { 3869 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3870 (IFF_PROMISC | IFF_ALLMULTI); 3871 3872 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3873 if (need_setfilt) 3874 dc_setfilt(sc); 3875 } else { 3876 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3877 dc_init_locked(sc); 3878 } 3879 } else { 3880 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3881 dc_stop(sc); 3882 } 3883 sc->dc_if_flags = ifp->if_flags; 3884 DC_UNLOCK(sc); 3885 break; 3886 case SIOCADDMULTI: 3887 case SIOCDELMULTI: 3888 DC_LOCK(sc); 3889 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3890 dc_setfilt(sc); 3891 DC_UNLOCK(sc); 3892 break; 3893 case SIOCGIFMEDIA: 3894 case SIOCSIFMEDIA: 3895 mii = device_get_softc(sc->dc_miibus); 3896 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3897 break; 3898 case SIOCSIFCAP: 3899#ifdef DEVICE_POLLING 3900 if (ifr->ifr_reqcap & IFCAP_POLLING && 3901 !(ifp->if_capenable & IFCAP_POLLING)) { 3902 error = ether_poll_register(dc_poll, ifp); 3903 if (error) 3904 return(error); 3905 DC_LOCK(sc); 3906 /* Disable interrupts */ 3907 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3908 ifp->if_capenable |= IFCAP_POLLING; 3909 DC_UNLOCK(sc); 3910 return (error); 3911 } 3912 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3913 ifp->if_capenable & IFCAP_POLLING) { 3914 error = ether_poll_deregister(ifp); 3915 /* Enable interrupts. */ 3916 DC_LOCK(sc); 3917 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3918 ifp->if_capenable &= ~IFCAP_POLLING; 3919 DC_UNLOCK(sc); 3920 return (error); 3921 } 3922#endif /* DEVICE_POLLING */ 3923 break; 3924 default: 3925 error = ether_ioctl(ifp, command, data); 3926 break; 3927 } 3928 3929 return (error); 3930} 3931 3932static void 3933dc_watchdog(void *xsc) 3934{ 3935 struct dc_softc *sc = xsc; 3936 struct ifnet *ifp; 3937 3938 DC_LOCK_ASSERT(sc); 3939 3940 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3941 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3942 return; 3943 } 3944 3945 ifp = sc->dc_ifp; 3946 ifp->if_oerrors++; 3947 device_printf(sc->dc_dev, "watchdog timeout\n"); 3948 3949 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3950 dc_init_locked(sc); 3951 3952 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3953 dc_start_locked(ifp); 3954} 3955 3956/* 3957 * Stop the adapter and free any mbufs allocated to the 3958 * RX and TX lists. 3959 */ 3960static void 3961dc_stop(struct dc_softc *sc) 3962{ 3963 struct ifnet *ifp; 3964 struct dc_list_data *ld; 3965 struct dc_chain_data *cd; 3966 int i; 3967 uint32_t ctl, netcfg; 3968 3969 DC_LOCK_ASSERT(sc); 3970 3971 ifp = sc->dc_ifp; 3972 ld = &sc->dc_ldata; 3973 cd = &sc->dc_cdata; 3974 3975 callout_stop(&sc->dc_stat_ch); 3976 callout_stop(&sc->dc_wdog_ch); 3977 sc->dc_wdog_timer = 0; 3978 sc->dc_link = 0; 3979 3980 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3981 3982 netcfg = CSR_READ_4(sc, DC_NETCFG); 3983 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3984 CSR_WRITE_4(sc, DC_NETCFG, 3985 netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3986 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3987 /* Wait the completion of TX/RX SM. */ 3988 if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)) 3989 dc_netcfg_wait(sc); 3990 3991 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3992 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3993 3994 /* 3995 * Free data in the RX lists. 3996 */ 3997 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3998 if (cd->dc_rx_chain[i] != NULL) { 3999 bus_dmamap_sync(sc->dc_rx_mtag, 4000 cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD); 4001 bus_dmamap_unload(sc->dc_rx_mtag, 4002 cd->dc_rx_map[i]); 4003 m_freem(cd->dc_rx_chain[i]); 4004 cd->dc_rx_chain[i] = NULL; 4005 } 4006 } 4007 bzero(ld->dc_rx_list, DC_RX_LIST_SZ); 4008 bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, 4009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4010 4011 /* 4012 * Free the TX list buffers. 4013 */ 4014 for (i = 0; i < DC_TX_LIST_CNT; i++) { 4015 if (cd->dc_tx_chain[i] != NULL) { 4016 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 4017 if (ctl & DC_TXCTL_SETUP) { 4018 bus_dmamap_sync(sc->dc_stag, sc->dc_smap, 4019 BUS_DMASYNC_POSTWRITE); 4020 } else { 4021 bus_dmamap_sync(sc->dc_tx_mtag, 4022 cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE); 4023 bus_dmamap_unload(sc->dc_tx_mtag, 4024 cd->dc_tx_map[i]); 4025 m_freem(cd->dc_tx_chain[i]); 4026 } 4027 cd->dc_tx_chain[i] = NULL; 4028 } 4029 } 4030 bzero(ld->dc_tx_list, DC_TX_LIST_SZ); 4031 bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, 4032 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4033} 4034 4035/* 4036 * Device suspend routine. Stop the interface and save some PCI 4037 * settings in case the BIOS doesn't restore them properly on 4038 * resume. 4039 */ 4040static int 4041dc_suspend(device_t dev) 4042{ 4043 struct dc_softc *sc; 4044 4045 sc = device_get_softc(dev); 4046 DC_LOCK(sc); 4047 dc_stop(sc); 4048 sc->suspended = 1; 4049 DC_UNLOCK(sc); 4050 4051 return (0); 4052} 4053 4054/* 4055 * Device resume routine. Restore some PCI settings in case the BIOS 4056 * doesn't, re-enable busmastering, and restart the interface if 4057 * appropriate. 4058 */ 4059static int 4060dc_resume(device_t dev) 4061{ 4062 struct dc_softc *sc; 4063 struct ifnet *ifp; 4064 4065 sc = device_get_softc(dev); 4066 ifp = sc->dc_ifp; 4067 4068 /* reinitialize interface if necessary */ 4069 DC_LOCK(sc); 4070 if (ifp->if_flags & IFF_UP) 4071 dc_init_locked(sc); 4072 4073 sc->suspended = 0; 4074 DC_UNLOCK(sc); 4075 4076 return (0); 4077} 4078 4079/* 4080 * Stop all chip I/O so that the kernel's probe routines don't 4081 * get confused by errant DMAs when rebooting. 4082 */ 4083static int 4084dc_shutdown(device_t dev) 4085{ 4086 struct dc_softc *sc; 4087 4088 sc = device_get_softc(dev); 4089 4090 DC_LOCK(sc); 4091 dc_stop(sc); 4092 DC_UNLOCK(sc); 4093 4094 return (0); 4095} 4096 4097static int 4098dc_check_multiport(struct dc_softc *sc) 4099{ 4100 struct dc_softc *dsc; 4101 devclass_t dc; 4102 device_t child; 4103 uint8_t *eaddr; 4104 int unit; 4105 4106 dc = devclass_find("dc"); 4107 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 4108 child = devclass_get_device(dc, unit); 4109 if (child == NULL) 4110 continue; 4111 if (child == sc->dc_dev) 4112 continue; 4113 if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 4114 continue; 4115 if (unit > device_get_unit(sc->dc_dev)) 4116 continue; 4117 if (device_is_attached(child) == 0) 4118 continue; 4119 dsc = device_get_softc(child); 4120 device_printf(sc->dc_dev, 4121 "Using station address of %s as base\n", 4122 device_get_nameunit(child)); 4123 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 4124 eaddr = (uint8_t *)sc->dc_eaddr; 4125 eaddr[5]++; 4126 /* Prepare SROM to parse again. */ 4127 if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL && 4128 sc->dc_romwidth != 0) { 4129 free(sc->dc_srom, M_DEVBUF); 4130 sc->dc_romwidth = dsc->dc_romwidth; 4131 sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth), 4132 M_DEVBUF, M_NOWAIT); 4133 if (sc->dc_srom == NULL) { 4134 device_printf(sc->dc_dev, 4135 "Could not allocate SROM buffer\n"); 4136 return (ENOMEM); 4137 } 4138 bcopy(dsc->dc_srom, sc->dc_srom, 4139 DC_ROM_SIZE(sc->dc_romwidth)); 4140 } 4141 return (0); 4142 } 4143 return (ENOENT); 4144} 4145