if_dc.c revision 226701
1/*-
2 * Copyright (c) 1997, 1998, 1999
3 *	Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the following acknowledgement:
15 *	This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 *    may be used to endorse or promote products derived from this software
18 *    without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/dc/if_dc.c 226701 2011-10-24 20:48:02Z yongari $");
35
36/*
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
39 *
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN983 (www.admtek.com.tw)
47 * ADMtek CardBus AN985 (www.admtek.com.tw)
48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985
49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
50 * Accton EN1217 (www.accton.com)
51 * Xircom X3201 (www.xircom.com)
52 * Abocom FE2500
53 * Conexant LANfinity (www.conexant.com)
54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com)
55 *
56 * Datasheets for the 21143 are available at developer.intel.com.
57 * Datasheets for the clone parts can be found at their respective sites.
58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
59 * The PNIC II is essentially a Macronix 98715A chip; the only difference
60 * worth noting is that its multicast hash table is only 128 bits wide
61 * instead of 512.
62 *
63 * Written by Bill Paul <wpaul@ee.columbia.edu>
64 * Electrical Engineering Department
65 * Columbia University, New York City
66 */
67/*
68 * The Intel 21143 is the successor to the DEC 21140. It is basically
69 * the same as the 21140 but with a few new features. The 21143 supports
70 * three kinds of media attachments:
71 *
72 * o MII port, for 10Mbps and 100Mbps support and NWAY
73 *   autonegotiation provided by an external PHY.
74 * o SYM port, for symbol mode 100Mbps support.
75 * o 10baseT port.
76 * o AUI/BNC port.
77 *
78 * The 100Mbps SYM port and 10baseT port can be used together in
79 * combination with the internal NWAY support to create a 10/100
80 * autosensing configuration.
81 *
82 * Note that not all tulip workalikes are handled in this driver: we only
83 * deal with those which are relatively well behaved. The Winbond is
84 * handled separately due to its different register offsets and the
85 * special handling needed for its various bugs. The PNIC is handled
86 * here, but I'm not thrilled about it.
87 *
88 * All of the workalike chips use some form of MII transceiver support
89 * with the exception of the Macronix chips, which also have a SYM port.
90 * The ASIX AX88140A is also documented to have a SYM port, but all
91 * the cards I've seen use an MII transceiver, probably because the
92 * AX88140A doesn't support internal NWAY.
93 */
94
95#ifdef HAVE_KERNEL_OPTION_HEADERS
96#include "opt_device_polling.h"
97#endif
98
99#include <sys/param.h>
100#include <sys/endian.h>
101#include <sys/systm.h>
102#include <sys/sockio.h>
103#include <sys/mbuf.h>
104#include <sys/malloc.h>
105#include <sys/kernel.h>
106#include <sys/module.h>
107#include <sys/socket.h>
108
109#include <net/if.h>
110#include <net/if_arp.h>
111#include <net/ethernet.h>
112#include <net/if_dl.h>
113#include <net/if_media.h>
114#include <net/if_types.h>
115#include <net/if_vlan_var.h>
116
117#include <net/bpf.h>
118
119#include <machine/bus.h>
120#include <machine/resource.h>
121#include <sys/bus.h>
122#include <sys/rman.h>
123
124#include <dev/mii/mii.h>
125#include <dev/mii/miivar.h>
126
127#include <dev/pci/pcireg.h>
128#include <dev/pci/pcivar.h>
129
130#define	DC_USEIOSPACE
131
132#include <dev/dc/if_dcreg.h>
133
134#ifdef __sparc64__
135#include <dev/ofw/openfirm.h>
136#include <machine/ofw_machdep.h>
137#endif
138
139MODULE_DEPEND(dc, pci, 1, 1, 1);
140MODULE_DEPEND(dc, ether, 1, 1, 1);
141MODULE_DEPEND(dc, miibus, 1, 1, 1);
142
143/*
144 * "device miibus" is required in kernel config.  See GENERIC if you get
145 * errors here.
146 */
147#include "miibus_if.h"
148
149/*
150 * Various supported device vendors/types and their names.
151 */
152static const struct dc_type dc_devs[] = {
153	{ DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0,
154		"Intel 21143 10/100BaseTX" },
155	{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0,
156		"Davicom DM9009 10/100BaseTX" },
157	{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0,
158		"Davicom DM9100 10/100BaseTX" },
159	{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A,
160		"Davicom DM9102A 10/100BaseTX" },
161	{ DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0,
162		"Davicom DM9102 10/100BaseTX" },
163	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0,
164		"ADMtek AL981 10/100BaseTX" },
165	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0,
166		"ADMtek AN983 10/100BaseTX" },
167	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0,
168		"ADMtek AN985 CardBus 10/100BaseTX or clone" },
169	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0,
170		"ADMtek ADM9511 10/100BaseTX" },
171	{ DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0,
172		"ADMtek ADM9513 10/100BaseTX" },
173	{ DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141,
174		"ASIX AX88141 10/100BaseTX" },
175	{ DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0,
176		"ASIX AX88140A 10/100BaseTX" },
177	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A,
178		"Macronix 98713A 10/100BaseTX" },
179	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0,
180		"Macronix 98713 10/100BaseTX" },
181	{ DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A,
182		"Compex RL100-TX 10/100BaseTX" },
183	{ DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0,
184		"Compex RL100-TX 10/100BaseTX" },
185	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725,
186		"Macronix 98725 10/100BaseTX" },
187	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C,
188		"Macronix 98715AEC-C 10/100BaseTX" },
189	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0,
190		"Macronix 98715/98715A 10/100BaseTX" },
191	{ DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0,
192		"Macronix 98727/98732 10/100BaseTX" },
193	{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0,
194		"LC82C115 PNIC II 10/100BaseTX" },
195	{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169,
196		"82c169 PNIC 10/100BaseTX" },
197	{ DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0,
198		"82c168 PNIC 10/100BaseTX" },
199	{ DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0,
200		"Accton EN1217 10/100BaseTX" },
201	{ DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0,
202		"Accton EN2242 MiniPCI 10/100BaseTX" },
203	{ DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0,
204		"Xircom X3201 10/100BaseTX" },
205	{ DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0,
206		"Neteasy DRP-32TXD Cardbus 10/100" },
207	{ DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0,
208		"Abocom FE2500 10/100BaseTX" },
209	{ DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0,
210		"Abocom FE2500MX 10/100BaseTX" },
211	{ DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0,
212		"Conexant LANfinity MiniPCI 10/100BaseTX" },
213	{ DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0,
214		"Hawking CB102 CardBus 10/100" },
215	{ DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0,
216		"PlaneX FNW-3602-T CardBus 10/100" },
217	{ DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0,
218		"3Com OfficeConnect 10/100B" },
219	{ DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0,
220		"Microsoft MN-120 CardBus 10/100" },
221	{ DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0,
222		"Microsoft MN-130 10/100" },
223	{ DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0,
224		"Linksys PCMPC200 CardBus 10/100" },
225	{ DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0,
226		"Linksys PCMPC200 CardBus 10/100" },
227	{ DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261), 0,
228		"ULi M5261 FastEthernet" },
229	{ DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263), 0,
230		"ULi M5263 FastEthernet" },
231	{ 0, 0, NULL }
232};
233
234static int dc_probe(device_t);
235static int dc_attach(device_t);
236static int dc_detach(device_t);
237static int dc_suspend(device_t);
238static int dc_resume(device_t);
239static const struct dc_type *dc_devtype(device_t);
240static void dc_discard_rxbuf(struct dc_softc *, int);
241static int dc_newbuf(struct dc_softc *, int);
242static int dc_encap(struct dc_softc *, struct mbuf **);
243static void dc_pnic_rx_bug_war(struct dc_softc *, int);
244static int dc_rx_resync(struct dc_softc *);
245static int dc_rxeof(struct dc_softc *);
246static void dc_txeof(struct dc_softc *);
247static void dc_tick(void *);
248static void dc_tx_underrun(struct dc_softc *);
249static void dc_intr(void *);
250static void dc_start(struct ifnet *);
251static void dc_start_locked(struct ifnet *);
252static int dc_ioctl(struct ifnet *, u_long, caddr_t);
253static void dc_init(void *);
254static void dc_init_locked(struct dc_softc *);
255static void dc_stop(struct dc_softc *);
256static void dc_watchdog(void *);
257static int dc_shutdown(device_t);
258static int dc_ifmedia_upd(struct ifnet *);
259static int dc_ifmedia_upd_locked(struct dc_softc *);
260static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *);
261
262static int dc_dma_alloc(struct dc_softc *);
263static void dc_dma_free(struct dc_softc *);
264static void dc_dma_map_addr(void *, bus_dma_segment_t *, int, int);
265
266static void dc_delay(struct dc_softc *);
267static void dc_eeprom_idle(struct dc_softc *);
268static void dc_eeprom_putbyte(struct dc_softc *, int);
269static void dc_eeprom_getword(struct dc_softc *, int, uint16_t *);
270static void dc_eeprom_getword_pnic(struct dc_softc *, int, uint16_t *);
271static void dc_eeprom_getword_xircom(struct dc_softc *, int, uint16_t *);
272static void dc_eeprom_width(struct dc_softc *);
273static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int);
274
275static void dc_mii_writebit(struct dc_softc *, int);
276static int dc_mii_readbit(struct dc_softc *);
277static void dc_mii_sync(struct dc_softc *);
278static void dc_mii_send(struct dc_softc *, uint32_t, int);
279static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *);
280static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *);
281static int dc_miibus_readreg(device_t, int, int);
282static int dc_miibus_writereg(device_t, int, int, int);
283static void dc_miibus_statchg(device_t);
284static void dc_miibus_mediainit(device_t);
285
286static void dc_setcfg(struct dc_softc *, int);
287static void dc_netcfg_wait(struct dc_softc *);
288static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *);
289static uint32_t dc_mchash_be(const uint8_t *);
290static void dc_setfilt_21143(struct dc_softc *);
291static void dc_setfilt_asix(struct dc_softc *);
292static void dc_setfilt_admtek(struct dc_softc *);
293static void dc_setfilt_uli(struct dc_softc *);
294static void dc_setfilt_xircom(struct dc_softc *);
295
296static void dc_setfilt(struct dc_softc *);
297
298static void dc_reset(struct dc_softc *);
299static int dc_list_rx_init(struct dc_softc *);
300static int dc_list_tx_init(struct dc_softc *);
301
302static int dc_read_srom(struct dc_softc *, int);
303static int dc_parse_21143_srom(struct dc_softc *);
304static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *);
305static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *);
306static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *);
307static void dc_apply_fixup(struct dc_softc *, int);
308static int dc_check_multiport(struct dc_softc *);
309
310#ifdef DC_USEIOSPACE
311#define	DC_RES			SYS_RES_IOPORT
312#define	DC_RID			DC_PCI_CFBIO
313#else
314#define	DC_RES			SYS_RES_MEMORY
315#define	DC_RID			DC_PCI_CFBMA
316#endif
317
318static device_method_t dc_methods[] = {
319	/* Device interface */
320	DEVMETHOD(device_probe,		dc_probe),
321	DEVMETHOD(device_attach,	dc_attach),
322	DEVMETHOD(device_detach,	dc_detach),
323	DEVMETHOD(device_suspend,	dc_suspend),
324	DEVMETHOD(device_resume,	dc_resume),
325	DEVMETHOD(device_shutdown,	dc_shutdown),
326
327	/* bus interface */
328	DEVMETHOD(bus_print_child,	bus_generic_print_child),
329	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
330
331	/* MII interface */
332	DEVMETHOD(miibus_readreg,	dc_miibus_readreg),
333	DEVMETHOD(miibus_writereg,	dc_miibus_writereg),
334	DEVMETHOD(miibus_statchg,	dc_miibus_statchg),
335	DEVMETHOD(miibus_mediainit,	dc_miibus_mediainit),
336
337	{ 0, 0 }
338};
339
340static driver_t dc_driver = {
341	"dc",
342	dc_methods,
343	sizeof(struct dc_softc)
344};
345
346static devclass_t dc_devclass;
347
348DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0);
349DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
350
351#define	DC_SETBIT(sc, reg, x)				\
352	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
353
354#define	DC_CLRBIT(sc, reg, x)				\
355	CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
356
357#define	SIO_SET(x)	DC_SETBIT(sc, DC_SIO, (x))
358#define	SIO_CLR(x)	DC_CLRBIT(sc, DC_SIO, (x))
359
360static void
361dc_delay(struct dc_softc *sc)
362{
363	int idx;
364
365	for (idx = (300 / 33) + 1; idx > 0; idx--)
366		CSR_READ_4(sc, DC_BUSCTL);
367}
368
369static void
370dc_eeprom_width(struct dc_softc *sc)
371{
372	int i;
373
374	/* Force EEPROM to idle state. */
375	dc_eeprom_idle(sc);
376
377	/* Enter EEPROM access mode. */
378	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
379	dc_delay(sc);
380	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
381	dc_delay(sc);
382	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
383	dc_delay(sc);
384	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
385	dc_delay(sc);
386
387	for (i = 3; i--;) {
388		if (6 & (1 << i))
389			DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
390		else
391			DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
392		dc_delay(sc);
393		DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
394		dc_delay(sc);
395		DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
396		dc_delay(sc);
397	}
398
399	for (i = 1; i <= 12; i++) {
400		DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
401		dc_delay(sc);
402		if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
403			DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
404			dc_delay(sc);
405			break;
406		}
407		DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
408		dc_delay(sc);
409	}
410
411	/* Turn off EEPROM access mode. */
412	dc_eeprom_idle(sc);
413
414	if (i < 4 || i > 12)
415		sc->dc_romwidth = 6;
416	else
417		sc->dc_romwidth = i;
418
419	/* Enter EEPROM access mode. */
420	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
421	dc_delay(sc);
422	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
423	dc_delay(sc);
424	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
425	dc_delay(sc);
426	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
427	dc_delay(sc);
428
429	/* Turn off EEPROM access mode. */
430	dc_eeprom_idle(sc);
431}
432
433static void
434dc_eeprom_idle(struct dc_softc *sc)
435{
436	int i;
437
438	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
439	dc_delay(sc);
440	DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
441	dc_delay(sc);
442	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
443	dc_delay(sc);
444	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
445	dc_delay(sc);
446
447	for (i = 0; i < 25; i++) {
448		DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
449		dc_delay(sc);
450		DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
451		dc_delay(sc);
452	}
453
454	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
455	dc_delay(sc);
456	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
457	dc_delay(sc);
458	CSR_WRITE_4(sc, DC_SIO, 0x00000000);
459}
460
461/*
462 * Send a read command and address to the EEPROM, check for ACK.
463 */
464static void
465dc_eeprom_putbyte(struct dc_softc *sc, int addr)
466{
467	int d, i;
468
469	d = DC_EECMD_READ >> 6;
470	for (i = 3; i--; ) {
471		if (d & (1 << i))
472			DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
473		else
474			DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
475		dc_delay(sc);
476		DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
477		dc_delay(sc);
478		DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
479		dc_delay(sc);
480	}
481
482	/*
483	 * Feed in each bit and strobe the clock.
484	 */
485	for (i = sc->dc_romwidth; i--;) {
486		if (addr & (1 << i)) {
487			SIO_SET(DC_SIO_EE_DATAIN);
488		} else {
489			SIO_CLR(DC_SIO_EE_DATAIN);
490		}
491		dc_delay(sc);
492		SIO_SET(DC_SIO_EE_CLK);
493		dc_delay(sc);
494		SIO_CLR(DC_SIO_EE_CLK);
495		dc_delay(sc);
496	}
497}
498
499/*
500 * Read a word of data stored in the EEPROM at address 'addr.'
501 * The PNIC 82c168/82c169 has its own non-standard way to read
502 * the EEPROM.
503 */
504static void
505dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, uint16_t *dest)
506{
507	int i;
508	uint32_t r;
509
510	CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr);
511
512	for (i = 0; i < DC_TIMEOUT; i++) {
513		DELAY(1);
514		r = CSR_READ_4(sc, DC_SIO);
515		if (!(r & DC_PN_SIOCTL_BUSY)) {
516			*dest = (uint16_t)(r & 0xFFFF);
517			return;
518		}
519	}
520}
521
522/*
523 * Read a word of data stored in the EEPROM at address 'addr.'
524 * The Xircom X3201 has its own non-standard way to read
525 * the EEPROM, too.
526 */
527static void
528dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, uint16_t *dest)
529{
530
531	SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
532
533	addr *= 2;
534	CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
535	*dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
536	addr += 1;
537	CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
538	*dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
539
540	SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ);
541}
542
543/*
544 * Read a word of data stored in the EEPROM at address 'addr.'
545 */
546static void
547dc_eeprom_getword(struct dc_softc *sc, int addr, uint16_t *dest)
548{
549	int i;
550	uint16_t word = 0;
551
552	/* Force EEPROM to idle state. */
553	dc_eeprom_idle(sc);
554
555	/* Enter EEPROM access mode. */
556	CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
557	dc_delay(sc);
558	DC_SETBIT(sc, DC_SIO,  DC_SIO_ROMCTL_READ);
559	dc_delay(sc);
560	DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
561	dc_delay(sc);
562	DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
563	dc_delay(sc);
564
565	/*
566	 * Send address of word we want to read.
567	 */
568	dc_eeprom_putbyte(sc, addr);
569
570	/*
571	 * Start reading bits from EEPROM.
572	 */
573	for (i = 0x8000; i; i >>= 1) {
574		SIO_SET(DC_SIO_EE_CLK);
575		dc_delay(sc);
576		if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
577			word |= i;
578		dc_delay(sc);
579		SIO_CLR(DC_SIO_EE_CLK);
580		dc_delay(sc);
581	}
582
583	/* Turn off EEPROM access mode. */
584	dc_eeprom_idle(sc);
585
586	*dest = word;
587}
588
589/*
590 * Read a sequence of words from the EEPROM.
591 */
592static void
593dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be)
594{
595	int i;
596	uint16_t word = 0, *ptr;
597
598	for (i = 0; i < cnt; i++) {
599		if (DC_IS_PNIC(sc))
600			dc_eeprom_getword_pnic(sc, off + i, &word);
601		else if (DC_IS_XIRCOM(sc))
602			dc_eeprom_getword_xircom(sc, off + i, &word);
603		else
604			dc_eeprom_getword(sc, off + i, &word);
605		ptr = (uint16_t *)(dest + (i * 2));
606		if (be)
607			*ptr = be16toh(word);
608		else
609			*ptr = le16toh(word);
610	}
611}
612
613/*
614 * The following two routines are taken from the Macronix 98713
615 * Application Notes pp.19-21.
616 */
617/*
618 * Write a bit to the MII bus.
619 */
620static void
621dc_mii_writebit(struct dc_softc *sc, int bit)
622{
623	uint32_t reg;
624
625	reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0);
626	CSR_WRITE_4(sc, DC_SIO, reg);
627	CSR_BARRIER_4(sc, DC_SIO,
628	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
629	DELAY(1);
630
631	CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK);
632	CSR_BARRIER_4(sc, DC_SIO,
633	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
634	DELAY(1);
635	CSR_WRITE_4(sc, DC_SIO, reg);
636	CSR_BARRIER_4(sc, DC_SIO,
637	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
638	DELAY(1);
639}
640
641/*
642 * Read a bit from the MII bus.
643 */
644static int
645dc_mii_readbit(struct dc_softc *sc)
646{
647	uint32_t reg;
648
649	reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR;
650	CSR_WRITE_4(sc, DC_SIO, reg);
651	CSR_BARRIER_4(sc, DC_SIO,
652	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
653	DELAY(1);
654	(void)CSR_READ_4(sc, DC_SIO);
655	CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK);
656	CSR_BARRIER_4(sc, DC_SIO,
657	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
658	DELAY(1);
659	CSR_WRITE_4(sc, DC_SIO, reg);
660	CSR_BARRIER_4(sc, DC_SIO,
661	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
662	DELAY(1);
663	if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
664		return (1);
665
666	return (0);
667}
668
669/*
670 * Sync the PHYs by setting data bit and strobing the clock 32 times.
671 */
672static void
673dc_mii_sync(struct dc_softc *sc)
674{
675	int i;
676
677	CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
678	CSR_BARRIER_4(sc, DC_SIO,
679	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
680	DELAY(1);
681
682	for (i = 0; i < 32; i++)
683		dc_mii_writebit(sc, 1);
684}
685
686/*
687 * Clock a series of bits through the MII.
688 */
689static void
690dc_mii_send(struct dc_softc *sc, uint32_t bits, int cnt)
691{
692	int i;
693
694	for (i = (0x1 << (cnt - 1)); i; i >>= 1)
695		dc_mii_writebit(sc, bits & i);
696}
697
698/*
699 * Read an PHY register through the MII.
700 */
701static int
702dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
703{
704	int i;
705
706	/*
707	 * Set up frame for RX.
708	 */
709	frame->mii_stdelim = DC_MII_STARTDELIM;
710	frame->mii_opcode = DC_MII_READOP;
711
712	/*
713	 * Sync the PHYs.
714	 */
715	dc_mii_sync(sc);
716
717	/*
718	 * Send command/address info.
719	 */
720	dc_mii_send(sc, frame->mii_stdelim, 2);
721	dc_mii_send(sc, frame->mii_opcode, 2);
722	dc_mii_send(sc, frame->mii_phyaddr, 5);
723	dc_mii_send(sc, frame->mii_regaddr, 5);
724
725	/*
726	 * Now try reading data bits.  If the turnaround failed, we still
727	 * need to clock through 16 cycles to keep the PHY(s) in sync.
728	 */
729	frame->mii_turnaround = dc_mii_readbit(sc);
730	if (frame->mii_turnaround != 0) {
731		for (i = 0; i < 16; i++)
732			dc_mii_readbit(sc);
733		goto fail;
734	}
735	for (i = 0x8000; i; i >>= 1) {
736		if (dc_mii_readbit(sc))
737			frame->mii_data |= i;
738	}
739
740fail:
741
742	/* Clock the idle bits. */
743	dc_mii_writebit(sc, 0);
744	dc_mii_writebit(sc, 0);
745
746	if (frame->mii_turnaround != 0)
747		return (1);
748	return (0);
749}
750
751/*
752 * Write to a PHY register through the MII.
753 */
754static int
755dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
756{
757
758	/*
759	 * Set up frame for TX.
760	 */
761	frame->mii_stdelim = DC_MII_STARTDELIM;
762	frame->mii_opcode = DC_MII_WRITEOP;
763	frame->mii_turnaround = DC_MII_TURNAROUND;
764
765	/*
766	 * Sync the PHYs.
767	 */
768	dc_mii_sync(sc);
769
770	dc_mii_send(sc, frame->mii_stdelim, 2);
771	dc_mii_send(sc, frame->mii_opcode, 2);
772	dc_mii_send(sc, frame->mii_phyaddr, 5);
773	dc_mii_send(sc, frame->mii_regaddr, 5);
774	dc_mii_send(sc, frame->mii_turnaround, 2);
775	dc_mii_send(sc, frame->mii_data, 16);
776
777	/* Clock the idle bits. */
778	dc_mii_writebit(sc, 0);
779	dc_mii_writebit(sc, 0);
780
781	return (0);
782}
783
784static int
785dc_miibus_readreg(device_t dev, int phy, int reg)
786{
787	struct dc_mii_frame frame;
788	struct dc_softc	 *sc;
789	int i, rval, phy_reg = 0;
790
791	sc = device_get_softc(dev);
792	bzero(&frame, sizeof(frame));
793
794	if (sc->dc_pmode != DC_PMODE_MII) {
795		if (phy == (MII_NPHY - 1)) {
796			switch (reg) {
797			case MII_BMSR:
798			/*
799			 * Fake something to make the probe
800			 * code think there's a PHY here.
801			 */
802				return (BMSR_MEDIAMASK);
803				break;
804			case MII_PHYIDR1:
805				if (DC_IS_PNIC(sc))
806					return (DC_VENDORID_LO);
807				return (DC_VENDORID_DEC);
808				break;
809			case MII_PHYIDR2:
810				if (DC_IS_PNIC(sc))
811					return (DC_DEVICEID_82C168);
812				return (DC_DEVICEID_21143);
813				break;
814			default:
815				return (0);
816				break;
817			}
818		} else
819			return (0);
820	}
821
822	if (DC_IS_PNIC(sc)) {
823		CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
824		    (phy << 23) | (reg << 18));
825		for (i = 0; i < DC_TIMEOUT; i++) {
826			DELAY(1);
827			rval = CSR_READ_4(sc, DC_PN_MII);
828			if (!(rval & DC_PN_MII_BUSY)) {
829				rval &= 0xFFFF;
830				return (rval == 0xFFFF ? 0 : rval);
831			}
832		}
833		return (0);
834	}
835
836	if (sc->dc_type == DC_TYPE_ULI_M5263) {
837		CSR_WRITE_4(sc, DC_ROM,
838		    ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
839		    ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |
840		    DC_ULI_PHY_OP_READ);
841		for (i = 0; i < DC_TIMEOUT; i++) {
842			DELAY(1);
843			rval = CSR_READ_4(sc, DC_ROM);
844			if ((rval & DC_ULI_PHY_OP_DONE) != 0) {
845				return (rval & DC_ULI_PHY_DATA_MASK);
846			}
847		}
848		if (i == DC_TIMEOUT)
849			device_printf(dev, "phy read timed out\n");
850		return (0);
851	}
852
853	if (DC_IS_COMET(sc)) {
854		switch (reg) {
855		case MII_BMCR:
856			phy_reg = DC_AL_BMCR;
857			break;
858		case MII_BMSR:
859			phy_reg = DC_AL_BMSR;
860			break;
861		case MII_PHYIDR1:
862			phy_reg = DC_AL_VENID;
863			break;
864		case MII_PHYIDR2:
865			phy_reg = DC_AL_DEVID;
866			break;
867		case MII_ANAR:
868			phy_reg = DC_AL_ANAR;
869			break;
870		case MII_ANLPAR:
871			phy_reg = DC_AL_LPAR;
872			break;
873		case MII_ANER:
874			phy_reg = DC_AL_ANER;
875			break;
876		default:
877			device_printf(dev, "phy_read: bad phy register %x\n",
878			    reg);
879			return (0);
880			break;
881		}
882
883		rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
884
885		if (rval == 0xFFFF)
886			return (0);
887		return (rval);
888	}
889
890	frame.mii_phyaddr = phy;
891	frame.mii_regaddr = reg;
892	if (sc->dc_type == DC_TYPE_98713) {
893		phy_reg = CSR_READ_4(sc, DC_NETCFG);
894		CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
895	}
896	dc_mii_readreg(sc, &frame);
897	if (sc->dc_type == DC_TYPE_98713)
898		CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
899
900	return (frame.mii_data);
901}
902
903static int
904dc_miibus_writereg(device_t dev, int phy, int reg, int data)
905{
906	struct dc_softc *sc;
907	struct dc_mii_frame frame;
908	int i, phy_reg = 0;
909
910	sc = device_get_softc(dev);
911	bzero(&frame, sizeof(frame));
912
913	if (DC_IS_PNIC(sc)) {
914		CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
915		    (phy << 23) | (reg << 10) | data);
916		for (i = 0; i < DC_TIMEOUT; i++) {
917			if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
918				break;
919		}
920		return (0);
921	}
922
923	if (sc->dc_type == DC_TYPE_ULI_M5263) {
924		CSR_WRITE_4(sc, DC_ROM,
925		    ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
926		    ((reg << DC_ULI_PHY_REG_SHIFT) & DC_ULI_PHY_REG_MASK) |
927		    ((data << DC_ULI_PHY_DATA_SHIFT) & DC_ULI_PHY_DATA_MASK) |
928		    DC_ULI_PHY_OP_WRITE);
929		DELAY(1);
930		return (0);
931	}
932
933	if (DC_IS_COMET(sc)) {
934		switch (reg) {
935		case MII_BMCR:
936			phy_reg = DC_AL_BMCR;
937			break;
938		case MII_BMSR:
939			phy_reg = DC_AL_BMSR;
940			break;
941		case MII_PHYIDR1:
942			phy_reg = DC_AL_VENID;
943			break;
944		case MII_PHYIDR2:
945			phy_reg = DC_AL_DEVID;
946			break;
947		case MII_ANAR:
948			phy_reg = DC_AL_ANAR;
949			break;
950		case MII_ANLPAR:
951			phy_reg = DC_AL_LPAR;
952			break;
953		case MII_ANER:
954			phy_reg = DC_AL_ANER;
955			break;
956		default:
957			device_printf(dev, "phy_write: bad phy register %x\n",
958			    reg);
959			return (0);
960			break;
961		}
962
963		CSR_WRITE_4(sc, phy_reg, data);
964		return (0);
965	}
966
967	frame.mii_phyaddr = phy;
968	frame.mii_regaddr = reg;
969	frame.mii_data = data;
970
971	if (sc->dc_type == DC_TYPE_98713) {
972		phy_reg = CSR_READ_4(sc, DC_NETCFG);
973		CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
974	}
975	dc_mii_writereg(sc, &frame);
976	if (sc->dc_type == DC_TYPE_98713)
977		CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
978
979	return (0);
980}
981
982static void
983dc_miibus_statchg(device_t dev)
984{
985	struct dc_softc *sc;
986	struct ifnet *ifp;
987	struct mii_data *mii;
988	struct ifmedia *ifm;
989
990	sc = device_get_softc(dev);
991
992	mii = device_get_softc(sc->dc_miibus);
993	ifp = sc->dc_ifp;
994	if (mii == NULL || ifp == NULL ||
995	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
996		return;
997
998	ifm = &mii->mii_media;
999	if (DC_IS_DAVICOM(sc) &&
1000	    IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
1001		dc_setcfg(sc, ifm->ifm_media);
1002		sc->dc_if_media = ifm->ifm_media;
1003		return;
1004	}
1005
1006	sc->dc_link = 0;
1007	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1008	    (IFM_ACTIVE | IFM_AVALID)) {
1009		switch (IFM_SUBTYPE(mii->mii_media_active)) {
1010		case IFM_10_T:
1011		case IFM_100_TX:
1012			sc->dc_link = 1;
1013			break;
1014		default:
1015			break;
1016		}
1017	}
1018	if (sc->dc_link == 0)
1019		return;
1020
1021	sc->dc_if_media = mii->mii_media_active;
1022	if (DC_IS_ADMTEK(sc))
1023		return;
1024	dc_setcfg(sc, mii->mii_media_active);
1025}
1026
1027/*
1028 * Special support for DM9102A cards with HomePNA PHYs. Note:
1029 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
1030 * to be impossible to talk to the management interface of the DM9801
1031 * PHY (its MDIO pin is not connected to anything). Consequently,
1032 * the driver has to just 'know' about the additional mode and deal
1033 * with it itself. *sigh*
1034 */
1035static void
1036dc_miibus_mediainit(device_t dev)
1037{
1038	struct dc_softc *sc;
1039	struct mii_data *mii;
1040	struct ifmedia *ifm;
1041	int rev;
1042
1043	rev = pci_get_revid(dev);
1044
1045	sc = device_get_softc(dev);
1046	mii = device_get_softc(sc->dc_miibus);
1047	ifm = &mii->mii_media;
1048
1049	if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
1050		ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
1051}
1052
1053#define	DC_BITS_512	9
1054#define	DC_BITS_128	7
1055#define	DC_BITS_64	6
1056
1057static uint32_t
1058dc_mchash_le(struct dc_softc *sc, const uint8_t *addr)
1059{
1060	uint32_t crc;
1061
1062	/* Compute CRC for the address value. */
1063	crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
1064
1065	/*
1066	 * The hash table on the PNIC II and the MX98715AEC-C/D/E
1067	 * chips is only 128 bits wide.
1068	 */
1069	if (sc->dc_flags & DC_128BIT_HASH)
1070		return (crc & ((1 << DC_BITS_128) - 1));
1071
1072	/* The hash table on the MX98715BEC is only 64 bits wide. */
1073	if (sc->dc_flags & DC_64BIT_HASH)
1074		return (crc & ((1 << DC_BITS_64) - 1));
1075
1076	/* Xircom's hash filtering table is different (read: weird) */
1077	/* Xircom uses the LEAST significant bits */
1078	if (DC_IS_XIRCOM(sc)) {
1079		if ((crc & 0x180) == 0x180)
1080			return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4));
1081		else
1082			return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 +
1083			    (12 << 4));
1084	}
1085
1086	return (crc & ((1 << DC_BITS_512) - 1));
1087}
1088
1089/*
1090 * Calculate CRC of a multicast group address, return the lower 6 bits.
1091 */
1092static uint32_t
1093dc_mchash_be(const uint8_t *addr)
1094{
1095	uint32_t crc;
1096
1097	/* Compute CRC for the address value. */
1098	crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
1099
1100	/* Return the filter bit position. */
1101	return ((crc >> 26) & 0x0000003F);
1102}
1103
1104/*
1105 * 21143-style RX filter setup routine. Filter programming is done by
1106 * downloading a special setup frame into the TX engine. 21143, Macronix,
1107 * PNIC, PNIC II and Davicom chips are programmed this way.
1108 *
1109 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1110 * address (our node address) and a 512-bit hash filter for multicast
1111 * frames. We also sneak the broadcast address into the hash filter since
1112 * we need that too.
1113 */
1114static void
1115dc_setfilt_21143(struct dc_softc *sc)
1116{
1117	uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
1118	struct dc_desc *sframe;
1119	uint32_t h, *sp;
1120	struct ifmultiaddr *ifma;
1121	struct ifnet *ifp;
1122	int i;
1123
1124	ifp = sc->dc_ifp;
1125
1126	i = sc->dc_cdata.dc_tx_prod;
1127	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1128	sc->dc_cdata.dc_tx_cnt++;
1129	sframe = &sc->dc_ldata.dc_tx_list[i];
1130	sp = sc->dc_cdata.dc_sbuf;
1131	bzero(sp, DC_SFRAME_LEN);
1132
1133	sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
1134	sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1135	    DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1136
1137	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1138
1139	/* If we want promiscuous mode, set the allframes bit. */
1140	if (ifp->if_flags & IFF_PROMISC)
1141		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1142	else
1143		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1144
1145	if (ifp->if_flags & IFF_ALLMULTI)
1146		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1147	else
1148		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1149
1150	if_maddr_rlock(ifp);
1151	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1152		if (ifma->ifma_addr->sa_family != AF_LINK)
1153			continue;
1154		h = dc_mchash_le(sc,
1155		    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1156		sp[h >> 4] |= htole32(1 << (h & 0xF));
1157	}
1158	if_maddr_runlock(ifp);
1159
1160	if (ifp->if_flags & IFF_BROADCAST) {
1161		h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1162		sp[h >> 4] |= htole32(1 << (h & 0xF));
1163	}
1164
1165	/* Set our MAC address. */
1166	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1167	sp[39] = DC_SP_MAC(eaddr[0]);
1168	sp[40] = DC_SP_MAC(eaddr[1]);
1169	sp[41] = DC_SP_MAC(eaddr[2]);
1170
1171	sframe->dc_status = htole32(DC_TXSTAT_OWN);
1172	bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1173	    BUS_DMASYNC_PREWRITE);
1174	bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1175	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1176
1177	/*
1178	 * The PNIC takes an exceedingly long time to process its
1179	 * setup frame; wait 10ms after posting the setup frame
1180	 * before proceeding, just so it has time to swallow its
1181	 * medicine.
1182	 */
1183	DELAY(10000);
1184
1185	sc->dc_wdog_timer = 5;
1186}
1187
1188static void
1189dc_setfilt_admtek(struct dc_softc *sc)
1190{
1191	uint8_t eaddr[ETHER_ADDR_LEN];
1192	struct ifnet *ifp;
1193	struct ifmultiaddr *ifma;
1194	int h = 0;
1195	uint32_t hashes[2] = { 0, 0 };
1196
1197	ifp = sc->dc_ifp;
1198
1199	/* Init our MAC address. */
1200	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1201	CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 |
1202	    eaddr[1] << 8 | eaddr[0]);
1203	CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]);
1204
1205	/* If we want promiscuous mode, set the allframes bit. */
1206	if (ifp->if_flags & IFF_PROMISC)
1207		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1208	else
1209		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1210
1211	if (ifp->if_flags & IFF_ALLMULTI)
1212		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1213	else
1214		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1215
1216	/* First, zot all the existing hash bits. */
1217	CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1218	CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1219
1220	/*
1221	 * If we're already in promisc or allmulti mode, we
1222	 * don't have to bother programming the multicast filter.
1223	 */
1224	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1225		return;
1226
1227	/* Now program new ones. */
1228	if_maddr_rlock(ifp);
1229	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1230		if (ifma->ifma_addr->sa_family != AF_LINK)
1231			continue;
1232		if (DC_IS_CENTAUR(sc))
1233			h = dc_mchash_le(sc,
1234			    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1235		else
1236			h = dc_mchash_be(
1237			    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1238		if (h < 32)
1239			hashes[0] |= (1 << h);
1240		else
1241			hashes[1] |= (1 << (h - 32));
1242	}
1243	if_maddr_runlock(ifp);
1244
1245	CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1246	CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1247}
1248
1249static void
1250dc_setfilt_asix(struct dc_softc *sc)
1251{
1252	uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
1253	struct ifnet *ifp;
1254	struct ifmultiaddr *ifma;
1255	int h = 0;
1256	uint32_t hashes[2] = { 0, 0 };
1257
1258	ifp = sc->dc_ifp;
1259
1260	/* Init our MAC address. */
1261	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1262	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1263	CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]);
1264	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1265	CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]);
1266
1267	/* If we want promiscuous mode, set the allframes bit. */
1268	if (ifp->if_flags & IFF_PROMISC)
1269		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1270	else
1271		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1272
1273	if (ifp->if_flags & IFF_ALLMULTI)
1274		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1275	else
1276		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1277
1278	/*
1279	 * The ASIX chip has a special bit to enable reception
1280	 * of broadcast frames.
1281	 */
1282	if (ifp->if_flags & IFF_BROADCAST)
1283		DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1284	else
1285		DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1286
1287	/* first, zot all the existing hash bits */
1288	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1289	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1290	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1291	CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1292
1293	/*
1294	 * If we're already in promisc or allmulti mode, we
1295	 * don't have to bother programming the multicast filter.
1296	 */
1297	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI))
1298		return;
1299
1300	/* now program new ones */
1301	if_maddr_rlock(ifp);
1302	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1303		if (ifma->ifma_addr->sa_family != AF_LINK)
1304			continue;
1305		h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1306		if (h < 32)
1307			hashes[0] |= (1 << h);
1308		else
1309			hashes[1] |= (1 << (h - 32));
1310	}
1311	if_maddr_runlock(ifp);
1312
1313	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1314	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1315	CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1316	CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1317}
1318
1319static void
1320dc_setfilt_uli(struct dc_softc *sc)
1321{
1322	uint8_t eaddr[ETHER_ADDR_LEN];
1323	struct ifnet *ifp;
1324	struct ifmultiaddr *ifma;
1325	struct dc_desc *sframe;
1326	uint32_t filter, *sp;
1327	uint8_t *ma;
1328	int i, mcnt;
1329
1330	ifp = sc->dc_ifp;
1331
1332	i = sc->dc_cdata.dc_tx_prod;
1333	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1334	sc->dc_cdata.dc_tx_cnt++;
1335	sframe = &sc->dc_ldata.dc_tx_list[i];
1336	sp = sc->dc_cdata.dc_sbuf;
1337	bzero(sp, DC_SFRAME_LEN);
1338
1339	sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
1340	sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1341	    DC_TXCTL_TLINK | DC_FILTER_PERFECT | DC_TXCTL_FINT);
1342
1343	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1344
1345	/* Set station address. */
1346	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1347	*sp++ = DC_SP_MAC(eaddr[1] << 8 | eaddr[0]);
1348	*sp++ = DC_SP_MAC(eaddr[3] << 8 | eaddr[2]);
1349	*sp++ = DC_SP_MAC(eaddr[5] << 8 | eaddr[4]);
1350
1351	/* Set broadcast address. */
1352	*sp++ = DC_SP_MAC(0xFFFF);
1353	*sp++ = DC_SP_MAC(0xFFFF);
1354	*sp++ = DC_SP_MAC(0xFFFF);
1355
1356	/* Extract current filter configuration. */
1357	filter = CSR_READ_4(sc, DC_NETCFG);
1358	filter &= ~(DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI);
1359
1360	/* Now build perfect filters. */
1361	mcnt = 0;
1362	if_maddr_rlock(ifp);
1363	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1364		if (ifma->ifma_addr->sa_family != AF_LINK)
1365			continue;
1366		if (mcnt >= DC_ULI_FILTER_NPERF) {
1367			filter |= DC_NETCFG_RX_ALLMULTI;
1368			break;
1369		}
1370		ma = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
1371		*sp++ = DC_SP_MAC(ma[1] << 8 | ma[0]);
1372		*sp++ = DC_SP_MAC(ma[3] << 8 | ma[2]);
1373		*sp++ = DC_SP_MAC(ma[5] << 8 | ma[4]);
1374		mcnt++;
1375	}
1376	if_maddr_runlock(ifp);
1377
1378	for (; mcnt < DC_ULI_FILTER_NPERF; mcnt++) {
1379		*sp++ = DC_SP_MAC(0xFFFF);
1380		*sp++ = DC_SP_MAC(0xFFFF);
1381		*sp++ = DC_SP_MAC(0xFFFF);
1382	}
1383
1384	if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON))
1385		CSR_WRITE_4(sc, DC_NETCFG,
1386		    filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1387	if (ifp->if_flags & IFF_PROMISC)
1388		filter |= DC_NETCFG_RX_PROMISC | DC_NETCFG_RX_ALLMULTI;
1389	if (ifp->if_flags & IFF_ALLMULTI)
1390		filter |= DC_NETCFG_RX_ALLMULTI;
1391	CSR_WRITE_4(sc, DC_NETCFG,
1392	    filter & ~(DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1393	if (filter & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON))
1394		CSR_WRITE_4(sc, DC_NETCFG, filter);
1395
1396	sframe->dc_status = htole32(DC_TXSTAT_OWN);
1397	bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1398	    BUS_DMASYNC_PREWRITE);
1399	bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1400	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1401
1402	/*
1403	 * Wait some time...
1404	 */
1405	DELAY(1000);
1406
1407	sc->dc_wdog_timer = 5;
1408}
1409
1410static void
1411dc_setfilt_xircom(struct dc_softc *sc)
1412{
1413	uint16_t eaddr[(ETHER_ADDR_LEN+1)/2];
1414	struct ifnet *ifp;
1415	struct ifmultiaddr *ifma;
1416	struct dc_desc *sframe;
1417	uint32_t h, *sp;
1418	int i;
1419
1420	ifp = sc->dc_ifp;
1421	DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1422
1423	i = sc->dc_cdata.dc_tx_prod;
1424	DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1425	sc->dc_cdata.dc_tx_cnt++;
1426	sframe = &sc->dc_ldata.dc_tx_list[i];
1427	sp = sc->dc_cdata.dc_sbuf;
1428	bzero(sp, DC_SFRAME_LEN);
1429
1430	sframe->dc_data = htole32(DC_ADDR_LO(sc->dc_saddr));
1431	sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP |
1432	    DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT);
1433
1434	sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf;
1435
1436	/* If we want promiscuous mode, set the allframes bit. */
1437	if (ifp->if_flags & IFF_PROMISC)
1438		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1439	else
1440		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1441
1442	if (ifp->if_flags & IFF_ALLMULTI)
1443		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1444	else
1445		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1446
1447	if_maddr_rlock(ifp);
1448	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1449		if (ifma->ifma_addr->sa_family != AF_LINK)
1450			continue;
1451		h = dc_mchash_le(sc,
1452		    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1453		sp[h >> 4] |= htole32(1 << (h & 0xF));
1454	}
1455	if_maddr_runlock(ifp);
1456
1457	if (ifp->if_flags & IFF_BROADCAST) {
1458		h = dc_mchash_le(sc, ifp->if_broadcastaddr);
1459		sp[h >> 4] |= htole32(1 << (h & 0xF));
1460	}
1461
1462	/* Set our MAC address. */
1463	bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN);
1464	sp[0] = DC_SP_MAC(eaddr[0]);
1465	sp[1] = DC_SP_MAC(eaddr[1]);
1466	sp[2] = DC_SP_MAC(eaddr[2]);
1467
1468	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1469	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1470	sframe->dc_status = htole32(DC_TXSTAT_OWN);
1471	bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_PREREAD |
1472	    BUS_DMASYNC_PREWRITE);
1473	bus_dmamap_sync(sc->dc_stag, sc->dc_smap, BUS_DMASYNC_PREWRITE);
1474	CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1475
1476	/*
1477	 * Wait some time...
1478	 */
1479	DELAY(1000);
1480
1481	sc->dc_wdog_timer = 5;
1482}
1483
1484static void
1485dc_setfilt(struct dc_softc *sc)
1486{
1487
1488	if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1489	    DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1490		dc_setfilt_21143(sc);
1491
1492	if (DC_IS_ASIX(sc))
1493		dc_setfilt_asix(sc);
1494
1495	if (DC_IS_ADMTEK(sc))
1496		dc_setfilt_admtek(sc);
1497
1498	if (DC_IS_ULI(sc))
1499		dc_setfilt_uli(sc);
1500
1501	if (DC_IS_XIRCOM(sc))
1502		dc_setfilt_xircom(sc);
1503}
1504
1505static void
1506dc_netcfg_wait(struct dc_softc *sc)
1507{
1508	uint32_t isr;
1509	int i;
1510
1511	for (i = 0; i < DC_TIMEOUT; i++) {
1512		isr = CSR_READ_4(sc, DC_ISR);
1513		if (isr & DC_ISR_TX_IDLE &&
1514		    ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1515		    (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1516			break;
1517		DELAY(10);
1518	}
1519	if (i == DC_TIMEOUT && bus_child_present(sc->dc_dev)) {
1520		if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc))
1521			device_printf(sc->dc_dev,
1522			    "%s: failed to force tx to idle state\n", __func__);
1523		if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1524		    (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
1525		    !DC_HAS_BROKEN_RXSTATE(sc))
1526			device_printf(sc->dc_dev,
1527			    "%s: failed to force rx to idle state\n", __func__);
1528	}
1529}
1530
1531/*
1532 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in
1533 * the netconfig register, we first have to put the transmit and/or
1534 * receive logic in the idle state.
1535 */
1536static void
1537dc_setcfg(struct dc_softc *sc, int media)
1538{
1539	int restart = 0, watchdogreg;
1540
1541	if (IFM_SUBTYPE(media) == IFM_NONE)
1542		return;
1543
1544	if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) {
1545		restart = 1;
1546		DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON));
1547		dc_netcfg_wait(sc);
1548	}
1549
1550	if (IFM_SUBTYPE(media) == IFM_100_TX) {
1551		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1552		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1553		if (sc->dc_pmode == DC_PMODE_MII) {
1554			if (DC_IS_INTEL(sc)) {
1555			/* There's a write enable bit here that reads as 1. */
1556				watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1557				watchdogreg &= ~DC_WDOG_CTLWREN;
1558				watchdogreg |= DC_WDOG_JABBERDIS;
1559				CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1560			} else {
1561				DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1562			}
1563			DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1564			    DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1565			if (sc->dc_type == DC_TYPE_98713)
1566				DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1567				    DC_NETCFG_SCRAMBLER));
1568			if (!DC_IS_DAVICOM(sc))
1569				DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1570			DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1571		} else {
1572			if (DC_IS_PNIC(sc)) {
1573				DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1574				DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1575				DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1576			}
1577			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1578			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1579			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1580		}
1581	}
1582
1583	if (IFM_SUBTYPE(media) == IFM_10_T) {
1584		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1585		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1586		if (sc->dc_pmode == DC_PMODE_MII) {
1587			/* There's a write enable bit here that reads as 1. */
1588			if (DC_IS_INTEL(sc)) {
1589				watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1590				watchdogreg &= ~DC_WDOG_CTLWREN;
1591				watchdogreg |= DC_WDOG_JABBERDIS;
1592				CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1593			} else {
1594				DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1595			}
1596			DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS |
1597			    DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER));
1598			if (sc->dc_type == DC_TYPE_98713)
1599				DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1600			if (!DC_IS_DAVICOM(sc))
1601				DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1602			DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1603		} else {
1604			if (DC_IS_PNIC(sc)) {
1605				DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1606				DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1607				DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1608			}
1609			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1610			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1611			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1612			if (DC_IS_INTEL(sc)) {
1613				DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1614				DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1615				if ((media & IFM_GMASK) == IFM_FDX)
1616					DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1617				else
1618					DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1619				DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1620				DC_CLRBIT(sc, DC_10BTCTRL,
1621				    DC_TCTL_AUTONEGENBL);
1622				DELAY(20000);
1623			}
1624		}
1625	}
1626
1627	/*
1628	 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1629	 * PHY and we want HomePNA mode, set the portsel bit to turn
1630	 * on the external MII port.
1631	 */
1632	if (DC_IS_DAVICOM(sc)) {
1633		if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1634			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1635			sc->dc_link = 1;
1636		} else {
1637			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1638		}
1639	}
1640
1641	if ((media & IFM_GMASK) == IFM_FDX) {
1642		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1643		if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1644			DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1645	} else {
1646		DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1647		if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1648			DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1649	}
1650
1651	if (restart)
1652		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON);
1653}
1654
1655static void
1656dc_reset(struct dc_softc *sc)
1657{
1658	int i;
1659
1660	DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1661
1662	for (i = 0; i < DC_TIMEOUT; i++) {
1663		DELAY(10);
1664		if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1665			break;
1666	}
1667
1668	if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) ||
1669	    DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc) || DC_IS_ULI(sc)) {
1670		DELAY(10000);
1671		DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1672		i = 0;
1673	}
1674
1675	if (i == DC_TIMEOUT)
1676		device_printf(sc->dc_dev, "reset never completed!\n");
1677
1678	/* Wait a little while for the chip to get its brains in order. */
1679	DELAY(1000);
1680
1681	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1682	CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1683	CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1684
1685	/*
1686	 * Bring the SIA out of reset. In some cases, it looks
1687	 * like failing to unreset the SIA soon enough gets it
1688	 * into a state where it will never come out of reset
1689	 * until we reset the whole chip again.
1690	 */
1691	if (DC_IS_INTEL(sc)) {
1692		DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1693		CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFFFFFF);
1694		CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1695	}
1696}
1697
1698static const struct dc_type *
1699dc_devtype(device_t dev)
1700{
1701	const struct dc_type *t;
1702	uint32_t devid;
1703	uint8_t rev;
1704
1705	t = dc_devs;
1706	devid = pci_get_devid(dev);
1707	rev = pci_get_revid(dev);
1708
1709	while (t->dc_name != NULL) {
1710		if (devid == t->dc_devid && rev >= t->dc_minrev)
1711			return (t);
1712		t++;
1713	}
1714
1715	return (NULL);
1716}
1717
1718/*
1719 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1720 * IDs against our list and return a device name if we find a match.
1721 * We do a little bit of extra work to identify the exact type of
1722 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1723 * but different revision IDs. The same is true for 98715/98715A
1724 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1725 * cases, the exact chip revision affects driver behavior.
1726 */
1727static int
1728dc_probe(device_t dev)
1729{
1730	const struct dc_type *t;
1731
1732	t = dc_devtype(dev);
1733
1734	if (t != NULL) {
1735		device_set_desc(dev, t->dc_name);
1736		return (BUS_PROBE_DEFAULT);
1737	}
1738
1739	return (ENXIO);
1740}
1741
1742static void
1743dc_apply_fixup(struct dc_softc *sc, int media)
1744{
1745	struct dc_mediainfo *m;
1746	uint8_t *p;
1747	int i;
1748	uint32_t reg;
1749
1750	m = sc->dc_mi;
1751
1752	while (m != NULL) {
1753		if (m->dc_media == media)
1754			break;
1755		m = m->dc_next;
1756	}
1757
1758	if (m == NULL)
1759		return;
1760
1761	for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1762		reg = (p[0] | (p[1] << 8)) << 16;
1763		CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1764	}
1765
1766	for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1767		reg = (p[0] | (p[1] << 8)) << 16;
1768		CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1769	}
1770}
1771
1772static int
1773dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1774{
1775	struct dc_mediainfo *m;
1776
1777	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1778	if (m == NULL) {
1779		device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1780		return (ENOMEM);
1781	}
1782	switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) {
1783	case DC_SIA_CODE_10BT:
1784		m->dc_media = IFM_10_T;
1785		break;
1786	case DC_SIA_CODE_10BT_FDX:
1787		m->dc_media = IFM_10_T | IFM_FDX;
1788		break;
1789	case DC_SIA_CODE_10B2:
1790		m->dc_media = IFM_10_2;
1791		break;
1792	case DC_SIA_CODE_10B5:
1793		m->dc_media = IFM_10_5;
1794		break;
1795	default:
1796		break;
1797	}
1798
1799	/*
1800	 * We need to ignore CSR13, CSR14, CSR15 for SIA mode.
1801	 * Things apparently already work for cards that do
1802	 * supply Media Specific Data.
1803	 */
1804	if (l->dc_sia_code & DC_SIA_CODE_EXT) {
1805		m->dc_gp_len = 2;
1806		m->dc_gp_ptr =
1807		(uint8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1808	} else {
1809		m->dc_gp_len = 2;
1810		m->dc_gp_ptr =
1811		(uint8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1812	}
1813
1814	m->dc_next = sc->dc_mi;
1815	sc->dc_mi = m;
1816
1817	sc->dc_pmode = DC_PMODE_SIA;
1818	return (0);
1819}
1820
1821static int
1822dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1823{
1824	struct dc_mediainfo *m;
1825
1826	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1827	if (m == NULL) {
1828		device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1829		return (ENOMEM);
1830	}
1831	if (l->dc_sym_code == DC_SYM_CODE_100BT)
1832		m->dc_media = IFM_100_TX;
1833
1834	if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1835		m->dc_media = IFM_100_TX | IFM_FDX;
1836
1837	m->dc_gp_len = 2;
1838	m->dc_gp_ptr = (uint8_t *)&l->dc_sym_gpio_ctl;
1839
1840	m->dc_next = sc->dc_mi;
1841	sc->dc_mi = m;
1842
1843	sc->dc_pmode = DC_PMODE_SYM;
1844	return (0);
1845}
1846
1847static int
1848dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1849{
1850	struct dc_mediainfo *m;
1851	uint8_t *p;
1852
1853	m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO);
1854	if (m == NULL) {
1855		device_printf(sc->dc_dev, "Could not allocate mediainfo\n");
1856		return (ENOMEM);
1857	}
1858	/* We abuse IFM_AUTO to represent MII. */
1859	m->dc_media = IFM_AUTO;
1860	m->dc_gp_len = l->dc_gpr_len;
1861
1862	p = (uint8_t *)l;
1863	p += sizeof(struct dc_eblock_mii);
1864	m->dc_gp_ptr = p;
1865	p += 2 * l->dc_gpr_len;
1866	m->dc_reset_len = *p;
1867	p++;
1868	m->dc_reset_ptr = p;
1869
1870	m->dc_next = sc->dc_mi;
1871	sc->dc_mi = m;
1872	return (0);
1873}
1874
1875static int
1876dc_read_srom(struct dc_softc *sc, int bits)
1877{
1878	int size;
1879
1880	size = DC_ROM_SIZE(bits);
1881	sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
1882	if (sc->dc_srom == NULL) {
1883		device_printf(sc->dc_dev, "Could not allocate SROM buffer\n");
1884		return (ENOMEM);
1885	}
1886	dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1887	return (0);
1888}
1889
1890static int
1891dc_parse_21143_srom(struct dc_softc *sc)
1892{
1893	struct dc_leaf_hdr *lhdr;
1894	struct dc_eblock_hdr *hdr;
1895	int error, have_mii, i, loff;
1896	char *ptr;
1897
1898	have_mii = 0;
1899	loff = sc->dc_srom[27];
1900	lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1901
1902	ptr = (char *)lhdr;
1903	ptr += sizeof(struct dc_leaf_hdr) - 1;
1904	/*
1905	 * Look if we got a MII media block.
1906	 */
1907	for (i = 0; i < lhdr->dc_mcnt; i++) {
1908		hdr = (struct dc_eblock_hdr *)ptr;
1909		if (hdr->dc_type == DC_EBLOCK_MII)
1910		    have_mii++;
1911
1912		ptr += (hdr->dc_len & 0x7F);
1913		ptr++;
1914	}
1915
1916	/*
1917	 * Do the same thing again. Only use SIA and SYM media
1918	 * blocks if no MII media block is available.
1919	 */
1920	ptr = (char *)lhdr;
1921	ptr += sizeof(struct dc_leaf_hdr) - 1;
1922	error = 0;
1923	for (i = 0; i < lhdr->dc_mcnt; i++) {
1924		hdr = (struct dc_eblock_hdr *)ptr;
1925		switch (hdr->dc_type) {
1926		case DC_EBLOCK_MII:
1927			error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1928			break;
1929		case DC_EBLOCK_SIA:
1930			if (! have_mii)
1931				error = dc_decode_leaf_sia(sc,
1932				    (struct dc_eblock_sia *)hdr);
1933			break;
1934		case DC_EBLOCK_SYM:
1935			if (! have_mii)
1936				error = dc_decode_leaf_sym(sc,
1937				    (struct dc_eblock_sym *)hdr);
1938			break;
1939		default:
1940			/* Don't care. Yet. */
1941			break;
1942		}
1943		ptr += (hdr->dc_len & 0x7F);
1944		ptr++;
1945	}
1946	return (error);
1947}
1948
1949static void
1950dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1951{
1952	bus_addr_t *paddr;
1953
1954	KASSERT(nseg == 1,
1955	    ("%s: wrong number of segments (%d)", __func__, nseg));
1956	paddr = arg;
1957	*paddr = segs->ds_addr;
1958}
1959
1960static int
1961dc_dma_alloc(struct dc_softc *sc)
1962{
1963	int error, i;
1964
1965	error = bus_dma_tag_create(bus_get_dma_tag(sc->dc_dev), 1, 0,
1966	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1967	    BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1968	    NULL, NULL, &sc->dc_ptag);
1969	if (error) {
1970		device_printf(sc->dc_dev,
1971		    "failed to allocate parent DMA tag\n");
1972		goto fail;
1973	}
1974
1975	/* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
1976	error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1977	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_RX_LIST_SZ, 1,
1978	    DC_RX_LIST_SZ, 0, NULL, NULL, &sc->dc_rx_ltag);
1979	if (error) {
1980		device_printf(sc->dc_dev, "failed to create RX list DMA tag\n");
1981		goto fail;
1982	}
1983
1984	error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
1985	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DC_TX_LIST_SZ, 1,
1986	    DC_TX_LIST_SZ, 0, NULL, NULL, &sc->dc_tx_ltag);
1987	if (error) {
1988		device_printf(sc->dc_dev, "failed to create TX list DMA tag\n");
1989		goto fail;
1990	}
1991
1992	/* RX descriptor list. */
1993	error = bus_dmamem_alloc(sc->dc_rx_ltag,
1994	    (void **)&sc->dc_ldata.dc_rx_list, BUS_DMA_NOWAIT |
1995	    BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_rx_lmap);
1996	if (error) {
1997		device_printf(sc->dc_dev,
1998		    "failed to allocate DMA'able memory for RX list\n");
1999		goto fail;
2000	}
2001	error = bus_dmamap_load(sc->dc_rx_ltag, sc->dc_rx_lmap,
2002	    sc->dc_ldata.dc_rx_list, DC_RX_LIST_SZ, dc_dma_map_addr,
2003	    &sc->dc_ldata.dc_rx_list_paddr, BUS_DMA_NOWAIT);
2004	if (error) {
2005		device_printf(sc->dc_dev,
2006		    "failed to load DMA'able memory for RX list\n");
2007		goto fail;
2008	}
2009	/* TX descriptor list. */
2010	error = bus_dmamem_alloc(sc->dc_tx_ltag,
2011	    (void **)&sc->dc_ldata.dc_tx_list, BUS_DMA_NOWAIT |
2012	    BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->dc_tx_lmap);
2013	if (error) {
2014		device_printf(sc->dc_dev,
2015		    "failed to allocate DMA'able memory for TX list\n");
2016		goto fail;
2017	}
2018	error = bus_dmamap_load(sc->dc_tx_ltag, sc->dc_tx_lmap,
2019	    sc->dc_ldata.dc_tx_list, DC_TX_LIST_SZ, dc_dma_map_addr,
2020	    &sc->dc_ldata.dc_tx_list_paddr, BUS_DMA_NOWAIT);
2021	if (error) {
2022		device_printf(sc->dc_dev,
2023		    "cannot load DMA'able memory for TX list\n");
2024		goto fail;
2025	}
2026
2027	/*
2028	 * Allocate a busdma tag and DMA safe memory for the multicast
2029	 * setup frame.
2030	 */
2031	error = bus_dma_tag_create(sc->dc_ptag, DC_LIST_ALIGN, 0,
2032	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2033	    DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN,
2034	    0, NULL, NULL, &sc->dc_stag);
2035	if (error) {
2036		device_printf(sc->dc_dev,
2037		    "failed to create DMA tag for setup frame\n");
2038		goto fail;
2039	}
2040	error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf,
2041	    BUS_DMA_NOWAIT, &sc->dc_smap);
2042	if (error) {
2043		device_printf(sc->dc_dev,
2044		    "failed to allocate DMA'able memory for setup frame\n");
2045		goto fail;
2046	}
2047	error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf,
2048	    DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT);
2049	if (error) {
2050		device_printf(sc->dc_dev,
2051		    "cannot load DMA'able memory for setup frame\n");
2052		goto fail;
2053	}
2054
2055	/* Allocate a busdma tag for RX mbufs. */
2056	error = bus_dma_tag_create(sc->dc_ptag, DC_RXBUF_ALIGN, 0,
2057	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2058	    MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->dc_rx_mtag);
2059	if (error) {
2060		device_printf(sc->dc_dev, "failed to create RX mbuf tag\n");
2061		goto fail;
2062	}
2063
2064	/* Allocate a busdma tag for TX mbufs. */
2065	error = bus_dma_tag_create(sc->dc_ptag, 1, 0,
2066	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2067	    MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES,
2068	    0, NULL, NULL, &sc->dc_tx_mtag);
2069	if (error) {
2070		device_printf(sc->dc_dev, "failed to create TX mbuf tag\n");
2071		goto fail;
2072	}
2073
2074	/* Create the TX/RX busdma maps. */
2075	for (i = 0; i < DC_TX_LIST_CNT; i++) {
2076		error = bus_dmamap_create(sc->dc_tx_mtag, 0,
2077		    &sc->dc_cdata.dc_tx_map[i]);
2078		if (error) {
2079			device_printf(sc->dc_dev,
2080			    "failed to create TX mbuf dmamap\n");
2081			goto fail;
2082		}
2083	}
2084	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2085		error = bus_dmamap_create(sc->dc_rx_mtag, 0,
2086		    &sc->dc_cdata.dc_rx_map[i]);
2087		if (error) {
2088			device_printf(sc->dc_dev,
2089			    "failed to create RX mbuf dmamap\n");
2090			goto fail;
2091		}
2092	}
2093	error = bus_dmamap_create(sc->dc_rx_mtag, 0, &sc->dc_sparemap);
2094	if (error) {
2095		device_printf(sc->dc_dev,
2096		    "failed to create spare RX mbuf dmamap\n");
2097		goto fail;
2098	}
2099
2100fail:
2101	return (error);
2102}
2103
2104static void
2105dc_dma_free(struct dc_softc *sc)
2106{
2107	int i;
2108
2109	/* RX buffers. */
2110	if (sc->dc_rx_mtag != NULL) {
2111		for (i = 0; i < DC_RX_LIST_CNT; i++) {
2112			if (sc->dc_cdata.dc_rx_map[i] != NULL)
2113				bus_dmamap_destroy(sc->dc_rx_mtag,
2114				    sc->dc_cdata.dc_rx_map[i]);
2115		}
2116		if (sc->dc_sparemap != NULL)
2117			bus_dmamap_destroy(sc->dc_rx_mtag, sc->dc_sparemap);
2118		bus_dma_tag_destroy(sc->dc_rx_mtag);
2119	}
2120
2121	/* TX buffers. */
2122	if (sc->dc_rx_mtag != NULL) {
2123		for (i = 0; i < DC_TX_LIST_CNT; i++) {
2124			if (sc->dc_cdata.dc_tx_map[i] != NULL)
2125				bus_dmamap_destroy(sc->dc_tx_mtag,
2126				    sc->dc_cdata.dc_tx_map[i]);
2127		}
2128		bus_dma_tag_destroy(sc->dc_tx_mtag);
2129	}
2130
2131	/* RX descriptor list. */
2132	if (sc->dc_rx_ltag) {
2133		if (sc->dc_rx_lmap != NULL)
2134			bus_dmamap_unload(sc->dc_rx_ltag, sc->dc_rx_lmap);
2135		if (sc->dc_rx_lmap != NULL && sc->dc_ldata.dc_rx_list != NULL)
2136			bus_dmamem_free(sc->dc_rx_ltag, sc->dc_ldata.dc_rx_list,
2137			    sc->dc_rx_lmap);
2138		bus_dma_tag_destroy(sc->dc_rx_ltag);
2139	}
2140
2141	/* TX descriptor list. */
2142	if (sc->dc_tx_ltag) {
2143		if (sc->dc_tx_lmap != NULL)
2144			bus_dmamap_unload(sc->dc_tx_ltag, sc->dc_tx_lmap);
2145		if (sc->dc_tx_lmap != NULL && sc->dc_ldata.dc_tx_list != NULL)
2146			bus_dmamem_free(sc->dc_tx_ltag, sc->dc_ldata.dc_tx_list,
2147			    sc->dc_tx_lmap);
2148		bus_dma_tag_destroy(sc->dc_tx_ltag);
2149	}
2150
2151	/* multicast setup frame. */
2152	if (sc->dc_stag) {
2153		if (sc->dc_smap != NULL)
2154			bus_dmamap_unload(sc->dc_stag, sc->dc_smap);
2155		if (sc->dc_smap != NULL && sc->dc_cdata.dc_sbuf != NULL)
2156			bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf,
2157			    sc->dc_smap);
2158		bus_dma_tag_destroy(sc->dc_stag);
2159	}
2160}
2161
2162/*
2163 * Attach the interface. Allocate softc structures, do ifmedia
2164 * setup and ethernet/BPF attach.
2165 */
2166static int
2167dc_attach(device_t dev)
2168{
2169	uint32_t eaddr[(ETHER_ADDR_LEN+3)/4];
2170	uint32_t command;
2171	struct dc_softc *sc;
2172	struct ifnet *ifp;
2173	struct dc_mediainfo *m;
2174	uint32_t reg, revision;
2175	uint16_t *srom;
2176	int error, mac_offset, n, phy, rid, tmp;
2177	uint8_t *mac;
2178
2179	sc = device_get_softc(dev);
2180	sc->dc_dev = dev;
2181
2182	mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
2183	    MTX_DEF);
2184
2185	/*
2186	 * Map control/status registers.
2187	 */
2188	pci_enable_busmaster(dev);
2189
2190	rid = DC_RID;
2191	sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
2192
2193	if (sc->dc_res == NULL) {
2194		device_printf(dev, "couldn't map ports/memory\n");
2195		error = ENXIO;
2196		goto fail;
2197	}
2198
2199	sc->dc_btag = rman_get_bustag(sc->dc_res);
2200	sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
2201
2202	/* Allocate interrupt. */
2203	rid = 0;
2204	sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2205	    RF_SHAREABLE | RF_ACTIVE);
2206
2207	if (sc->dc_irq == NULL) {
2208		device_printf(dev, "couldn't map interrupt\n");
2209		error = ENXIO;
2210		goto fail;
2211	}
2212
2213	/* Need this info to decide on a chip type. */
2214	sc->dc_info = dc_devtype(dev);
2215	revision = pci_get_revid(dev);
2216
2217	error = 0;
2218	/* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */
2219	if (sc->dc_info->dc_devid !=
2220	    DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) &&
2221	    sc->dc_info->dc_devid !=
2222	    DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201))
2223		dc_eeprom_width(sc);
2224
2225	switch (sc->dc_info->dc_devid) {
2226	case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143):
2227		sc->dc_type = DC_TYPE_21143;
2228		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2229		sc->dc_flags |= DC_REDUCED_MII_POLL;
2230		/* Save EEPROM contents so we can parse them later. */
2231		error = dc_read_srom(sc, sc->dc_romwidth);
2232		if (error != 0)
2233			goto fail;
2234		break;
2235	case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009):
2236	case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100):
2237	case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102):
2238		sc->dc_type = DC_TYPE_DM9102;
2239		sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS;
2240		sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD;
2241		sc->dc_flags |= DC_TX_ALIGN;
2242		sc->dc_pmode = DC_PMODE_MII;
2243
2244		/* Increase the latency timer value. */
2245		pci_write_config(dev, PCIR_LATTIMER, 0x80, 1);
2246		break;
2247	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981):
2248		sc->dc_type = DC_TYPE_AL981;
2249		sc->dc_flags |= DC_TX_USE_TX_INTR;
2250		sc->dc_flags |= DC_TX_ADMTEK_WAR;
2251		sc->dc_pmode = DC_PMODE_MII;
2252		error = dc_read_srom(sc, sc->dc_romwidth);
2253		if (error != 0)
2254			goto fail;
2255		break;
2256	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983):
2257	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985):
2258	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511):
2259	case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513):
2260	case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD):
2261	case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500):
2262	case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX):
2263	case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242):
2264	case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX):
2265	case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T):
2266	case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB):
2267	case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120):
2268	case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130):
2269	case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08):
2270	case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09):
2271		sc->dc_type = DC_TYPE_AN983;
2272		sc->dc_flags |= DC_64BIT_HASH;
2273		sc->dc_flags |= DC_TX_USE_TX_INTR;
2274		sc->dc_flags |= DC_TX_ADMTEK_WAR;
2275		sc->dc_pmode = DC_PMODE_MII;
2276		/* Don't read SROM for - auto-loaded on reset */
2277		break;
2278	case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713):
2279	case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP):
2280		if (revision < DC_REVISION_98713A) {
2281			sc->dc_type = DC_TYPE_98713;
2282		}
2283		if (revision >= DC_REVISION_98713A) {
2284			sc->dc_type = DC_TYPE_98713A;
2285			sc->dc_flags |= DC_21143_NWAY;
2286		}
2287		sc->dc_flags |= DC_REDUCED_MII_POLL;
2288		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2289		break;
2290	case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5):
2291	case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217):
2292		/*
2293		 * Macronix MX98715AEC-C/D/E parts have only a
2294		 * 128-bit hash table. We need to deal with these
2295		 * in the same manner as the PNIC II so that we
2296		 * get the right number of bits out of the
2297		 * CRC routine.
2298		 */
2299		if (revision >= DC_REVISION_98715AEC_C &&
2300		    revision < DC_REVISION_98725)
2301			sc->dc_flags |= DC_128BIT_HASH;
2302		sc->dc_type = DC_TYPE_987x5;
2303		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2304		sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2305		break;
2306	case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727):
2307		sc->dc_type = DC_TYPE_987x5;
2308		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR;
2309		sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2310		break;
2311	case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115):
2312		sc->dc_type = DC_TYPE_PNICII;
2313		sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH;
2314		sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY;
2315		break;
2316	case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168):
2317		sc->dc_type = DC_TYPE_PNIC;
2318		sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS;
2319		sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
2320		sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT);
2321		if (sc->dc_pnic_rx_buf == NULL) {
2322			device_printf(sc->dc_dev,
2323			    "Could not allocate PNIC RX buffer\n");
2324			error = ENOMEM;
2325			goto fail;
2326		}
2327		if (revision < DC_REVISION_82C169)
2328			sc->dc_pmode = DC_PMODE_SYM;
2329		break;
2330	case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A):
2331		sc->dc_type = DC_TYPE_ASIX;
2332		sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG;
2333		sc->dc_flags |= DC_REDUCED_MII_POLL;
2334		sc->dc_pmode = DC_PMODE_MII;
2335		break;
2336	case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201):
2337		sc->dc_type = DC_TYPE_XIRCOM;
2338		sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
2339				DC_TX_ALIGN;
2340		/*
2341		 * We don't actually need to coalesce, but we're doing
2342		 * it to obtain a double word aligned buffer.
2343		 * The DC_TX_COALESCE flag is required.
2344		 */
2345		sc->dc_pmode = DC_PMODE_MII;
2346		break;
2347	case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112):
2348		sc->dc_type = DC_TYPE_CONEXANT;
2349		sc->dc_flags |= DC_TX_INTR_ALWAYS;
2350		sc->dc_flags |= DC_REDUCED_MII_POLL;
2351		sc->dc_pmode = DC_PMODE_MII;
2352		error = dc_read_srom(sc, sc->dc_romwidth);
2353		if (error != 0)
2354			goto fail;
2355		break;
2356	case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261):
2357	case DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5263):
2358		if (sc->dc_info->dc_devid ==
2359		    DC_DEVID(DC_VENDORID_ULI, DC_DEVICEID_M5261))
2360			sc->dc_type = DC_TYPE_ULI_M5261;
2361		else
2362			sc->dc_type = DC_TYPE_ULI_M5263;
2363		/* TX buffers should be aligned on 4 byte boundary. */
2364		sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE |
2365		    DC_TX_ALIGN;
2366		sc->dc_pmode = DC_PMODE_MII;
2367		error = dc_read_srom(sc, sc->dc_romwidth);
2368		if (error != 0)
2369			goto fail;
2370		break;
2371	default:
2372		device_printf(dev, "unknown device: %x\n",
2373		    sc->dc_info->dc_devid);
2374		break;
2375	}
2376
2377	/* Save the cache line size. */
2378	if (DC_IS_DAVICOM(sc))
2379		sc->dc_cachesize = 0;
2380	else
2381		sc->dc_cachesize = pci_get_cachelnsz(dev);
2382
2383	/* Reset the adapter. */
2384	dc_reset(sc);
2385
2386	/* Take 21143 out of snooze mode */
2387	if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) {
2388		command = pci_read_config(dev, DC_PCI_CFDD, 4);
2389		command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE);
2390		pci_write_config(dev, DC_PCI_CFDD, command, 4);
2391	}
2392
2393	/*
2394	 * Try to learn something about the supported media.
2395	 * We know that ASIX and ADMtek and Davicom devices
2396	 * will *always* be using MII media, so that's a no-brainer.
2397	 * The tricky ones are the Macronix/PNIC II and the
2398	 * Intel 21143.
2399	 */
2400	if (DC_IS_INTEL(sc)) {
2401		error = dc_parse_21143_srom(sc);
2402		if (error != 0)
2403			goto fail;
2404	} else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2405		if (sc->dc_type == DC_TYPE_98713)
2406			sc->dc_pmode = DC_PMODE_MII;
2407		else
2408			sc->dc_pmode = DC_PMODE_SYM;
2409	} else if (!sc->dc_pmode)
2410		sc->dc_pmode = DC_PMODE_MII;
2411
2412	/*
2413	 * Get station address from the EEPROM.
2414	 */
2415	switch(sc->dc_type) {
2416	case DC_TYPE_98713:
2417	case DC_TYPE_98713A:
2418	case DC_TYPE_987x5:
2419	case DC_TYPE_PNICII:
2420		dc_read_eeprom(sc, (caddr_t)&mac_offset,
2421		    (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
2422		dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
2423		break;
2424	case DC_TYPE_PNIC:
2425		dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
2426		break;
2427	case DC_TYPE_DM9102:
2428		dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2429#ifdef __sparc64__
2430		/*
2431		 * If this is an onboard dc(4) the station address read from
2432		 * the EEPROM is all zero and we have to get it from the FCode.
2433		 */
2434		if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0)
2435			OF_getetheraddr(dev, (caddr_t)&eaddr);
2436#endif
2437		break;
2438	case DC_TYPE_21143:
2439	case DC_TYPE_ASIX:
2440		dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2441		break;
2442	case DC_TYPE_AL981:
2443	case DC_TYPE_AN983:
2444		reg = CSR_READ_4(sc, DC_AL_PAR0);
2445		mac = (uint8_t *)&eaddr[0];
2446		mac[0] = (reg >> 0) & 0xff;
2447		mac[1] = (reg >> 8) & 0xff;
2448		mac[2] = (reg >> 16) & 0xff;
2449		mac[3] = (reg >> 24) & 0xff;
2450		reg = CSR_READ_4(sc, DC_AL_PAR1);
2451		mac[4] = (reg >> 0) & 0xff;
2452		mac[5] = (reg >> 8) & 0xff;
2453		break;
2454	case DC_TYPE_CONEXANT:
2455		bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr,
2456		    ETHER_ADDR_LEN);
2457		break;
2458	case DC_TYPE_XIRCOM:
2459		/* The MAC comes from the CIS. */
2460		mac = pci_get_ether(dev);
2461		if (!mac) {
2462			device_printf(dev, "No station address in CIS!\n");
2463			error = ENXIO;
2464			goto fail;
2465		}
2466		bcopy(mac, eaddr, ETHER_ADDR_LEN);
2467		break;
2468	case DC_TYPE_ULI_M5261:
2469	case DC_TYPE_ULI_M5263:
2470		srom = (uint16_t *)sc->dc_srom;
2471		if (srom == NULL || *srom == 0xFFFF || *srom == 0) {
2472			/*
2473			 * No valid SROM present, read station address
2474			 * from ID Table.
2475			 */
2476			device_printf(dev,
2477			    "Reading station address from ID Table.\n");
2478			CSR_WRITE_4(sc, DC_BUSCTL, 0x10000);
2479			CSR_WRITE_4(sc, DC_SIARESET, 0x01C0);
2480			CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000);
2481			CSR_WRITE_4(sc, DC_10BTCTRL, 0x0010);
2482			CSR_WRITE_4(sc, DC_10BTCTRL, 0x0000);
2483			CSR_WRITE_4(sc, DC_SIARESET, 0x0000);
2484			CSR_WRITE_4(sc, DC_SIARESET, 0x01B0);
2485			mac = (uint8_t *)eaddr;
2486			for (n = 0; n < ETHER_ADDR_LEN; n++)
2487				mac[n] = (uint8_t)CSR_READ_4(sc, DC_10BTCTRL);
2488			CSR_WRITE_4(sc, DC_SIARESET, 0x0000);
2489			CSR_WRITE_4(sc, DC_BUSCTL, 0x0000);
2490			DELAY(10);
2491		} else
2492			dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3,
2493			    0);
2494		break;
2495	default:
2496		dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
2497		break;
2498	}
2499
2500	bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr));
2501	/*
2502	 * If we still have invalid station address, see whether we can
2503	 * find station address for chip 0.  Some multi-port controllers
2504	 * just store station address for chip 0 if they have a shared
2505	 * SROM.
2506	 */
2507	if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) ||
2508	    (sc->dc_eaddr[0] == 0xffffffff &&
2509	    (sc->dc_eaddr[1] & 0xffff) == 0xffff)) {
2510		error = dc_check_multiport(sc);
2511		if (error == 0) {
2512			bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr));
2513			/* Extract media information. */
2514			if (DC_IS_INTEL(sc) && sc->dc_srom != NULL) {
2515				while (sc->dc_mi != NULL) {
2516					m = sc->dc_mi->dc_next;
2517					free(sc->dc_mi, M_DEVBUF);
2518					sc->dc_mi = m;
2519				}
2520				error = dc_parse_21143_srom(sc);
2521				if (error != 0)
2522					goto fail;
2523			}
2524		} else if (error == ENOMEM)
2525			goto fail;
2526		else
2527			error = 0;
2528	}
2529
2530	if ((error = dc_dma_alloc(sc)) != 0)
2531		goto fail;
2532
2533	ifp = sc->dc_ifp = if_alloc(IFT_ETHER);
2534	if (ifp == NULL) {
2535		device_printf(dev, "can not if_alloc()\n");
2536		error = ENOSPC;
2537		goto fail;
2538	}
2539	ifp->if_softc = sc;
2540	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2541	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2542	ifp->if_ioctl = dc_ioctl;
2543	ifp->if_start = dc_start;
2544	ifp->if_init = dc_init;
2545	IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1);
2546	ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1;
2547	IFQ_SET_READY(&ifp->if_snd);
2548
2549	/*
2550	 * Do MII setup. If this is a 21143, check for a PHY on the
2551	 * MII bus after applying any necessary fixups to twiddle the
2552	 * GPIO bits. If we don't end up finding a PHY, restore the
2553	 * old selection (SIA only or SIA/SYM) and attach the dcphy
2554	 * driver instead.
2555	 */
2556	tmp = 0;
2557	if (DC_IS_INTEL(sc)) {
2558		dc_apply_fixup(sc, IFM_AUTO);
2559		tmp = sc->dc_pmode;
2560		sc->dc_pmode = DC_PMODE_MII;
2561	}
2562
2563	/*
2564	 * Setup General Purpose port mode and data so the tulip can talk
2565	 * to the MII.  This needs to be done before mii_attach so that
2566	 * we can actually see them.
2567	 */
2568	if (DC_IS_XIRCOM(sc)) {
2569		CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2570		    DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2571		DELAY(10);
2572		CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2573		    DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
2574		DELAY(10);
2575	}
2576
2577	phy = MII_PHY_ANY;
2578	/*
2579	 * Note: both the AL981 and AN983 have internal PHYs, however the
2580	 * AL981 provides direct access to the PHY registers while the AN983
2581	 * uses a serial MII interface. The AN983's MII interface is also
2582	 * buggy in that you can read from any MII address (0 to 31), but
2583	 * only address 1 behaves normally. To deal with both cases, we
2584	 * pretend that the PHY is at MII address 1.
2585	 */
2586	if (DC_IS_ADMTEK(sc))
2587		phy = DC_ADMTEK_PHYADDR;
2588
2589	/*
2590	 * Note: the ukphy probes of the RS7112 report a PHY at MII address
2591	 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the
2592	 * correct one.
2593	 */
2594	if (DC_IS_CONEXANT(sc))
2595		phy = DC_CONEXANT_PHYADDR;
2596
2597	error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd,
2598	    dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
2599
2600	if (error && DC_IS_INTEL(sc)) {
2601		sc->dc_pmode = tmp;
2602		if (sc->dc_pmode != DC_PMODE_SIA)
2603			sc->dc_pmode = DC_PMODE_SYM;
2604		sc->dc_flags |= DC_21143_NWAY;
2605		mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd,
2606		    dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY,
2607		    MII_OFFSET_ANY, 0);
2608		/*
2609		 * For non-MII cards, we need to have the 21143
2610		 * drive the LEDs. Except there are some systems
2611		 * like the NEC VersaPro NoteBook PC which have no
2612		 * LEDs, and twiddling these bits has adverse effects
2613		 * on them. (I.e. you suddenly can't get a link.)
2614		 */
2615		if (!(pci_get_subvendor(dev) == 0x1033 &&
2616		    pci_get_subdevice(dev) == 0x8028))
2617			sc->dc_flags |= DC_TULIP_LEDS;
2618		error = 0;
2619	}
2620
2621	if (error) {
2622		device_printf(dev, "attaching PHYs failed\n");
2623		goto fail;
2624	}
2625
2626	if (DC_IS_ADMTEK(sc)) {
2627		/*
2628		 * Set automatic TX underrun recovery for the ADMtek chips
2629		 */
2630		DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2631	}
2632
2633	/*
2634	 * Tell the upper layer(s) we support long frames.
2635	 */
2636	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2637	ifp->if_capabilities |= IFCAP_VLAN_MTU;
2638	ifp->if_capenable = ifp->if_capabilities;
2639#ifdef DEVICE_POLLING
2640	ifp->if_capabilities |= IFCAP_POLLING;
2641#endif
2642
2643	callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0);
2644	callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0);
2645
2646	/*
2647	 * Call MI attach routine.
2648	 */
2649	ether_ifattach(ifp, (caddr_t)eaddr);
2650
2651	/* Hook interrupt last to avoid having to lock softc */
2652	error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE,
2653	    NULL, dc_intr, sc, &sc->dc_intrhand);
2654
2655	if (error) {
2656		device_printf(dev, "couldn't set up irq\n");
2657		ether_ifdetach(ifp);
2658		goto fail;
2659	}
2660
2661fail:
2662	if (error)
2663		dc_detach(dev);
2664	return (error);
2665}
2666
2667/*
2668 * Shutdown hardware and free up resources. This can be called any
2669 * time after the mutex has been initialized. It is called in both
2670 * the error case in attach and the normal detach case so it needs
2671 * to be careful about only freeing resources that have actually been
2672 * allocated.
2673 */
2674static int
2675dc_detach(device_t dev)
2676{
2677	struct dc_softc *sc;
2678	struct ifnet *ifp;
2679	struct dc_mediainfo *m;
2680
2681	sc = device_get_softc(dev);
2682	KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized"));
2683
2684	ifp = sc->dc_ifp;
2685
2686#ifdef DEVICE_POLLING
2687	if (ifp->if_capenable & IFCAP_POLLING)
2688		ether_poll_deregister(ifp);
2689#endif
2690
2691	/* These should only be active if attach succeeded */
2692	if (device_is_attached(dev)) {
2693		DC_LOCK(sc);
2694		dc_stop(sc);
2695		DC_UNLOCK(sc);
2696		callout_drain(&sc->dc_stat_ch);
2697		callout_drain(&sc->dc_wdog_ch);
2698		ether_ifdetach(ifp);
2699	}
2700	if (sc->dc_miibus)
2701		device_delete_child(dev, sc->dc_miibus);
2702	bus_generic_detach(dev);
2703
2704	if (sc->dc_intrhand)
2705		bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2706	if (sc->dc_irq)
2707		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2708	if (sc->dc_res)
2709		bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2710
2711	if (ifp)
2712		if_free(ifp);
2713
2714	dc_dma_free(sc);
2715
2716	free(sc->dc_pnic_rx_buf, M_DEVBUF);
2717
2718	while (sc->dc_mi != NULL) {
2719		m = sc->dc_mi->dc_next;
2720		free(sc->dc_mi, M_DEVBUF);
2721		sc->dc_mi = m;
2722	}
2723	free(sc->dc_srom, M_DEVBUF);
2724
2725	mtx_destroy(&sc->dc_mtx);
2726
2727	return (0);
2728}
2729
2730/*
2731 * Initialize the transmit descriptors.
2732 */
2733static int
2734dc_list_tx_init(struct dc_softc *sc)
2735{
2736	struct dc_chain_data *cd;
2737	struct dc_list_data *ld;
2738	int i, nexti;
2739
2740	cd = &sc->dc_cdata;
2741	ld = &sc->dc_ldata;
2742	for (i = 0; i < DC_TX_LIST_CNT; i++) {
2743		if (i == DC_TX_LIST_CNT - 1)
2744			nexti = 0;
2745		else
2746			nexti = i + 1;
2747		ld->dc_tx_list[i].dc_status = 0;
2748		ld->dc_tx_list[i].dc_ctl = 0;
2749		ld->dc_tx_list[i].dc_data = 0;
2750		ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti));
2751		cd->dc_tx_chain[i] = NULL;
2752	}
2753
2754	cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2755	cd->dc_tx_pkts = 0;
2756	bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
2757	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2758	return (0);
2759}
2760
2761
2762/*
2763 * Initialize the RX descriptors and allocate mbufs for them. Note that
2764 * we arrange the descriptors in a closed ring, so that the last descriptor
2765 * points back to the first.
2766 */
2767static int
2768dc_list_rx_init(struct dc_softc *sc)
2769{
2770	struct dc_chain_data *cd;
2771	struct dc_list_data *ld;
2772	int i, nexti;
2773
2774	cd = &sc->dc_cdata;
2775	ld = &sc->dc_ldata;
2776
2777	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2778		if (dc_newbuf(sc, i) != 0)
2779			return (ENOBUFS);
2780		if (i == DC_RX_LIST_CNT - 1)
2781			nexti = 0;
2782		else
2783			nexti = i + 1;
2784		ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti));
2785	}
2786
2787	cd->dc_rx_prod = 0;
2788	bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
2789	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2790	return (0);
2791}
2792
2793/*
2794 * Initialize an RX descriptor and attach an MBUF cluster.
2795 */
2796static int
2797dc_newbuf(struct dc_softc *sc, int i)
2798{
2799	struct mbuf *m;
2800	bus_dmamap_t map;
2801	bus_dma_segment_t segs[1];
2802	int error, nseg;
2803
2804	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2805	if (m == NULL)
2806		return (ENOBUFS);
2807	m->m_len = m->m_pkthdr.len = MCLBYTES;
2808	m_adj(m, sizeof(u_int64_t));
2809
2810	/*
2811	 * If this is a PNIC chip, zero the buffer. This is part
2812	 * of the workaround for the receive bug in the 82c168 and
2813	 * 82c169 chips.
2814	 */
2815	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2816		bzero(mtod(m, char *), m->m_len);
2817
2818	error = bus_dmamap_load_mbuf_sg(sc->dc_rx_mtag, sc->dc_sparemap,
2819	    m, segs, &nseg, 0);
2820	if (error) {
2821		m_freem(m);
2822		return (error);
2823	}
2824	KASSERT(nseg == 1, ("%s: wrong number of segments (%d)", __func__,
2825	    nseg));
2826	if (sc->dc_cdata.dc_rx_chain[i] != NULL)
2827		bus_dmamap_unload(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i]);
2828
2829	map = sc->dc_cdata.dc_rx_map[i];
2830	sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap;
2831	sc->dc_sparemap = map;
2832	sc->dc_cdata.dc_rx_chain[i] = m;
2833	bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i],
2834	    BUS_DMASYNC_PREREAD);
2835
2836	sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2837	sc->dc_ldata.dc_rx_list[i].dc_data =
2838	    htole32(DC_ADDR_LO(segs[0].ds_addr));
2839	sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
2840	bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
2841	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2842	return (0);
2843}
2844
2845/*
2846 * Grrrrr.
2847 * The PNIC chip has a terrible bug in it that manifests itself during
2848 * periods of heavy activity. The exact mode of failure if difficult to
2849 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2850 * will happen on slow machines. The bug is that sometimes instead of
2851 * uploading one complete frame during reception, it uploads what looks
2852 * like the entire contents of its FIFO memory. The frame we want is at
2853 * the end of the whole mess, but we never know exactly how much data has
2854 * been uploaded, so salvaging the frame is hard.
2855 *
2856 * There is only one way to do it reliably, and it's disgusting.
2857 * Here's what we know:
2858 *
2859 * - We know there will always be somewhere between one and three extra
2860 *   descriptors uploaded.
2861 *
2862 * - We know the desired received frame will always be at the end of the
2863 *   total data upload.
2864 *
2865 * - We know the size of the desired received frame because it will be
2866 *   provided in the length field of the status word in the last descriptor.
2867 *
2868 * Here's what we do:
2869 *
2870 * - When we allocate buffers for the receive ring, we bzero() them.
2871 *   This means that we know that the buffer contents should be all
2872 *   zeros, except for data uploaded by the chip.
2873 *
2874 * - We also force the PNIC chip to upload frames that include the
2875 *   ethernet CRC at the end.
2876 *
2877 * - We gather all of the bogus frame data into a single buffer.
2878 *
2879 * - We then position a pointer at the end of this buffer and scan
2880 *   backwards until we encounter the first non-zero byte of data.
2881 *   This is the end of the received frame. We know we will encounter
2882 *   some data at the end of the frame because the CRC will always be
2883 *   there, so even if the sender transmits a packet of all zeros,
2884 *   we won't be fooled.
2885 *
2886 * - We know the size of the actual received frame, so we subtract
2887 *   that value from the current pointer location. This brings us
2888 *   to the start of the actual received packet.
2889 *
2890 * - We copy this into an mbuf and pass it on, along with the actual
2891 *   frame length.
2892 *
2893 * The performance hit is tremendous, but it beats dropping frames all
2894 * the time.
2895 */
2896
2897#define	DC_WHOLEFRAME	(DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG)
2898static void
2899dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2900{
2901	struct dc_desc *cur_rx;
2902	struct dc_desc *c = NULL;
2903	struct mbuf *m = NULL;
2904	unsigned char *ptr;
2905	int i, total_len;
2906	uint32_t rxstat = 0;
2907
2908	i = sc->dc_pnic_rx_bug_save;
2909	cur_rx = &sc->dc_ldata.dc_rx_list[idx];
2910	ptr = sc->dc_pnic_rx_buf;
2911	bzero(ptr, DC_RXLEN * 5);
2912
2913	/* Copy all the bytes from the bogus buffers. */
2914	while (1) {
2915		c = &sc->dc_ldata.dc_rx_list[i];
2916		rxstat = le32toh(c->dc_status);
2917		m = sc->dc_cdata.dc_rx_chain[i];
2918		bcopy(mtod(m, char *), ptr, DC_RXLEN);
2919		ptr += DC_RXLEN;
2920		/* If this is the last buffer, break out. */
2921		if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2922			break;
2923		dc_discard_rxbuf(sc, i);
2924		DC_INC(i, DC_RX_LIST_CNT);
2925	}
2926
2927	/* Find the length of the actual receive frame. */
2928	total_len = DC_RXBYTES(rxstat);
2929
2930	/* Scan backwards until we hit a non-zero byte. */
2931	while (*ptr == 0x00)
2932		ptr--;
2933
2934	/* Round off. */
2935	if ((uintptr_t)(ptr) & 0x3)
2936		ptr -= 1;
2937
2938	/* Now find the start of the frame. */
2939	ptr -= total_len;
2940	if (ptr < sc->dc_pnic_rx_buf)
2941		ptr = sc->dc_pnic_rx_buf;
2942
2943	/*
2944	 * Now copy the salvaged frame to the last mbuf and fake up
2945	 * the status word to make it look like a successful
2946	 * frame reception.
2947	 */
2948	bcopy(ptr, mtod(m, char *), total_len);
2949	cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
2950}
2951
2952/*
2953 * This routine searches the RX ring for dirty descriptors in the
2954 * event that the rxeof routine falls out of sync with the chip's
2955 * current descriptor pointer. This may happen sometimes as a result
2956 * of a "no RX buffer available" condition that happens when the chip
2957 * consumes all of the RX buffers before the driver has a chance to
2958 * process the RX ring. This routine may need to be called more than
2959 * once to bring the driver back in sync with the chip, however we
2960 * should still be getting RX DONE interrupts to drive the search
2961 * for new packets in the RX ring, so we should catch up eventually.
2962 */
2963static int
2964dc_rx_resync(struct dc_softc *sc)
2965{
2966	struct dc_desc *cur_rx;
2967	int i, pos;
2968
2969	pos = sc->dc_cdata.dc_rx_prod;
2970
2971	for (i = 0; i < DC_RX_LIST_CNT; i++) {
2972		cur_rx = &sc->dc_ldata.dc_rx_list[pos];
2973		if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN))
2974			break;
2975		DC_INC(pos, DC_RX_LIST_CNT);
2976	}
2977
2978	/* If the ring really is empty, then just return. */
2979	if (i == DC_RX_LIST_CNT)
2980		return (0);
2981
2982	/* We've fallen behing the chip: catch it. */
2983	sc->dc_cdata.dc_rx_prod = pos;
2984
2985	return (EAGAIN);
2986}
2987
2988static void
2989dc_discard_rxbuf(struct dc_softc *sc, int i)
2990{
2991	struct mbuf *m;
2992
2993	if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2994		m = sc->dc_cdata.dc_rx_chain[i];
2995		bzero(mtod(m, char *), m->m_len);
2996	}
2997
2998	sc->dc_ldata.dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN);
2999	sc->dc_ldata.dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN);
3000	bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_PREREAD |
3001	    BUS_DMASYNC_PREWRITE);
3002}
3003
3004/*
3005 * A frame has been uploaded: pass the resulting mbuf chain up to
3006 * the higher level protocols.
3007 */
3008static int
3009dc_rxeof(struct dc_softc *sc)
3010{
3011	struct mbuf *m;
3012	struct ifnet *ifp;
3013	struct dc_desc *cur_rx;
3014	int i, total_len, rx_npkts;
3015	uint32_t rxstat;
3016
3017	DC_LOCK_ASSERT(sc);
3018
3019	ifp = sc->dc_ifp;
3020	rx_npkts = 0;
3021
3022	bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap, BUS_DMASYNC_POSTREAD |
3023	    BUS_DMASYNC_POSTWRITE);
3024	for (i = sc->dc_cdata.dc_rx_prod;
3025	    (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
3026	    DC_INC(i, DC_RX_LIST_CNT)) {
3027#ifdef DEVICE_POLLING
3028		if (ifp->if_capenable & IFCAP_POLLING) {
3029			if (sc->rxcycles <= 0)
3030				break;
3031			sc->rxcycles--;
3032		}
3033#endif
3034		cur_rx = &sc->dc_ldata.dc_rx_list[i];
3035		rxstat = le32toh(cur_rx->dc_status);
3036		if ((rxstat & DC_RXSTAT_OWN) != 0)
3037			break;
3038		m = sc->dc_cdata.dc_rx_chain[i];
3039		bus_dmamap_sync(sc->dc_rx_mtag, sc->dc_cdata.dc_rx_map[i],
3040		    BUS_DMASYNC_POSTREAD);
3041		total_len = DC_RXBYTES(rxstat);
3042		rx_npkts++;
3043
3044		if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
3045			if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
3046				if (rxstat & DC_RXSTAT_FIRSTFRAG)
3047					sc->dc_pnic_rx_bug_save = i;
3048				if ((rxstat & DC_RXSTAT_LASTFRAG) == 0)
3049					continue;
3050				dc_pnic_rx_bug_war(sc, i);
3051				rxstat = le32toh(cur_rx->dc_status);
3052				total_len = DC_RXBYTES(rxstat);
3053			}
3054		}
3055
3056		/*
3057		 * If an error occurs, update stats, clear the
3058		 * status word and leave the mbuf cluster in place:
3059		 * it should simply get re-used next time this descriptor
3060		 * comes up in the ring.  However, don't report long
3061		 * frames as errors since they could be vlans.
3062		 */
3063		if ((rxstat & DC_RXSTAT_RXERR)) {
3064			if (!(rxstat & DC_RXSTAT_GIANT) ||
3065			    (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
3066				       DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
3067				       DC_RXSTAT_RUNT   | DC_RXSTAT_DE))) {
3068				ifp->if_ierrors++;
3069				if (rxstat & DC_RXSTAT_COLLSEEN)
3070					ifp->if_collisions++;
3071				dc_discard_rxbuf(sc, i);
3072				if (rxstat & DC_RXSTAT_CRCERR)
3073					continue;
3074				else {
3075					ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3076					dc_init_locked(sc);
3077					return (rx_npkts);
3078				}
3079			}
3080		}
3081
3082		/* No errors; receive the packet. */
3083		total_len -= ETHER_CRC_LEN;
3084#ifdef __NO_STRICT_ALIGNMENT
3085		/*
3086		 * On architectures without alignment problems we try to
3087		 * allocate a new buffer for the receive ring, and pass up
3088		 * the one where the packet is already, saving the expensive
3089		 * copy done in m_devget().
3090		 * If we are on an architecture with alignment problems, or
3091		 * if the allocation fails, then use m_devget and leave the
3092		 * existing buffer in the receive ring.
3093		 */
3094		if (dc_newbuf(sc, i) != 0) {
3095			dc_discard_rxbuf(sc, i);
3096			ifp->if_iqdrops++;
3097			continue;
3098		}
3099		m->m_pkthdr.rcvif = ifp;
3100		m->m_pkthdr.len = m->m_len = total_len;
3101#else
3102		{
3103			struct mbuf *m0;
3104
3105			m0 = m_devget(mtod(m, char *), total_len,
3106				ETHER_ALIGN, ifp, NULL);
3107			dc_discard_rxbuf(sc, i);
3108			if (m0 == NULL) {
3109				ifp->if_iqdrops++;
3110				continue;
3111			}
3112			m = m0;
3113		}
3114#endif
3115
3116		ifp->if_ipackets++;
3117		DC_UNLOCK(sc);
3118		(*ifp->if_input)(ifp, m);
3119		DC_LOCK(sc);
3120	}
3121
3122	sc->dc_cdata.dc_rx_prod = i;
3123	return (rx_npkts);
3124}
3125
3126/*
3127 * A frame was downloaded to the chip. It's safe for us to clean up
3128 * the list buffers.
3129 */
3130static void
3131dc_txeof(struct dc_softc *sc)
3132{
3133	struct dc_desc *cur_tx;
3134	struct ifnet *ifp;
3135	int idx, setup;
3136	uint32_t ctl, txstat;
3137
3138	if (sc->dc_cdata.dc_tx_cnt == 0)
3139		return;
3140
3141	ifp = sc->dc_ifp;
3142
3143	/*
3144	 * Go through our tx list and free mbufs for those
3145	 * frames that have been transmitted.
3146	 */
3147	bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap, BUS_DMASYNC_POSTREAD |
3148	    BUS_DMASYNC_POSTWRITE);
3149	setup = 0;
3150	for (idx = sc->dc_cdata.dc_tx_cons; idx != sc->dc_cdata.dc_tx_prod;
3151	    DC_INC(idx, DC_TX_LIST_CNT), sc->dc_cdata.dc_tx_cnt--) {
3152		cur_tx = &sc->dc_ldata.dc_tx_list[idx];
3153		txstat = le32toh(cur_tx->dc_status);
3154		ctl = le32toh(cur_tx->dc_ctl);
3155
3156		if (txstat & DC_TXSTAT_OWN)
3157			break;
3158
3159		if (sc->dc_cdata.dc_tx_chain[idx] == NULL)
3160			continue;
3161
3162		if (ctl & DC_TXCTL_SETUP) {
3163			cur_tx->dc_ctl = htole32(ctl & ~DC_TXCTL_SETUP);
3164			setup++;
3165			bus_dmamap_sync(sc->dc_stag, sc->dc_smap,
3166			    BUS_DMASYNC_POSTWRITE);
3167			/*
3168			 * Yes, the PNIC is so brain damaged
3169			 * that it will sometimes generate a TX
3170			 * underrun error while DMAing the RX
3171			 * filter setup frame. If we detect this,
3172			 * we have to send the setup frame again,
3173			 * or else the filter won't be programmed
3174			 * correctly.
3175			 */
3176			if (DC_IS_PNIC(sc)) {
3177				if (txstat & DC_TXSTAT_ERRSUM)
3178					dc_setfilt(sc);
3179			}
3180			sc->dc_cdata.dc_tx_chain[idx] = NULL;
3181			continue;
3182		}
3183
3184		if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
3185			/*
3186			 * XXX: Why does my Xircom taunt me so?
3187			 * For some reason it likes setting the CARRLOST flag
3188			 * even when the carrier is there. wtf?!?
3189			 * Who knows, but Conexant chips have the
3190			 * same problem. Maybe they took lessons
3191			 * from Xircom.
3192			 */
3193			if (/*sc->dc_type == DC_TYPE_21143 &&*/
3194			    sc->dc_pmode == DC_PMODE_MII &&
3195			    ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
3196			    DC_TXSTAT_NOCARRIER)))
3197				txstat &= ~DC_TXSTAT_ERRSUM;
3198		} else {
3199			if (/*sc->dc_type == DC_TYPE_21143 &&*/
3200			    sc->dc_pmode == DC_PMODE_MII &&
3201			    ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM |
3202			    DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST)))
3203				txstat &= ~DC_TXSTAT_ERRSUM;
3204		}
3205
3206		if (txstat & DC_TXSTAT_ERRSUM) {
3207			ifp->if_oerrors++;
3208			if (txstat & DC_TXSTAT_EXCESSCOLL)
3209				ifp->if_collisions++;
3210			if (txstat & DC_TXSTAT_LATECOLL)
3211				ifp->if_collisions++;
3212			if (!(txstat & DC_TXSTAT_UNDERRUN)) {
3213				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3214				dc_init_locked(sc);
3215				return;
3216			}
3217		} else
3218			ifp->if_opackets++;
3219		ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
3220
3221		bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx],
3222		    BUS_DMASYNC_POSTWRITE);
3223		bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]);
3224		m_freem(sc->dc_cdata.dc_tx_chain[idx]);
3225		sc->dc_cdata.dc_tx_chain[idx] = NULL;
3226	}
3227	sc->dc_cdata.dc_tx_cons = idx;
3228
3229	if (sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3230		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3231		if (sc->dc_cdata.dc_tx_cnt == 0)
3232			sc->dc_wdog_timer = 0;
3233	}
3234	if (setup > 0)
3235		bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
3236		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3237}
3238
3239static void
3240dc_tick(void *xsc)
3241{
3242	struct dc_softc *sc;
3243	struct mii_data *mii;
3244	struct ifnet *ifp;
3245	uint32_t r;
3246
3247	sc = xsc;
3248	DC_LOCK_ASSERT(sc);
3249	ifp = sc->dc_ifp;
3250	mii = device_get_softc(sc->dc_miibus);
3251
3252	/*
3253	 * Reclaim transmitted frames for controllers that do
3254	 * not generate TX completion interrupt for every frame.
3255	 */
3256	if (sc->dc_flags & DC_TX_USE_TX_INTR)
3257		dc_txeof(sc);
3258
3259	if (sc->dc_flags & DC_REDUCED_MII_POLL) {
3260		if (sc->dc_flags & DC_21143_NWAY) {
3261			r = CSR_READ_4(sc, DC_10BTSTAT);
3262			if (IFM_SUBTYPE(mii->mii_media_active) ==
3263			    IFM_100_TX && (r & DC_TSTAT_LS100)) {
3264				sc->dc_link = 0;
3265				mii_mediachg(mii);
3266			}
3267			if (IFM_SUBTYPE(mii->mii_media_active) ==
3268			    IFM_10_T && (r & DC_TSTAT_LS10)) {
3269				sc->dc_link = 0;
3270				mii_mediachg(mii);
3271			}
3272			if (sc->dc_link == 0)
3273				mii_tick(mii);
3274		} else {
3275			/*
3276			 * For NICs which never report DC_RXSTATE_WAIT, we
3277			 * have to bite the bullet...
3278			 */
3279			if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,
3280			    DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) &&
3281			    sc->dc_cdata.dc_tx_cnt == 0)
3282				mii_tick(mii);
3283		}
3284	} else
3285		mii_tick(mii);
3286
3287	/*
3288	 * When the init routine completes, we expect to be able to send
3289	 * packets right away, and in fact the network code will send a
3290	 * gratuitous ARP the moment the init routine marks the interface
3291	 * as running. However, even though the MAC may have been initialized,
3292	 * there may be a delay of a few seconds before the PHY completes
3293	 * autonegotiation and the link is brought up. Any transmissions
3294	 * made during that delay will be lost. Dealing with this is tricky:
3295	 * we can't just pause in the init routine while waiting for the
3296	 * PHY to come ready since that would bring the whole system to
3297	 * a screeching halt for several seconds.
3298	 *
3299	 * What we do here is prevent the TX start routine from sending
3300	 * any packets until a link has been established. After the
3301	 * interface has been initialized, the tick routine will poll
3302	 * the state of the PHY until the IFM_ACTIVE flag is set. Until
3303	 * that time, packets will stay in the send queue, and once the
3304	 * link comes up, they will be flushed out to the wire.
3305	 */
3306	if (sc->dc_link != 0 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3307		dc_start_locked(ifp);
3308
3309	if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
3310		callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3311	else
3312		callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3313}
3314
3315/*
3316 * A transmit underrun has occurred.  Back off the transmit threshold,
3317 * or switch to store and forward mode if we have to.
3318 */
3319static void
3320dc_tx_underrun(struct dc_softc *sc)
3321{
3322	uint32_t netcfg, isr;
3323	int i, reinit;
3324
3325	reinit = 0;
3326	netcfg = CSR_READ_4(sc, DC_NETCFG);
3327	device_printf(sc->dc_dev, "TX underrun -- ");
3328	if ((sc->dc_flags & DC_TX_STORENFWD) == 0) {
3329		if (sc->dc_txthresh + DC_TXTHRESH_INC > DC_TXTHRESH_MAX) {
3330			printf("using store and forward mode\n");
3331			netcfg |= DC_NETCFG_STORENFWD;
3332		} else {
3333			printf("increasing TX threshold\n");
3334			sc->dc_txthresh += DC_TXTHRESH_INC;
3335			netcfg &= ~DC_NETCFG_TX_THRESH;
3336			netcfg |= sc->dc_txthresh;
3337		}
3338
3339		if (DC_IS_INTEL(sc)) {
3340			/*
3341			 * The real 21143 requires that the transmitter be idle
3342			 * in order to change the transmit threshold or store
3343			 * and forward state.
3344			 */
3345			CSR_WRITE_4(sc, DC_NETCFG, netcfg & ~DC_NETCFG_TX_ON);
3346
3347			for (i = 0; i < DC_TIMEOUT; i++) {
3348				isr = CSR_READ_4(sc, DC_ISR);
3349				if (isr & DC_ISR_TX_IDLE)
3350					break;
3351				DELAY(10);
3352			}
3353			if (i == DC_TIMEOUT) {
3354				device_printf(sc->dc_dev,
3355				    "%s: failed to force tx to idle state\n",
3356				    __func__);
3357				reinit++;
3358			}
3359		}
3360	} else {
3361		printf("resetting\n");
3362		reinit++;
3363	}
3364
3365	if (reinit == 0) {
3366		CSR_WRITE_4(sc, DC_NETCFG, netcfg);
3367		if (DC_IS_INTEL(sc))
3368			CSR_WRITE_4(sc, DC_NETCFG, netcfg | DC_NETCFG_TX_ON);
3369	} else {
3370		sc->dc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3371		dc_init_locked(sc);
3372	}
3373}
3374
3375#ifdef DEVICE_POLLING
3376static poll_handler_t dc_poll;
3377
3378static int
3379dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3380{
3381	struct dc_softc *sc = ifp->if_softc;
3382	int rx_npkts = 0;
3383
3384	DC_LOCK(sc);
3385
3386	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3387		DC_UNLOCK(sc);
3388		return (rx_npkts);
3389	}
3390
3391	sc->rxcycles = count;
3392	rx_npkts = dc_rxeof(sc);
3393	dc_txeof(sc);
3394	if (!IFQ_IS_EMPTY(&ifp->if_snd) &&
3395	    !(ifp->if_drv_flags & IFF_DRV_OACTIVE))
3396		dc_start_locked(ifp);
3397
3398	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
3399		uint32_t	status;
3400
3401		status = CSR_READ_4(sc, DC_ISR);
3402		status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF |
3403			DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN |
3404			DC_ISR_BUS_ERR);
3405		if (!status) {
3406			DC_UNLOCK(sc);
3407			return (rx_npkts);
3408		}
3409		/* ack what we have */
3410		CSR_WRITE_4(sc, DC_ISR, status);
3411
3412		if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) {
3413			uint32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3414			ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3415
3416			if (dc_rx_resync(sc))
3417				dc_rxeof(sc);
3418		}
3419		/* restart transmit unit if necessary */
3420		if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
3421			CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3422
3423		if (status & DC_ISR_TX_UNDERRUN)
3424			dc_tx_underrun(sc);
3425
3426		if (status & DC_ISR_BUS_ERR) {
3427			if_printf(ifp, "%s: bus error\n", __func__);
3428			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3429			dc_init_locked(sc);
3430		}
3431	}
3432	DC_UNLOCK(sc);
3433	return (rx_npkts);
3434}
3435#endif /* DEVICE_POLLING */
3436
3437static void
3438dc_intr(void *arg)
3439{
3440	struct dc_softc *sc;
3441	struct ifnet *ifp;
3442	uint32_t r, status;
3443	int n;
3444
3445	sc = arg;
3446
3447	if (sc->suspended)
3448		return;
3449
3450	DC_LOCK(sc);
3451	status = CSR_READ_4(sc, DC_ISR);
3452	if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0) {
3453		DC_UNLOCK(sc);
3454		return;
3455	}
3456	ifp = sc->dc_ifp;
3457#ifdef DEVICE_POLLING
3458	if (ifp->if_capenable & IFCAP_POLLING) {
3459		DC_UNLOCK(sc);
3460		return;
3461	}
3462#endif
3463	/* Disable interrupts. */
3464	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3465
3466	for (n = 16; n > 0; n--) {
3467		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3468			break;
3469		/* Ack interrupts. */
3470		CSR_WRITE_4(sc, DC_ISR, status);
3471
3472		if (status & DC_ISR_RX_OK) {
3473			if (dc_rxeof(sc) == 0) {
3474				while (dc_rx_resync(sc))
3475					dc_rxeof(sc);
3476			}
3477		}
3478
3479		if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF))
3480			dc_txeof(sc);
3481
3482		if (status & DC_ISR_TX_IDLE) {
3483			dc_txeof(sc);
3484			if (sc->dc_cdata.dc_tx_cnt) {
3485				DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3486				CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3487			}
3488		}
3489
3490		if (status & DC_ISR_TX_UNDERRUN)
3491			dc_tx_underrun(sc);
3492
3493		if ((status & DC_ISR_RX_WATDOGTIMEO)
3494		    || (status & DC_ISR_RX_NOBUF)) {
3495			r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
3496			ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
3497			if (dc_rxeof(sc) == 0) {
3498				while (dc_rx_resync(sc))
3499					dc_rxeof(sc);
3500			}
3501		}
3502
3503		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3504			dc_start_locked(ifp);
3505
3506		if (status & DC_ISR_BUS_ERR) {
3507			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3508			dc_init_locked(sc);
3509			DC_UNLOCK(sc);
3510			return;
3511		}
3512		status = CSR_READ_4(sc, DC_ISR);
3513		if (status == 0xFFFFFFFF || (status & DC_INTRS) == 0)
3514			break;
3515	}
3516
3517	/* Re-enable interrupts. */
3518	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3519		CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3520
3521	DC_UNLOCK(sc);
3522}
3523
3524/*
3525 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
3526 * pointers to the fragment pointers.
3527 */
3528static int
3529dc_encap(struct dc_softc *sc, struct mbuf **m_head)
3530{
3531	bus_dma_segment_t segs[DC_MAXFRAGS];
3532	bus_dmamap_t map;
3533	struct dc_desc *f;
3534	struct mbuf *m;
3535	int cur, defragged, error, first, frag, i, idx, nseg;
3536
3537	m = NULL;
3538	defragged = 0;
3539	if (sc->dc_flags & DC_TX_COALESCE &&
3540	    ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) {
3541		m = m_defrag(*m_head, M_DONTWAIT);
3542		defragged = 1;
3543	} else {
3544		/*
3545		 * Count the number of frags in this chain to see if we
3546		 * need to m_collapse.  Since the descriptor list is shared
3547		 * by all packets, we'll m_collapse long chains so that they
3548		 * do not use up the entire list, even if they would fit.
3549		 */
3550		i = 0;
3551		for (m = *m_head; m != NULL; m = m->m_next)
3552			i++;
3553		if (i > DC_TX_LIST_CNT / 4 ||
3554		    DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <=
3555		    DC_TX_LIST_RSVD) {
3556			m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS);
3557			defragged = 1;
3558		}
3559	}
3560	if (defragged != 0) {
3561		if (m == NULL) {
3562			m_freem(*m_head);
3563			*m_head = NULL;
3564			return (ENOBUFS);
3565		}
3566		*m_head = m;
3567	}
3568
3569	idx = sc->dc_cdata.dc_tx_prod;
3570	error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag,
3571	    sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3572	if (error == EFBIG) {
3573		if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT,
3574		    DC_MAXFRAGS)) == NULL) {
3575			m_freem(*m_head);
3576			*m_head = NULL;
3577			return (defragged != 0 ? error : ENOBUFS);
3578		}
3579		*m_head = m;
3580		error = bus_dmamap_load_mbuf_sg(sc->dc_tx_mtag,
3581		    sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0);
3582		if (error != 0) {
3583			m_freem(*m_head);
3584			*m_head = NULL;
3585			return (error);
3586		}
3587	} else if (error != 0)
3588		return (error);
3589	KASSERT(nseg <= DC_MAXFRAGS,
3590	    ("%s: wrong number of segments (%d)", __func__, nseg));
3591	if (nseg == 0) {
3592		m_freem(*m_head);
3593		*m_head = NULL;
3594		return (EIO);
3595	}
3596
3597	/* Check descriptor overruns. */
3598	if (sc->dc_cdata.dc_tx_cnt + nseg > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3599		bus_dmamap_unload(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx]);
3600		return (ENOBUFS);
3601	}
3602	bus_dmamap_sync(sc->dc_tx_mtag, sc->dc_cdata.dc_tx_map[idx],
3603	    BUS_DMASYNC_PREWRITE);
3604
3605	first = cur = frag = sc->dc_cdata.dc_tx_prod;
3606	for (i = 0; i < nseg; i++) {
3607		if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
3608		    (frag == (DC_TX_LIST_CNT - 1)) &&
3609		    (first != sc->dc_cdata.dc_tx_first)) {
3610			bus_dmamap_unload(sc->dc_tx_mtag,
3611			    sc->dc_cdata.dc_tx_map[first]);
3612			m_freem(*m_head);
3613			*m_head = NULL;
3614			return (ENOBUFS);
3615		}
3616
3617		f = &sc->dc_ldata.dc_tx_list[frag];
3618		f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len);
3619		if (i == 0) {
3620			f->dc_status = 0;
3621			f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG);
3622		} else
3623			f->dc_status = htole32(DC_TXSTAT_OWN);
3624		f->dc_data = htole32(DC_ADDR_LO(segs[i].ds_addr));
3625		cur = frag;
3626		DC_INC(frag, DC_TX_LIST_CNT);
3627	}
3628
3629	sc->dc_cdata.dc_tx_prod = frag;
3630	sc->dc_cdata.dc_tx_cnt += nseg;
3631	sc->dc_cdata.dc_tx_chain[cur] = *m_head;
3632	sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
3633	if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
3634		sc->dc_ldata.dc_tx_list[first].dc_ctl |=
3635		    htole32(DC_TXCTL_FINT);
3636	if (sc->dc_flags & DC_TX_INTR_ALWAYS)
3637		sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3638	if (sc->dc_flags & DC_TX_USE_TX_INTR &&
3639	    ++sc->dc_cdata.dc_tx_pkts >= 8) {
3640		sc->dc_cdata.dc_tx_pkts = 0;
3641		sc->dc_ldata.dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT);
3642	}
3643	sc->dc_ldata.dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN);
3644
3645	bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
3646	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3647
3648	/*
3649	 * Swap the last and the first dmamaps to ensure the map for
3650	 * this transmission is placed at the last descriptor.
3651	 */
3652	map = sc->dc_cdata.dc_tx_map[cur];
3653	sc->dc_cdata.dc_tx_map[cur] = sc->dc_cdata.dc_tx_map[first];
3654	sc->dc_cdata.dc_tx_map[first] = map;
3655
3656	return (0);
3657}
3658
3659static void
3660dc_start(struct ifnet *ifp)
3661{
3662	struct dc_softc *sc;
3663
3664	sc = ifp->if_softc;
3665	DC_LOCK(sc);
3666	dc_start_locked(ifp);
3667	DC_UNLOCK(sc);
3668}
3669
3670/*
3671 * Main transmit routine
3672 * To avoid having to do mbuf copies, we put pointers to the mbuf data
3673 * regions directly in the transmit lists.  We also save a copy of the
3674 * pointers since the transmit list fragment pointers are physical
3675 * addresses.
3676 */
3677static void
3678dc_start_locked(struct ifnet *ifp)
3679{
3680	struct dc_softc *sc;
3681	struct mbuf *m_head;
3682	int queued;
3683
3684	sc = ifp->if_softc;
3685
3686	DC_LOCK_ASSERT(sc);
3687
3688	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
3689	    IFF_DRV_RUNNING || sc->dc_link == 0)
3690		return;
3691
3692	sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod;
3693
3694	for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
3695		/*
3696		 * If there's no way we can send any packets, return now.
3697		 */
3698		if (sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_CNT - DC_TX_LIST_RSVD) {
3699			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3700			break;
3701		}
3702		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
3703		if (m_head == NULL)
3704			break;
3705
3706		if (dc_encap(sc, &m_head)) {
3707			if (m_head == NULL)
3708				break;
3709			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
3710			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3711			break;
3712		}
3713
3714		queued++;
3715		/*
3716		 * If there's a BPF listener, bounce a copy of this frame
3717		 * to him.
3718		 */
3719		BPF_MTAP(ifp, m_head);
3720	}
3721
3722	if (queued > 0) {
3723		/* Transmit */
3724		if (!(sc->dc_flags & DC_TX_POLL))
3725			CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3726
3727		/*
3728		 * Set a timeout in case the chip goes out to lunch.
3729		 */
3730		sc->dc_wdog_timer = 5;
3731	}
3732}
3733
3734static void
3735dc_init(void *xsc)
3736{
3737	struct dc_softc *sc = xsc;
3738
3739	DC_LOCK(sc);
3740	dc_init_locked(sc);
3741	DC_UNLOCK(sc);
3742}
3743
3744static void
3745dc_init_locked(struct dc_softc *sc)
3746{
3747	struct ifnet *ifp = sc->dc_ifp;
3748	struct mii_data *mii;
3749	struct ifmedia *ifm;
3750
3751	DC_LOCK_ASSERT(sc);
3752
3753	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3754		return;
3755
3756	mii = device_get_softc(sc->dc_miibus);
3757
3758	/*
3759	 * Cancel pending I/O and free all RX/TX buffers.
3760	 */
3761	dc_stop(sc);
3762	dc_reset(sc);
3763	if (DC_IS_INTEL(sc)) {
3764		ifm = &mii->mii_media;
3765		dc_apply_fixup(sc, ifm->ifm_media);
3766	}
3767
3768	/*
3769	 * Set cache alignment and burst length.
3770	 */
3771	if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc) || DC_IS_ULI(sc))
3772		CSR_WRITE_4(sc, DC_BUSCTL, 0);
3773	else
3774		CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE);
3775	/*
3776	 * Evenly share the bus between receive and transmit process.
3777	 */
3778	if (DC_IS_INTEL(sc))
3779		DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3780	if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3781		DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3782	} else {
3783		DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3784	}
3785	if (sc->dc_flags & DC_TX_POLL)
3786		DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3787	switch(sc->dc_cachesize) {
3788	case 32:
3789		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3790		break;
3791	case 16:
3792		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3793		break;
3794	case 8:
3795		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3796		break;
3797	case 0:
3798	default:
3799		DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3800		break;
3801	}
3802
3803	if (sc->dc_flags & DC_TX_STORENFWD)
3804		DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3805	else {
3806		if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3807			DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3808		} else {
3809			DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3810			DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3811		}
3812	}
3813
3814	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3815	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3816
3817	if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3818		/*
3819		 * The app notes for the 98713 and 98715A say that
3820		 * in order to have the chips operate properly, a magic
3821		 * number must be written to CSR16. Macronix does not
3822		 * document the meaning of these bits so there's no way
3823		 * to know exactly what they do. The 98713 has a magic
3824		 * number all its own; the rest all use a different one.
3825		 */
3826		DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3827		if (sc->dc_type == DC_TYPE_98713)
3828			DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3829		else
3830			DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3831	}
3832
3833	if (DC_IS_XIRCOM(sc)) {
3834		/*
3835		 * setup General Purpose Port mode and data so the tulip
3836		 * can talk to the MII.
3837		 */
3838		CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
3839			   DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3840		DELAY(10);
3841		CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
3842			   DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT);
3843		DELAY(10);
3844	}
3845
3846	DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3847	DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3848
3849	/* Init circular RX list. */
3850	if (dc_list_rx_init(sc) == ENOBUFS) {
3851		device_printf(sc->dc_dev,
3852		    "initialization failed: no memory for rx buffers\n");
3853		dc_stop(sc);
3854		return;
3855	}
3856
3857	/*
3858	 * Init TX descriptors.
3859	 */
3860	dc_list_tx_init(sc);
3861
3862	/*
3863	 * Load the address of the RX list.
3864	 */
3865	CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0));
3866	CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0));
3867
3868	/*
3869	 * Enable interrupts.
3870	 */
3871#ifdef DEVICE_POLLING
3872	/*
3873	 * ... but only if we are not polling, and make sure they are off in
3874	 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3875	 * after a reset.
3876	 */
3877	if (ifp->if_capenable & IFCAP_POLLING)
3878		CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3879	else
3880#endif
3881	CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3882	CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3883
3884	/* Initialize TX jabber and RX watchdog timer. */
3885	if (DC_IS_ULI(sc))
3886		CSR_WRITE_4(sc, DC_WATCHDOG, DC_WDOG_JABBERCLK |
3887		    DC_WDOG_HOSTUNJAB);
3888
3889	/* Enable transmitter. */
3890	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3891
3892	/*
3893	 * If this is an Intel 21143 and we're not using the
3894	 * MII port, program the LED control pins so we get
3895	 * link and activity indications.
3896	 */
3897	if (sc->dc_flags & DC_TULIP_LEDS) {
3898		CSR_WRITE_4(sc, DC_WATCHDOG,
3899		    DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY);
3900		CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3901	}
3902
3903	/*
3904	 * Load the RX/multicast filter. We do this sort of late
3905	 * because the filter programming scheme on the 21143 and
3906	 * some clones requires DMAing a setup frame via the TX
3907	 * engine, and we need the transmitter enabled for that.
3908	 */
3909	dc_setfilt(sc);
3910
3911	/* Enable receiver. */
3912	DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3913	CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3914
3915	ifp->if_drv_flags |= IFF_DRV_RUNNING;
3916	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3917
3918	dc_ifmedia_upd_locked(sc);
3919
3920	/* Clear missed frames and overflow counter. */
3921	CSR_READ_4(sc, DC_FRAMESDISCARDED);
3922
3923	/* Don't start the ticker if this is a homePNA link. */
3924	if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3925		sc->dc_link = 1;
3926	else {
3927		if (sc->dc_flags & DC_21143_NWAY)
3928			callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc);
3929		else
3930			callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc);
3931	}
3932
3933	sc->dc_wdog_timer = 0;
3934	callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
3935}
3936
3937/*
3938 * Set media options.
3939 */
3940static int
3941dc_ifmedia_upd(struct ifnet *ifp)
3942{
3943	struct dc_softc *sc;
3944	int error;
3945
3946	sc = ifp->if_softc;
3947	DC_LOCK(sc);
3948	error = dc_ifmedia_upd_locked(sc);
3949	DC_UNLOCK(sc);
3950	return (error);
3951}
3952
3953static int
3954dc_ifmedia_upd_locked(struct dc_softc *sc)
3955{
3956	struct mii_data *mii;
3957	struct ifmedia *ifm;
3958	int error;
3959
3960	DC_LOCK_ASSERT(sc);
3961
3962	sc->dc_link = 0;
3963	mii = device_get_softc(sc->dc_miibus);
3964	error = mii_mediachg(mii);
3965	if (error == 0) {
3966		ifm = &mii->mii_media;
3967		if (DC_IS_INTEL(sc))
3968			dc_setcfg(sc, ifm->ifm_media);
3969		else if (DC_IS_DAVICOM(sc) &&
3970		    IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3971			dc_setcfg(sc, ifm->ifm_media);
3972	}
3973
3974	return (error);
3975}
3976
3977/*
3978 * Report current media status.
3979 */
3980static void
3981dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3982{
3983	struct dc_softc *sc;
3984	struct mii_data *mii;
3985	struct ifmedia *ifm;
3986
3987	sc = ifp->if_softc;
3988	mii = device_get_softc(sc->dc_miibus);
3989	DC_LOCK(sc);
3990	mii_pollstat(mii);
3991	ifm = &mii->mii_media;
3992	if (DC_IS_DAVICOM(sc)) {
3993		if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3994			ifmr->ifm_active = ifm->ifm_media;
3995			ifmr->ifm_status = 0;
3996			DC_UNLOCK(sc);
3997			return;
3998		}
3999	}
4000	ifmr->ifm_active = mii->mii_media_active;
4001	ifmr->ifm_status = mii->mii_media_status;
4002	DC_UNLOCK(sc);
4003}
4004
4005static int
4006dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4007{
4008	struct dc_softc *sc = ifp->if_softc;
4009	struct ifreq *ifr = (struct ifreq *)data;
4010	struct mii_data *mii;
4011	int error = 0;
4012
4013	switch (command) {
4014	case SIOCSIFFLAGS:
4015		DC_LOCK(sc);
4016		if (ifp->if_flags & IFF_UP) {
4017			int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
4018				(IFF_PROMISC | IFF_ALLMULTI);
4019
4020			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4021				if (need_setfilt)
4022					dc_setfilt(sc);
4023			} else {
4024				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4025				dc_init_locked(sc);
4026			}
4027		} else {
4028			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4029				dc_stop(sc);
4030		}
4031		sc->dc_if_flags = ifp->if_flags;
4032		DC_UNLOCK(sc);
4033		break;
4034	case SIOCADDMULTI:
4035	case SIOCDELMULTI:
4036		DC_LOCK(sc);
4037		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4038			dc_setfilt(sc);
4039		DC_UNLOCK(sc);
4040		break;
4041	case SIOCGIFMEDIA:
4042	case SIOCSIFMEDIA:
4043		mii = device_get_softc(sc->dc_miibus);
4044		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
4045		break;
4046	case SIOCSIFCAP:
4047#ifdef DEVICE_POLLING
4048		if (ifr->ifr_reqcap & IFCAP_POLLING &&
4049		    !(ifp->if_capenable & IFCAP_POLLING)) {
4050			error = ether_poll_register(dc_poll, ifp);
4051			if (error)
4052				return(error);
4053			DC_LOCK(sc);
4054			/* Disable interrupts */
4055			CSR_WRITE_4(sc, DC_IMR, 0x00000000);
4056			ifp->if_capenable |= IFCAP_POLLING;
4057			DC_UNLOCK(sc);
4058			return (error);
4059		}
4060		if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
4061		    ifp->if_capenable & IFCAP_POLLING) {
4062			error = ether_poll_deregister(ifp);
4063			/* Enable interrupts. */
4064			DC_LOCK(sc);
4065			CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
4066			ifp->if_capenable &= ~IFCAP_POLLING;
4067			DC_UNLOCK(sc);
4068			return (error);
4069		}
4070#endif /* DEVICE_POLLING */
4071		break;
4072	default:
4073		error = ether_ioctl(ifp, command, data);
4074		break;
4075	}
4076
4077	return (error);
4078}
4079
4080static void
4081dc_watchdog(void *xsc)
4082{
4083	struct dc_softc *sc = xsc;
4084	struct ifnet *ifp;
4085
4086	DC_LOCK_ASSERT(sc);
4087
4088	if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) {
4089		callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc);
4090		return;
4091	}
4092
4093	ifp = sc->dc_ifp;
4094	ifp->if_oerrors++;
4095	device_printf(sc->dc_dev, "watchdog timeout\n");
4096
4097	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4098	dc_init_locked(sc);
4099
4100	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4101		dc_start_locked(ifp);
4102}
4103
4104/*
4105 * Stop the adapter and free any mbufs allocated to the
4106 * RX and TX lists.
4107 */
4108static void
4109dc_stop(struct dc_softc *sc)
4110{
4111	struct ifnet *ifp;
4112	struct dc_list_data *ld;
4113	struct dc_chain_data *cd;
4114	int i;
4115	uint32_t ctl, netcfg;
4116
4117	DC_LOCK_ASSERT(sc);
4118
4119	ifp = sc->dc_ifp;
4120	ld = &sc->dc_ldata;
4121	cd = &sc->dc_cdata;
4122
4123	callout_stop(&sc->dc_stat_ch);
4124	callout_stop(&sc->dc_wdog_ch);
4125	sc->dc_wdog_timer = 0;
4126	sc->dc_link = 0;
4127
4128	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4129
4130	netcfg = CSR_READ_4(sc, DC_NETCFG);
4131	if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON))
4132		CSR_WRITE_4(sc, DC_NETCFG,
4133		   netcfg & ~(DC_NETCFG_RX_ON | DC_NETCFG_TX_ON));
4134	CSR_WRITE_4(sc, DC_IMR, 0x00000000);
4135	/* Wait the completion of TX/RX SM. */
4136	if (netcfg & (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON))
4137		dc_netcfg_wait(sc);
4138
4139	CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
4140	CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
4141
4142	/*
4143	 * Free data in the RX lists.
4144	 */
4145	for (i = 0; i < DC_RX_LIST_CNT; i++) {
4146		if (cd->dc_rx_chain[i] != NULL) {
4147			bus_dmamap_sync(sc->dc_rx_mtag,
4148			    cd->dc_rx_map[i], BUS_DMASYNC_POSTREAD);
4149			bus_dmamap_unload(sc->dc_rx_mtag,
4150			    cd->dc_rx_map[i]);
4151			m_freem(cd->dc_rx_chain[i]);
4152			cd->dc_rx_chain[i] = NULL;
4153		}
4154	}
4155	bzero(ld->dc_rx_list, DC_RX_LIST_SZ);
4156	bus_dmamap_sync(sc->dc_rx_ltag, sc->dc_rx_lmap,
4157	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4158
4159	/*
4160	 * Free the TX list buffers.
4161	 */
4162	for (i = 0; i < DC_TX_LIST_CNT; i++) {
4163		if (cd->dc_tx_chain[i] != NULL) {
4164			ctl = le32toh(ld->dc_tx_list[i].dc_ctl);
4165			if (ctl & DC_TXCTL_SETUP) {
4166				bus_dmamap_sync(sc->dc_stag, sc->dc_smap,
4167				    BUS_DMASYNC_POSTWRITE);
4168			} else {
4169				bus_dmamap_sync(sc->dc_tx_mtag,
4170				    cd->dc_tx_map[i], BUS_DMASYNC_POSTWRITE);
4171				bus_dmamap_unload(sc->dc_tx_mtag,
4172				    cd->dc_tx_map[i]);
4173				m_freem(cd->dc_tx_chain[i]);
4174			}
4175			cd->dc_tx_chain[i] = NULL;
4176		}
4177	}
4178	bzero(ld->dc_tx_list, DC_TX_LIST_SZ);
4179	bus_dmamap_sync(sc->dc_tx_ltag, sc->dc_tx_lmap,
4180	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4181}
4182
4183/*
4184 * Device suspend routine.  Stop the interface and save some PCI
4185 * settings in case the BIOS doesn't restore them properly on
4186 * resume.
4187 */
4188static int
4189dc_suspend(device_t dev)
4190{
4191	struct dc_softc *sc;
4192
4193	sc = device_get_softc(dev);
4194	DC_LOCK(sc);
4195	dc_stop(sc);
4196	sc->suspended = 1;
4197	DC_UNLOCK(sc);
4198
4199	return (0);
4200}
4201
4202/*
4203 * Device resume routine.  Restore some PCI settings in case the BIOS
4204 * doesn't, re-enable busmastering, and restart the interface if
4205 * appropriate.
4206 */
4207static int
4208dc_resume(device_t dev)
4209{
4210	struct dc_softc *sc;
4211	struct ifnet *ifp;
4212
4213	sc = device_get_softc(dev);
4214	ifp = sc->dc_ifp;
4215
4216	/* reinitialize interface if necessary */
4217	DC_LOCK(sc);
4218	if (ifp->if_flags & IFF_UP)
4219		dc_init_locked(sc);
4220
4221	sc->suspended = 0;
4222	DC_UNLOCK(sc);
4223
4224	return (0);
4225}
4226
4227/*
4228 * Stop all chip I/O so that the kernel's probe routines don't
4229 * get confused by errant DMAs when rebooting.
4230 */
4231static int
4232dc_shutdown(device_t dev)
4233{
4234	struct dc_softc *sc;
4235
4236	sc = device_get_softc(dev);
4237
4238	DC_LOCK(sc);
4239	dc_stop(sc);
4240	DC_UNLOCK(sc);
4241
4242	return (0);
4243}
4244
4245static int
4246dc_check_multiport(struct dc_softc *sc)
4247{
4248	struct dc_softc *dsc;
4249	devclass_t dc;
4250	device_t child;
4251	uint8_t *eaddr;
4252	int unit;
4253
4254	dc = devclass_find("dc");
4255	for (unit = 0; unit < devclass_get_maxunit(dc); unit++) {
4256		child = devclass_get_device(dc, unit);
4257		if (child == NULL)
4258			continue;
4259		if (child == sc->dc_dev)
4260			continue;
4261		if (device_get_parent(child) != device_get_parent(sc->dc_dev))
4262			continue;
4263		if (unit > device_get_unit(sc->dc_dev))
4264			continue;
4265		if (device_is_attached(child) == 0)
4266			continue;
4267		dsc = device_get_softc(child);
4268		device_printf(sc->dc_dev,
4269		    "Using station address of %s as base\n",
4270		    device_get_nameunit(child));
4271		bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN);
4272		eaddr = (uint8_t *)sc->dc_eaddr;
4273		eaddr[5]++;
4274		/* Prepare SROM to parse again. */
4275		if (DC_IS_INTEL(sc) && dsc->dc_srom != NULL &&
4276		    sc->dc_romwidth != 0) {
4277			free(sc->dc_srom, M_DEVBUF);
4278			sc->dc_romwidth = dsc->dc_romwidth;
4279			sc->dc_srom = malloc(DC_ROM_SIZE(sc->dc_romwidth),
4280			    M_DEVBUF, M_NOWAIT);
4281			if (sc->dc_srom == NULL) {
4282				device_printf(sc->dc_dev,
4283				    "Could not allocate SROM buffer\n");
4284				return (ENOMEM);
4285			}
4286			bcopy(dsc->dc_srom, sc->dc_srom,
4287			    DC_ROM_SIZE(sc->dc_romwidth));
4288		}
4289		return (0);
4290	}
4291	return (ENOENT);
4292}
4293