if_dc.c revision 218786
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/dc/if_dc.c 218786 2011-02-18 01:56:25Z yongari $"); 35 36/* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN983 (www.admtek.com.tw) 47 * ADMtek CardBus AN985 (www.admtek.com.tw) 48 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek CardBus AN985 49 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 50 * Accton EN1217 (www.accton.com) 51 * Xircom X3201 (www.xircom.com) 52 * Abocom FE2500 53 * Conexant LANfinity (www.conexant.com) 54 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 55 * 56 * Datasheets for the 21143 are available at developer.intel.com. 57 * Datasheets for the clone parts can be found at their respective sites. 58 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 59 * The PNIC II is essentially a Macronix 98715A chip; the only difference 60 * worth noting is that its multicast hash table is only 128 bits wide 61 * instead of 512. 62 * 63 * Written by Bill Paul <wpaul@ee.columbia.edu> 64 * Electrical Engineering Department 65 * Columbia University, New York City 66 */ 67/* 68 * The Intel 21143 is the successor to the DEC 21140. It is basically 69 * the same as the 21140 but with a few new features. The 21143 supports 70 * three kinds of media attachments: 71 * 72 * o MII port, for 10Mbps and 100Mbps support and NWAY 73 * autonegotiation provided by an external PHY. 74 * o SYM port, for symbol mode 100Mbps support. 75 * o 10baseT port. 76 * o AUI/BNC port. 77 * 78 * The 100Mbps SYM port and 10baseT port can be used together in 79 * combination with the internal NWAY support to create a 10/100 80 * autosensing configuration. 81 * 82 * Note that not all tulip workalikes are handled in this driver: we only 83 * deal with those which are relatively well behaved. The Winbond is 84 * handled separately due to its different register offsets and the 85 * special handling needed for its various bugs. The PNIC is handled 86 * here, but I'm not thrilled about it. 87 * 88 * All of the workalike chips use some form of MII transceiver support 89 * with the exception of the Macronix chips, which also have a SYM port. 90 * The ASIX AX88140A is also documented to have a SYM port, but all 91 * the cards I've seen use an MII transceiver, probably because the 92 * AX88140A doesn't support internal NWAY. 93 */ 94 95#ifdef HAVE_KERNEL_OPTION_HEADERS 96#include "opt_device_polling.h" 97#endif 98 99#include <sys/param.h> 100#include <sys/endian.h> 101#include <sys/systm.h> 102#include <sys/sockio.h> 103#include <sys/mbuf.h> 104#include <sys/malloc.h> 105#include <sys/kernel.h> 106#include <sys/module.h> 107#include <sys/socket.h> 108 109#include <net/if.h> 110#include <net/if_arp.h> 111#include <net/ethernet.h> 112#include <net/if_dl.h> 113#include <net/if_media.h> 114#include <net/if_types.h> 115#include <net/if_vlan_var.h> 116 117#include <net/bpf.h> 118 119#include <machine/bus.h> 120#include <machine/resource.h> 121#include <sys/bus.h> 122#include <sys/rman.h> 123 124#include <dev/mii/mii.h> 125#include <dev/mii/miivar.h> 126 127#include <dev/pci/pcireg.h> 128#include <dev/pci/pcivar.h> 129 130#define DC_USEIOSPACE 131 132#include <dev/dc/if_dcreg.h> 133 134#ifdef __sparc64__ 135#include <dev/ofw/openfirm.h> 136#include <machine/ofw_machdep.h> 137#endif 138 139MODULE_DEPEND(dc, pci, 1, 1, 1); 140MODULE_DEPEND(dc, ether, 1, 1, 1); 141MODULE_DEPEND(dc, miibus, 1, 1, 1); 142 143/* 144 * "device miibus" is required in kernel config. See GENERIC if you get 145 * errors here. 146 */ 147#include "miibus_if.h" 148 149/* 150 * Various supported device vendors/types and their names. 151 */ 152static const struct dc_type dc_devs[] = { 153 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 154 "Intel 21143 10/100BaseTX" }, 155 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 156 "Davicom DM9009 10/100BaseTX" }, 157 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 158 "Davicom DM9100 10/100BaseTX" }, 159 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 160 "Davicom DM9102A 10/100BaseTX" }, 161 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 162 "Davicom DM9102 10/100BaseTX" }, 163 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 164 "ADMtek AL981 10/100BaseTX" }, 165 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983), 0, 166 "ADMtek AN983 10/100BaseTX" }, 167 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 168 "ADMtek AN985 CardBus 10/100BaseTX or clone" }, 169 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 170 "ADMtek ADM9511 10/100BaseTX" }, 171 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 172 "ADMtek ADM9513 10/100BaseTX" }, 173 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 174 "ASIX AX88141 10/100BaseTX" }, 175 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 176 "ASIX AX88140A 10/100BaseTX" }, 177 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 178 "Macronix 98713A 10/100BaseTX" }, 179 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 180 "Macronix 98713 10/100BaseTX" }, 181 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 184 "Compex RL100-TX 10/100BaseTX" }, 185 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 186 "Macronix 98725 10/100BaseTX" }, 187 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 188 "Macronix 98715AEC-C 10/100BaseTX" }, 189 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 190 "Macronix 98715/98715A 10/100BaseTX" }, 191 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 192 "Macronix 98727/98732 10/100BaseTX" }, 193 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 194 "LC82C115 PNIC II 10/100BaseTX" }, 195 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 196 "82c169 PNIC 10/100BaseTX" }, 197 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 198 "82c168 PNIC 10/100BaseTX" }, 199 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 200 "Accton EN1217 10/100BaseTX" }, 201 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 202 "Accton EN2242 MiniPCI 10/100BaseTX" }, 203 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 204 "Xircom X3201 10/100BaseTX" }, 205 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 206 "Neteasy DRP-32TXD Cardbus 10/100" }, 207 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 208 "Abocom FE2500 10/100BaseTX" }, 209 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 210 "Abocom FE2500MX 10/100BaseTX" }, 211 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 212 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 213 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 214 "Hawking CB102 CardBus 10/100" }, 215 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 216 "PlaneX FNW-3602-T CardBus 10/100" }, 217 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 218 "3Com OfficeConnect 10/100B" }, 219 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 220 "Microsoft MN-120 CardBus 10/100" }, 221 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 222 "Microsoft MN-130 10/100" }, 223 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 224 "Linksys PCMPC200 CardBus 10/100" }, 225 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 226 "Linksys PCMPC200 CardBus 10/100" }, 227 { 0, 0, NULL } 228}; 229 230static int dc_probe(device_t); 231static int dc_attach(device_t); 232static int dc_detach(device_t); 233static int dc_suspend(device_t); 234static int dc_resume(device_t); 235static const struct dc_type *dc_devtype(device_t); 236static int dc_newbuf(struct dc_softc *, int, int); 237static int dc_encap(struct dc_softc *, struct mbuf **); 238static void dc_pnic_rx_bug_war(struct dc_softc *, int); 239static int dc_rx_resync(struct dc_softc *); 240static int dc_rxeof(struct dc_softc *); 241static void dc_txeof(struct dc_softc *); 242static void dc_tick(void *); 243static void dc_tx_underrun(struct dc_softc *); 244static void dc_intr(void *); 245static void dc_start(struct ifnet *); 246static void dc_start_locked(struct ifnet *); 247static int dc_ioctl(struct ifnet *, u_long, caddr_t); 248static void dc_init(void *); 249static void dc_init_locked(struct dc_softc *); 250static void dc_stop(struct dc_softc *); 251static void dc_watchdog(void *); 252static int dc_shutdown(device_t); 253static int dc_ifmedia_upd(struct ifnet *); 254static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 255 256static void dc_delay(struct dc_softc *); 257static void dc_eeprom_idle(struct dc_softc *); 258static void dc_eeprom_putbyte(struct dc_softc *, int); 259static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 260static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 261static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 262static void dc_eeprom_width(struct dc_softc *); 263static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 264 265static void dc_mii_writebit(struct dc_softc *, int); 266static int dc_mii_readbit(struct dc_softc *); 267static void dc_mii_sync(struct dc_softc *); 268static void dc_mii_send(struct dc_softc *, u_int32_t, int); 269static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 270static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 271static int dc_miibus_readreg(device_t, int, int); 272static int dc_miibus_writereg(device_t, int, int, int); 273static void dc_miibus_statchg(device_t); 274static void dc_miibus_mediainit(device_t); 275 276static void dc_setcfg(struct dc_softc *, int); 277static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 278static uint32_t dc_mchash_be(const uint8_t *); 279static void dc_setfilt_21143(struct dc_softc *); 280static void dc_setfilt_asix(struct dc_softc *); 281static void dc_setfilt_admtek(struct dc_softc *); 282static void dc_setfilt_xircom(struct dc_softc *); 283 284static void dc_setfilt(struct dc_softc *); 285 286static void dc_reset(struct dc_softc *); 287static int dc_list_rx_init(struct dc_softc *); 288static int dc_list_tx_init(struct dc_softc *); 289 290static int dc_read_srom(struct dc_softc *, int); 291static int dc_parse_21143_srom(struct dc_softc *); 292static int dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 293static int dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 294static int dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 295static void dc_apply_fixup(struct dc_softc *, int); 296static int dc_check_multiport(struct dc_softc *); 297 298#ifdef DC_USEIOSPACE 299#define DC_RES SYS_RES_IOPORT 300#define DC_RID DC_PCI_CFBIO 301#else 302#define DC_RES SYS_RES_MEMORY 303#define DC_RID DC_PCI_CFBMA 304#endif 305 306static device_method_t dc_methods[] = { 307 /* Device interface */ 308 DEVMETHOD(device_probe, dc_probe), 309 DEVMETHOD(device_attach, dc_attach), 310 DEVMETHOD(device_detach, dc_detach), 311 DEVMETHOD(device_suspend, dc_suspend), 312 DEVMETHOD(device_resume, dc_resume), 313 DEVMETHOD(device_shutdown, dc_shutdown), 314 315 /* bus interface */ 316 DEVMETHOD(bus_print_child, bus_generic_print_child), 317 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 318 319 /* MII interface */ 320 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 321 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 322 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 323 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 324 325 { 0, 0 } 326}; 327 328static driver_t dc_driver = { 329 "dc", 330 dc_methods, 331 sizeof(struct dc_softc) 332}; 333 334static devclass_t dc_devclass; 335 336DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 337DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 338 339#define DC_SETBIT(sc, reg, x) \ 340 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 341 342#define DC_CLRBIT(sc, reg, x) \ 343 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 344 345#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 346#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 347 348static void 349dc_delay(struct dc_softc *sc) 350{ 351 int idx; 352 353 for (idx = (300 / 33) + 1; idx > 0; idx--) 354 CSR_READ_4(sc, DC_BUSCTL); 355} 356 357static void 358dc_eeprom_width(struct dc_softc *sc) 359{ 360 int i; 361 362 /* Force EEPROM to idle state. */ 363 dc_eeprom_idle(sc); 364 365 /* Enter EEPROM access mode. */ 366 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 367 dc_delay(sc); 368 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 369 dc_delay(sc); 370 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 371 dc_delay(sc); 372 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 373 dc_delay(sc); 374 375 for (i = 3; i--;) { 376 if (6 & (1 << i)) 377 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 378 else 379 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 380 dc_delay(sc); 381 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 382 dc_delay(sc); 383 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 384 dc_delay(sc); 385 } 386 387 for (i = 1; i <= 12; i++) { 388 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 389 dc_delay(sc); 390 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 391 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 392 dc_delay(sc); 393 break; 394 } 395 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 396 dc_delay(sc); 397 } 398 399 /* Turn off EEPROM access mode. */ 400 dc_eeprom_idle(sc); 401 402 if (i < 4 || i > 12) 403 sc->dc_romwidth = 6; 404 else 405 sc->dc_romwidth = i; 406 407 /* Enter EEPROM access mode. */ 408 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 409 dc_delay(sc); 410 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 411 dc_delay(sc); 412 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 413 dc_delay(sc); 414 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 415 dc_delay(sc); 416 417 /* Turn off EEPROM access mode. */ 418 dc_eeprom_idle(sc); 419} 420 421static void 422dc_eeprom_idle(struct dc_softc *sc) 423{ 424 int i; 425 426 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 427 dc_delay(sc); 428 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 429 dc_delay(sc); 430 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 431 dc_delay(sc); 432 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 433 dc_delay(sc); 434 435 for (i = 0; i < 25; i++) { 436 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 437 dc_delay(sc); 438 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 439 dc_delay(sc); 440 } 441 442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 443 dc_delay(sc); 444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 445 dc_delay(sc); 446 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 447} 448 449/* 450 * Send a read command and address to the EEPROM, check for ACK. 451 */ 452static void 453dc_eeprom_putbyte(struct dc_softc *sc, int addr) 454{ 455 int d, i; 456 457 d = DC_EECMD_READ >> 6; 458 for (i = 3; i--; ) { 459 if (d & (1 << i)) 460 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 461 else 462 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 463 dc_delay(sc); 464 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 465 dc_delay(sc); 466 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 467 dc_delay(sc); 468 } 469 470 /* 471 * Feed in each bit and strobe the clock. 472 */ 473 for (i = sc->dc_romwidth; i--;) { 474 if (addr & (1 << i)) { 475 SIO_SET(DC_SIO_EE_DATAIN); 476 } else { 477 SIO_CLR(DC_SIO_EE_DATAIN); 478 } 479 dc_delay(sc); 480 SIO_SET(DC_SIO_EE_CLK); 481 dc_delay(sc); 482 SIO_CLR(DC_SIO_EE_CLK); 483 dc_delay(sc); 484 } 485} 486 487/* 488 * Read a word of data stored in the EEPROM at address 'addr.' 489 * The PNIC 82c168/82c169 has its own non-standard way to read 490 * the EEPROM. 491 */ 492static void 493dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 494{ 495 int i; 496 u_int32_t r; 497 498 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 499 500 for (i = 0; i < DC_TIMEOUT; i++) { 501 DELAY(1); 502 r = CSR_READ_4(sc, DC_SIO); 503 if (!(r & DC_PN_SIOCTL_BUSY)) { 504 *dest = (u_int16_t)(r & 0xFFFF); 505 return; 506 } 507 } 508} 509 510/* 511 * Read a word of data stored in the EEPROM at address 'addr.' 512 * The Xircom X3201 has its own non-standard way to read 513 * the EEPROM, too. 514 */ 515static void 516dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 517{ 518 519 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 520 521 addr *= 2; 522 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 523 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 524 addr += 1; 525 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 526 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 527 528 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 529} 530 531/* 532 * Read a word of data stored in the EEPROM at address 'addr.' 533 */ 534static void 535dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 536{ 537 int i; 538 u_int16_t word = 0; 539 540 /* Force EEPROM to idle state. */ 541 dc_eeprom_idle(sc); 542 543 /* Enter EEPROM access mode. */ 544 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 545 dc_delay(sc); 546 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 547 dc_delay(sc); 548 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 549 dc_delay(sc); 550 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 551 dc_delay(sc); 552 553 /* 554 * Send address of word we want to read. 555 */ 556 dc_eeprom_putbyte(sc, addr); 557 558 /* 559 * Start reading bits from EEPROM. 560 */ 561 for (i = 0x8000; i; i >>= 1) { 562 SIO_SET(DC_SIO_EE_CLK); 563 dc_delay(sc); 564 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 565 word |= i; 566 dc_delay(sc); 567 SIO_CLR(DC_SIO_EE_CLK); 568 dc_delay(sc); 569 } 570 571 /* Turn off EEPROM access mode. */ 572 dc_eeprom_idle(sc); 573 574 *dest = word; 575} 576 577/* 578 * Read a sequence of words from the EEPROM. 579 */ 580static void 581dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 582{ 583 int i; 584 u_int16_t word = 0, *ptr; 585 586 for (i = 0; i < cnt; i++) { 587 if (DC_IS_PNIC(sc)) 588 dc_eeprom_getword_pnic(sc, off + i, &word); 589 else if (DC_IS_XIRCOM(sc)) 590 dc_eeprom_getword_xircom(sc, off + i, &word); 591 else 592 dc_eeprom_getword(sc, off + i, &word); 593 ptr = (u_int16_t *)(dest + (i * 2)); 594 if (be) 595 *ptr = be16toh(word); 596 else 597 *ptr = le16toh(word); 598 } 599} 600 601/* 602 * The following two routines are taken from the Macronix 98713 603 * Application Notes pp.19-21. 604 */ 605/* 606 * Write a bit to the MII bus. 607 */ 608static void 609dc_mii_writebit(struct dc_softc *sc, int bit) 610{ 611 uint32_t reg; 612 613 reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0); 614 CSR_WRITE_4(sc, DC_SIO, reg); 615 CSR_BARRIER_4(sc, DC_SIO, 616 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 617 DELAY(1); 618 619 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); 620 CSR_BARRIER_4(sc, DC_SIO, 621 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 622 DELAY(1); 623 CSR_WRITE_4(sc, DC_SIO, reg); 624 CSR_BARRIER_4(sc, DC_SIO, 625 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 626 DELAY(1); 627} 628 629/* 630 * Read a bit from the MII bus. 631 */ 632static int 633dc_mii_readbit(struct dc_softc *sc) 634{ 635 uint32_t reg; 636 637 reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR; 638 CSR_WRITE_4(sc, DC_SIO, reg); 639 CSR_BARRIER_4(sc, DC_SIO, 640 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 641 DELAY(1); 642 (void)CSR_READ_4(sc, DC_SIO); 643 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); 644 CSR_BARRIER_4(sc, DC_SIO, 645 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 646 DELAY(1); 647 CSR_WRITE_4(sc, DC_SIO, reg); 648 CSR_BARRIER_4(sc, DC_SIO, 649 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 650 DELAY(1); 651 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 652 return (1); 653 654 return (0); 655} 656 657/* 658 * Sync the PHYs by setting data bit and strobing the clock 32 times. 659 */ 660static void 661dc_mii_sync(struct dc_softc *sc) 662{ 663 int i; 664 665 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 666 CSR_BARRIER_4(sc, DC_SIO, 667 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 668 DELAY(1); 669 670 for (i = 0; i < 32; i++) 671 dc_mii_writebit(sc, 1); 672} 673 674/* 675 * Clock a series of bits through the MII. 676 */ 677static void 678dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 679{ 680 int i; 681 682 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 683 dc_mii_writebit(sc, bits & i); 684} 685 686/* 687 * Read an PHY register through the MII. 688 */ 689static int 690dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 691{ 692 int i; 693 694 /* 695 * Set up frame for RX. 696 */ 697 frame->mii_stdelim = DC_MII_STARTDELIM; 698 frame->mii_opcode = DC_MII_READOP; 699 700 /* 701 * Sync the PHYs. 702 */ 703 dc_mii_sync(sc); 704 705 /* 706 * Send command/address info. 707 */ 708 dc_mii_send(sc, frame->mii_stdelim, 2); 709 dc_mii_send(sc, frame->mii_opcode, 2); 710 dc_mii_send(sc, frame->mii_phyaddr, 5); 711 dc_mii_send(sc, frame->mii_regaddr, 5); 712 713 /* 714 * Now try reading data bits. If the turnaround failed, we still 715 * need to clock through 16 cycles to keep the PHY(s) in sync. 716 */ 717 frame->mii_turnaround = dc_mii_readbit(sc); 718 if (frame->mii_turnaround != 0) { 719 for (i = 0; i < 16; i++) 720 dc_mii_readbit(sc); 721 goto fail; 722 } 723 for (i = 0x8000; i; i >>= 1) { 724 if (dc_mii_readbit(sc)) 725 frame->mii_data |= i; 726 } 727 728fail: 729 730 /* Clock the idle bits. */ 731 dc_mii_writebit(sc, 0); 732 dc_mii_writebit(sc, 0); 733 734 if (frame->mii_turnaround != 0) 735 return (1); 736 return (0); 737} 738 739/* 740 * Write to a PHY register through the MII. 741 */ 742static int 743dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 744{ 745 746 /* 747 * Set up frame for TX. 748 */ 749 frame->mii_stdelim = DC_MII_STARTDELIM; 750 frame->mii_opcode = DC_MII_WRITEOP; 751 frame->mii_turnaround = DC_MII_TURNAROUND; 752 753 /* 754 * Sync the PHYs. 755 */ 756 dc_mii_sync(sc); 757 758 dc_mii_send(sc, frame->mii_stdelim, 2); 759 dc_mii_send(sc, frame->mii_opcode, 2); 760 dc_mii_send(sc, frame->mii_phyaddr, 5); 761 dc_mii_send(sc, frame->mii_regaddr, 5); 762 dc_mii_send(sc, frame->mii_turnaround, 2); 763 dc_mii_send(sc, frame->mii_data, 16); 764 765 /* Clock the idle bits. */ 766 dc_mii_writebit(sc, 0); 767 dc_mii_writebit(sc, 0); 768 769 return (0); 770} 771 772static int 773dc_miibus_readreg(device_t dev, int phy, int reg) 774{ 775 struct dc_mii_frame frame; 776 struct dc_softc *sc; 777 int i, rval, phy_reg = 0; 778 779 sc = device_get_softc(dev); 780 bzero(&frame, sizeof(frame)); 781 782 if (sc->dc_pmode != DC_PMODE_MII) { 783 if (phy == (MII_NPHY - 1)) { 784 switch (reg) { 785 case MII_BMSR: 786 /* 787 * Fake something to make the probe 788 * code think there's a PHY here. 789 */ 790 return (BMSR_MEDIAMASK); 791 break; 792 case MII_PHYIDR1: 793 if (DC_IS_PNIC(sc)) 794 return (DC_VENDORID_LO); 795 return (DC_VENDORID_DEC); 796 break; 797 case MII_PHYIDR2: 798 if (DC_IS_PNIC(sc)) 799 return (DC_DEVICEID_82C168); 800 return (DC_DEVICEID_21143); 801 break; 802 default: 803 return (0); 804 break; 805 } 806 } else 807 return (0); 808 } 809 810 if (DC_IS_PNIC(sc)) { 811 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 812 (phy << 23) | (reg << 18)); 813 for (i = 0; i < DC_TIMEOUT; i++) { 814 DELAY(1); 815 rval = CSR_READ_4(sc, DC_PN_MII); 816 if (!(rval & DC_PN_MII_BUSY)) { 817 rval &= 0xFFFF; 818 return (rval == 0xFFFF ? 0 : rval); 819 } 820 } 821 return (0); 822 } 823 824 if (DC_IS_COMET(sc)) { 825 switch (reg) { 826 case MII_BMCR: 827 phy_reg = DC_AL_BMCR; 828 break; 829 case MII_BMSR: 830 phy_reg = DC_AL_BMSR; 831 break; 832 case MII_PHYIDR1: 833 phy_reg = DC_AL_VENID; 834 break; 835 case MII_PHYIDR2: 836 phy_reg = DC_AL_DEVID; 837 break; 838 case MII_ANAR: 839 phy_reg = DC_AL_ANAR; 840 break; 841 case MII_ANLPAR: 842 phy_reg = DC_AL_LPAR; 843 break; 844 case MII_ANER: 845 phy_reg = DC_AL_ANER; 846 break; 847 default: 848 device_printf(dev, "phy_read: bad phy register %x\n", 849 reg); 850 return (0); 851 break; 852 } 853 854 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 855 856 if (rval == 0xFFFF) 857 return (0); 858 return (rval); 859 } 860 861 frame.mii_phyaddr = phy; 862 frame.mii_regaddr = reg; 863 if (sc->dc_type == DC_TYPE_98713) { 864 phy_reg = CSR_READ_4(sc, DC_NETCFG); 865 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 866 } 867 dc_mii_readreg(sc, &frame); 868 if (sc->dc_type == DC_TYPE_98713) 869 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 870 871 return (frame.mii_data); 872} 873 874static int 875dc_miibus_writereg(device_t dev, int phy, int reg, int data) 876{ 877 struct dc_softc *sc; 878 struct dc_mii_frame frame; 879 int i, phy_reg = 0; 880 881 sc = device_get_softc(dev); 882 bzero(&frame, sizeof(frame)); 883 884 if (DC_IS_PNIC(sc)) { 885 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 886 (phy << 23) | (reg << 10) | data); 887 for (i = 0; i < DC_TIMEOUT; i++) { 888 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 889 break; 890 } 891 return (0); 892 } 893 894 if (DC_IS_COMET(sc)) { 895 switch (reg) { 896 case MII_BMCR: 897 phy_reg = DC_AL_BMCR; 898 break; 899 case MII_BMSR: 900 phy_reg = DC_AL_BMSR; 901 break; 902 case MII_PHYIDR1: 903 phy_reg = DC_AL_VENID; 904 break; 905 case MII_PHYIDR2: 906 phy_reg = DC_AL_DEVID; 907 break; 908 case MII_ANAR: 909 phy_reg = DC_AL_ANAR; 910 break; 911 case MII_ANLPAR: 912 phy_reg = DC_AL_LPAR; 913 break; 914 case MII_ANER: 915 phy_reg = DC_AL_ANER; 916 break; 917 default: 918 device_printf(dev, "phy_write: bad phy register %x\n", 919 reg); 920 return (0); 921 break; 922 } 923 924 CSR_WRITE_4(sc, phy_reg, data); 925 return (0); 926 } 927 928 frame.mii_phyaddr = phy; 929 frame.mii_regaddr = reg; 930 frame.mii_data = data; 931 932 if (sc->dc_type == DC_TYPE_98713) { 933 phy_reg = CSR_READ_4(sc, DC_NETCFG); 934 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 935 } 936 dc_mii_writereg(sc, &frame); 937 if (sc->dc_type == DC_TYPE_98713) 938 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 939 940 return (0); 941} 942 943static void 944dc_miibus_statchg(device_t dev) 945{ 946 struct dc_softc *sc; 947 struct mii_data *mii; 948 struct ifmedia *ifm; 949 950 sc = device_get_softc(dev); 951 if (DC_IS_ADMTEK(sc)) 952 return; 953 954 mii = device_get_softc(sc->dc_miibus); 955 ifm = &mii->mii_media; 956 if (DC_IS_DAVICOM(sc) && 957 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 958 dc_setcfg(sc, ifm->ifm_media); 959 sc->dc_if_media = ifm->ifm_media; 960 } else { 961 dc_setcfg(sc, mii->mii_media_active); 962 sc->dc_if_media = mii->mii_media_active; 963 } 964} 965 966/* 967 * Special support for DM9102A cards with HomePNA PHYs. Note: 968 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 969 * to be impossible to talk to the management interface of the DM9801 970 * PHY (its MDIO pin is not connected to anything). Consequently, 971 * the driver has to just 'know' about the additional mode and deal 972 * with it itself. *sigh* 973 */ 974static void 975dc_miibus_mediainit(device_t dev) 976{ 977 struct dc_softc *sc; 978 struct mii_data *mii; 979 struct ifmedia *ifm; 980 int rev; 981 982 rev = pci_get_revid(dev); 983 984 sc = device_get_softc(dev); 985 mii = device_get_softc(sc->dc_miibus); 986 ifm = &mii->mii_media; 987 988 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 989 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 990} 991 992#define DC_BITS_512 9 993#define DC_BITS_128 7 994#define DC_BITS_64 6 995 996static uint32_t 997dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 998{ 999 uint32_t crc; 1000 1001 /* Compute CRC for the address value. */ 1002 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1003 1004 /* 1005 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1006 * chips is only 128 bits wide. 1007 */ 1008 if (sc->dc_flags & DC_128BIT_HASH) 1009 return (crc & ((1 << DC_BITS_128) - 1)); 1010 1011 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1012 if (sc->dc_flags & DC_64BIT_HASH) 1013 return (crc & ((1 << DC_BITS_64) - 1)); 1014 1015 /* Xircom's hash filtering table is different (read: weird) */ 1016 /* Xircom uses the LEAST significant bits */ 1017 if (DC_IS_XIRCOM(sc)) { 1018 if ((crc & 0x180) == 0x180) 1019 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1020 else 1021 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1022 (12 << 4)); 1023 } 1024 1025 return (crc & ((1 << DC_BITS_512) - 1)); 1026} 1027 1028/* 1029 * Calculate CRC of a multicast group address, return the lower 6 bits. 1030 */ 1031static uint32_t 1032dc_mchash_be(const uint8_t *addr) 1033{ 1034 uint32_t crc; 1035 1036 /* Compute CRC for the address value. */ 1037 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1038 1039 /* Return the filter bit position. */ 1040 return ((crc >> 26) & 0x0000003F); 1041} 1042 1043/* 1044 * 21143-style RX filter setup routine. Filter programming is done by 1045 * downloading a special setup frame into the TX engine. 21143, Macronix, 1046 * PNIC, PNIC II and Davicom chips are programmed this way. 1047 * 1048 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1049 * address (our node address) and a 512-bit hash filter for multicast 1050 * frames. We also sneak the broadcast address into the hash filter since 1051 * we need that too. 1052 */ 1053static void 1054dc_setfilt_21143(struct dc_softc *sc) 1055{ 1056 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1057 struct dc_desc *sframe; 1058 u_int32_t h, *sp; 1059 struct ifmultiaddr *ifma; 1060 struct ifnet *ifp; 1061 int i; 1062 1063 ifp = sc->dc_ifp; 1064 1065 i = sc->dc_cdata.dc_tx_prod; 1066 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1067 sc->dc_cdata.dc_tx_cnt++; 1068 sframe = &sc->dc_ldata->dc_tx_list[i]; 1069 sp = sc->dc_cdata.dc_sbuf; 1070 bzero(sp, DC_SFRAME_LEN); 1071 1072 sframe->dc_data = htole32(sc->dc_saddr); 1073 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1074 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1075 1076 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1077 1078 /* If we want promiscuous mode, set the allframes bit. */ 1079 if (ifp->if_flags & IFF_PROMISC) 1080 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1081 else 1082 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1083 1084 if (ifp->if_flags & IFF_ALLMULTI) 1085 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1086 else 1087 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1088 1089 if_maddr_rlock(ifp); 1090 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1091 if (ifma->ifma_addr->sa_family != AF_LINK) 1092 continue; 1093 h = dc_mchash_le(sc, 1094 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1095 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1096 } 1097 if_maddr_runlock(ifp); 1098 1099 if (ifp->if_flags & IFF_BROADCAST) { 1100 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1101 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1102 } 1103 1104 /* Set our MAC address. */ 1105 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1106 sp[39] = DC_SP_MAC(eaddr[0]); 1107 sp[40] = DC_SP_MAC(eaddr[1]); 1108 sp[41] = DC_SP_MAC(eaddr[2]); 1109 1110 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1111 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1112 1113 /* 1114 * The PNIC takes an exceedingly long time to process its 1115 * setup frame; wait 10ms after posting the setup frame 1116 * before proceeding, just so it has time to swallow its 1117 * medicine. 1118 */ 1119 DELAY(10000); 1120 1121 sc->dc_wdog_timer = 5; 1122} 1123 1124static void 1125dc_setfilt_admtek(struct dc_softc *sc) 1126{ 1127 uint8_t eaddr[ETHER_ADDR_LEN]; 1128 struct ifnet *ifp; 1129 struct ifmultiaddr *ifma; 1130 int h = 0; 1131 u_int32_t hashes[2] = { 0, 0 }; 1132 1133 ifp = sc->dc_ifp; 1134 1135 /* Init our MAC address. */ 1136 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1137 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1138 eaddr[1] << 8 | eaddr[0]); 1139 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1140 1141 /* If we want promiscuous mode, set the allframes bit. */ 1142 if (ifp->if_flags & IFF_PROMISC) 1143 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1144 else 1145 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1146 1147 if (ifp->if_flags & IFF_ALLMULTI) 1148 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1149 else 1150 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1151 1152 /* First, zot all the existing hash bits. */ 1153 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1154 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1155 1156 /* 1157 * If we're already in promisc or allmulti mode, we 1158 * don't have to bother programming the multicast filter. 1159 */ 1160 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1161 return; 1162 1163 /* Now program new ones. */ 1164 if_maddr_rlock(ifp); 1165 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1166 if (ifma->ifma_addr->sa_family != AF_LINK) 1167 continue; 1168 if (DC_IS_CENTAUR(sc)) 1169 h = dc_mchash_le(sc, 1170 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1171 else 1172 h = dc_mchash_be( 1173 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1174 if (h < 32) 1175 hashes[0] |= (1 << h); 1176 else 1177 hashes[1] |= (1 << (h - 32)); 1178 } 1179 if_maddr_runlock(ifp); 1180 1181 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1182 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1183} 1184 1185static void 1186dc_setfilt_asix(struct dc_softc *sc) 1187{ 1188 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1189 struct ifnet *ifp; 1190 struct ifmultiaddr *ifma; 1191 int h = 0; 1192 u_int32_t hashes[2] = { 0, 0 }; 1193 1194 ifp = sc->dc_ifp; 1195 1196 /* Init our MAC address. */ 1197 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1198 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1199 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1200 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1201 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1202 1203 /* If we want promiscuous mode, set the allframes bit. */ 1204 if (ifp->if_flags & IFF_PROMISC) 1205 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1206 else 1207 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1208 1209 if (ifp->if_flags & IFF_ALLMULTI) 1210 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1211 else 1212 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1213 1214 /* 1215 * The ASIX chip has a special bit to enable reception 1216 * of broadcast frames. 1217 */ 1218 if (ifp->if_flags & IFF_BROADCAST) 1219 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1220 else 1221 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1222 1223 /* first, zot all the existing hash bits */ 1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1226 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1227 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1228 1229 /* 1230 * If we're already in promisc or allmulti mode, we 1231 * don't have to bother programming the multicast filter. 1232 */ 1233 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1234 return; 1235 1236 /* now program new ones */ 1237 if_maddr_rlock(ifp); 1238 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1239 if (ifma->ifma_addr->sa_family != AF_LINK) 1240 continue; 1241 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1242 if (h < 32) 1243 hashes[0] |= (1 << h); 1244 else 1245 hashes[1] |= (1 << (h - 32)); 1246 } 1247 if_maddr_runlock(ifp); 1248 1249 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1250 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1251 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1252 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1253} 1254 1255static void 1256dc_setfilt_xircom(struct dc_softc *sc) 1257{ 1258 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1259 struct ifnet *ifp; 1260 struct ifmultiaddr *ifma; 1261 struct dc_desc *sframe; 1262 u_int32_t h, *sp; 1263 int i; 1264 1265 ifp = sc->dc_ifp; 1266 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1267 1268 i = sc->dc_cdata.dc_tx_prod; 1269 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1270 sc->dc_cdata.dc_tx_cnt++; 1271 sframe = &sc->dc_ldata->dc_tx_list[i]; 1272 sp = sc->dc_cdata.dc_sbuf; 1273 bzero(sp, DC_SFRAME_LEN); 1274 1275 sframe->dc_data = htole32(sc->dc_saddr); 1276 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1277 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1278 1279 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1280 1281 /* If we want promiscuous mode, set the allframes bit. */ 1282 if (ifp->if_flags & IFF_PROMISC) 1283 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1284 else 1285 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1286 1287 if (ifp->if_flags & IFF_ALLMULTI) 1288 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1289 else 1290 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1291 1292 if_maddr_rlock(ifp); 1293 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1294 if (ifma->ifma_addr->sa_family != AF_LINK) 1295 continue; 1296 h = dc_mchash_le(sc, 1297 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1298 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1299 } 1300 if_maddr_runlock(ifp); 1301 1302 if (ifp->if_flags & IFF_BROADCAST) { 1303 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1304 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1305 } 1306 1307 /* Set our MAC address. */ 1308 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1309 sp[0] = DC_SP_MAC(eaddr[0]); 1310 sp[1] = DC_SP_MAC(eaddr[1]); 1311 sp[2] = DC_SP_MAC(eaddr[2]); 1312 1313 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1314 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1315 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1316 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1317 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1318 1319 /* 1320 * Wait some time... 1321 */ 1322 DELAY(1000); 1323 1324 sc->dc_wdog_timer = 5; 1325} 1326 1327static void 1328dc_setfilt(struct dc_softc *sc) 1329{ 1330 1331 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1332 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1333 dc_setfilt_21143(sc); 1334 1335 if (DC_IS_ASIX(sc)) 1336 dc_setfilt_asix(sc); 1337 1338 if (DC_IS_ADMTEK(sc)) 1339 dc_setfilt_admtek(sc); 1340 1341 if (DC_IS_XIRCOM(sc)) 1342 dc_setfilt_xircom(sc); 1343} 1344 1345/* 1346 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1347 * the netconfig register, we first have to put the transmit and/or 1348 * receive logic in the idle state. 1349 */ 1350static void 1351dc_setcfg(struct dc_softc *sc, int media) 1352{ 1353 int i, restart = 0, watchdogreg; 1354 u_int32_t isr; 1355 1356 if (IFM_SUBTYPE(media) == IFM_NONE) 1357 return; 1358 1359 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1360 restart = 1; 1361 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1362 1363 for (i = 0; i < DC_TIMEOUT; i++) { 1364 isr = CSR_READ_4(sc, DC_ISR); 1365 if (isr & DC_ISR_TX_IDLE && 1366 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1367 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1368 break; 1369 DELAY(10); 1370 } 1371 1372 if (i == DC_TIMEOUT) { 1373 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1374 device_printf(sc->dc_dev, 1375 "%s: failed to force tx to idle state\n", 1376 __func__); 1377 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1378 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1379 !DC_HAS_BROKEN_RXSTATE(sc)) 1380 device_printf(sc->dc_dev, 1381 "%s: failed to force rx to idle state\n", 1382 __func__); 1383 } 1384 } 1385 1386 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1387 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1388 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1389 if (sc->dc_pmode == DC_PMODE_MII) { 1390 if (DC_IS_INTEL(sc)) { 1391 /* There's a write enable bit here that reads as 1. */ 1392 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1393 watchdogreg &= ~DC_WDOG_CTLWREN; 1394 watchdogreg |= DC_WDOG_JABBERDIS; 1395 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1396 } else { 1397 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1398 } 1399 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1400 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1401 if (sc->dc_type == DC_TYPE_98713) 1402 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1403 DC_NETCFG_SCRAMBLER)); 1404 if (!DC_IS_DAVICOM(sc)) 1405 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1406 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1407 if (DC_IS_INTEL(sc)) 1408 dc_apply_fixup(sc, IFM_AUTO); 1409 } else { 1410 if (DC_IS_PNIC(sc)) { 1411 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1412 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1413 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1414 } 1415 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1416 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1417 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1418 if (DC_IS_INTEL(sc)) 1419 dc_apply_fixup(sc, 1420 (media & IFM_GMASK) == IFM_FDX ? 1421 IFM_100_TX | IFM_FDX : IFM_100_TX); 1422 } 1423 } 1424 1425 if (IFM_SUBTYPE(media) == IFM_10_T) { 1426 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1427 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1428 if (sc->dc_pmode == DC_PMODE_MII) { 1429 /* There's a write enable bit here that reads as 1. */ 1430 if (DC_IS_INTEL(sc)) { 1431 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1432 watchdogreg &= ~DC_WDOG_CTLWREN; 1433 watchdogreg |= DC_WDOG_JABBERDIS; 1434 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1435 } else { 1436 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1437 } 1438 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1439 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1440 if (sc->dc_type == DC_TYPE_98713) 1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1442 if (!DC_IS_DAVICOM(sc)) 1443 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1444 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1445 if (DC_IS_INTEL(sc)) 1446 dc_apply_fixup(sc, IFM_AUTO); 1447 } else { 1448 if (DC_IS_PNIC(sc)) { 1449 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1450 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1451 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1452 } 1453 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1454 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1455 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1456 if (DC_IS_INTEL(sc)) { 1457 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1458 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1459 if ((media & IFM_GMASK) == IFM_FDX) 1460 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1461 else 1462 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1463 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1464 DC_CLRBIT(sc, DC_10BTCTRL, 1465 DC_TCTL_AUTONEGENBL); 1466 dc_apply_fixup(sc, 1467 (media & IFM_GMASK) == IFM_FDX ? 1468 IFM_10_T | IFM_FDX : IFM_10_T); 1469 DELAY(20000); 1470 } 1471 } 1472 } 1473 1474 /* 1475 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1476 * PHY and we want HomePNA mode, set the portsel bit to turn 1477 * on the external MII port. 1478 */ 1479 if (DC_IS_DAVICOM(sc)) { 1480 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1481 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1482 sc->dc_link = 1; 1483 } else { 1484 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1485 } 1486 } 1487 1488 if ((media & IFM_GMASK) == IFM_FDX) { 1489 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1490 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1491 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1492 } else { 1493 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1494 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1495 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1496 } 1497 1498 if (restart) 1499 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1500} 1501 1502static void 1503dc_reset(struct dc_softc *sc) 1504{ 1505 int i; 1506 1507 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1508 1509 for (i = 0; i < DC_TIMEOUT; i++) { 1510 DELAY(10); 1511 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1512 break; 1513 } 1514 1515 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1516 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1517 DELAY(10000); 1518 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1519 i = 0; 1520 } 1521 1522 if (i == DC_TIMEOUT) 1523 device_printf(sc->dc_dev, "reset never completed!\n"); 1524 1525 /* Wait a little while for the chip to get its brains in order. */ 1526 DELAY(1000); 1527 1528 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1529 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1530 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1531 1532 /* 1533 * Bring the SIA out of reset. In some cases, it looks 1534 * like failing to unreset the SIA soon enough gets it 1535 * into a state where it will never come out of reset 1536 * until we reset the whole chip again. 1537 */ 1538 if (DC_IS_INTEL(sc)) { 1539 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1540 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1541 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1542 } 1543} 1544 1545static const struct dc_type * 1546dc_devtype(device_t dev) 1547{ 1548 const struct dc_type *t; 1549 u_int32_t devid; 1550 u_int8_t rev; 1551 1552 t = dc_devs; 1553 devid = pci_get_devid(dev); 1554 rev = pci_get_revid(dev); 1555 1556 while (t->dc_name != NULL) { 1557 if (devid == t->dc_devid && rev >= t->dc_minrev) 1558 return (t); 1559 t++; 1560 } 1561 1562 return (NULL); 1563} 1564 1565/* 1566 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1567 * IDs against our list and return a device name if we find a match. 1568 * We do a little bit of extra work to identify the exact type of 1569 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1570 * but different revision IDs. The same is true for 98715/98715A 1571 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1572 * cases, the exact chip revision affects driver behavior. 1573 */ 1574static int 1575dc_probe(device_t dev) 1576{ 1577 const struct dc_type *t; 1578 1579 t = dc_devtype(dev); 1580 1581 if (t != NULL) { 1582 device_set_desc(dev, t->dc_name); 1583 return (BUS_PROBE_DEFAULT); 1584 } 1585 1586 return (ENXIO); 1587} 1588 1589static void 1590dc_apply_fixup(struct dc_softc *sc, int media) 1591{ 1592 struct dc_mediainfo *m; 1593 u_int8_t *p; 1594 int i; 1595 u_int32_t reg; 1596 1597 m = sc->dc_mi; 1598 1599 while (m != NULL) { 1600 if (m->dc_media == media) 1601 break; 1602 m = m->dc_next; 1603 } 1604 1605 if (m == NULL) 1606 return; 1607 1608 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1609 reg = (p[0] | (p[1] << 8)) << 16; 1610 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1611 } 1612 1613 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1614 reg = (p[0] | (p[1] << 8)) << 16; 1615 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1616 } 1617} 1618 1619static int 1620dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1621{ 1622 struct dc_mediainfo *m; 1623 1624 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1625 if (m == NULL) { 1626 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1627 return (ENOMEM); 1628 } 1629 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1630 case DC_SIA_CODE_10BT: 1631 m->dc_media = IFM_10_T; 1632 break; 1633 case DC_SIA_CODE_10BT_FDX: 1634 m->dc_media = IFM_10_T | IFM_FDX; 1635 break; 1636 case DC_SIA_CODE_10B2: 1637 m->dc_media = IFM_10_2; 1638 break; 1639 case DC_SIA_CODE_10B5: 1640 m->dc_media = IFM_10_5; 1641 break; 1642 default: 1643 break; 1644 } 1645 1646 /* 1647 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1648 * Things apparently already work for cards that do 1649 * supply Media Specific Data. 1650 */ 1651 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1652 m->dc_gp_len = 2; 1653 m->dc_gp_ptr = 1654 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1655 } else { 1656 m->dc_gp_len = 2; 1657 m->dc_gp_ptr = 1658 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1659 } 1660 1661 m->dc_next = sc->dc_mi; 1662 sc->dc_mi = m; 1663 1664 sc->dc_pmode = DC_PMODE_SIA; 1665 return (0); 1666} 1667 1668static int 1669dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1670{ 1671 struct dc_mediainfo *m; 1672 1673 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1674 if (m == NULL) { 1675 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1676 return (ENOMEM); 1677 } 1678 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1679 m->dc_media = IFM_100_TX; 1680 1681 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1682 m->dc_media = IFM_100_TX | IFM_FDX; 1683 1684 m->dc_gp_len = 2; 1685 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1686 1687 m->dc_next = sc->dc_mi; 1688 sc->dc_mi = m; 1689 1690 sc->dc_pmode = DC_PMODE_SYM; 1691 return (0); 1692} 1693 1694static int 1695dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1696{ 1697 struct dc_mediainfo *m; 1698 u_int8_t *p; 1699 1700 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1701 if (m == NULL) { 1702 device_printf(sc->dc_dev, "Could not allocate mediainfo\n"); 1703 return (ENOMEM); 1704 } 1705 /* We abuse IFM_AUTO to represent MII. */ 1706 m->dc_media = IFM_AUTO; 1707 m->dc_gp_len = l->dc_gpr_len; 1708 1709 p = (u_int8_t *)l; 1710 p += sizeof(struct dc_eblock_mii); 1711 m->dc_gp_ptr = p; 1712 p += 2 * l->dc_gpr_len; 1713 m->dc_reset_len = *p; 1714 p++; 1715 m->dc_reset_ptr = p; 1716 1717 m->dc_next = sc->dc_mi; 1718 sc->dc_mi = m; 1719 return (0); 1720} 1721 1722static int 1723dc_read_srom(struct dc_softc *sc, int bits) 1724{ 1725 int size; 1726 1727 size = DC_ROM_SIZE(bits); 1728 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1729 if (sc->dc_srom == NULL) { 1730 device_printf(sc->dc_dev, "Could not allocate SROM buffer\n"); 1731 return (ENOMEM); 1732 } 1733 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1734 return (0); 1735} 1736 1737static int 1738dc_parse_21143_srom(struct dc_softc *sc) 1739{ 1740 struct dc_leaf_hdr *lhdr; 1741 struct dc_eblock_hdr *hdr; 1742 int error, have_mii, i, loff; 1743 char *ptr; 1744 1745 have_mii = 0; 1746 loff = sc->dc_srom[27]; 1747 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1748 1749 ptr = (char *)lhdr; 1750 ptr += sizeof(struct dc_leaf_hdr) - 1; 1751 /* 1752 * Look if we got a MII media block. 1753 */ 1754 for (i = 0; i < lhdr->dc_mcnt; i++) { 1755 hdr = (struct dc_eblock_hdr *)ptr; 1756 if (hdr->dc_type == DC_EBLOCK_MII) 1757 have_mii++; 1758 1759 ptr += (hdr->dc_len & 0x7F); 1760 ptr++; 1761 } 1762 1763 /* 1764 * Do the same thing again. Only use SIA and SYM media 1765 * blocks if no MII media block is available. 1766 */ 1767 ptr = (char *)lhdr; 1768 ptr += sizeof(struct dc_leaf_hdr) - 1; 1769 error = 0; 1770 for (i = 0; i < lhdr->dc_mcnt; i++) { 1771 hdr = (struct dc_eblock_hdr *)ptr; 1772 switch (hdr->dc_type) { 1773 case DC_EBLOCK_MII: 1774 error = dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1775 break; 1776 case DC_EBLOCK_SIA: 1777 if (! have_mii) 1778 error = dc_decode_leaf_sia(sc, 1779 (struct dc_eblock_sia *)hdr); 1780 break; 1781 case DC_EBLOCK_SYM: 1782 if (! have_mii) 1783 error = dc_decode_leaf_sym(sc, 1784 (struct dc_eblock_sym *)hdr); 1785 break; 1786 default: 1787 /* Don't care. Yet. */ 1788 break; 1789 } 1790 ptr += (hdr->dc_len & 0x7F); 1791 ptr++; 1792 } 1793 return (error); 1794} 1795 1796static void 1797dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1798{ 1799 u_int32_t *paddr; 1800 1801 KASSERT(nseg == 1, 1802 ("%s: wrong number of segments (%d)", __func__, nseg)); 1803 paddr = arg; 1804 *paddr = segs->ds_addr; 1805} 1806 1807/* 1808 * Attach the interface. Allocate softc structures, do ifmedia 1809 * setup and ethernet/BPF attach. 1810 */ 1811static int 1812dc_attach(device_t dev) 1813{ 1814 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1815 u_int32_t command; 1816 struct dc_softc *sc; 1817 struct ifnet *ifp; 1818 u_int32_t reg, revision; 1819 int error, i, mac_offset, phy, rid, tmp; 1820 u_int8_t *mac; 1821 1822 sc = device_get_softc(dev); 1823 sc->dc_dev = dev; 1824 1825 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1826 MTX_DEF); 1827 1828 /* 1829 * Map control/status registers. 1830 */ 1831 pci_enable_busmaster(dev); 1832 1833 rid = DC_RID; 1834 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1835 1836 if (sc->dc_res == NULL) { 1837 device_printf(dev, "couldn't map ports/memory\n"); 1838 error = ENXIO; 1839 goto fail; 1840 } 1841 1842 sc->dc_btag = rman_get_bustag(sc->dc_res); 1843 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1844 1845 /* Allocate interrupt. */ 1846 rid = 0; 1847 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1848 RF_SHAREABLE | RF_ACTIVE); 1849 1850 if (sc->dc_irq == NULL) { 1851 device_printf(dev, "couldn't map interrupt\n"); 1852 error = ENXIO; 1853 goto fail; 1854 } 1855 1856 /* Need this info to decide on a chip type. */ 1857 sc->dc_info = dc_devtype(dev); 1858 revision = pci_get_revid(dev); 1859 1860 error = 0; 1861 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1862 if (sc->dc_info->dc_devid != 1863 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 1864 sc->dc_info->dc_devid != 1865 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 1866 dc_eeprom_width(sc); 1867 1868 switch (sc->dc_info->dc_devid) { 1869 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 1870 sc->dc_type = DC_TYPE_21143; 1871 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1872 sc->dc_flags |= DC_REDUCED_MII_POLL; 1873 /* Save EEPROM contents so we can parse them later. */ 1874 error = dc_read_srom(sc, sc->dc_romwidth); 1875 if (error != 0) 1876 goto fail; 1877 break; 1878 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 1879 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 1880 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 1881 sc->dc_type = DC_TYPE_DM9102; 1882 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1883 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1884 sc->dc_flags |= DC_TX_ALIGN; 1885 sc->dc_pmode = DC_PMODE_MII; 1886 1887 /* Increase the latency timer value. */ 1888 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 1889 break; 1890 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 1891 sc->dc_type = DC_TYPE_AL981; 1892 sc->dc_flags |= DC_TX_USE_TX_INTR; 1893 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1894 sc->dc_pmode = DC_PMODE_MII; 1895 error = dc_read_srom(sc, sc->dc_romwidth); 1896 if (error != 0) 1897 goto fail; 1898 break; 1899 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN983): 1900 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 1901 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 1902 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 1903 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 1904 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 1905 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 1906 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 1907 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 1908 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 1909 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 1910 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 1911 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 1912 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 1913 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 1914 sc->dc_type = DC_TYPE_AN983; 1915 sc->dc_flags |= DC_64BIT_HASH; 1916 sc->dc_flags |= DC_TX_USE_TX_INTR; 1917 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1918 sc->dc_pmode = DC_PMODE_MII; 1919 /* Don't read SROM for - auto-loaded on reset */ 1920 break; 1921 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 1922 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 1923 if (revision < DC_REVISION_98713A) { 1924 sc->dc_type = DC_TYPE_98713; 1925 } 1926 if (revision >= DC_REVISION_98713A) { 1927 sc->dc_type = DC_TYPE_98713A; 1928 sc->dc_flags |= DC_21143_NWAY; 1929 } 1930 sc->dc_flags |= DC_REDUCED_MII_POLL; 1931 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1932 break; 1933 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 1934 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 1935 /* 1936 * Macronix MX98715AEC-C/D/E parts have only a 1937 * 128-bit hash table. We need to deal with these 1938 * in the same manner as the PNIC II so that we 1939 * get the right number of bits out of the 1940 * CRC routine. 1941 */ 1942 if (revision >= DC_REVISION_98715AEC_C && 1943 revision < DC_REVISION_98725) 1944 sc->dc_flags |= DC_128BIT_HASH; 1945 sc->dc_type = DC_TYPE_987x5; 1946 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1947 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1948 break; 1949 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 1950 sc->dc_type = DC_TYPE_987x5; 1951 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1952 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1953 break; 1954 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 1955 sc->dc_type = DC_TYPE_PNICII; 1956 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1957 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1958 break; 1959 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 1960 sc->dc_type = DC_TYPE_PNIC; 1961 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1962 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1963 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1964 if (sc->dc_pnic_rx_buf == NULL) { 1965 device_printf(sc->dc_dev, 1966 "Could not allocate PNIC RX buffer\n"); 1967 error = ENOMEM; 1968 goto fail; 1969 } 1970 if (revision < DC_REVISION_82C169) 1971 sc->dc_pmode = DC_PMODE_SYM; 1972 break; 1973 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 1974 sc->dc_type = DC_TYPE_ASIX; 1975 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1976 sc->dc_flags |= DC_REDUCED_MII_POLL; 1977 sc->dc_pmode = DC_PMODE_MII; 1978 break; 1979 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 1980 sc->dc_type = DC_TYPE_XIRCOM; 1981 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1982 DC_TX_ALIGN; 1983 /* 1984 * We don't actually need to coalesce, but we're doing 1985 * it to obtain a double word aligned buffer. 1986 * The DC_TX_COALESCE flag is required. 1987 */ 1988 sc->dc_pmode = DC_PMODE_MII; 1989 break; 1990 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 1991 sc->dc_type = DC_TYPE_CONEXANT; 1992 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1993 sc->dc_flags |= DC_REDUCED_MII_POLL; 1994 sc->dc_pmode = DC_PMODE_MII; 1995 error = dc_read_srom(sc, sc->dc_romwidth); 1996 if (error != 0) 1997 goto fail; 1998 break; 1999 default: 2000 device_printf(dev, "unknown device: %x\n", 2001 sc->dc_info->dc_devid); 2002 break; 2003 } 2004 2005 /* Save the cache line size. */ 2006 if (DC_IS_DAVICOM(sc)) 2007 sc->dc_cachesize = 0; 2008 else 2009 sc->dc_cachesize = pci_get_cachelnsz(dev); 2010 2011 /* Reset the adapter. */ 2012 dc_reset(sc); 2013 2014 /* Take 21143 out of snooze mode */ 2015 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2016 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2017 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2018 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2019 } 2020 2021 /* 2022 * Try to learn something about the supported media. 2023 * We know that ASIX and ADMtek and Davicom devices 2024 * will *always* be using MII media, so that's a no-brainer. 2025 * The tricky ones are the Macronix/PNIC II and the 2026 * Intel 21143. 2027 */ 2028 if (DC_IS_INTEL(sc)) { 2029 error = dc_parse_21143_srom(sc); 2030 if (error != 0) 2031 goto fail; 2032 } else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2033 if (sc->dc_type == DC_TYPE_98713) 2034 sc->dc_pmode = DC_PMODE_MII; 2035 else 2036 sc->dc_pmode = DC_PMODE_SYM; 2037 } else if (!sc->dc_pmode) 2038 sc->dc_pmode = DC_PMODE_MII; 2039 2040 /* 2041 * Get station address from the EEPROM. 2042 */ 2043 switch(sc->dc_type) { 2044 case DC_TYPE_98713: 2045 case DC_TYPE_98713A: 2046 case DC_TYPE_987x5: 2047 case DC_TYPE_PNICII: 2048 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2049 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2050 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2051 break; 2052 case DC_TYPE_PNIC: 2053 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2054 break; 2055 case DC_TYPE_DM9102: 2056 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2057#ifdef __sparc64__ 2058 /* 2059 * If this is an onboard dc(4) the station address read from 2060 * the EEPROM is all zero and we have to get it from the FCode. 2061 */ 2062 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2063 OF_getetheraddr(dev, (caddr_t)&eaddr); 2064#endif 2065 break; 2066 case DC_TYPE_21143: 2067 case DC_TYPE_ASIX: 2068 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2069 break; 2070 case DC_TYPE_AL981: 2071 case DC_TYPE_AN983: 2072 reg = CSR_READ_4(sc, DC_AL_PAR0); 2073 mac = (uint8_t *)&eaddr[0]; 2074 mac[0] = (reg >> 0) & 0xff; 2075 mac[1] = (reg >> 8) & 0xff; 2076 mac[2] = (reg >> 16) & 0xff; 2077 mac[3] = (reg >> 24) & 0xff; 2078 reg = CSR_READ_4(sc, DC_AL_PAR1); 2079 mac[4] = (reg >> 0) & 0xff; 2080 mac[5] = (reg >> 8) & 0xff; 2081 break; 2082 case DC_TYPE_CONEXANT: 2083 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2084 ETHER_ADDR_LEN); 2085 break; 2086 case DC_TYPE_XIRCOM: 2087 /* The MAC comes from the CIS. */ 2088 mac = pci_get_ether(dev); 2089 if (!mac) { 2090 device_printf(dev, "No station address in CIS!\n"); 2091 error = ENXIO; 2092 goto fail; 2093 } 2094 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2095 break; 2096 default: 2097 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2098 break; 2099 } 2100 2101 bcopy(eaddr, sc->dc_eaddr, sizeof(eaddr)); 2102 /* 2103 * If we still have invalid station address, see whether we can 2104 * find station address for chip 0. Some multi-port controllers 2105 * just store station address for chip 0 if they have a shared 2106 * SROM. 2107 */ 2108 if ((sc->dc_eaddr[0] == 0 && (sc->dc_eaddr[1] & ~0xffff) == 0) || 2109 (sc->dc_eaddr[0] == 0xffffffff && 2110 (sc->dc_eaddr[1] & 0xffff) == 0xffff)) { 2111 if (dc_check_multiport(sc) == 0) 2112 bcopy(sc->dc_eaddr, eaddr, sizeof(eaddr)); 2113 } 2114 2115 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2116 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2117 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2118 sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data), 2119 0, NULL, NULL, &sc->dc_ltag); 2120 if (error) { 2121 device_printf(dev, "failed to allocate busdma tag\n"); 2122 error = ENXIO; 2123 goto fail; 2124 } 2125 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2126 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2127 if (error) { 2128 device_printf(dev, "failed to allocate DMA safe memory\n"); 2129 error = ENXIO; 2130 goto fail; 2131 } 2132 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2133 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2134 BUS_DMA_NOWAIT); 2135 if (error) { 2136 device_printf(dev, "cannot get address of the descriptors\n"); 2137 error = ENXIO; 2138 goto fail; 2139 } 2140 2141 /* 2142 * Allocate a busdma tag and DMA safe memory for the multicast 2143 * setup frame. 2144 */ 2145 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2146 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2147 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 2148 0, NULL, NULL, &sc->dc_stag); 2149 if (error) { 2150 device_printf(dev, "failed to allocate busdma tag\n"); 2151 error = ENXIO; 2152 goto fail; 2153 } 2154 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2155 BUS_DMA_NOWAIT, &sc->dc_smap); 2156 if (error) { 2157 device_printf(dev, "failed to allocate DMA safe memory\n"); 2158 error = ENXIO; 2159 goto fail; 2160 } 2161 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2162 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2163 if (error) { 2164 device_printf(dev, "cannot get address of the descriptors\n"); 2165 error = ENXIO; 2166 goto fail; 2167 } 2168 2169 /* Allocate a busdma tag for mbufs. */ 2170 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 2171 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2172 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 2173 0, NULL, NULL, &sc->dc_mtag); 2174 if (error) { 2175 device_printf(dev, "failed to allocate busdma tag\n"); 2176 error = ENXIO; 2177 goto fail; 2178 } 2179 2180 /* Create the TX/RX busdma maps. */ 2181 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2182 error = bus_dmamap_create(sc->dc_mtag, 0, 2183 &sc->dc_cdata.dc_tx_map[i]); 2184 if (error) { 2185 device_printf(dev, "failed to init TX ring\n"); 2186 error = ENXIO; 2187 goto fail; 2188 } 2189 } 2190 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2191 error = bus_dmamap_create(sc->dc_mtag, 0, 2192 &sc->dc_cdata.dc_rx_map[i]); 2193 if (error) { 2194 device_printf(dev, "failed to init RX ring\n"); 2195 error = ENXIO; 2196 goto fail; 2197 } 2198 } 2199 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2200 if (error) { 2201 device_printf(dev, "failed to init RX ring\n"); 2202 error = ENXIO; 2203 goto fail; 2204 } 2205 2206 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2207 if (ifp == NULL) { 2208 device_printf(dev, "can not if_alloc()\n"); 2209 error = ENOSPC; 2210 goto fail; 2211 } 2212 ifp->if_softc = sc; 2213 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2214 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2215 ifp->if_ioctl = dc_ioctl; 2216 ifp->if_start = dc_start; 2217 ifp->if_init = dc_init; 2218 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2219 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2220 IFQ_SET_READY(&ifp->if_snd); 2221 2222 /* 2223 * Do MII setup. If this is a 21143, check for a PHY on the 2224 * MII bus after applying any necessary fixups to twiddle the 2225 * GPIO bits. If we don't end up finding a PHY, restore the 2226 * old selection (SIA only or SIA/SYM) and attach the dcphy 2227 * driver instead. 2228 */ 2229 tmp = 0; 2230 if (DC_IS_INTEL(sc)) { 2231 dc_apply_fixup(sc, IFM_AUTO); 2232 tmp = sc->dc_pmode; 2233 sc->dc_pmode = DC_PMODE_MII; 2234 } 2235 2236 /* 2237 * Setup General Purpose port mode and data so the tulip can talk 2238 * to the MII. This needs to be done before mii_attach so that 2239 * we can actually see them. 2240 */ 2241 if (DC_IS_XIRCOM(sc)) { 2242 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2243 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2244 DELAY(10); 2245 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2246 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2247 DELAY(10); 2248 } 2249 2250 phy = MII_PHY_ANY; 2251 /* 2252 * Note: both the AL981 and AN983 have internal PHYs, however the 2253 * AL981 provides direct access to the PHY registers while the AN983 2254 * uses a serial MII interface. The AN983's MII interface is also 2255 * buggy in that you can read from any MII address (0 to 31), but 2256 * only address 1 behaves normally. To deal with both cases, we 2257 * pretend that the PHY is at MII address 1. 2258 */ 2259 if (DC_IS_ADMTEK(sc)) 2260 phy = DC_ADMTEK_PHYADDR; 2261 2262 /* 2263 * Note: the ukphy probes of the RS7112 report a PHY at MII address 2264 * 0 (possibly HomePNA?) and 1 (ethernet) so we only respond to the 2265 * correct one. 2266 */ 2267 if (DC_IS_CONEXANT(sc)) 2268 phy = DC_CONEXANT_PHYADDR; 2269 2270 error = mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2271 dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 2272 2273 if (error && DC_IS_INTEL(sc)) { 2274 sc->dc_pmode = tmp; 2275 if (sc->dc_pmode != DC_PMODE_SIA) 2276 sc->dc_pmode = DC_PMODE_SYM; 2277 sc->dc_flags |= DC_21143_NWAY; 2278 mii_attach(dev, &sc->dc_miibus, ifp, dc_ifmedia_upd, 2279 dc_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 2280 MII_OFFSET_ANY, 0); 2281 /* 2282 * For non-MII cards, we need to have the 21143 2283 * drive the LEDs. Except there are some systems 2284 * like the NEC VersaPro NoteBook PC which have no 2285 * LEDs, and twiddling these bits has adverse effects 2286 * on them. (I.e. you suddenly can't get a link.) 2287 */ 2288 if (!(pci_get_subvendor(dev) == 0x1033 && 2289 pci_get_subdevice(dev) == 0x8028)) 2290 sc->dc_flags |= DC_TULIP_LEDS; 2291 error = 0; 2292 } 2293 2294 if (error) { 2295 device_printf(dev, "attaching PHYs failed\n"); 2296 goto fail; 2297 } 2298 2299 if (DC_IS_ADMTEK(sc)) { 2300 /* 2301 * Set automatic TX underrun recovery for the ADMtek chips 2302 */ 2303 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2304 } 2305 2306 /* 2307 * Tell the upper layer(s) we support long frames. 2308 */ 2309 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2310 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2311 ifp->if_capenable = ifp->if_capabilities; 2312#ifdef DEVICE_POLLING 2313 ifp->if_capabilities |= IFCAP_POLLING; 2314#endif 2315 2316 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2317 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2318 2319 /* 2320 * Call MI attach routine. 2321 */ 2322 ether_ifattach(ifp, (caddr_t)eaddr); 2323 2324 /* Hook interrupt last to avoid having to lock softc */ 2325 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2326 NULL, dc_intr, sc, &sc->dc_intrhand); 2327 2328 if (error) { 2329 device_printf(dev, "couldn't set up irq\n"); 2330 ether_ifdetach(ifp); 2331 goto fail; 2332 } 2333 2334fail: 2335 if (error) 2336 dc_detach(dev); 2337 return (error); 2338} 2339 2340/* 2341 * Shutdown hardware and free up resources. This can be called any 2342 * time after the mutex has been initialized. It is called in both 2343 * the error case in attach and the normal detach case so it needs 2344 * to be careful about only freeing resources that have actually been 2345 * allocated. 2346 */ 2347static int 2348dc_detach(device_t dev) 2349{ 2350 struct dc_softc *sc; 2351 struct ifnet *ifp; 2352 struct dc_mediainfo *m; 2353 int i; 2354 2355 sc = device_get_softc(dev); 2356 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2357 2358 ifp = sc->dc_ifp; 2359 2360#ifdef DEVICE_POLLING 2361 if (ifp->if_capenable & IFCAP_POLLING) 2362 ether_poll_deregister(ifp); 2363#endif 2364 2365 /* These should only be active if attach succeeded */ 2366 if (device_is_attached(dev)) { 2367 DC_LOCK(sc); 2368 dc_stop(sc); 2369 DC_UNLOCK(sc); 2370 callout_drain(&sc->dc_stat_ch); 2371 callout_drain(&sc->dc_wdog_ch); 2372 ether_ifdetach(ifp); 2373 } 2374 if (sc->dc_miibus) 2375 device_delete_child(dev, sc->dc_miibus); 2376 bus_generic_detach(dev); 2377 2378 if (sc->dc_intrhand) 2379 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2380 if (sc->dc_irq) 2381 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2382 if (sc->dc_res) 2383 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2384 2385 if (ifp) 2386 if_free(ifp); 2387 2388 if (sc->dc_cdata.dc_sbuf != NULL) 2389 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2390 if (sc->dc_ldata != NULL) 2391 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2392 if (sc->dc_mtag) { 2393 for (i = 0; i < DC_TX_LIST_CNT; i++) 2394 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2395 bus_dmamap_destroy(sc->dc_mtag, 2396 sc->dc_cdata.dc_tx_map[i]); 2397 for (i = 0; i < DC_RX_LIST_CNT; i++) 2398 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2399 bus_dmamap_destroy(sc->dc_mtag, 2400 sc->dc_cdata.dc_rx_map[i]); 2401 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2402 } 2403 if (sc->dc_stag) 2404 bus_dma_tag_destroy(sc->dc_stag); 2405 if (sc->dc_mtag) 2406 bus_dma_tag_destroy(sc->dc_mtag); 2407 if (sc->dc_ltag) 2408 bus_dma_tag_destroy(sc->dc_ltag); 2409 2410 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2411 2412 while (sc->dc_mi != NULL) { 2413 m = sc->dc_mi->dc_next; 2414 free(sc->dc_mi, M_DEVBUF); 2415 sc->dc_mi = m; 2416 } 2417 free(sc->dc_srom, M_DEVBUF); 2418 2419 mtx_destroy(&sc->dc_mtx); 2420 2421 return (0); 2422} 2423 2424/* 2425 * Initialize the transmit descriptors. 2426 */ 2427static int 2428dc_list_tx_init(struct dc_softc *sc) 2429{ 2430 struct dc_chain_data *cd; 2431 struct dc_list_data *ld; 2432 int i, nexti; 2433 2434 cd = &sc->dc_cdata; 2435 ld = sc->dc_ldata; 2436 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2437 if (i == DC_TX_LIST_CNT - 1) 2438 nexti = 0; 2439 else 2440 nexti = i + 1; 2441 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2442 cd->dc_tx_chain[i] = NULL; 2443 ld->dc_tx_list[i].dc_data = 0; 2444 ld->dc_tx_list[i].dc_ctl = 0; 2445 } 2446 2447 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2448 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2449 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2450 return (0); 2451} 2452 2453 2454/* 2455 * Initialize the RX descriptors and allocate mbufs for them. Note that 2456 * we arrange the descriptors in a closed ring, so that the last descriptor 2457 * points back to the first. 2458 */ 2459static int 2460dc_list_rx_init(struct dc_softc *sc) 2461{ 2462 struct dc_chain_data *cd; 2463 struct dc_list_data *ld; 2464 int i, nexti; 2465 2466 cd = &sc->dc_cdata; 2467 ld = sc->dc_ldata; 2468 2469 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2470 if (dc_newbuf(sc, i, 1) != 0) 2471 return (ENOBUFS); 2472 if (i == DC_RX_LIST_CNT - 1) 2473 nexti = 0; 2474 else 2475 nexti = i + 1; 2476 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2477 } 2478 2479 cd->dc_rx_prod = 0; 2480 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2481 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2482 return (0); 2483} 2484 2485/* 2486 * Initialize an RX descriptor and attach an MBUF cluster. 2487 */ 2488static int 2489dc_newbuf(struct dc_softc *sc, int i, int alloc) 2490{ 2491 struct mbuf *m_new; 2492 bus_dmamap_t tmp; 2493 bus_dma_segment_t segs[1]; 2494 int error, nseg; 2495 2496 if (alloc) { 2497 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2498 if (m_new == NULL) 2499 return (ENOBUFS); 2500 } else { 2501 m_new = sc->dc_cdata.dc_rx_chain[i]; 2502 m_new->m_data = m_new->m_ext.ext_buf; 2503 } 2504 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2505 m_adj(m_new, sizeof(u_int64_t)); 2506 2507 /* 2508 * If this is a PNIC chip, zero the buffer. This is part 2509 * of the workaround for the receive bug in the 82c168 and 2510 * 82c169 chips. 2511 */ 2512 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2513 bzero(mtod(m_new, char *), m_new->m_len); 2514 2515 /* No need to remap the mbuf if we're reusing it. */ 2516 if (alloc) { 2517 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap, 2518 m_new, segs, &nseg, 0); 2519 if (error) { 2520 m_freem(m_new); 2521 return (error); 2522 } 2523 KASSERT(nseg == 1, 2524 ("%s: wrong number of segments (%d)", __func__, nseg)); 2525 sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr); 2526 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2527 tmp = sc->dc_cdata.dc_rx_map[i]; 2528 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2529 sc->dc_sparemap = tmp; 2530 sc->dc_cdata.dc_rx_chain[i] = m_new; 2531 } 2532 2533 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2534 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2535 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2536 BUS_DMASYNC_PREREAD); 2537 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2538 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2539 return (0); 2540} 2541 2542/* 2543 * Grrrrr. 2544 * The PNIC chip has a terrible bug in it that manifests itself during 2545 * periods of heavy activity. The exact mode of failure if difficult to 2546 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2547 * will happen on slow machines. The bug is that sometimes instead of 2548 * uploading one complete frame during reception, it uploads what looks 2549 * like the entire contents of its FIFO memory. The frame we want is at 2550 * the end of the whole mess, but we never know exactly how much data has 2551 * been uploaded, so salvaging the frame is hard. 2552 * 2553 * There is only one way to do it reliably, and it's disgusting. 2554 * Here's what we know: 2555 * 2556 * - We know there will always be somewhere between one and three extra 2557 * descriptors uploaded. 2558 * 2559 * - We know the desired received frame will always be at the end of the 2560 * total data upload. 2561 * 2562 * - We know the size of the desired received frame because it will be 2563 * provided in the length field of the status word in the last descriptor. 2564 * 2565 * Here's what we do: 2566 * 2567 * - When we allocate buffers for the receive ring, we bzero() them. 2568 * This means that we know that the buffer contents should be all 2569 * zeros, except for data uploaded by the chip. 2570 * 2571 * - We also force the PNIC chip to upload frames that include the 2572 * ethernet CRC at the end. 2573 * 2574 * - We gather all of the bogus frame data into a single buffer. 2575 * 2576 * - We then position a pointer at the end of this buffer and scan 2577 * backwards until we encounter the first non-zero byte of data. 2578 * This is the end of the received frame. We know we will encounter 2579 * some data at the end of the frame because the CRC will always be 2580 * there, so even if the sender transmits a packet of all zeros, 2581 * we won't be fooled. 2582 * 2583 * - We know the size of the actual received frame, so we subtract 2584 * that value from the current pointer location. This brings us 2585 * to the start of the actual received packet. 2586 * 2587 * - We copy this into an mbuf and pass it on, along with the actual 2588 * frame length. 2589 * 2590 * The performance hit is tremendous, but it beats dropping frames all 2591 * the time. 2592 */ 2593 2594#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2595static void 2596dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2597{ 2598 struct dc_desc *cur_rx; 2599 struct dc_desc *c = NULL; 2600 struct mbuf *m = NULL; 2601 unsigned char *ptr; 2602 int i, total_len; 2603 u_int32_t rxstat = 0; 2604 2605 i = sc->dc_pnic_rx_bug_save; 2606 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2607 ptr = sc->dc_pnic_rx_buf; 2608 bzero(ptr, DC_RXLEN * 5); 2609 2610 /* Copy all the bytes from the bogus buffers. */ 2611 while (1) { 2612 c = &sc->dc_ldata->dc_rx_list[i]; 2613 rxstat = le32toh(c->dc_status); 2614 m = sc->dc_cdata.dc_rx_chain[i]; 2615 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2616 ptr += DC_RXLEN; 2617 /* If this is the last buffer, break out. */ 2618 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2619 break; 2620 dc_newbuf(sc, i, 0); 2621 DC_INC(i, DC_RX_LIST_CNT); 2622 } 2623 2624 /* Find the length of the actual receive frame. */ 2625 total_len = DC_RXBYTES(rxstat); 2626 2627 /* Scan backwards until we hit a non-zero byte. */ 2628 while (*ptr == 0x00) 2629 ptr--; 2630 2631 /* Round off. */ 2632 if ((uintptr_t)(ptr) & 0x3) 2633 ptr -= 1; 2634 2635 /* Now find the start of the frame. */ 2636 ptr -= total_len; 2637 if (ptr < sc->dc_pnic_rx_buf) 2638 ptr = sc->dc_pnic_rx_buf; 2639 2640 /* 2641 * Now copy the salvaged frame to the last mbuf and fake up 2642 * the status word to make it look like a successful 2643 * frame reception. 2644 */ 2645 dc_newbuf(sc, i, 0); 2646 bcopy(ptr, mtod(m, char *), total_len); 2647 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2648} 2649 2650/* 2651 * This routine searches the RX ring for dirty descriptors in the 2652 * event that the rxeof routine falls out of sync with the chip's 2653 * current descriptor pointer. This may happen sometimes as a result 2654 * of a "no RX buffer available" condition that happens when the chip 2655 * consumes all of the RX buffers before the driver has a chance to 2656 * process the RX ring. This routine may need to be called more than 2657 * once to bring the driver back in sync with the chip, however we 2658 * should still be getting RX DONE interrupts to drive the search 2659 * for new packets in the RX ring, so we should catch up eventually. 2660 */ 2661static int 2662dc_rx_resync(struct dc_softc *sc) 2663{ 2664 struct dc_desc *cur_rx; 2665 int i, pos; 2666 2667 pos = sc->dc_cdata.dc_rx_prod; 2668 2669 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2670 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2671 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2672 break; 2673 DC_INC(pos, DC_RX_LIST_CNT); 2674 } 2675 2676 /* If the ring really is empty, then just return. */ 2677 if (i == DC_RX_LIST_CNT) 2678 return (0); 2679 2680 /* We've fallen behing the chip: catch it. */ 2681 sc->dc_cdata.dc_rx_prod = pos; 2682 2683 return (EAGAIN); 2684} 2685 2686/* 2687 * A frame has been uploaded: pass the resulting mbuf chain up to 2688 * the higher level protocols. 2689 */ 2690static int 2691dc_rxeof(struct dc_softc *sc) 2692{ 2693 struct mbuf *m, *m0; 2694 struct ifnet *ifp; 2695 struct dc_desc *cur_rx; 2696 int i, total_len, rx_npkts; 2697 u_int32_t rxstat; 2698 2699 DC_LOCK_ASSERT(sc); 2700 2701 ifp = sc->dc_ifp; 2702 i = sc->dc_cdata.dc_rx_prod; 2703 total_len = 0; 2704 rx_npkts = 0; 2705 2706 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2707 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2708 DC_RXSTAT_OWN)) { 2709#ifdef DEVICE_POLLING 2710 if (ifp->if_capenable & IFCAP_POLLING) { 2711 if (sc->rxcycles <= 0) 2712 break; 2713 sc->rxcycles--; 2714 } 2715#endif 2716 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2717 rxstat = le32toh(cur_rx->dc_status); 2718 m = sc->dc_cdata.dc_rx_chain[i]; 2719 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2720 BUS_DMASYNC_POSTREAD); 2721 total_len = DC_RXBYTES(rxstat); 2722 2723 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2724 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2725 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2726 sc->dc_pnic_rx_bug_save = i; 2727 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2728 DC_INC(i, DC_RX_LIST_CNT); 2729 continue; 2730 } 2731 dc_pnic_rx_bug_war(sc, i); 2732 rxstat = le32toh(cur_rx->dc_status); 2733 total_len = DC_RXBYTES(rxstat); 2734 } 2735 } 2736 2737 /* 2738 * If an error occurs, update stats, clear the 2739 * status word and leave the mbuf cluster in place: 2740 * it should simply get re-used next time this descriptor 2741 * comes up in the ring. However, don't report long 2742 * frames as errors since they could be vlans. 2743 */ 2744 if ((rxstat & DC_RXSTAT_RXERR)) { 2745 if (!(rxstat & DC_RXSTAT_GIANT) || 2746 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2747 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2748 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2749 ifp->if_ierrors++; 2750 if (rxstat & DC_RXSTAT_COLLSEEN) 2751 ifp->if_collisions++; 2752 dc_newbuf(sc, i, 0); 2753 if (rxstat & DC_RXSTAT_CRCERR) { 2754 DC_INC(i, DC_RX_LIST_CNT); 2755 continue; 2756 } else { 2757 dc_init_locked(sc); 2758 return (rx_npkts); 2759 } 2760 } 2761 } 2762 2763 /* No errors; receive the packet. */ 2764 total_len -= ETHER_CRC_LEN; 2765#ifdef __NO_STRICT_ALIGNMENT 2766 /* 2767 * On architectures without alignment problems we try to 2768 * allocate a new buffer for the receive ring, and pass up 2769 * the one where the packet is already, saving the expensive 2770 * copy done in m_devget(). 2771 * If we are on an architecture with alignment problems, or 2772 * if the allocation fails, then use m_devget and leave the 2773 * existing buffer in the receive ring. 2774 */ 2775 if (dc_newbuf(sc, i, 1) == 0) { 2776 m->m_pkthdr.rcvif = ifp; 2777 m->m_pkthdr.len = m->m_len = total_len; 2778 DC_INC(i, DC_RX_LIST_CNT); 2779 } else 2780#endif 2781 { 2782 m0 = m_devget(mtod(m, char *), total_len, 2783 ETHER_ALIGN, ifp, NULL); 2784 dc_newbuf(sc, i, 0); 2785 DC_INC(i, DC_RX_LIST_CNT); 2786 if (m0 == NULL) { 2787 ifp->if_ierrors++; 2788 continue; 2789 } 2790 m = m0; 2791 } 2792 2793 ifp->if_ipackets++; 2794 DC_UNLOCK(sc); 2795 (*ifp->if_input)(ifp, m); 2796 DC_LOCK(sc); 2797 rx_npkts++; 2798 } 2799 2800 sc->dc_cdata.dc_rx_prod = i; 2801 return (rx_npkts); 2802} 2803 2804/* 2805 * A frame was downloaded to the chip. It's safe for us to clean up 2806 * the list buffers. 2807 */ 2808static void 2809dc_txeof(struct dc_softc *sc) 2810{ 2811 struct dc_desc *cur_tx = NULL; 2812 struct ifnet *ifp; 2813 int idx; 2814 u_int32_t ctl, txstat; 2815 2816 ifp = sc->dc_ifp; 2817 2818 /* 2819 * Go through our tx list and free mbufs for those 2820 * frames that have been transmitted. 2821 */ 2822 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2823 idx = sc->dc_cdata.dc_tx_cons; 2824 while (idx != sc->dc_cdata.dc_tx_prod) { 2825 2826 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2827 txstat = le32toh(cur_tx->dc_status); 2828 ctl = le32toh(cur_tx->dc_ctl); 2829 2830 if (txstat & DC_TXSTAT_OWN) 2831 break; 2832 2833 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2834 if (ctl & DC_TXCTL_SETUP) { 2835 /* 2836 * Yes, the PNIC is so brain damaged 2837 * that it will sometimes generate a TX 2838 * underrun error while DMAing the RX 2839 * filter setup frame. If we detect this, 2840 * we have to send the setup frame again, 2841 * or else the filter won't be programmed 2842 * correctly. 2843 */ 2844 if (DC_IS_PNIC(sc)) { 2845 if (txstat & DC_TXSTAT_ERRSUM) 2846 dc_setfilt(sc); 2847 } 2848 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2849 } 2850 sc->dc_cdata.dc_tx_cnt--; 2851 DC_INC(idx, DC_TX_LIST_CNT); 2852 continue; 2853 } 2854 2855 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2856 /* 2857 * XXX: Why does my Xircom taunt me so? 2858 * For some reason it likes setting the CARRLOST flag 2859 * even when the carrier is there. wtf?!? 2860 * Who knows, but Conexant chips have the 2861 * same problem. Maybe they took lessons 2862 * from Xircom. 2863 */ 2864 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2865 sc->dc_pmode == DC_PMODE_MII && 2866 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2867 DC_TXSTAT_NOCARRIER))) 2868 txstat &= ~DC_TXSTAT_ERRSUM; 2869 } else { 2870 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2871 sc->dc_pmode == DC_PMODE_MII && 2872 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2873 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2874 txstat &= ~DC_TXSTAT_ERRSUM; 2875 } 2876 2877 if (txstat & DC_TXSTAT_ERRSUM) { 2878 ifp->if_oerrors++; 2879 if (txstat & DC_TXSTAT_EXCESSCOLL) 2880 ifp->if_collisions++; 2881 if (txstat & DC_TXSTAT_LATECOLL) 2882 ifp->if_collisions++; 2883 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2884 dc_init_locked(sc); 2885 return; 2886 } 2887 } 2888 2889 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2890 2891 ifp->if_opackets++; 2892 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2893 bus_dmamap_sync(sc->dc_mtag, 2894 sc->dc_cdata.dc_tx_map[idx], 2895 BUS_DMASYNC_POSTWRITE); 2896 bus_dmamap_unload(sc->dc_mtag, 2897 sc->dc_cdata.dc_tx_map[idx]); 2898 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2899 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2900 } 2901 2902 sc->dc_cdata.dc_tx_cnt--; 2903 DC_INC(idx, DC_TX_LIST_CNT); 2904 } 2905 sc->dc_cdata.dc_tx_cons = idx; 2906 2907 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD) 2908 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2909 2910 if (sc->dc_cdata.dc_tx_cnt == 0) 2911 sc->dc_wdog_timer = 0; 2912} 2913 2914static void 2915dc_tick(void *xsc) 2916{ 2917 struct dc_softc *sc; 2918 struct mii_data *mii; 2919 struct ifnet *ifp; 2920 u_int32_t r; 2921 2922 sc = xsc; 2923 DC_LOCK_ASSERT(sc); 2924 ifp = sc->dc_ifp; 2925 mii = device_get_softc(sc->dc_miibus); 2926 2927 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2928 if (sc->dc_flags & DC_21143_NWAY) { 2929 r = CSR_READ_4(sc, DC_10BTSTAT); 2930 if (IFM_SUBTYPE(mii->mii_media_active) == 2931 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2932 sc->dc_link = 0; 2933 mii_mediachg(mii); 2934 } 2935 if (IFM_SUBTYPE(mii->mii_media_active) == 2936 IFM_10_T && (r & DC_TSTAT_LS10)) { 2937 sc->dc_link = 0; 2938 mii_mediachg(mii); 2939 } 2940 if (sc->dc_link == 0) 2941 mii_tick(mii); 2942 } else { 2943 /* 2944 * For NICs which never report DC_RXSTATE_WAIT, we 2945 * have to bite the bullet... 2946 */ 2947 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 2948 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 2949 sc->dc_cdata.dc_tx_cnt == 0) { 2950 mii_tick(mii); 2951 if (!(mii->mii_media_status & IFM_ACTIVE)) 2952 sc->dc_link = 0; 2953 } 2954 } 2955 } else 2956 mii_tick(mii); 2957 2958 /* 2959 * When the init routine completes, we expect to be able to send 2960 * packets right away, and in fact the network code will send a 2961 * gratuitous ARP the moment the init routine marks the interface 2962 * as running. However, even though the MAC may have been initialized, 2963 * there may be a delay of a few seconds before the PHY completes 2964 * autonegotiation and the link is brought up. Any transmissions 2965 * made during that delay will be lost. Dealing with this is tricky: 2966 * we can't just pause in the init routine while waiting for the 2967 * PHY to come ready since that would bring the whole system to 2968 * a screeching halt for several seconds. 2969 * 2970 * What we do here is prevent the TX start routine from sending 2971 * any packets until a link has been established. After the 2972 * interface has been initialized, the tick routine will poll 2973 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2974 * that time, packets will stay in the send queue, and once the 2975 * link comes up, they will be flushed out to the wire. 2976 */ 2977 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2978 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2979 sc->dc_link++; 2980 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2981 dc_start_locked(ifp); 2982 } 2983 2984 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2985 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2986 else 2987 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2988} 2989 2990/* 2991 * A transmit underrun has occurred. Back off the transmit threshold, 2992 * or switch to store and forward mode if we have to. 2993 */ 2994static void 2995dc_tx_underrun(struct dc_softc *sc) 2996{ 2997 u_int32_t isr; 2998 int i; 2999 3000 if (DC_IS_DAVICOM(sc)) 3001 dc_init_locked(sc); 3002 3003 if (DC_IS_INTEL(sc)) { 3004 /* 3005 * The real 21143 requires that the transmitter be idle 3006 * in order to change the transmit threshold or store 3007 * and forward state. 3008 */ 3009 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3010 3011 for (i = 0; i < DC_TIMEOUT; i++) { 3012 isr = CSR_READ_4(sc, DC_ISR); 3013 if (isr & DC_ISR_TX_IDLE) 3014 break; 3015 DELAY(10); 3016 } 3017 if (i == DC_TIMEOUT) { 3018 device_printf(sc->dc_dev, 3019 "%s: failed to force tx to idle state\n", 3020 __func__); 3021 dc_init_locked(sc); 3022 } 3023 } 3024 3025 device_printf(sc->dc_dev, "TX underrun -- "); 3026 sc->dc_txthresh += DC_TXTHRESH_INC; 3027 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3028 printf("using store and forward mode\n"); 3029 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3030 } else { 3031 printf("increasing TX threshold\n"); 3032 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3033 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3034 } 3035 3036 if (DC_IS_INTEL(sc)) 3037 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3038} 3039 3040#ifdef DEVICE_POLLING 3041static poll_handler_t dc_poll; 3042 3043static int 3044dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3045{ 3046 struct dc_softc *sc = ifp->if_softc; 3047 int rx_npkts = 0; 3048 3049 DC_LOCK(sc); 3050 3051 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3052 DC_UNLOCK(sc); 3053 return (rx_npkts); 3054 } 3055 3056 sc->rxcycles = count; 3057 rx_npkts = dc_rxeof(sc); 3058 dc_txeof(sc); 3059 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3060 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3061 dc_start_locked(ifp); 3062 3063 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3064 u_int32_t status; 3065 3066 status = CSR_READ_4(sc, DC_ISR); 3067 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3068 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3069 DC_ISR_BUS_ERR); 3070 if (!status) { 3071 DC_UNLOCK(sc); 3072 return (rx_npkts); 3073 } 3074 /* ack what we have */ 3075 CSR_WRITE_4(sc, DC_ISR, status); 3076 3077 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3078 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3079 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3080 3081 if (dc_rx_resync(sc)) 3082 dc_rxeof(sc); 3083 } 3084 /* restart transmit unit if necessary */ 3085 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3086 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3087 3088 if (status & DC_ISR_TX_UNDERRUN) 3089 dc_tx_underrun(sc); 3090 3091 if (status & DC_ISR_BUS_ERR) { 3092 if_printf(ifp, "%s: bus error\n", __func__); 3093 dc_reset(sc); 3094 dc_init_locked(sc); 3095 } 3096 } 3097 DC_UNLOCK(sc); 3098 return (rx_npkts); 3099} 3100#endif /* DEVICE_POLLING */ 3101 3102static void 3103dc_intr(void *arg) 3104{ 3105 struct dc_softc *sc; 3106 struct ifnet *ifp; 3107 u_int32_t status; 3108 3109 sc = arg; 3110 3111 if (sc->suspended) 3112 return; 3113 3114 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3115 return; 3116 3117 DC_LOCK(sc); 3118 ifp = sc->dc_ifp; 3119#ifdef DEVICE_POLLING 3120 if (ifp->if_capenable & IFCAP_POLLING) { 3121 DC_UNLOCK(sc); 3122 return; 3123 } 3124#endif 3125 3126 /* Suppress unwanted interrupts */ 3127 if (!(ifp->if_flags & IFF_UP)) { 3128 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3129 dc_stop(sc); 3130 DC_UNLOCK(sc); 3131 return; 3132 } 3133 3134 /* Disable interrupts. */ 3135 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3136 3137 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3138 status != 0xFFFFFFFF && 3139 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3140 3141 CSR_WRITE_4(sc, DC_ISR, status); 3142 3143 if (status & DC_ISR_RX_OK) { 3144 int curpkts; 3145 curpkts = ifp->if_ipackets; 3146 dc_rxeof(sc); 3147 if (curpkts == ifp->if_ipackets) { 3148 while (dc_rx_resync(sc)) 3149 dc_rxeof(sc); 3150 } 3151 } 3152 3153 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3154 dc_txeof(sc); 3155 3156 if (status & DC_ISR_TX_IDLE) { 3157 dc_txeof(sc); 3158 if (sc->dc_cdata.dc_tx_cnt) { 3159 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3160 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3161 } 3162 } 3163 3164 if (status & DC_ISR_TX_UNDERRUN) 3165 dc_tx_underrun(sc); 3166 3167 if ((status & DC_ISR_RX_WATDOGTIMEO) 3168 || (status & DC_ISR_RX_NOBUF)) { 3169 int curpkts; 3170 curpkts = ifp->if_ipackets; 3171 dc_rxeof(sc); 3172 if (curpkts == ifp->if_ipackets) { 3173 while (dc_rx_resync(sc)) 3174 dc_rxeof(sc); 3175 } 3176 } 3177 3178 if (status & DC_ISR_BUS_ERR) { 3179 dc_reset(sc); 3180 dc_init_locked(sc); 3181 } 3182 } 3183 3184 /* Re-enable interrupts. */ 3185 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3186 3187 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3188 dc_start_locked(ifp); 3189 3190 DC_UNLOCK(sc); 3191} 3192 3193/* 3194 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3195 * pointers to the fragment pointers. 3196 */ 3197static int 3198dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3199{ 3200 bus_dma_segment_t segs[DC_MAXFRAGS]; 3201 struct dc_desc *f; 3202 struct mbuf *m; 3203 int cur, defragged, error, first, frag, i, idx, nseg; 3204 3205 /* 3206 * If there's no way we can send any packets, return now. 3207 */ 3208 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD) 3209 return (ENOBUFS); 3210 3211 m = NULL; 3212 defragged = 0; 3213 if (sc->dc_flags & DC_TX_COALESCE && 3214 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3215 m = m_defrag(*m_head, M_DONTWAIT); 3216 defragged = 1; 3217 } else { 3218 /* 3219 * Count the number of frags in this chain to see if we 3220 * need to m_collapse. Since the descriptor list is shared 3221 * by all packets, we'll m_collapse long chains so that they 3222 * do not use up the entire list, even if they would fit. 3223 */ 3224 i = 0; 3225 for (m = *m_head; m != NULL; m = m->m_next) 3226 i++; 3227 if (i > DC_TX_LIST_CNT / 4 || 3228 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3229 DC_TX_LIST_RSVD) { 3230 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); 3231 defragged = 1; 3232 } 3233 } 3234 if (defragged != 0) { 3235 if (m == NULL) { 3236 m_freem(*m_head); 3237 *m_head = NULL; 3238 return (ENOBUFS); 3239 } 3240 *m_head = m; 3241 } 3242 3243 idx = sc->dc_cdata.dc_tx_prod; 3244 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3245 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3246 if (error == EFBIG) { 3247 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, 3248 DC_MAXFRAGS)) == NULL) { 3249 m_freem(*m_head); 3250 *m_head = NULL; 3251 return (defragged != 0 ? error : ENOBUFS); 3252 } 3253 *m_head = m; 3254 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3255 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3256 if (error != 0) { 3257 m_freem(*m_head); 3258 *m_head = NULL; 3259 return (error); 3260 } 3261 } else if (error != 0) 3262 return (error); 3263 KASSERT(nseg <= DC_MAXFRAGS, 3264 ("%s: wrong number of segments (%d)", __func__, nseg)); 3265 if (nseg == 0) { 3266 m_freem(*m_head); 3267 *m_head = NULL; 3268 return (EIO); 3269 } 3270 3271 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3272 for (i = 0; i < nseg; i++) { 3273 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3274 (frag == (DC_TX_LIST_CNT - 1)) && 3275 (first != sc->dc_cdata.dc_tx_first)) { 3276 bus_dmamap_unload(sc->dc_mtag, 3277 sc->dc_cdata.dc_tx_map[first]); 3278 m_freem(*m_head); 3279 *m_head = NULL; 3280 return (ENOBUFS); 3281 } 3282 3283 f = &sc->dc_ldata->dc_tx_list[frag]; 3284 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3285 if (i == 0) { 3286 f->dc_status = 0; 3287 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3288 } else 3289 f->dc_status = htole32(DC_TXSTAT_OWN); 3290 f->dc_data = htole32(segs[i].ds_addr); 3291 cur = frag; 3292 DC_INC(frag, DC_TX_LIST_CNT); 3293 } 3294 3295 sc->dc_cdata.dc_tx_prod = frag; 3296 sc->dc_cdata.dc_tx_cnt += nseg; 3297 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3298 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3299 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3300 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3301 htole32(DC_TXCTL_FINT); 3302 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3303 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3304 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3305 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3306 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3307 3308 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3309 BUS_DMASYNC_PREWRITE); 3310 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3311 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3312 return (0); 3313} 3314 3315static void 3316dc_start(struct ifnet *ifp) 3317{ 3318 struct dc_softc *sc; 3319 3320 sc = ifp->if_softc; 3321 DC_LOCK(sc); 3322 dc_start_locked(ifp); 3323 DC_UNLOCK(sc); 3324} 3325 3326/* 3327 * Main transmit routine 3328 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3329 * regions directly in the transmit lists. We also save a copy of the 3330 * pointers since the transmit list fragment pointers are physical 3331 * addresses. 3332 */ 3333static void 3334dc_start_locked(struct ifnet *ifp) 3335{ 3336 struct dc_softc *sc; 3337 struct mbuf *m_head = NULL; 3338 unsigned int queued = 0; 3339 int idx; 3340 3341 sc = ifp->if_softc; 3342 3343 DC_LOCK_ASSERT(sc); 3344 3345 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3346 return; 3347 3348 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3349 return; 3350 3351 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3352 3353 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3354 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3355 if (m_head == NULL) 3356 break; 3357 3358 if (dc_encap(sc, &m_head)) { 3359 if (m_head == NULL) 3360 break; 3361 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3362 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3363 break; 3364 } 3365 idx = sc->dc_cdata.dc_tx_prod; 3366 3367 queued++; 3368 /* 3369 * If there's a BPF listener, bounce a copy of this frame 3370 * to him. 3371 */ 3372 BPF_MTAP(ifp, m_head); 3373 3374 if (sc->dc_flags & DC_TX_ONE) { 3375 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3376 break; 3377 } 3378 } 3379 3380 if (queued > 0) { 3381 /* Transmit */ 3382 if (!(sc->dc_flags & DC_TX_POLL)) 3383 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3384 3385 /* 3386 * Set a timeout in case the chip goes out to lunch. 3387 */ 3388 sc->dc_wdog_timer = 5; 3389 } 3390} 3391 3392static void 3393dc_init(void *xsc) 3394{ 3395 struct dc_softc *sc = xsc; 3396 3397 DC_LOCK(sc); 3398 dc_init_locked(sc); 3399 DC_UNLOCK(sc); 3400} 3401 3402static void 3403dc_init_locked(struct dc_softc *sc) 3404{ 3405 struct ifnet *ifp = sc->dc_ifp; 3406 struct mii_data *mii; 3407 3408 DC_LOCK_ASSERT(sc); 3409 3410 mii = device_get_softc(sc->dc_miibus); 3411 3412 /* 3413 * Cancel pending I/O and free all RX/TX buffers. 3414 */ 3415 dc_stop(sc); 3416 dc_reset(sc); 3417 3418 /* 3419 * Set cache alignment and burst length. 3420 */ 3421 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3422 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3423 else 3424 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3425 /* 3426 * Evenly share the bus between receive and transmit process. 3427 */ 3428 if (DC_IS_INTEL(sc)) 3429 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3430 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3431 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3432 } else { 3433 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3434 } 3435 if (sc->dc_flags & DC_TX_POLL) 3436 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3437 switch(sc->dc_cachesize) { 3438 case 32: 3439 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3440 break; 3441 case 16: 3442 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3443 break; 3444 case 8: 3445 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3446 break; 3447 case 0: 3448 default: 3449 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3450 break; 3451 } 3452 3453 if (sc->dc_flags & DC_TX_STORENFWD) 3454 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3455 else { 3456 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3457 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3458 } else { 3459 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3460 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3461 } 3462 } 3463 3464 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3465 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3466 3467 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3468 /* 3469 * The app notes for the 98713 and 98715A say that 3470 * in order to have the chips operate properly, a magic 3471 * number must be written to CSR16. Macronix does not 3472 * document the meaning of these bits so there's no way 3473 * to know exactly what they do. The 98713 has a magic 3474 * number all its own; the rest all use a different one. 3475 */ 3476 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3477 if (sc->dc_type == DC_TYPE_98713) 3478 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3479 else 3480 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3481 } 3482 3483 if (DC_IS_XIRCOM(sc)) { 3484 /* 3485 * setup General Purpose Port mode and data so the tulip 3486 * can talk to the MII. 3487 */ 3488 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3489 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3490 DELAY(10); 3491 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3492 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3493 DELAY(10); 3494 } 3495 3496 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3497 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3498 3499 /* Init circular RX list. */ 3500 if (dc_list_rx_init(sc) == ENOBUFS) { 3501 device_printf(sc->dc_dev, 3502 "initialization failed: no memory for rx buffers\n"); 3503 dc_stop(sc); 3504 return; 3505 } 3506 3507 /* 3508 * Init TX descriptors. 3509 */ 3510 dc_list_tx_init(sc); 3511 3512 /* 3513 * Load the address of the RX list. 3514 */ 3515 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3516 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3517 3518 /* 3519 * Enable interrupts. 3520 */ 3521#ifdef DEVICE_POLLING 3522 /* 3523 * ... but only if we are not polling, and make sure they are off in 3524 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3525 * after a reset. 3526 */ 3527 if (ifp->if_capenable & IFCAP_POLLING) 3528 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3529 else 3530#endif 3531 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3532 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3533 3534 /* Enable transmitter. */ 3535 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3536 3537 /* 3538 * If this is an Intel 21143 and we're not using the 3539 * MII port, program the LED control pins so we get 3540 * link and activity indications. 3541 */ 3542 if (sc->dc_flags & DC_TULIP_LEDS) { 3543 CSR_WRITE_4(sc, DC_WATCHDOG, 3544 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3545 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3546 } 3547 3548 /* 3549 * Load the RX/multicast filter. We do this sort of late 3550 * because the filter programming scheme on the 21143 and 3551 * some clones requires DMAing a setup frame via the TX 3552 * engine, and we need the transmitter enabled for that. 3553 */ 3554 dc_setfilt(sc); 3555 3556 /* Enable receiver. */ 3557 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3558 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3559 3560 mii_mediachg(mii); 3561 dc_setcfg(sc, sc->dc_if_media); 3562 3563 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3564 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3565 3566 /* Don't start the ticker if this is a homePNA link. */ 3567 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3568 sc->dc_link = 1; 3569 else { 3570 if (sc->dc_flags & DC_21143_NWAY) 3571 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3572 else 3573 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3574 } 3575 3576 sc->dc_wdog_timer = 0; 3577 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3578} 3579 3580/* 3581 * Set media options. 3582 */ 3583static int 3584dc_ifmedia_upd(struct ifnet *ifp) 3585{ 3586 struct dc_softc *sc; 3587 struct mii_data *mii; 3588 struct ifmedia *ifm; 3589 3590 sc = ifp->if_softc; 3591 mii = device_get_softc(sc->dc_miibus); 3592 DC_LOCK(sc); 3593 mii_mediachg(mii); 3594 ifm = &mii->mii_media; 3595 3596 if (DC_IS_DAVICOM(sc) && 3597 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3598 dc_setcfg(sc, ifm->ifm_media); 3599 else 3600 sc->dc_link = 0; 3601 DC_UNLOCK(sc); 3602 3603 return (0); 3604} 3605 3606/* 3607 * Report current media status. 3608 */ 3609static void 3610dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3611{ 3612 struct dc_softc *sc; 3613 struct mii_data *mii; 3614 struct ifmedia *ifm; 3615 3616 sc = ifp->if_softc; 3617 mii = device_get_softc(sc->dc_miibus); 3618 DC_LOCK(sc); 3619 mii_pollstat(mii); 3620 ifm = &mii->mii_media; 3621 if (DC_IS_DAVICOM(sc)) { 3622 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3623 ifmr->ifm_active = ifm->ifm_media; 3624 ifmr->ifm_status = 0; 3625 DC_UNLOCK(sc); 3626 return; 3627 } 3628 } 3629 ifmr->ifm_active = mii->mii_media_active; 3630 ifmr->ifm_status = mii->mii_media_status; 3631 DC_UNLOCK(sc); 3632} 3633 3634static int 3635dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3636{ 3637 struct dc_softc *sc = ifp->if_softc; 3638 struct ifreq *ifr = (struct ifreq *)data; 3639 struct mii_data *mii; 3640 int error = 0; 3641 3642 switch (command) { 3643 case SIOCSIFFLAGS: 3644 DC_LOCK(sc); 3645 if (ifp->if_flags & IFF_UP) { 3646 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3647 (IFF_PROMISC | IFF_ALLMULTI); 3648 3649 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3650 if (need_setfilt) 3651 dc_setfilt(sc); 3652 } else { 3653 sc->dc_txthresh = 0; 3654 dc_init_locked(sc); 3655 } 3656 } else { 3657 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3658 dc_stop(sc); 3659 } 3660 sc->dc_if_flags = ifp->if_flags; 3661 DC_UNLOCK(sc); 3662 error = 0; 3663 break; 3664 case SIOCADDMULTI: 3665 case SIOCDELMULTI: 3666 DC_LOCK(sc); 3667 dc_setfilt(sc); 3668 DC_UNLOCK(sc); 3669 error = 0; 3670 break; 3671 case SIOCGIFMEDIA: 3672 case SIOCSIFMEDIA: 3673 mii = device_get_softc(sc->dc_miibus); 3674 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3675 break; 3676 case SIOCSIFCAP: 3677#ifdef DEVICE_POLLING 3678 if (ifr->ifr_reqcap & IFCAP_POLLING && 3679 !(ifp->if_capenable & IFCAP_POLLING)) { 3680 error = ether_poll_register(dc_poll, ifp); 3681 if (error) 3682 return(error); 3683 DC_LOCK(sc); 3684 /* Disable interrupts */ 3685 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3686 ifp->if_capenable |= IFCAP_POLLING; 3687 DC_UNLOCK(sc); 3688 return (error); 3689 } 3690 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3691 ifp->if_capenable & IFCAP_POLLING) { 3692 error = ether_poll_deregister(ifp); 3693 /* Enable interrupts. */ 3694 DC_LOCK(sc); 3695 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3696 ifp->if_capenable &= ~IFCAP_POLLING; 3697 DC_UNLOCK(sc); 3698 return (error); 3699 } 3700#endif /* DEVICE_POLLING */ 3701 break; 3702 default: 3703 error = ether_ioctl(ifp, command, data); 3704 break; 3705 } 3706 3707 return (error); 3708} 3709 3710static void 3711dc_watchdog(void *xsc) 3712{ 3713 struct dc_softc *sc = xsc; 3714 struct ifnet *ifp; 3715 3716 DC_LOCK_ASSERT(sc); 3717 3718 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3719 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3720 return; 3721 } 3722 3723 ifp = sc->dc_ifp; 3724 ifp->if_oerrors++; 3725 device_printf(sc->dc_dev, "watchdog timeout\n"); 3726 3727 dc_stop(sc); 3728 dc_reset(sc); 3729 dc_init_locked(sc); 3730 3731 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3732 dc_start_locked(ifp); 3733} 3734 3735/* 3736 * Stop the adapter and free any mbufs allocated to the 3737 * RX and TX lists. 3738 */ 3739static void 3740dc_stop(struct dc_softc *sc) 3741{ 3742 struct ifnet *ifp; 3743 struct dc_list_data *ld; 3744 struct dc_chain_data *cd; 3745 int i; 3746 u_int32_t ctl; 3747 3748 DC_LOCK_ASSERT(sc); 3749 3750 ifp = sc->dc_ifp; 3751 ld = sc->dc_ldata; 3752 cd = &sc->dc_cdata; 3753 3754 callout_stop(&sc->dc_stat_ch); 3755 callout_stop(&sc->dc_wdog_ch); 3756 sc->dc_wdog_timer = 0; 3757 3758 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3759 3760 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3761 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3762 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3763 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3764 sc->dc_link = 0; 3765 3766 /* 3767 * Free data in the RX lists. 3768 */ 3769 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3770 if (cd->dc_rx_chain[i] != NULL) { 3771 m_freem(cd->dc_rx_chain[i]); 3772 cd->dc_rx_chain[i] = NULL; 3773 } 3774 } 3775 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3776 3777 /* 3778 * Free the TX list buffers. 3779 */ 3780 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3781 if (cd->dc_tx_chain[i] != NULL) { 3782 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3783 if ((ctl & DC_TXCTL_SETUP) || 3784 !(ctl & DC_TXCTL_LASTFRAG)) { 3785 cd->dc_tx_chain[i] = NULL; 3786 continue; 3787 } 3788 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3789 m_freem(cd->dc_tx_chain[i]); 3790 cd->dc_tx_chain[i] = NULL; 3791 } 3792 } 3793 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3794} 3795 3796/* 3797 * Device suspend routine. Stop the interface and save some PCI 3798 * settings in case the BIOS doesn't restore them properly on 3799 * resume. 3800 */ 3801static int 3802dc_suspend(device_t dev) 3803{ 3804 struct dc_softc *sc; 3805 3806 sc = device_get_softc(dev); 3807 DC_LOCK(sc); 3808 dc_stop(sc); 3809 sc->suspended = 1; 3810 DC_UNLOCK(sc); 3811 3812 return (0); 3813} 3814 3815/* 3816 * Device resume routine. Restore some PCI settings in case the BIOS 3817 * doesn't, re-enable busmastering, and restart the interface if 3818 * appropriate. 3819 */ 3820static int 3821dc_resume(device_t dev) 3822{ 3823 struct dc_softc *sc; 3824 struct ifnet *ifp; 3825 3826 sc = device_get_softc(dev); 3827 ifp = sc->dc_ifp; 3828 3829 /* reinitialize interface if necessary */ 3830 DC_LOCK(sc); 3831 if (ifp->if_flags & IFF_UP) 3832 dc_init_locked(sc); 3833 3834 sc->suspended = 0; 3835 DC_UNLOCK(sc); 3836 3837 return (0); 3838} 3839 3840/* 3841 * Stop all chip I/O so that the kernel's probe routines don't 3842 * get confused by errant DMAs when rebooting. 3843 */ 3844static int 3845dc_shutdown(device_t dev) 3846{ 3847 struct dc_softc *sc; 3848 3849 sc = device_get_softc(dev); 3850 3851 DC_LOCK(sc); 3852 dc_stop(sc); 3853 DC_UNLOCK(sc); 3854 3855 return (0); 3856} 3857 3858static int 3859dc_check_multiport(struct dc_softc *sc) 3860{ 3861 struct dc_softc *dsc; 3862 devclass_t dc; 3863 device_t child; 3864 uint8_t *eaddr; 3865 int unit; 3866 3867 dc = devclass_find("dc"); 3868 for (unit = 0; unit < devclass_get_maxunit(dc); unit++) { 3869 child = devclass_get_device(dc, unit); 3870 if (child == NULL) 3871 continue; 3872 if (child == sc->dc_dev) 3873 continue; 3874 if (device_get_parent(child) != device_get_parent(sc->dc_dev)) 3875 continue; 3876 if (unit > device_get_unit(sc->dc_dev)) 3877 continue; 3878 dsc = device_get_softc(child); 3879 device_printf(sc->dc_dev, "Using station address of %s as base", 3880 device_get_nameunit(child)); 3881 bcopy(dsc->dc_eaddr, sc->dc_eaddr, ETHER_ADDR_LEN); 3882 eaddr = (uint8_t *)sc->dc_eaddr; 3883 eaddr[5]++; 3884 return (0); 3885 } 3886 return (ENOENT); 3887} 3888