if_dc.c revision 193096
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/dc/if_dc.c 193096 2009-05-30 15:14:44Z attilio $"); 35 36/* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66/* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94#ifdef HAVE_KERNEL_OPTION_HEADERS 95#include "opt_device_polling.h" 96#endif 97 98#include <sys/param.h> 99#include <sys/endian.h> 100#include <sys/systm.h> 101#include <sys/sockio.h> 102#include <sys/mbuf.h> 103#include <sys/malloc.h> 104#include <sys/kernel.h> 105#include <sys/module.h> 106#include <sys/socket.h> 107 108#include <net/if.h> 109#include <net/if_arp.h> 110#include <net/ethernet.h> 111#include <net/if_dl.h> 112#include <net/if_media.h> 113#include <net/if_types.h> 114#include <net/if_vlan_var.h> 115 116#include <net/bpf.h> 117 118#include <machine/bus.h> 119#include <machine/resource.h> 120#include <sys/bus.h> 121#include <sys/rman.h> 122 123#include <dev/mii/mii.h> 124#include <dev/mii/miivar.h> 125 126#include <dev/pci/pcireg.h> 127#include <dev/pci/pcivar.h> 128 129#define DC_USEIOSPACE 130 131#include <dev/dc/if_dcreg.h> 132 133#ifdef __sparc64__ 134#include <dev/ofw/openfirm.h> 135#include <machine/ofw_machdep.h> 136#endif 137 138MODULE_DEPEND(dc, pci, 1, 1, 1); 139MODULE_DEPEND(dc, ether, 1, 1, 1); 140MODULE_DEPEND(dc, miibus, 1, 1, 1); 141 142/* 143 * "device miibus" is required in kernel config. See GENERIC if you get 144 * errors here. 145 */ 146#include "miibus_if.h" 147 148/* 149 * Various supported device vendors/types and their names. 150 */ 151static const struct dc_type dc_devs[] = { 152 { DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143), 0, 153 "Intel 21143 10/100BaseTX" }, 154 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009), 0, 155 "Davicom DM9009 10/100BaseTX" }, 156 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100), 0, 157 "Davicom DM9100 10/100BaseTX" }, 158 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), DC_REVISION_DM9102A, 159 "Davicom DM9102A 10/100BaseTX" }, 160 { DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102), 0, 161 "Davicom DM9102 10/100BaseTX" }, 162 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981), 0, 163 "ADMtek AL981 10/100BaseTX" }, 164 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985), 0, 165 "ADMtek AN985 10/100BaseTX" }, 166 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511), 0, 167 "ADMtek ADM9511 10/100BaseTX" }, 168 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513), 0, 169 "ADMtek ADM9513 10/100BaseTX" }, 170 { DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511), 0, 171 "Netgear FA511 10/100BaseTX" }, 172 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), DC_REVISION_88141, 173 "ASIX AX88141 10/100BaseTX" }, 174 { DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A), 0, 175 "ASIX AX88140A 10/100BaseTX" }, 176 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), DC_REVISION_98713A, 177 "Macronix 98713A 10/100BaseTX" }, 178 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713), 0, 179 "Macronix 98713 10/100BaseTX" }, 180 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), DC_REVISION_98713A, 181 "Compex RL100-TX 10/100BaseTX" }, 182 { DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP), 0, 183 "Compex RL100-TX 10/100BaseTX" }, 184 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98725, 185 "Macronix 98725 10/100BaseTX" }, 186 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), DC_REVISION_98715AEC_C, 187 "Macronix 98715AEC-C 10/100BaseTX" }, 188 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5), 0, 189 "Macronix 98715/98715A 10/100BaseTX" }, 190 { DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727), 0, 191 "Macronix 98727/98732 10/100BaseTX" }, 192 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115), 0, 193 "LC82C115 PNIC II 10/100BaseTX" }, 194 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), DC_REVISION_82C169, 195 "82c169 PNIC 10/100BaseTX" }, 196 { DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168), 0, 197 "82c168 PNIC 10/100BaseTX" }, 198 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217), 0, 199 "Accton EN1217 10/100BaseTX" }, 200 { DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242), 0, 201 "Accton EN2242 MiniPCI 10/100BaseTX" }, 202 { DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201), 0, 203 "Xircom X3201 10/100BaseTX" }, 204 { DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD), 0, 205 "Neteasy DRP-32TXD Cardbus 10/100" }, 206 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500), 0, 207 "Abocom FE2500 10/100BaseTX" }, 208 { DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX), 0, 209 "Abocom FE2500MX 10/100BaseTX" }, 210 { DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112), 0, 211 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 212 { DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX), 0, 213 "Hawking CB102 CardBus 10/100" }, 214 { DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T), 0, 215 "PlaneX FNW-3602-T CardBus 10/100" }, 216 { DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB), 0, 217 "3Com OfficeConnect 10/100B" }, 218 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120), 0, 219 "Microsoft MN-120 CardBus 10/100" }, 220 { DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130), 0, 221 "Microsoft MN-130 10/100" }, 222 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08), 0, 223 "Linksys PCMPC200 CardBus 10/100" }, 224 { DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09), 0, 225 "Linksys PCMPC200 CardBus 10/100" }, 226 { 0, 0, NULL } 227}; 228 229static int dc_probe(device_t); 230static int dc_attach(device_t); 231static int dc_detach(device_t); 232static int dc_suspend(device_t); 233static int dc_resume(device_t); 234static const struct dc_type *dc_devtype(device_t); 235static int dc_newbuf(struct dc_softc *, int, int); 236static int dc_encap(struct dc_softc *, struct mbuf **); 237static void dc_pnic_rx_bug_war(struct dc_softc *, int); 238static int dc_rx_resync(struct dc_softc *); 239static int dc_rxeof(struct dc_softc *); 240static void dc_txeof(struct dc_softc *); 241static void dc_tick(void *); 242static void dc_tx_underrun(struct dc_softc *); 243static void dc_intr(void *); 244static void dc_start(struct ifnet *); 245static void dc_start_locked(struct ifnet *); 246static int dc_ioctl(struct ifnet *, u_long, caddr_t); 247static void dc_init(void *); 248static void dc_init_locked(struct dc_softc *); 249static void dc_stop(struct dc_softc *); 250static void dc_watchdog(void *); 251static int dc_shutdown(device_t); 252static int dc_ifmedia_upd(struct ifnet *); 253static void dc_ifmedia_sts(struct ifnet *, struct ifmediareq *); 254 255static void dc_delay(struct dc_softc *); 256static void dc_eeprom_idle(struct dc_softc *); 257static void dc_eeprom_putbyte(struct dc_softc *, int); 258static void dc_eeprom_getword(struct dc_softc *, int, u_int16_t *); 259static void dc_eeprom_getword_pnic(struct dc_softc *, int, u_int16_t *); 260static void dc_eeprom_getword_xircom(struct dc_softc *, int, u_int16_t *); 261static void dc_eeprom_width(struct dc_softc *); 262static void dc_read_eeprom(struct dc_softc *, caddr_t, int, int, int); 263 264static void dc_mii_writebit(struct dc_softc *, int); 265static int dc_mii_readbit(struct dc_softc *); 266static void dc_mii_sync(struct dc_softc *); 267static void dc_mii_send(struct dc_softc *, u_int32_t, int); 268static int dc_mii_readreg(struct dc_softc *, struct dc_mii_frame *); 269static int dc_mii_writereg(struct dc_softc *, struct dc_mii_frame *); 270static int dc_miibus_readreg(device_t, int, int); 271static int dc_miibus_writereg(device_t, int, int, int); 272static void dc_miibus_statchg(device_t); 273static void dc_miibus_mediainit(device_t); 274 275static void dc_setcfg(struct dc_softc *, int); 276static uint32_t dc_mchash_le(struct dc_softc *, const uint8_t *); 277static uint32_t dc_mchash_be(const uint8_t *); 278static void dc_setfilt_21143(struct dc_softc *); 279static void dc_setfilt_asix(struct dc_softc *); 280static void dc_setfilt_admtek(struct dc_softc *); 281static void dc_setfilt_xircom(struct dc_softc *); 282 283static void dc_setfilt(struct dc_softc *); 284 285static void dc_reset(struct dc_softc *); 286static int dc_list_rx_init(struct dc_softc *); 287static int dc_list_tx_init(struct dc_softc *); 288 289static void dc_read_srom(struct dc_softc *, int); 290static void dc_parse_21143_srom(struct dc_softc *); 291static void dc_decode_leaf_sia(struct dc_softc *, struct dc_eblock_sia *); 292static void dc_decode_leaf_mii(struct dc_softc *, struct dc_eblock_mii *); 293static void dc_decode_leaf_sym(struct dc_softc *, struct dc_eblock_sym *); 294static void dc_apply_fixup(struct dc_softc *, int); 295 296#ifdef DC_USEIOSPACE 297#define DC_RES SYS_RES_IOPORT 298#define DC_RID DC_PCI_CFBIO 299#else 300#define DC_RES SYS_RES_MEMORY 301#define DC_RID DC_PCI_CFBMA 302#endif 303 304static device_method_t dc_methods[] = { 305 /* Device interface */ 306 DEVMETHOD(device_probe, dc_probe), 307 DEVMETHOD(device_attach, dc_attach), 308 DEVMETHOD(device_detach, dc_detach), 309 DEVMETHOD(device_suspend, dc_suspend), 310 DEVMETHOD(device_resume, dc_resume), 311 DEVMETHOD(device_shutdown, dc_shutdown), 312 313 /* bus interface */ 314 DEVMETHOD(bus_print_child, bus_generic_print_child), 315 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 316 317 /* MII interface */ 318 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 319 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 320 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 321 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 322 323 { 0, 0 } 324}; 325 326static driver_t dc_driver = { 327 "dc", 328 dc_methods, 329 sizeof(struct dc_softc) 330}; 331 332static devclass_t dc_devclass; 333 334DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 335DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 336 337#define DC_SETBIT(sc, reg, x) \ 338 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 339 340#define DC_CLRBIT(sc, reg, x) \ 341 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 342 343#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 344#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 345 346static void 347dc_delay(struct dc_softc *sc) 348{ 349 int idx; 350 351 for (idx = (300 / 33) + 1; idx > 0; idx--) 352 CSR_READ_4(sc, DC_BUSCTL); 353} 354 355static void 356dc_eeprom_width(struct dc_softc *sc) 357{ 358 int i; 359 360 /* Force EEPROM to idle state. */ 361 dc_eeprom_idle(sc); 362 363 /* Enter EEPROM access mode. */ 364 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 365 dc_delay(sc); 366 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 367 dc_delay(sc); 368 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 369 dc_delay(sc); 370 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 371 dc_delay(sc); 372 373 for (i = 3; i--;) { 374 if (6 & (1 << i)) 375 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 376 else 377 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 378 dc_delay(sc); 379 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 380 dc_delay(sc); 381 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 382 dc_delay(sc); 383 } 384 385 for (i = 1; i <= 12; i++) { 386 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 387 dc_delay(sc); 388 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 389 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 break; 392 } 393 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 394 dc_delay(sc); 395 } 396 397 /* Turn off EEPROM access mode. */ 398 dc_eeprom_idle(sc); 399 400 if (i < 4 || i > 12) 401 sc->dc_romwidth = 6; 402 else 403 sc->dc_romwidth = i; 404 405 /* Enter EEPROM access mode. */ 406 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 407 dc_delay(sc); 408 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 409 dc_delay(sc); 410 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 411 dc_delay(sc); 412 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 413 dc_delay(sc); 414 415 /* Turn off EEPROM access mode. */ 416 dc_eeprom_idle(sc); 417} 418 419static void 420dc_eeprom_idle(struct dc_softc *sc) 421{ 422 int i; 423 424 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 425 dc_delay(sc); 426 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 427 dc_delay(sc); 428 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 429 dc_delay(sc); 430 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 431 dc_delay(sc); 432 433 for (i = 0; i < 25; i++) { 434 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 435 dc_delay(sc); 436 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 437 dc_delay(sc); 438 } 439 440 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 441 dc_delay(sc); 442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 443 dc_delay(sc); 444 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 445} 446 447/* 448 * Send a read command and address to the EEPROM, check for ACK. 449 */ 450static void 451dc_eeprom_putbyte(struct dc_softc *sc, int addr) 452{ 453 int d, i; 454 455 d = DC_EECMD_READ >> 6; 456 for (i = 3; i--; ) { 457 if (d & (1 << i)) 458 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 459 else 460 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 461 dc_delay(sc); 462 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 463 dc_delay(sc); 464 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 465 dc_delay(sc); 466 } 467 468 /* 469 * Feed in each bit and strobe the clock. 470 */ 471 for (i = sc->dc_romwidth; i--;) { 472 if (addr & (1 << i)) { 473 SIO_SET(DC_SIO_EE_DATAIN); 474 } else { 475 SIO_CLR(DC_SIO_EE_DATAIN); 476 } 477 dc_delay(sc); 478 SIO_SET(DC_SIO_EE_CLK); 479 dc_delay(sc); 480 SIO_CLR(DC_SIO_EE_CLK); 481 dc_delay(sc); 482 } 483} 484 485/* 486 * Read a word of data stored in the EEPROM at address 'addr.' 487 * The PNIC 82c168/82c169 has its own non-standard way to read 488 * the EEPROM. 489 */ 490static void 491dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 492{ 493 int i; 494 u_int32_t r; 495 496 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 497 498 for (i = 0; i < DC_TIMEOUT; i++) { 499 DELAY(1); 500 r = CSR_READ_4(sc, DC_SIO); 501 if (!(r & DC_PN_SIOCTL_BUSY)) { 502 *dest = (u_int16_t)(r & 0xFFFF); 503 return; 504 } 505 } 506} 507 508/* 509 * Read a word of data stored in the EEPROM at address 'addr.' 510 * The Xircom X3201 has its own non-standard way to read 511 * the EEPROM, too. 512 */ 513static void 514dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 515{ 516 517 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 518 519 addr *= 2; 520 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 521 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 522 addr += 1; 523 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 524 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 525 526 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 527} 528 529/* 530 * Read a word of data stored in the EEPROM at address 'addr.' 531 */ 532static void 533dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 534{ 535 int i; 536 u_int16_t word = 0; 537 538 /* Force EEPROM to idle state. */ 539 dc_eeprom_idle(sc); 540 541 /* Enter EEPROM access mode. */ 542 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 543 dc_delay(sc); 544 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 545 dc_delay(sc); 546 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 547 dc_delay(sc); 548 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 549 dc_delay(sc); 550 551 /* 552 * Send address of word we want to read. 553 */ 554 dc_eeprom_putbyte(sc, addr); 555 556 /* 557 * Start reading bits from EEPROM. 558 */ 559 for (i = 0x8000; i; i >>= 1) { 560 SIO_SET(DC_SIO_EE_CLK); 561 dc_delay(sc); 562 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 563 word |= i; 564 dc_delay(sc); 565 SIO_CLR(DC_SIO_EE_CLK); 566 dc_delay(sc); 567 } 568 569 /* Turn off EEPROM access mode. */ 570 dc_eeprom_idle(sc); 571 572 *dest = word; 573} 574 575/* 576 * Read a sequence of words from the EEPROM. 577 */ 578static void 579dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 580{ 581 int i; 582 u_int16_t word = 0, *ptr; 583 584 for (i = 0; i < cnt; i++) { 585 if (DC_IS_PNIC(sc)) 586 dc_eeprom_getword_pnic(sc, off + i, &word); 587 else if (DC_IS_XIRCOM(sc)) 588 dc_eeprom_getword_xircom(sc, off + i, &word); 589 else 590 dc_eeprom_getword(sc, off + i, &word); 591 ptr = (u_int16_t *)(dest + (i * 2)); 592 if (be) 593 *ptr = be16toh(word); 594 else 595 *ptr = le16toh(word); 596 } 597} 598 599/* 600 * The following two routines are taken from the Macronix 98713 601 * Application Notes pp.19-21. 602 */ 603/* 604 * Write a bit to the MII bus. 605 */ 606static void 607dc_mii_writebit(struct dc_softc *sc, int bit) 608{ 609 uint32_t reg; 610 611 reg = DC_SIO_ROMCTL_WRITE | (bit != 0 ? DC_SIO_MII_DATAOUT : 0); 612 CSR_WRITE_4(sc, DC_SIO, reg); 613 CSR_BARRIER_4(sc, DC_SIO, 614 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 615 DELAY(1); 616 617 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); 618 CSR_BARRIER_4(sc, DC_SIO, 619 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 620 DELAY(1); 621 CSR_WRITE_4(sc, DC_SIO, reg); 622 CSR_BARRIER_4(sc, DC_SIO, 623 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 624 DELAY(1); 625} 626 627/* 628 * Read a bit from the MII bus. 629 */ 630static int 631dc_mii_readbit(struct dc_softc *sc) 632{ 633 uint32_t reg; 634 635 reg = DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR; 636 CSR_WRITE_4(sc, DC_SIO, reg); 637 CSR_BARRIER_4(sc, DC_SIO, 638 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 639 DELAY(1); 640 (void)CSR_READ_4(sc, DC_SIO); 641 CSR_WRITE_4(sc, DC_SIO, reg | DC_SIO_MII_CLK); 642 CSR_BARRIER_4(sc, DC_SIO, 643 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 644 DELAY(1); 645 CSR_WRITE_4(sc, DC_SIO, reg); 646 CSR_BARRIER_4(sc, DC_SIO, 647 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 648 DELAY(1); 649 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 650 return (1); 651 652 return (0); 653} 654 655/* 656 * Sync the PHYs by setting data bit and strobing the clock 32 times. 657 */ 658static void 659dc_mii_sync(struct dc_softc *sc) 660{ 661 int i; 662 663 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 664 CSR_BARRIER_4(sc, DC_SIO, 665 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 666 DELAY(1); 667 668 for (i = 0; i < 32; i++) 669 dc_mii_writebit(sc, 1); 670} 671 672/* 673 * Clock a series of bits through the MII. 674 */ 675static void 676dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 677{ 678 int i; 679 680 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 681 dc_mii_writebit(sc, bits & i); 682} 683 684/* 685 * Read an PHY register through the MII. 686 */ 687static int 688dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 689{ 690 int i; 691 692 /* 693 * Set up frame for RX. 694 */ 695 frame->mii_stdelim = DC_MII_STARTDELIM; 696 frame->mii_opcode = DC_MII_READOP; 697 698 /* 699 * Sync the PHYs. 700 */ 701 dc_mii_sync(sc); 702 703 /* 704 * Send command/address info. 705 */ 706 dc_mii_send(sc, frame->mii_stdelim, 2); 707 dc_mii_send(sc, frame->mii_opcode, 2); 708 dc_mii_send(sc, frame->mii_phyaddr, 5); 709 dc_mii_send(sc, frame->mii_regaddr, 5); 710 711 /* 712 * Now try reading data bits. If the turnaround failed, we still 713 * need to clock through 16 cycles to keep the PHY(s) in sync. 714 */ 715 frame->mii_turnaround = dc_mii_readbit(sc); 716 if (frame->mii_turnaround != 0) { 717 for (i = 0; i < 16; i++) 718 dc_mii_readbit(sc); 719 goto fail; 720 } 721 for (i = 0x8000; i; i >>= 1) { 722 if (dc_mii_readbit(sc)) 723 frame->mii_data |= i; 724 } 725 726fail: 727 728 /* Clock the idle bits. */ 729 dc_mii_writebit(sc, 0); 730 dc_mii_writebit(sc, 0); 731 732 if (frame->mii_turnaround != 0) 733 return (1); 734 return (0); 735} 736 737/* 738 * Write to a PHY register through the MII. 739 */ 740static int 741dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 742{ 743 744 /* 745 * Set up frame for TX. 746 */ 747 frame->mii_stdelim = DC_MII_STARTDELIM; 748 frame->mii_opcode = DC_MII_WRITEOP; 749 frame->mii_turnaround = DC_MII_TURNAROUND; 750 751 /* 752 * Sync the PHYs. 753 */ 754 dc_mii_sync(sc); 755 756 dc_mii_send(sc, frame->mii_stdelim, 2); 757 dc_mii_send(sc, frame->mii_opcode, 2); 758 dc_mii_send(sc, frame->mii_phyaddr, 5); 759 dc_mii_send(sc, frame->mii_regaddr, 5); 760 dc_mii_send(sc, frame->mii_turnaround, 2); 761 dc_mii_send(sc, frame->mii_data, 16); 762 763 /* Clock the idle bits. */ 764 dc_mii_writebit(sc, 0); 765 dc_mii_writebit(sc, 0); 766 767 return (0); 768} 769 770static int 771dc_miibus_readreg(device_t dev, int phy, int reg) 772{ 773 struct dc_mii_frame frame; 774 struct dc_softc *sc; 775 int i, rval, phy_reg = 0; 776 777 sc = device_get_softc(dev); 778 bzero(&frame, sizeof(frame)); 779 780 /* 781 * Note: both the AL981 and AN985 have internal PHYs, 782 * however the AL981 provides direct access to the PHY 783 * registers while the AN985 uses a serial MII interface. 784 * The AN985's MII interface is also buggy in that you 785 * can read from any MII address (0 to 31), but only address 1 786 * behaves normally. To deal with both cases, we pretend 787 * that the PHY is at MII address 1. 788 */ 789 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 790 return (0); 791 792 /* 793 * Note: the ukphy probes of the RS7112 report a PHY at 794 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 795 * so we only respond to correct one. 796 */ 797 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 798 return (0); 799 800 if (sc->dc_pmode != DC_PMODE_MII) { 801 if (phy == (MII_NPHY - 1)) { 802 switch (reg) { 803 case MII_BMSR: 804 /* 805 * Fake something to make the probe 806 * code think there's a PHY here. 807 */ 808 return (BMSR_MEDIAMASK); 809 break; 810 case MII_PHYIDR1: 811 if (DC_IS_PNIC(sc)) 812 return (DC_VENDORID_LO); 813 return (DC_VENDORID_DEC); 814 break; 815 case MII_PHYIDR2: 816 if (DC_IS_PNIC(sc)) 817 return (DC_DEVICEID_82C168); 818 return (DC_DEVICEID_21143); 819 break; 820 default: 821 return (0); 822 break; 823 } 824 } else 825 return (0); 826 } 827 828 if (DC_IS_PNIC(sc)) { 829 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 830 (phy << 23) | (reg << 18)); 831 for (i = 0; i < DC_TIMEOUT; i++) { 832 DELAY(1); 833 rval = CSR_READ_4(sc, DC_PN_MII); 834 if (!(rval & DC_PN_MII_BUSY)) { 835 rval &= 0xFFFF; 836 return (rval == 0xFFFF ? 0 : rval); 837 } 838 } 839 return (0); 840 } 841 842 if (DC_IS_COMET(sc)) { 843 switch (reg) { 844 case MII_BMCR: 845 phy_reg = DC_AL_BMCR; 846 break; 847 case MII_BMSR: 848 phy_reg = DC_AL_BMSR; 849 break; 850 case MII_PHYIDR1: 851 phy_reg = DC_AL_VENID; 852 break; 853 case MII_PHYIDR2: 854 phy_reg = DC_AL_DEVID; 855 break; 856 case MII_ANAR: 857 phy_reg = DC_AL_ANAR; 858 break; 859 case MII_ANLPAR: 860 phy_reg = DC_AL_LPAR; 861 break; 862 case MII_ANER: 863 phy_reg = DC_AL_ANER; 864 break; 865 default: 866 device_printf(dev, "phy_read: bad phy register %x\n", 867 reg); 868 return (0); 869 break; 870 } 871 872 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 873 874 if (rval == 0xFFFF) 875 return (0); 876 return (rval); 877 } 878 879 frame.mii_phyaddr = phy; 880 frame.mii_regaddr = reg; 881 if (sc->dc_type == DC_TYPE_98713) { 882 phy_reg = CSR_READ_4(sc, DC_NETCFG); 883 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 884 } 885 dc_mii_readreg(sc, &frame); 886 if (sc->dc_type == DC_TYPE_98713) 887 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 888 889 return (frame.mii_data); 890} 891 892static int 893dc_miibus_writereg(device_t dev, int phy, int reg, int data) 894{ 895 struct dc_softc *sc; 896 struct dc_mii_frame frame; 897 int i, phy_reg = 0; 898 899 sc = device_get_softc(dev); 900 bzero(&frame, sizeof(frame)); 901 902 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 903 return (0); 904 905 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 906 return (0); 907 908 if (DC_IS_PNIC(sc)) { 909 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 910 (phy << 23) | (reg << 10) | data); 911 for (i = 0; i < DC_TIMEOUT; i++) { 912 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 913 break; 914 } 915 return (0); 916 } 917 918 if (DC_IS_COMET(sc)) { 919 switch (reg) { 920 case MII_BMCR: 921 phy_reg = DC_AL_BMCR; 922 break; 923 case MII_BMSR: 924 phy_reg = DC_AL_BMSR; 925 break; 926 case MII_PHYIDR1: 927 phy_reg = DC_AL_VENID; 928 break; 929 case MII_PHYIDR2: 930 phy_reg = DC_AL_DEVID; 931 break; 932 case MII_ANAR: 933 phy_reg = DC_AL_ANAR; 934 break; 935 case MII_ANLPAR: 936 phy_reg = DC_AL_LPAR; 937 break; 938 case MII_ANER: 939 phy_reg = DC_AL_ANER; 940 break; 941 default: 942 device_printf(dev, "phy_write: bad phy register %x\n", 943 reg); 944 return (0); 945 break; 946 } 947 948 CSR_WRITE_4(sc, phy_reg, data); 949 return (0); 950 } 951 952 frame.mii_phyaddr = phy; 953 frame.mii_regaddr = reg; 954 frame.mii_data = data; 955 956 if (sc->dc_type == DC_TYPE_98713) { 957 phy_reg = CSR_READ_4(sc, DC_NETCFG); 958 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 959 } 960 dc_mii_writereg(sc, &frame); 961 if (sc->dc_type == DC_TYPE_98713) 962 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 963 964 return (0); 965} 966 967static void 968dc_miibus_statchg(device_t dev) 969{ 970 struct dc_softc *sc; 971 struct mii_data *mii; 972 struct ifmedia *ifm; 973 974 sc = device_get_softc(dev); 975 if (DC_IS_ADMTEK(sc)) 976 return; 977 978 mii = device_get_softc(sc->dc_miibus); 979 ifm = &mii->mii_media; 980 if (DC_IS_DAVICOM(sc) && 981 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 982 dc_setcfg(sc, ifm->ifm_media); 983 sc->dc_if_media = ifm->ifm_media; 984 } else { 985 dc_setcfg(sc, mii->mii_media_active); 986 sc->dc_if_media = mii->mii_media_active; 987 } 988} 989 990/* 991 * Special support for DM9102A cards with HomePNA PHYs. Note: 992 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 993 * to be impossible to talk to the management interface of the DM9801 994 * PHY (its MDIO pin is not connected to anything). Consequently, 995 * the driver has to just 'know' about the additional mode and deal 996 * with it itself. *sigh* 997 */ 998static void 999dc_miibus_mediainit(device_t dev) 1000{ 1001 struct dc_softc *sc; 1002 struct mii_data *mii; 1003 struct ifmedia *ifm; 1004 int rev; 1005 1006 rev = pci_get_revid(dev); 1007 1008 sc = device_get_softc(dev); 1009 mii = device_get_softc(sc->dc_miibus); 1010 ifm = &mii->mii_media; 1011 1012 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1013 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1014} 1015 1016#define DC_BITS_512 9 1017#define DC_BITS_128 7 1018#define DC_BITS_64 6 1019 1020static uint32_t 1021dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1022{ 1023 uint32_t crc; 1024 1025 /* Compute CRC for the address value. */ 1026 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1027 1028 /* 1029 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1030 * chips is only 128 bits wide. 1031 */ 1032 if (sc->dc_flags & DC_128BIT_HASH) 1033 return (crc & ((1 << DC_BITS_128) - 1)); 1034 1035 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1036 if (sc->dc_flags & DC_64BIT_HASH) 1037 return (crc & ((1 << DC_BITS_64) - 1)); 1038 1039 /* Xircom's hash filtering table is different (read: weird) */ 1040 /* Xircom uses the LEAST significant bits */ 1041 if (DC_IS_XIRCOM(sc)) { 1042 if ((crc & 0x180) == 0x180) 1043 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1044 else 1045 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1046 (12 << 4)); 1047 } 1048 1049 return (crc & ((1 << DC_BITS_512) - 1)); 1050} 1051 1052/* 1053 * Calculate CRC of a multicast group address, return the lower 6 bits. 1054 */ 1055static uint32_t 1056dc_mchash_be(const uint8_t *addr) 1057{ 1058 uint32_t crc; 1059 1060 /* Compute CRC for the address value. */ 1061 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1062 1063 /* Return the filter bit position. */ 1064 return ((crc >> 26) & 0x0000003F); 1065} 1066 1067/* 1068 * 21143-style RX filter setup routine. Filter programming is done by 1069 * downloading a special setup frame into the TX engine. 21143, Macronix, 1070 * PNIC, PNIC II and Davicom chips are programmed this way. 1071 * 1072 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1073 * address (our node address) and a 512-bit hash filter for multicast 1074 * frames. We also sneak the broadcast address into the hash filter since 1075 * we need that too. 1076 */ 1077static void 1078dc_setfilt_21143(struct dc_softc *sc) 1079{ 1080 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1081 struct dc_desc *sframe; 1082 u_int32_t h, *sp; 1083 struct ifmultiaddr *ifma; 1084 struct ifnet *ifp; 1085 int i; 1086 1087 ifp = sc->dc_ifp; 1088 1089 i = sc->dc_cdata.dc_tx_prod; 1090 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1091 sc->dc_cdata.dc_tx_cnt++; 1092 sframe = &sc->dc_ldata->dc_tx_list[i]; 1093 sp = sc->dc_cdata.dc_sbuf; 1094 bzero(sp, DC_SFRAME_LEN); 1095 1096 sframe->dc_data = htole32(sc->dc_saddr); 1097 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1098 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1099 1100 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1101 1102 /* If we want promiscuous mode, set the allframes bit. */ 1103 if (ifp->if_flags & IFF_PROMISC) 1104 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1105 else 1106 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1107 1108 if (ifp->if_flags & IFF_ALLMULTI) 1109 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1110 else 1111 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1112 1113 IF_ADDR_LOCK(ifp); 1114 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1115 if (ifma->ifma_addr->sa_family != AF_LINK) 1116 continue; 1117 h = dc_mchash_le(sc, 1118 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1119 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1120 } 1121 IF_ADDR_UNLOCK(ifp); 1122 1123 if (ifp->if_flags & IFF_BROADCAST) { 1124 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1125 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1126 } 1127 1128 /* Set our MAC address. */ 1129 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1130 sp[39] = DC_SP_MAC(eaddr[0]); 1131 sp[40] = DC_SP_MAC(eaddr[1]); 1132 sp[41] = DC_SP_MAC(eaddr[2]); 1133 1134 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1135 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1136 1137 /* 1138 * The PNIC takes an exceedingly long time to process its 1139 * setup frame; wait 10ms after posting the setup frame 1140 * before proceeding, just so it has time to swallow its 1141 * medicine. 1142 */ 1143 DELAY(10000); 1144 1145 sc->dc_wdog_timer = 5; 1146} 1147 1148static void 1149dc_setfilt_admtek(struct dc_softc *sc) 1150{ 1151 uint8_t eaddr[ETHER_ADDR_LEN]; 1152 struct ifnet *ifp; 1153 struct ifmultiaddr *ifma; 1154 int h = 0; 1155 u_int32_t hashes[2] = { 0, 0 }; 1156 1157 ifp = sc->dc_ifp; 1158 1159 /* Init our MAC address. */ 1160 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1161 CSR_WRITE_4(sc, DC_AL_PAR0, eaddr[3] << 24 | eaddr[2] << 16 | 1162 eaddr[1] << 8 | eaddr[0]); 1163 CSR_WRITE_4(sc, DC_AL_PAR1, eaddr[5] << 8 | eaddr[4]); 1164 1165 /* If we want promiscuous mode, set the allframes bit. */ 1166 if (ifp->if_flags & IFF_PROMISC) 1167 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1168 else 1169 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1170 1171 if (ifp->if_flags & IFF_ALLMULTI) 1172 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1173 else 1174 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1175 1176 /* First, zot all the existing hash bits. */ 1177 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1178 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1179 1180 /* 1181 * If we're already in promisc or allmulti mode, we 1182 * don't have to bother programming the multicast filter. 1183 */ 1184 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1185 return; 1186 1187 /* Now program new ones. */ 1188 IF_ADDR_LOCK(ifp); 1189 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1190 if (ifma->ifma_addr->sa_family != AF_LINK) 1191 continue; 1192 if (DC_IS_CENTAUR(sc)) 1193 h = dc_mchash_le(sc, 1194 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1195 else 1196 h = dc_mchash_be( 1197 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1198 if (h < 32) 1199 hashes[0] |= (1 << h); 1200 else 1201 hashes[1] |= (1 << (h - 32)); 1202 } 1203 IF_ADDR_UNLOCK(ifp); 1204 1205 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1206 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1207} 1208 1209static void 1210dc_setfilt_asix(struct dc_softc *sc) 1211{ 1212 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1213 struct ifnet *ifp; 1214 struct ifmultiaddr *ifma; 1215 int h = 0; 1216 u_int32_t hashes[2] = { 0, 0 }; 1217 1218 ifp = sc->dc_ifp; 1219 1220 /* Init our MAC address. */ 1221 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1222 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1223 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[0]); 1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, eaddr[1]); 1226 1227 /* If we want promiscuous mode, set the allframes bit. */ 1228 if (ifp->if_flags & IFF_PROMISC) 1229 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1230 else 1231 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1232 1233 if (ifp->if_flags & IFF_ALLMULTI) 1234 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1235 else 1236 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1237 1238 /* 1239 * The ASIX chip has a special bit to enable reception 1240 * of broadcast frames. 1241 */ 1242 if (ifp->if_flags & IFF_BROADCAST) 1243 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1244 else 1245 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1246 1247 /* first, zot all the existing hash bits */ 1248 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1249 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1250 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1251 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1252 1253 /* 1254 * If we're already in promisc or allmulti mode, we 1255 * don't have to bother programming the multicast filter. 1256 */ 1257 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1258 return; 1259 1260 /* now program new ones */ 1261 IF_ADDR_LOCK(ifp); 1262 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1263 if (ifma->ifma_addr->sa_family != AF_LINK) 1264 continue; 1265 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1266 if (h < 32) 1267 hashes[0] |= (1 << h); 1268 else 1269 hashes[1] |= (1 << (h - 32)); 1270 } 1271 IF_ADDR_UNLOCK(ifp); 1272 1273 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1274 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1275 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1276 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1277} 1278 1279static void 1280dc_setfilt_xircom(struct dc_softc *sc) 1281{ 1282 uint16_t eaddr[(ETHER_ADDR_LEN+1)/2]; 1283 struct ifnet *ifp; 1284 struct ifmultiaddr *ifma; 1285 struct dc_desc *sframe; 1286 u_int32_t h, *sp; 1287 int i; 1288 1289 ifp = sc->dc_ifp; 1290 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1291 1292 i = sc->dc_cdata.dc_tx_prod; 1293 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1294 sc->dc_cdata.dc_tx_cnt++; 1295 sframe = &sc->dc_ldata->dc_tx_list[i]; 1296 sp = sc->dc_cdata.dc_sbuf; 1297 bzero(sp, DC_SFRAME_LEN); 1298 1299 sframe->dc_data = htole32(sc->dc_saddr); 1300 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1301 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1302 1303 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1304 1305 /* If we want promiscuous mode, set the allframes bit. */ 1306 if (ifp->if_flags & IFF_PROMISC) 1307 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1308 else 1309 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1310 1311 if (ifp->if_flags & IFF_ALLMULTI) 1312 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1313 else 1314 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1315 1316 IF_ADDR_LOCK(ifp); 1317 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1318 if (ifma->ifma_addr->sa_family != AF_LINK) 1319 continue; 1320 h = dc_mchash_le(sc, 1321 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1322 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1323 } 1324 IF_ADDR_UNLOCK(ifp); 1325 1326 if (ifp->if_flags & IFF_BROADCAST) { 1327 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1328 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1329 } 1330 1331 /* Set our MAC address. */ 1332 bcopy(IF_LLADDR(sc->dc_ifp), eaddr, ETHER_ADDR_LEN); 1333 sp[0] = DC_SP_MAC(eaddr[0]); 1334 sp[1] = DC_SP_MAC(eaddr[1]); 1335 sp[2] = DC_SP_MAC(eaddr[2]); 1336 1337 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1338 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1339 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1340 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1341 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1342 1343 /* 1344 * Wait some time... 1345 */ 1346 DELAY(1000); 1347 1348 sc->dc_wdog_timer = 5; 1349} 1350 1351static void 1352dc_setfilt(struct dc_softc *sc) 1353{ 1354 1355 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1356 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1357 dc_setfilt_21143(sc); 1358 1359 if (DC_IS_ASIX(sc)) 1360 dc_setfilt_asix(sc); 1361 1362 if (DC_IS_ADMTEK(sc)) 1363 dc_setfilt_admtek(sc); 1364 1365 if (DC_IS_XIRCOM(sc)) 1366 dc_setfilt_xircom(sc); 1367} 1368 1369/* 1370 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1371 * the netconfig register, we first have to put the transmit and/or 1372 * receive logic in the idle state. 1373 */ 1374static void 1375dc_setcfg(struct dc_softc *sc, int media) 1376{ 1377 int i, restart = 0, watchdogreg; 1378 u_int32_t isr; 1379 1380 if (IFM_SUBTYPE(media) == IFM_NONE) 1381 return; 1382 1383 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1384 restart = 1; 1385 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1386 1387 for (i = 0; i < DC_TIMEOUT; i++) { 1388 isr = CSR_READ_4(sc, DC_ISR); 1389 if (isr & DC_ISR_TX_IDLE && 1390 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1391 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1392 break; 1393 DELAY(10); 1394 } 1395 1396 if (i == DC_TIMEOUT) { 1397 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc)) 1398 device_printf(sc->dc_dev, 1399 "%s: failed to force tx to idle state\n", 1400 __func__); 1401 if (!((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1402 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 1403 !DC_HAS_BROKEN_RXSTATE(sc)) 1404 device_printf(sc->dc_dev, 1405 "%s: failed to force rx to idle state\n", 1406 __func__); 1407 } 1408 } 1409 1410 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1411 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1412 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1413 if (sc->dc_pmode == DC_PMODE_MII) { 1414 if (DC_IS_INTEL(sc)) { 1415 /* There's a write enable bit here that reads as 1. */ 1416 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1417 watchdogreg &= ~DC_WDOG_CTLWREN; 1418 watchdogreg |= DC_WDOG_JABBERDIS; 1419 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1420 } else { 1421 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1422 } 1423 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1424 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1425 if (sc->dc_type == DC_TYPE_98713) 1426 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1427 DC_NETCFG_SCRAMBLER)); 1428 if (!DC_IS_DAVICOM(sc)) 1429 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1430 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1431 if (DC_IS_INTEL(sc)) 1432 dc_apply_fixup(sc, IFM_AUTO); 1433 } else { 1434 if (DC_IS_PNIC(sc)) { 1435 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1436 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1437 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1438 } 1439 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1440 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1441 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1442 if (DC_IS_INTEL(sc)) 1443 dc_apply_fixup(sc, 1444 (media & IFM_GMASK) == IFM_FDX ? 1445 IFM_100_TX | IFM_FDX : IFM_100_TX); 1446 } 1447 } 1448 1449 if (IFM_SUBTYPE(media) == IFM_10_T) { 1450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1451 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1452 if (sc->dc_pmode == DC_PMODE_MII) { 1453 /* There's a write enable bit here that reads as 1. */ 1454 if (DC_IS_INTEL(sc)) { 1455 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1456 watchdogreg &= ~DC_WDOG_CTLWREN; 1457 watchdogreg |= DC_WDOG_JABBERDIS; 1458 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1459 } else { 1460 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1461 } 1462 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1463 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1464 if (sc->dc_type == DC_TYPE_98713) 1465 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1466 if (!DC_IS_DAVICOM(sc)) 1467 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1468 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1469 if (DC_IS_INTEL(sc)) 1470 dc_apply_fixup(sc, IFM_AUTO); 1471 } else { 1472 if (DC_IS_PNIC(sc)) { 1473 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1474 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1475 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1476 } 1477 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1478 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1479 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1480 if (DC_IS_INTEL(sc)) { 1481 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1482 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1483 if ((media & IFM_GMASK) == IFM_FDX) 1484 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1485 else 1486 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1487 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1488 DC_CLRBIT(sc, DC_10BTCTRL, 1489 DC_TCTL_AUTONEGENBL); 1490 dc_apply_fixup(sc, 1491 (media & IFM_GMASK) == IFM_FDX ? 1492 IFM_10_T | IFM_FDX : IFM_10_T); 1493 DELAY(20000); 1494 } 1495 } 1496 } 1497 1498 /* 1499 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1500 * PHY and we want HomePNA mode, set the portsel bit to turn 1501 * on the external MII port. 1502 */ 1503 if (DC_IS_DAVICOM(sc)) { 1504 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1505 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1506 sc->dc_link = 1; 1507 } else { 1508 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1509 } 1510 } 1511 1512 if ((media & IFM_GMASK) == IFM_FDX) { 1513 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1514 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1515 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1516 } else { 1517 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1518 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1519 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1520 } 1521 1522 if (restart) 1523 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1524} 1525 1526static void 1527dc_reset(struct dc_softc *sc) 1528{ 1529 int i; 1530 1531 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1532 1533 for (i = 0; i < DC_TIMEOUT; i++) { 1534 DELAY(10); 1535 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1536 break; 1537 } 1538 1539 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1540 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1541 DELAY(10000); 1542 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1543 i = 0; 1544 } 1545 1546 if (i == DC_TIMEOUT) 1547 device_printf(sc->dc_dev, "reset never completed!\n"); 1548 1549 /* Wait a little while for the chip to get its brains in order. */ 1550 DELAY(1000); 1551 1552 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1553 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1554 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1555 1556 /* 1557 * Bring the SIA out of reset. In some cases, it looks 1558 * like failing to unreset the SIA soon enough gets it 1559 * into a state where it will never come out of reset 1560 * until we reset the whole chip again. 1561 */ 1562 if (DC_IS_INTEL(sc)) { 1563 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1564 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1565 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1566 } 1567} 1568 1569static const struct dc_type * 1570dc_devtype(device_t dev) 1571{ 1572 const struct dc_type *t; 1573 u_int32_t devid; 1574 u_int8_t rev; 1575 1576 t = dc_devs; 1577 devid = pci_get_devid(dev); 1578 rev = pci_get_revid(dev); 1579 1580 while (t->dc_name != NULL) { 1581 if (devid == t->dc_devid && rev >= t->dc_minrev) 1582 return (t); 1583 t++; 1584 } 1585 1586 return (NULL); 1587} 1588 1589/* 1590 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1591 * IDs against our list and return a device name if we find a match. 1592 * We do a little bit of extra work to identify the exact type of 1593 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1594 * but different revision IDs. The same is true for 98715/98715A 1595 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1596 * cases, the exact chip revision affects driver behavior. 1597 */ 1598static int 1599dc_probe(device_t dev) 1600{ 1601 const struct dc_type *t; 1602 1603 t = dc_devtype(dev); 1604 1605 if (t != NULL) { 1606 device_set_desc(dev, t->dc_name); 1607 return (BUS_PROBE_DEFAULT); 1608 } 1609 1610 return (ENXIO); 1611} 1612 1613static void 1614dc_apply_fixup(struct dc_softc *sc, int media) 1615{ 1616 struct dc_mediainfo *m; 1617 u_int8_t *p; 1618 int i; 1619 u_int32_t reg; 1620 1621 m = sc->dc_mi; 1622 1623 while (m != NULL) { 1624 if (m->dc_media == media) 1625 break; 1626 m = m->dc_next; 1627 } 1628 1629 if (m == NULL) 1630 return; 1631 1632 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1633 reg = (p[0] | (p[1] << 8)) << 16; 1634 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1635 } 1636 1637 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1638 reg = (p[0] | (p[1] << 8)) << 16; 1639 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1640 } 1641} 1642 1643static void 1644dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1645{ 1646 struct dc_mediainfo *m; 1647 1648 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1649 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1650 case DC_SIA_CODE_10BT: 1651 m->dc_media = IFM_10_T; 1652 break; 1653 case DC_SIA_CODE_10BT_FDX: 1654 m->dc_media = IFM_10_T | IFM_FDX; 1655 break; 1656 case DC_SIA_CODE_10B2: 1657 m->dc_media = IFM_10_2; 1658 break; 1659 case DC_SIA_CODE_10B5: 1660 m->dc_media = IFM_10_5; 1661 break; 1662 default: 1663 break; 1664 } 1665 1666 /* 1667 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1668 * Things apparently already work for cards that do 1669 * supply Media Specific Data. 1670 */ 1671 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1672 m->dc_gp_len = 2; 1673 m->dc_gp_ptr = 1674 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1675 } else { 1676 m->dc_gp_len = 2; 1677 m->dc_gp_ptr = 1678 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1679 } 1680 1681 m->dc_next = sc->dc_mi; 1682 sc->dc_mi = m; 1683 1684 sc->dc_pmode = DC_PMODE_SIA; 1685} 1686 1687static void 1688dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1689{ 1690 struct dc_mediainfo *m; 1691 1692 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1693 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1694 m->dc_media = IFM_100_TX; 1695 1696 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1697 m->dc_media = IFM_100_TX | IFM_FDX; 1698 1699 m->dc_gp_len = 2; 1700 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1701 1702 m->dc_next = sc->dc_mi; 1703 sc->dc_mi = m; 1704 1705 sc->dc_pmode = DC_PMODE_SYM; 1706} 1707 1708static void 1709dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1710{ 1711 struct dc_mediainfo *m; 1712 u_int8_t *p; 1713 1714 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1715 /* We abuse IFM_AUTO to represent MII. */ 1716 m->dc_media = IFM_AUTO; 1717 m->dc_gp_len = l->dc_gpr_len; 1718 1719 p = (u_int8_t *)l; 1720 p += sizeof(struct dc_eblock_mii); 1721 m->dc_gp_ptr = p; 1722 p += 2 * l->dc_gpr_len; 1723 m->dc_reset_len = *p; 1724 p++; 1725 m->dc_reset_ptr = p; 1726 1727 m->dc_next = sc->dc_mi; 1728 sc->dc_mi = m; 1729} 1730 1731static void 1732dc_read_srom(struct dc_softc *sc, int bits) 1733{ 1734 int size; 1735 1736 size = 2 << bits; 1737 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1738 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1739} 1740 1741static void 1742dc_parse_21143_srom(struct dc_softc *sc) 1743{ 1744 struct dc_leaf_hdr *lhdr; 1745 struct dc_eblock_hdr *hdr; 1746 int have_mii, i, loff; 1747 char *ptr; 1748 1749 have_mii = 0; 1750 loff = sc->dc_srom[27]; 1751 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1752 1753 ptr = (char *)lhdr; 1754 ptr += sizeof(struct dc_leaf_hdr) - 1; 1755 /* 1756 * Look if we got a MII media block. 1757 */ 1758 for (i = 0; i < lhdr->dc_mcnt; i++) { 1759 hdr = (struct dc_eblock_hdr *)ptr; 1760 if (hdr->dc_type == DC_EBLOCK_MII) 1761 have_mii++; 1762 1763 ptr += (hdr->dc_len & 0x7F); 1764 ptr++; 1765 } 1766 1767 /* 1768 * Do the same thing again. Only use SIA and SYM media 1769 * blocks if no MII media block is available. 1770 */ 1771 ptr = (char *)lhdr; 1772 ptr += sizeof(struct dc_leaf_hdr) - 1; 1773 for (i = 0; i < lhdr->dc_mcnt; i++) { 1774 hdr = (struct dc_eblock_hdr *)ptr; 1775 switch (hdr->dc_type) { 1776 case DC_EBLOCK_MII: 1777 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1778 break; 1779 case DC_EBLOCK_SIA: 1780 if (! have_mii) 1781 dc_decode_leaf_sia(sc, 1782 (struct dc_eblock_sia *)hdr); 1783 break; 1784 case DC_EBLOCK_SYM: 1785 if (! have_mii) 1786 dc_decode_leaf_sym(sc, 1787 (struct dc_eblock_sym *)hdr); 1788 break; 1789 default: 1790 /* Don't care. Yet. */ 1791 break; 1792 } 1793 ptr += (hdr->dc_len & 0x7F); 1794 ptr++; 1795 } 1796} 1797 1798static void 1799dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1800{ 1801 u_int32_t *paddr; 1802 1803 KASSERT(nseg == 1, 1804 ("%s: wrong number of segments (%d)", __func__, nseg)); 1805 paddr = arg; 1806 *paddr = segs->ds_addr; 1807} 1808 1809/* 1810 * Attach the interface. Allocate softc structures, do ifmedia 1811 * setup and ethernet/BPF attach. 1812 */ 1813static int 1814dc_attach(device_t dev) 1815{ 1816 int tmp = 0; 1817 uint32_t eaddr[(ETHER_ADDR_LEN+3)/4]; 1818 u_int32_t command; 1819 struct dc_softc *sc; 1820 struct ifnet *ifp; 1821 u_int32_t reg, revision; 1822 int error = 0, rid, mac_offset; 1823 int i; 1824 u_int8_t *mac; 1825 1826 sc = device_get_softc(dev); 1827 sc->dc_dev = dev; 1828 1829 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1830 MTX_DEF); 1831 1832 /* 1833 * Map control/status registers. 1834 */ 1835 pci_enable_busmaster(dev); 1836 1837 rid = DC_RID; 1838 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1839 1840 if (sc->dc_res == NULL) { 1841 device_printf(dev, "couldn't map ports/memory\n"); 1842 error = ENXIO; 1843 goto fail; 1844 } 1845 1846 sc->dc_btag = rman_get_bustag(sc->dc_res); 1847 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1848 1849 /* Allocate interrupt. */ 1850 rid = 0; 1851 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1852 RF_SHAREABLE | RF_ACTIVE); 1853 1854 if (sc->dc_irq == NULL) { 1855 device_printf(dev, "couldn't map interrupt\n"); 1856 error = ENXIO; 1857 goto fail; 1858 } 1859 1860 /* Need this info to decide on a chip type. */ 1861 sc->dc_info = dc_devtype(dev); 1862 revision = pci_get_revid(dev); 1863 1864 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1865 if (sc->dc_info->dc_devid != 1866 DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168) && 1867 sc->dc_info->dc_devid != 1868 DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201)) 1869 dc_eeprom_width(sc); 1870 1871 switch (sc->dc_info->dc_devid) { 1872 case DC_DEVID(DC_VENDORID_DEC, DC_DEVICEID_21143): 1873 sc->dc_type = DC_TYPE_21143; 1874 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1875 sc->dc_flags |= DC_REDUCED_MII_POLL; 1876 /* Save EEPROM contents so we can parse them later. */ 1877 dc_read_srom(sc, sc->dc_romwidth); 1878 break; 1879 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009): 1880 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100): 1881 case DC_DEVID(DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102): 1882 sc->dc_type = DC_TYPE_DM9102; 1883 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1884 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1885 sc->dc_flags |= DC_TX_ALIGN; 1886 sc->dc_pmode = DC_PMODE_MII; 1887 1888 /* Increase the latency timer value. */ 1889 pci_write_config(dev, PCIR_LATTIMER, 0x80, 1); 1890 break; 1891 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AL981): 1892 sc->dc_type = DC_TYPE_AL981; 1893 sc->dc_flags |= DC_TX_USE_TX_INTR; 1894 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1895 sc->dc_pmode = DC_PMODE_MII; 1896 dc_read_srom(sc, sc->dc_romwidth); 1897 break; 1898 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_AN985): 1899 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511): 1900 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513): 1901 case DC_DEVID(DC_VENDORID_DLINK, DC_DEVICEID_DRP32TXD): 1902 case DC_DEVID(DC_VENDORID_ADMTEK, DC_DEVICEID_FA511): 1903 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500): 1904 case DC_DEVID(DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX): 1905 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN2242): 1906 case DC_DEVID(DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX): 1907 case DC_DEVID(DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T): 1908 case DC_DEVID(DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB): 1909 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120): 1910 case DC_DEVID(DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130): 1911 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB08): 1912 case DC_DEVID(DC_VENDORID_LINKSYS, DC_DEVICEID_PCMPC200_AB09): 1913 sc->dc_type = DC_TYPE_AN985; 1914 sc->dc_flags |= DC_64BIT_HASH; 1915 sc->dc_flags |= DC_TX_USE_TX_INTR; 1916 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1917 sc->dc_pmode = DC_PMODE_MII; 1918 /* Don't read SROM for - auto-loaded on reset */ 1919 break; 1920 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98713): 1921 case DC_DEVID(DC_VENDORID_CP, DC_DEVICEID_98713_CP): 1922 if (revision < DC_REVISION_98713A) { 1923 sc->dc_type = DC_TYPE_98713; 1924 } 1925 if (revision >= DC_REVISION_98713A) { 1926 sc->dc_type = DC_TYPE_98713A; 1927 sc->dc_flags |= DC_21143_NWAY; 1928 } 1929 sc->dc_flags |= DC_REDUCED_MII_POLL; 1930 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1931 break; 1932 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_987x5): 1933 case DC_DEVID(DC_VENDORID_ACCTON, DC_DEVICEID_EN1217): 1934 /* 1935 * Macronix MX98715AEC-C/D/E parts have only a 1936 * 128-bit hash table. We need to deal with these 1937 * in the same manner as the PNIC II so that we 1938 * get the right number of bits out of the 1939 * CRC routine. 1940 */ 1941 if (revision >= DC_REVISION_98715AEC_C && 1942 revision < DC_REVISION_98725) 1943 sc->dc_flags |= DC_128BIT_HASH; 1944 sc->dc_type = DC_TYPE_987x5; 1945 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1946 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1947 break; 1948 case DC_DEVID(DC_VENDORID_MX, DC_DEVICEID_98727): 1949 sc->dc_type = DC_TYPE_987x5; 1950 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1951 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1952 break; 1953 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C115): 1954 sc->dc_type = DC_TYPE_PNICII; 1955 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1956 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1957 break; 1958 case DC_DEVID(DC_VENDORID_LO, DC_DEVICEID_82C168): 1959 sc->dc_type = DC_TYPE_PNIC; 1960 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1961 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1962 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1963 if (revision < DC_REVISION_82C169) 1964 sc->dc_pmode = DC_PMODE_SYM; 1965 break; 1966 case DC_DEVID(DC_VENDORID_ASIX, DC_DEVICEID_AX88140A): 1967 sc->dc_type = DC_TYPE_ASIX; 1968 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1969 sc->dc_flags |= DC_REDUCED_MII_POLL; 1970 sc->dc_pmode = DC_PMODE_MII; 1971 break; 1972 case DC_DEVID(DC_VENDORID_XIRCOM, DC_DEVICEID_X3201): 1973 sc->dc_type = DC_TYPE_XIRCOM; 1974 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1975 DC_TX_ALIGN; 1976 /* 1977 * We don't actually need to coalesce, but we're doing 1978 * it to obtain a double word aligned buffer. 1979 * The DC_TX_COALESCE flag is required. 1980 */ 1981 sc->dc_pmode = DC_PMODE_MII; 1982 break; 1983 case DC_DEVID(DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112): 1984 sc->dc_type = DC_TYPE_CONEXANT; 1985 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1986 sc->dc_flags |= DC_REDUCED_MII_POLL; 1987 sc->dc_pmode = DC_PMODE_MII; 1988 dc_read_srom(sc, sc->dc_romwidth); 1989 break; 1990 default: 1991 device_printf(dev, "unknown device: %x\n", 1992 sc->dc_info->dc_devid); 1993 break; 1994 } 1995 1996 /* Save the cache line size. */ 1997 if (DC_IS_DAVICOM(sc)) 1998 sc->dc_cachesize = 0; 1999 else 2000 sc->dc_cachesize = pci_get_cachelnsz(dev); 2001 2002 /* Reset the adapter. */ 2003 dc_reset(sc); 2004 2005 /* Take 21143 out of snooze mode */ 2006 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2007 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2008 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2009 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2010 } 2011 2012 /* 2013 * Try to learn something about the supported media. 2014 * We know that ASIX and ADMtek and Davicom devices 2015 * will *always* be using MII media, so that's a no-brainer. 2016 * The tricky ones are the Macronix/PNIC II and the 2017 * Intel 21143. 2018 */ 2019 if (DC_IS_INTEL(sc)) 2020 dc_parse_21143_srom(sc); 2021 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2022 if (sc->dc_type == DC_TYPE_98713) 2023 sc->dc_pmode = DC_PMODE_MII; 2024 else 2025 sc->dc_pmode = DC_PMODE_SYM; 2026 } else if (!sc->dc_pmode) 2027 sc->dc_pmode = DC_PMODE_MII; 2028 2029 /* 2030 * Get station address from the EEPROM. 2031 */ 2032 switch(sc->dc_type) { 2033 case DC_TYPE_98713: 2034 case DC_TYPE_98713A: 2035 case DC_TYPE_987x5: 2036 case DC_TYPE_PNICII: 2037 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2038 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2039 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2040 break; 2041 case DC_TYPE_PNIC: 2042 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2043 break; 2044 case DC_TYPE_DM9102: 2045 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2046#ifdef __sparc64__ 2047 /* 2048 * If this is an onboard dc(4) the station address read from 2049 * the EEPROM is all zero and we have to get it from the FCode. 2050 */ 2051 if (eaddr[0] == 0 && (eaddr[1] & ~0xffff) == 0) 2052 OF_getetheraddr(dev, (caddr_t)&eaddr); 2053#endif 2054 break; 2055 case DC_TYPE_21143: 2056 case DC_TYPE_ASIX: 2057 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2058 break; 2059 case DC_TYPE_AL981: 2060 case DC_TYPE_AN985: 2061 reg = CSR_READ_4(sc, DC_AL_PAR0); 2062 mac = (uint8_t *)&eaddr[0]; 2063 mac[0] = (reg >> 0) & 0xff; 2064 mac[1] = (reg >> 8) & 0xff; 2065 mac[2] = (reg >> 16) & 0xff; 2066 mac[3] = (reg >> 24) & 0xff; 2067 reg = CSR_READ_4(sc, DC_AL_PAR1); 2068 mac[4] = (reg >> 0) & 0xff; 2069 mac[5] = (reg >> 8) & 0xff; 2070 break; 2071 case DC_TYPE_CONEXANT: 2072 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2073 ETHER_ADDR_LEN); 2074 break; 2075 case DC_TYPE_XIRCOM: 2076 /* The MAC comes from the CIS. */ 2077 mac = pci_get_ether(dev); 2078 if (!mac) { 2079 device_printf(dev, "No station address in CIS!\n"); 2080 error = ENXIO; 2081 goto fail; 2082 } 2083 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2084 break; 2085 default: 2086 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2087 break; 2088 } 2089 2090 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2091 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2092 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2093 sizeof(struct dc_list_data), 1, sizeof(struct dc_list_data), 2094 0, NULL, NULL, &sc->dc_ltag); 2095 if (error) { 2096 device_printf(dev, "failed to allocate busdma tag\n"); 2097 error = ENXIO; 2098 goto fail; 2099 } 2100 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2101 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2102 if (error) { 2103 device_printf(dev, "failed to allocate DMA safe memory\n"); 2104 error = ENXIO; 2105 goto fail; 2106 } 2107 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2108 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2109 BUS_DMA_NOWAIT); 2110 if (error) { 2111 device_printf(dev, "cannot get address of the descriptors\n"); 2112 error = ENXIO; 2113 goto fail; 2114 } 2115 2116 /* 2117 * Allocate a busdma tag and DMA safe memory for the multicast 2118 * setup frame. 2119 */ 2120 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0, 2121 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2122 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 2123 0, NULL, NULL, &sc->dc_stag); 2124 if (error) { 2125 device_printf(dev, "failed to allocate busdma tag\n"); 2126 error = ENXIO; 2127 goto fail; 2128 } 2129 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2130 BUS_DMA_NOWAIT, &sc->dc_smap); 2131 if (error) { 2132 device_printf(dev, "failed to allocate DMA safe memory\n"); 2133 error = ENXIO; 2134 goto fail; 2135 } 2136 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2137 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2138 if (error) { 2139 device_printf(dev, "cannot get address of the descriptors\n"); 2140 error = ENXIO; 2141 goto fail; 2142 } 2143 2144 /* Allocate a busdma tag for mbufs. */ 2145 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 2146 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2147 MCLBYTES * DC_MAXFRAGS, DC_MAXFRAGS, MCLBYTES, 2148 0, NULL, NULL, &sc->dc_mtag); 2149 if (error) { 2150 device_printf(dev, "failed to allocate busdma tag\n"); 2151 error = ENXIO; 2152 goto fail; 2153 } 2154 2155 /* Create the TX/RX busdma maps. */ 2156 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2157 error = bus_dmamap_create(sc->dc_mtag, 0, 2158 &sc->dc_cdata.dc_tx_map[i]); 2159 if (error) { 2160 device_printf(dev, "failed to init TX ring\n"); 2161 error = ENXIO; 2162 goto fail; 2163 } 2164 } 2165 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2166 error = bus_dmamap_create(sc->dc_mtag, 0, 2167 &sc->dc_cdata.dc_rx_map[i]); 2168 if (error) { 2169 device_printf(dev, "failed to init RX ring\n"); 2170 error = ENXIO; 2171 goto fail; 2172 } 2173 } 2174 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2175 if (error) { 2176 device_printf(dev, "failed to init RX ring\n"); 2177 error = ENXIO; 2178 goto fail; 2179 } 2180 2181 ifp = sc->dc_ifp = if_alloc(IFT_ETHER); 2182 if (ifp == NULL) { 2183 device_printf(dev, "can not if_alloc()\n"); 2184 error = ENOSPC; 2185 goto fail; 2186 } 2187 ifp->if_softc = sc; 2188 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2189 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2190 ifp->if_ioctl = dc_ioctl; 2191 ifp->if_start = dc_start; 2192 ifp->if_init = dc_init; 2193 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2194 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2195 IFQ_SET_READY(&ifp->if_snd); 2196 2197 /* 2198 * Do MII setup. If this is a 21143, check for a PHY on the 2199 * MII bus after applying any necessary fixups to twiddle the 2200 * GPIO bits. If we don't end up finding a PHY, restore the 2201 * old selection (SIA only or SIA/SYM) and attach the dcphy 2202 * driver instead. 2203 */ 2204 if (DC_IS_INTEL(sc)) { 2205 dc_apply_fixup(sc, IFM_AUTO); 2206 tmp = sc->dc_pmode; 2207 sc->dc_pmode = DC_PMODE_MII; 2208 } 2209 2210 /* 2211 * Setup General Purpose port mode and data so the tulip can talk 2212 * to the MII. This needs to be done before mii_phy_probe so that 2213 * we can actually see them. 2214 */ 2215 if (DC_IS_XIRCOM(sc)) { 2216 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2217 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2218 DELAY(10); 2219 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2220 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2221 DELAY(10); 2222 } 2223 2224 error = mii_phy_probe(dev, &sc->dc_miibus, 2225 dc_ifmedia_upd, dc_ifmedia_sts); 2226 2227 if (error && DC_IS_INTEL(sc)) { 2228 sc->dc_pmode = tmp; 2229 if (sc->dc_pmode != DC_PMODE_SIA) 2230 sc->dc_pmode = DC_PMODE_SYM; 2231 sc->dc_flags |= DC_21143_NWAY; 2232 mii_phy_probe(dev, &sc->dc_miibus, 2233 dc_ifmedia_upd, dc_ifmedia_sts); 2234 /* 2235 * For non-MII cards, we need to have the 21143 2236 * drive the LEDs. Except there are some systems 2237 * like the NEC VersaPro NoteBook PC which have no 2238 * LEDs, and twiddling these bits has adverse effects 2239 * on them. (I.e. you suddenly can't get a link.) 2240 */ 2241 if (!(pci_get_subvendor(dev) == 0x1033 && 2242 pci_get_subdevice(dev) == 0x8028)) 2243 sc->dc_flags |= DC_TULIP_LEDS; 2244 error = 0; 2245 } 2246 2247 if (error) { 2248 device_printf(dev, "MII without any PHY!\n"); 2249 goto fail; 2250 } 2251 2252 if (DC_IS_ADMTEK(sc)) { 2253 /* 2254 * Set automatic TX underrun recovery for the ADMtek chips 2255 */ 2256 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2257 } 2258 2259 /* 2260 * Tell the upper layer(s) we support long frames. 2261 */ 2262 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2263 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2264 ifp->if_capenable = ifp->if_capabilities; 2265#ifdef DEVICE_POLLING 2266 ifp->if_capabilities |= IFCAP_POLLING; 2267#endif 2268 2269 callout_init_mtx(&sc->dc_stat_ch, &sc->dc_mtx, 0); 2270 callout_init_mtx(&sc->dc_wdog_ch, &sc->dc_mtx, 0); 2271 2272 /* 2273 * Call MI attach routine. 2274 */ 2275 ether_ifattach(ifp, (caddr_t)eaddr); 2276 2277 /* Hook interrupt last to avoid having to lock softc */ 2278 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | INTR_MPSAFE, 2279 NULL, dc_intr, sc, &sc->dc_intrhand); 2280 2281 if (error) { 2282 device_printf(dev, "couldn't set up irq\n"); 2283 ether_ifdetach(ifp); 2284 goto fail; 2285 } 2286 2287fail: 2288 if (error) 2289 dc_detach(dev); 2290 return (error); 2291} 2292 2293/* 2294 * Shutdown hardware and free up resources. This can be called any 2295 * time after the mutex has been initialized. It is called in both 2296 * the error case in attach and the normal detach case so it needs 2297 * to be careful about only freeing resources that have actually been 2298 * allocated. 2299 */ 2300static int 2301dc_detach(device_t dev) 2302{ 2303 struct dc_softc *sc; 2304 struct ifnet *ifp; 2305 struct dc_mediainfo *m; 2306 int i; 2307 2308 sc = device_get_softc(dev); 2309 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2310 2311 ifp = sc->dc_ifp; 2312 2313#ifdef DEVICE_POLLING 2314 if (ifp->if_capenable & IFCAP_POLLING) 2315 ether_poll_deregister(ifp); 2316#endif 2317 2318 /* These should only be active if attach succeeded */ 2319 if (device_is_attached(dev)) { 2320 DC_LOCK(sc); 2321 dc_stop(sc); 2322 DC_UNLOCK(sc); 2323 callout_drain(&sc->dc_stat_ch); 2324 callout_drain(&sc->dc_wdog_ch); 2325 ether_ifdetach(ifp); 2326 } 2327 if (sc->dc_miibus) 2328 device_delete_child(dev, sc->dc_miibus); 2329 bus_generic_detach(dev); 2330 2331 if (sc->dc_intrhand) 2332 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2333 if (sc->dc_irq) 2334 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2335 if (sc->dc_res) 2336 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2337 2338 if (ifp) 2339 if_free(ifp); 2340 2341 if (sc->dc_cdata.dc_sbuf != NULL) 2342 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2343 if (sc->dc_ldata != NULL) 2344 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2345 if (sc->dc_mtag) { 2346 for (i = 0; i < DC_TX_LIST_CNT; i++) 2347 if (sc->dc_cdata.dc_tx_map[i] != NULL) 2348 bus_dmamap_destroy(sc->dc_mtag, 2349 sc->dc_cdata.dc_tx_map[i]); 2350 for (i = 0; i < DC_RX_LIST_CNT; i++) 2351 if (sc->dc_cdata.dc_rx_map[i] != NULL) 2352 bus_dmamap_destroy(sc->dc_mtag, 2353 sc->dc_cdata.dc_rx_map[i]); 2354 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2355 } 2356 if (sc->dc_stag) 2357 bus_dma_tag_destroy(sc->dc_stag); 2358 if (sc->dc_mtag) 2359 bus_dma_tag_destroy(sc->dc_mtag); 2360 if (sc->dc_ltag) 2361 bus_dma_tag_destroy(sc->dc_ltag); 2362 2363 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2364 2365 while (sc->dc_mi != NULL) { 2366 m = sc->dc_mi->dc_next; 2367 free(sc->dc_mi, M_DEVBUF); 2368 sc->dc_mi = m; 2369 } 2370 free(sc->dc_srom, M_DEVBUF); 2371 2372 mtx_destroy(&sc->dc_mtx); 2373 2374 return (0); 2375} 2376 2377/* 2378 * Initialize the transmit descriptors. 2379 */ 2380static int 2381dc_list_tx_init(struct dc_softc *sc) 2382{ 2383 struct dc_chain_data *cd; 2384 struct dc_list_data *ld; 2385 int i, nexti; 2386 2387 cd = &sc->dc_cdata; 2388 ld = sc->dc_ldata; 2389 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2390 if (i == DC_TX_LIST_CNT - 1) 2391 nexti = 0; 2392 else 2393 nexti = i + 1; 2394 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2395 cd->dc_tx_chain[i] = NULL; 2396 ld->dc_tx_list[i].dc_data = 0; 2397 ld->dc_tx_list[i].dc_ctl = 0; 2398 } 2399 2400 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2401 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2402 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2403 return (0); 2404} 2405 2406 2407/* 2408 * Initialize the RX descriptors and allocate mbufs for them. Note that 2409 * we arrange the descriptors in a closed ring, so that the last descriptor 2410 * points back to the first. 2411 */ 2412static int 2413dc_list_rx_init(struct dc_softc *sc) 2414{ 2415 struct dc_chain_data *cd; 2416 struct dc_list_data *ld; 2417 int i, nexti; 2418 2419 cd = &sc->dc_cdata; 2420 ld = sc->dc_ldata; 2421 2422 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2423 if (dc_newbuf(sc, i, 1) != 0) 2424 return (ENOBUFS); 2425 if (i == DC_RX_LIST_CNT - 1) 2426 nexti = 0; 2427 else 2428 nexti = i + 1; 2429 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2430 } 2431 2432 cd->dc_rx_prod = 0; 2433 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2434 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2435 return (0); 2436} 2437 2438/* 2439 * Initialize an RX descriptor and attach an MBUF cluster. 2440 */ 2441static int 2442dc_newbuf(struct dc_softc *sc, int i, int alloc) 2443{ 2444 struct mbuf *m_new; 2445 bus_dmamap_t tmp; 2446 bus_dma_segment_t segs[1]; 2447 int error, nseg; 2448 2449 if (alloc) { 2450 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2451 if (m_new == NULL) 2452 return (ENOBUFS); 2453 } else { 2454 m_new = sc->dc_cdata.dc_rx_chain[i]; 2455 m_new->m_data = m_new->m_ext.ext_buf; 2456 } 2457 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2458 m_adj(m_new, sizeof(u_int64_t)); 2459 2460 /* 2461 * If this is a PNIC chip, zero the buffer. This is part 2462 * of the workaround for the receive bug in the 82c168 and 2463 * 82c169 chips. 2464 */ 2465 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2466 bzero(mtod(m_new, char *), m_new->m_len); 2467 2468 /* No need to remap the mbuf if we're reusing it. */ 2469 if (alloc) { 2470 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, sc->dc_sparemap, 2471 m_new, segs, &nseg, 0); 2472 if (error) { 2473 m_freem(m_new); 2474 return (error); 2475 } 2476 KASSERT(nseg == 1, 2477 ("%s: wrong number of segments (%d)", __func__, nseg)); 2478 sc->dc_ldata->dc_rx_list[i].dc_data = htole32(segs->ds_addr); 2479 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2480 tmp = sc->dc_cdata.dc_rx_map[i]; 2481 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2482 sc->dc_sparemap = tmp; 2483 sc->dc_cdata.dc_rx_chain[i] = m_new; 2484 } 2485 2486 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2487 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2488 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2489 BUS_DMASYNC_PREREAD); 2490 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2491 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2492 return (0); 2493} 2494 2495/* 2496 * Grrrrr. 2497 * The PNIC chip has a terrible bug in it that manifests itself during 2498 * periods of heavy activity. The exact mode of failure if difficult to 2499 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2500 * will happen on slow machines. The bug is that sometimes instead of 2501 * uploading one complete frame during reception, it uploads what looks 2502 * like the entire contents of its FIFO memory. The frame we want is at 2503 * the end of the whole mess, but we never know exactly how much data has 2504 * been uploaded, so salvaging the frame is hard. 2505 * 2506 * There is only one way to do it reliably, and it's disgusting. 2507 * Here's what we know: 2508 * 2509 * - We know there will always be somewhere between one and three extra 2510 * descriptors uploaded. 2511 * 2512 * - We know the desired received frame will always be at the end of the 2513 * total data upload. 2514 * 2515 * - We know the size of the desired received frame because it will be 2516 * provided in the length field of the status word in the last descriptor. 2517 * 2518 * Here's what we do: 2519 * 2520 * - When we allocate buffers for the receive ring, we bzero() them. 2521 * This means that we know that the buffer contents should be all 2522 * zeros, except for data uploaded by the chip. 2523 * 2524 * - We also force the PNIC chip to upload frames that include the 2525 * ethernet CRC at the end. 2526 * 2527 * - We gather all of the bogus frame data into a single buffer. 2528 * 2529 * - We then position a pointer at the end of this buffer and scan 2530 * backwards until we encounter the first non-zero byte of data. 2531 * This is the end of the received frame. We know we will encounter 2532 * some data at the end of the frame because the CRC will always be 2533 * there, so even if the sender transmits a packet of all zeros, 2534 * we won't be fooled. 2535 * 2536 * - We know the size of the actual received frame, so we subtract 2537 * that value from the current pointer location. This brings us 2538 * to the start of the actual received packet. 2539 * 2540 * - We copy this into an mbuf and pass it on, along with the actual 2541 * frame length. 2542 * 2543 * The performance hit is tremendous, but it beats dropping frames all 2544 * the time. 2545 */ 2546 2547#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2548static void 2549dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2550{ 2551 struct dc_desc *cur_rx; 2552 struct dc_desc *c = NULL; 2553 struct mbuf *m = NULL; 2554 unsigned char *ptr; 2555 int i, total_len; 2556 u_int32_t rxstat = 0; 2557 2558 i = sc->dc_pnic_rx_bug_save; 2559 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2560 ptr = sc->dc_pnic_rx_buf; 2561 bzero(ptr, DC_RXLEN * 5); 2562 2563 /* Copy all the bytes from the bogus buffers. */ 2564 while (1) { 2565 c = &sc->dc_ldata->dc_rx_list[i]; 2566 rxstat = le32toh(c->dc_status); 2567 m = sc->dc_cdata.dc_rx_chain[i]; 2568 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2569 ptr += DC_RXLEN; 2570 /* If this is the last buffer, break out. */ 2571 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2572 break; 2573 dc_newbuf(sc, i, 0); 2574 DC_INC(i, DC_RX_LIST_CNT); 2575 } 2576 2577 /* Find the length of the actual receive frame. */ 2578 total_len = DC_RXBYTES(rxstat); 2579 2580 /* Scan backwards until we hit a non-zero byte. */ 2581 while (*ptr == 0x00) 2582 ptr--; 2583 2584 /* Round off. */ 2585 if ((uintptr_t)(ptr) & 0x3) 2586 ptr -= 1; 2587 2588 /* Now find the start of the frame. */ 2589 ptr -= total_len; 2590 if (ptr < sc->dc_pnic_rx_buf) 2591 ptr = sc->dc_pnic_rx_buf; 2592 2593 /* 2594 * Now copy the salvaged frame to the last mbuf and fake up 2595 * the status word to make it look like a successful 2596 * frame reception. 2597 */ 2598 dc_newbuf(sc, i, 0); 2599 bcopy(ptr, mtod(m, char *), total_len); 2600 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2601} 2602 2603/* 2604 * This routine searches the RX ring for dirty descriptors in the 2605 * event that the rxeof routine falls out of sync with the chip's 2606 * current descriptor pointer. This may happen sometimes as a result 2607 * of a "no RX buffer available" condition that happens when the chip 2608 * consumes all of the RX buffers before the driver has a chance to 2609 * process the RX ring. This routine may need to be called more than 2610 * once to bring the driver back in sync with the chip, however we 2611 * should still be getting RX DONE interrupts to drive the search 2612 * for new packets in the RX ring, so we should catch up eventually. 2613 */ 2614static int 2615dc_rx_resync(struct dc_softc *sc) 2616{ 2617 struct dc_desc *cur_rx; 2618 int i, pos; 2619 2620 pos = sc->dc_cdata.dc_rx_prod; 2621 2622 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2623 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2624 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2625 break; 2626 DC_INC(pos, DC_RX_LIST_CNT); 2627 } 2628 2629 /* If the ring really is empty, then just return. */ 2630 if (i == DC_RX_LIST_CNT) 2631 return (0); 2632 2633 /* We've fallen behing the chip: catch it. */ 2634 sc->dc_cdata.dc_rx_prod = pos; 2635 2636 return (EAGAIN); 2637} 2638 2639/* 2640 * A frame has been uploaded: pass the resulting mbuf chain up to 2641 * the higher level protocols. 2642 */ 2643static int 2644dc_rxeof(struct dc_softc *sc) 2645{ 2646 struct mbuf *m, *m0; 2647 struct ifnet *ifp; 2648 struct dc_desc *cur_rx; 2649 int i, total_len, rx_npkts; 2650 u_int32_t rxstat; 2651 2652 DC_LOCK_ASSERT(sc); 2653 2654 ifp = sc->dc_ifp; 2655 i = sc->dc_cdata.dc_rx_prod; 2656 total_len = 0; 2657 rx_npkts = 0; 2658 2659 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2660 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2661 DC_RXSTAT_OWN)) { 2662#ifdef DEVICE_POLLING 2663 if (ifp->if_capenable & IFCAP_POLLING) { 2664 if (sc->rxcycles <= 0) 2665 break; 2666 sc->rxcycles--; 2667 } 2668#endif 2669 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2670 rxstat = le32toh(cur_rx->dc_status); 2671 m = sc->dc_cdata.dc_rx_chain[i]; 2672 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2673 BUS_DMASYNC_POSTREAD); 2674 total_len = DC_RXBYTES(rxstat); 2675 2676 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2677 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2678 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2679 sc->dc_pnic_rx_bug_save = i; 2680 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2681 DC_INC(i, DC_RX_LIST_CNT); 2682 continue; 2683 } 2684 dc_pnic_rx_bug_war(sc, i); 2685 rxstat = le32toh(cur_rx->dc_status); 2686 total_len = DC_RXBYTES(rxstat); 2687 } 2688 } 2689 2690 /* 2691 * If an error occurs, update stats, clear the 2692 * status word and leave the mbuf cluster in place: 2693 * it should simply get re-used next time this descriptor 2694 * comes up in the ring. However, don't report long 2695 * frames as errors since they could be vlans. 2696 */ 2697 if ((rxstat & DC_RXSTAT_RXERR)) { 2698 if (!(rxstat & DC_RXSTAT_GIANT) || 2699 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2700 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2701 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2702 ifp->if_ierrors++; 2703 if (rxstat & DC_RXSTAT_COLLSEEN) 2704 ifp->if_collisions++; 2705 dc_newbuf(sc, i, 0); 2706 if (rxstat & DC_RXSTAT_CRCERR) { 2707 DC_INC(i, DC_RX_LIST_CNT); 2708 continue; 2709 } else { 2710 dc_init_locked(sc); 2711 return (rx_npkts); 2712 } 2713 } 2714 } 2715 2716 /* No errors; receive the packet. */ 2717 total_len -= ETHER_CRC_LEN; 2718#ifdef __NO_STRICT_ALIGNMENT 2719 /* 2720 * On architectures without alignment problems we try to 2721 * allocate a new buffer for the receive ring, and pass up 2722 * the one where the packet is already, saving the expensive 2723 * copy done in m_devget(). 2724 * If we are on an architecture with alignment problems, or 2725 * if the allocation fails, then use m_devget and leave the 2726 * existing buffer in the receive ring. 2727 */ 2728 if (dc_newbuf(sc, i, 1) == 0) { 2729 m->m_pkthdr.rcvif = ifp; 2730 m->m_pkthdr.len = m->m_len = total_len; 2731 DC_INC(i, DC_RX_LIST_CNT); 2732 } else 2733#endif 2734 { 2735 m0 = m_devget(mtod(m, char *), total_len, 2736 ETHER_ALIGN, ifp, NULL); 2737 dc_newbuf(sc, i, 0); 2738 DC_INC(i, DC_RX_LIST_CNT); 2739 if (m0 == NULL) { 2740 ifp->if_ierrors++; 2741 continue; 2742 } 2743 m = m0; 2744 } 2745 2746 ifp->if_ipackets++; 2747 DC_UNLOCK(sc); 2748 (*ifp->if_input)(ifp, m); 2749 DC_LOCK(sc); 2750 rx_npkts++; 2751 } 2752 2753 sc->dc_cdata.dc_rx_prod = i; 2754 return (rx_npkts); 2755} 2756 2757/* 2758 * A frame was downloaded to the chip. It's safe for us to clean up 2759 * the list buffers. 2760 */ 2761static void 2762dc_txeof(struct dc_softc *sc) 2763{ 2764 struct dc_desc *cur_tx = NULL; 2765 struct ifnet *ifp; 2766 int idx; 2767 u_int32_t ctl, txstat; 2768 2769 ifp = sc->dc_ifp; 2770 2771 /* 2772 * Go through our tx list and free mbufs for those 2773 * frames that have been transmitted. 2774 */ 2775 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2776 idx = sc->dc_cdata.dc_tx_cons; 2777 while (idx != sc->dc_cdata.dc_tx_prod) { 2778 2779 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2780 txstat = le32toh(cur_tx->dc_status); 2781 ctl = le32toh(cur_tx->dc_ctl); 2782 2783 if (txstat & DC_TXSTAT_OWN) 2784 break; 2785 2786 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2787 if (ctl & DC_TXCTL_SETUP) { 2788 /* 2789 * Yes, the PNIC is so brain damaged 2790 * that it will sometimes generate a TX 2791 * underrun error while DMAing the RX 2792 * filter setup frame. If we detect this, 2793 * we have to send the setup frame again, 2794 * or else the filter won't be programmed 2795 * correctly. 2796 */ 2797 if (DC_IS_PNIC(sc)) { 2798 if (txstat & DC_TXSTAT_ERRSUM) 2799 dc_setfilt(sc); 2800 } 2801 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2802 } 2803 sc->dc_cdata.dc_tx_cnt--; 2804 DC_INC(idx, DC_TX_LIST_CNT); 2805 continue; 2806 } 2807 2808 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2809 /* 2810 * XXX: Why does my Xircom taunt me so? 2811 * For some reason it likes setting the CARRLOST flag 2812 * even when the carrier is there. wtf?!? 2813 * Who knows, but Conexant chips have the 2814 * same problem. Maybe they took lessons 2815 * from Xircom. 2816 */ 2817 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2818 sc->dc_pmode == DC_PMODE_MII && 2819 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2820 DC_TXSTAT_NOCARRIER))) 2821 txstat &= ~DC_TXSTAT_ERRSUM; 2822 } else { 2823 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2824 sc->dc_pmode == DC_PMODE_MII && 2825 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2826 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2827 txstat &= ~DC_TXSTAT_ERRSUM; 2828 } 2829 2830 if (txstat & DC_TXSTAT_ERRSUM) { 2831 ifp->if_oerrors++; 2832 if (txstat & DC_TXSTAT_EXCESSCOLL) 2833 ifp->if_collisions++; 2834 if (txstat & DC_TXSTAT_LATECOLL) 2835 ifp->if_collisions++; 2836 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2837 dc_init_locked(sc); 2838 return; 2839 } 2840 } 2841 2842 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2843 2844 ifp->if_opackets++; 2845 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2846 bus_dmamap_sync(sc->dc_mtag, 2847 sc->dc_cdata.dc_tx_map[idx], 2848 BUS_DMASYNC_POSTWRITE); 2849 bus_dmamap_unload(sc->dc_mtag, 2850 sc->dc_cdata.dc_tx_map[idx]); 2851 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2852 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2853 } 2854 2855 sc->dc_cdata.dc_tx_cnt--; 2856 DC_INC(idx, DC_TX_LIST_CNT); 2857 } 2858 sc->dc_cdata.dc_tx_cons = idx; 2859 2860 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > DC_TX_LIST_RSVD) 2861 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2862 2863 if (sc->dc_cdata.dc_tx_cnt == 0) 2864 sc->dc_wdog_timer = 0; 2865} 2866 2867static void 2868dc_tick(void *xsc) 2869{ 2870 struct dc_softc *sc; 2871 struct mii_data *mii; 2872 struct ifnet *ifp; 2873 u_int32_t r; 2874 2875 sc = xsc; 2876 DC_LOCK_ASSERT(sc); 2877 ifp = sc->dc_ifp; 2878 mii = device_get_softc(sc->dc_miibus); 2879 2880 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2881 if (sc->dc_flags & DC_21143_NWAY) { 2882 r = CSR_READ_4(sc, DC_10BTSTAT); 2883 if (IFM_SUBTYPE(mii->mii_media_active) == 2884 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2885 sc->dc_link = 0; 2886 mii_mediachg(mii); 2887 } 2888 if (IFM_SUBTYPE(mii->mii_media_active) == 2889 IFM_10_T && (r & DC_TSTAT_LS10)) { 2890 sc->dc_link = 0; 2891 mii_mediachg(mii); 2892 } 2893 if (sc->dc_link == 0) 2894 mii_tick(mii); 2895 } else { 2896 /* 2897 * For NICs which never report DC_RXSTATE_WAIT, we 2898 * have to bite the bullet... 2899 */ 2900 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc, 2901 DC_ISR) & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT) && 2902 sc->dc_cdata.dc_tx_cnt == 0) { 2903 mii_tick(mii); 2904 if (!(mii->mii_media_status & IFM_ACTIVE)) 2905 sc->dc_link = 0; 2906 } 2907 } 2908 } else 2909 mii_tick(mii); 2910 2911 /* 2912 * When the init routine completes, we expect to be able to send 2913 * packets right away, and in fact the network code will send a 2914 * gratuitous ARP the moment the init routine marks the interface 2915 * as running. However, even though the MAC may have been initialized, 2916 * there may be a delay of a few seconds before the PHY completes 2917 * autonegotiation and the link is brought up. Any transmissions 2918 * made during that delay will be lost. Dealing with this is tricky: 2919 * we can't just pause in the init routine while waiting for the 2920 * PHY to come ready since that would bring the whole system to 2921 * a screeching halt for several seconds. 2922 * 2923 * What we do here is prevent the TX start routine from sending 2924 * any packets until a link has been established. After the 2925 * interface has been initialized, the tick routine will poll 2926 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2927 * that time, packets will stay in the send queue, and once the 2928 * link comes up, they will be flushed out to the wire. 2929 */ 2930 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2931 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2932 sc->dc_link++; 2933 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2934 dc_start_locked(ifp); 2935 } 2936 2937 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2938 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2939 else 2940 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2941} 2942 2943/* 2944 * A transmit underrun has occurred. Back off the transmit threshold, 2945 * or switch to store and forward mode if we have to. 2946 */ 2947static void 2948dc_tx_underrun(struct dc_softc *sc) 2949{ 2950 u_int32_t isr; 2951 int i; 2952 2953 if (DC_IS_DAVICOM(sc)) 2954 dc_init_locked(sc); 2955 2956 if (DC_IS_INTEL(sc)) { 2957 /* 2958 * The real 21143 requires that the transmitter be idle 2959 * in order to change the transmit threshold or store 2960 * and forward state. 2961 */ 2962 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2963 2964 for (i = 0; i < DC_TIMEOUT; i++) { 2965 isr = CSR_READ_4(sc, DC_ISR); 2966 if (isr & DC_ISR_TX_IDLE) 2967 break; 2968 DELAY(10); 2969 } 2970 if (i == DC_TIMEOUT) { 2971 device_printf(sc->dc_dev, 2972 "%s: failed to force tx to idle state\n", 2973 __func__); 2974 dc_init_locked(sc); 2975 } 2976 } 2977 2978 device_printf(sc->dc_dev, "TX underrun -- "); 2979 sc->dc_txthresh += DC_TXTHRESH_INC; 2980 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2981 printf("using store and forward mode\n"); 2982 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2983 } else { 2984 printf("increasing TX threshold\n"); 2985 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2986 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2987 } 2988 2989 if (DC_IS_INTEL(sc)) 2990 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2991} 2992 2993#ifdef DEVICE_POLLING 2994static poll_handler_t dc_poll; 2995 2996static int 2997dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2998{ 2999 struct dc_softc *sc = ifp->if_softc; 3000 int rx_npkts = 0; 3001 3002 DC_LOCK(sc); 3003 3004 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3005 DC_UNLOCK(sc); 3006 return (rx_npkts); 3007 } 3008 3009 sc->rxcycles = count; 3010 rx_npkts = dc_rxeof(sc); 3011 dc_txeof(sc); 3012 if (!IFQ_IS_EMPTY(&ifp->if_snd) && 3013 !(ifp->if_drv_flags & IFF_DRV_OACTIVE)) 3014 dc_start_locked(ifp); 3015 3016 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3017 u_int32_t status; 3018 3019 status = CSR_READ_4(sc, DC_ISR); 3020 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3021 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3022 DC_ISR_BUS_ERR); 3023 if (!status) { 3024 DC_UNLOCK(sc); 3025 return (rx_npkts); 3026 } 3027 /* ack what we have */ 3028 CSR_WRITE_4(sc, DC_ISR, status); 3029 3030 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3031 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3032 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3033 3034 if (dc_rx_resync(sc)) 3035 dc_rxeof(sc); 3036 } 3037 /* restart transmit unit if necessary */ 3038 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3039 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3040 3041 if (status & DC_ISR_TX_UNDERRUN) 3042 dc_tx_underrun(sc); 3043 3044 if (status & DC_ISR_BUS_ERR) { 3045 if_printf(ifp, "%s: bus error\n", __func__); 3046 dc_reset(sc); 3047 dc_init_locked(sc); 3048 } 3049 } 3050 DC_UNLOCK(sc); 3051 return (rx_npkts); 3052} 3053#endif /* DEVICE_POLLING */ 3054 3055static void 3056dc_intr(void *arg) 3057{ 3058 struct dc_softc *sc; 3059 struct ifnet *ifp; 3060 u_int32_t status; 3061 3062 sc = arg; 3063 3064 if (sc->suspended) 3065 return; 3066 3067 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3068 return; 3069 3070 DC_LOCK(sc); 3071 ifp = sc->dc_ifp; 3072#ifdef DEVICE_POLLING 3073 if (ifp->if_capenable & IFCAP_POLLING) { 3074 DC_UNLOCK(sc); 3075 return; 3076 } 3077#endif 3078 3079 /* Suppress unwanted interrupts */ 3080 if (!(ifp->if_flags & IFF_UP)) { 3081 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3082 dc_stop(sc); 3083 DC_UNLOCK(sc); 3084 return; 3085 } 3086 3087 /* Disable interrupts. */ 3088 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3089 3090 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 3091 status != 0xFFFFFFFF && 3092 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3093 3094 CSR_WRITE_4(sc, DC_ISR, status); 3095 3096 if (status & DC_ISR_RX_OK) { 3097 int curpkts; 3098 curpkts = ifp->if_ipackets; 3099 dc_rxeof(sc); 3100 if (curpkts == ifp->if_ipackets) { 3101 while (dc_rx_resync(sc)) 3102 dc_rxeof(sc); 3103 } 3104 } 3105 3106 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3107 dc_txeof(sc); 3108 3109 if (status & DC_ISR_TX_IDLE) { 3110 dc_txeof(sc); 3111 if (sc->dc_cdata.dc_tx_cnt) { 3112 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3113 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3114 } 3115 } 3116 3117 if (status & DC_ISR_TX_UNDERRUN) 3118 dc_tx_underrun(sc); 3119 3120 if ((status & DC_ISR_RX_WATDOGTIMEO) 3121 || (status & DC_ISR_RX_NOBUF)) { 3122 int curpkts; 3123 curpkts = ifp->if_ipackets; 3124 dc_rxeof(sc); 3125 if (curpkts == ifp->if_ipackets) { 3126 while (dc_rx_resync(sc)) 3127 dc_rxeof(sc); 3128 } 3129 } 3130 3131 if (status & DC_ISR_BUS_ERR) { 3132 dc_reset(sc); 3133 dc_init_locked(sc); 3134 } 3135 } 3136 3137 /* Re-enable interrupts. */ 3138 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3139 3140 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3141 dc_start_locked(ifp); 3142 3143 DC_UNLOCK(sc); 3144} 3145 3146/* 3147 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3148 * pointers to the fragment pointers. 3149 */ 3150static int 3151dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3152{ 3153 bus_dma_segment_t segs[DC_MAXFRAGS]; 3154 struct dc_desc *f; 3155 struct mbuf *m; 3156 int cur, defragged, error, first, frag, i, idx, nseg; 3157 3158 /* 3159 * If there's no way we can send any packets, return now. 3160 */ 3161 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt <= DC_TX_LIST_RSVD) 3162 return (ENOBUFS); 3163 3164 m = NULL; 3165 defragged = 0; 3166 if (sc->dc_flags & DC_TX_COALESCE && 3167 ((*m_head)->m_next != NULL || sc->dc_flags & DC_TX_ALIGN)) { 3168 m = m_defrag(*m_head, M_DONTWAIT); 3169 defragged = 1; 3170 } else { 3171 /* 3172 * Count the number of frags in this chain to see if we 3173 * need to m_collapse. Since the descriptor list is shared 3174 * by all packets, we'll m_collapse long chains so that they 3175 * do not use up the entire list, even if they would fit. 3176 */ 3177 i = 0; 3178 for (m = *m_head; m != NULL; m = m->m_next) 3179 i++; 3180 if (i > DC_TX_LIST_CNT / 4 || 3181 DC_TX_LIST_CNT - i + sc->dc_cdata.dc_tx_cnt <= 3182 DC_TX_LIST_RSVD) { 3183 m = m_collapse(*m_head, M_DONTWAIT, DC_MAXFRAGS); 3184 defragged = 1; 3185 } 3186 } 3187 if (defragged != 0) { 3188 if (m == NULL) { 3189 m_freem(*m_head); 3190 *m_head = NULL; 3191 return (ENOBUFS); 3192 } 3193 *m_head = m; 3194 } 3195 3196 idx = sc->dc_cdata.dc_tx_prod; 3197 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3198 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3199 if (error == EFBIG) { 3200 if (defragged != 0 || (m = m_collapse(*m_head, M_DONTWAIT, 3201 DC_MAXFRAGS)) == NULL) { 3202 m_freem(*m_head); 3203 *m_head = NULL; 3204 return (defragged != 0 ? error : ENOBUFS); 3205 } 3206 *m_head = m; 3207 error = bus_dmamap_load_mbuf_sg(sc->dc_mtag, 3208 sc->dc_cdata.dc_tx_map[idx], *m_head, segs, &nseg, 0); 3209 if (error != 0) { 3210 m_freem(*m_head); 3211 *m_head = NULL; 3212 return (error); 3213 } 3214 } else if (error != 0) 3215 return (error); 3216 KASSERT(nseg <= DC_MAXFRAGS, 3217 ("%s: wrong number of segments (%d)", __func__, nseg)); 3218 if (nseg == 0) { 3219 m_freem(*m_head); 3220 *m_head = NULL; 3221 return (EIO); 3222 } 3223 3224 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3225 for (i = 0; i < nseg; i++) { 3226 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3227 (frag == (DC_TX_LIST_CNT - 1)) && 3228 (first != sc->dc_cdata.dc_tx_first)) { 3229 bus_dmamap_unload(sc->dc_mtag, 3230 sc->dc_cdata.dc_tx_map[first]); 3231 m_freem(*m_head); 3232 *m_head = NULL; 3233 return (ENOBUFS); 3234 } 3235 3236 f = &sc->dc_ldata->dc_tx_list[frag]; 3237 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3238 if (i == 0) { 3239 f->dc_status = 0; 3240 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3241 } else 3242 f->dc_status = htole32(DC_TXSTAT_OWN); 3243 f->dc_data = htole32(segs[i].ds_addr); 3244 cur = frag; 3245 DC_INC(frag, DC_TX_LIST_CNT); 3246 } 3247 3248 sc->dc_cdata.dc_tx_prod = frag; 3249 sc->dc_cdata.dc_tx_cnt += nseg; 3250 sc->dc_cdata.dc_tx_chain[cur] = *m_head; 3251 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3252 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3253 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3254 htole32(DC_TXCTL_FINT); 3255 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3256 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3257 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3258 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3259 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3260 3261 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3262 BUS_DMASYNC_PREWRITE); 3263 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3264 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3265 return (0); 3266} 3267 3268static void 3269dc_start(struct ifnet *ifp) 3270{ 3271 struct dc_softc *sc; 3272 3273 sc = ifp->if_softc; 3274 DC_LOCK(sc); 3275 dc_start_locked(ifp); 3276 DC_UNLOCK(sc); 3277} 3278 3279/* 3280 * Main transmit routine 3281 * To avoid having to do mbuf copies, we put pointers to the mbuf data 3282 * regions directly in the transmit lists. We also save a copy of the 3283 * pointers since the transmit list fragment pointers are physical 3284 * addresses. 3285 */ 3286static void 3287dc_start_locked(struct ifnet *ifp) 3288{ 3289 struct dc_softc *sc; 3290 struct mbuf *m_head = NULL; 3291 unsigned int queued = 0; 3292 int idx; 3293 3294 sc = ifp->if_softc; 3295 3296 DC_LOCK_ASSERT(sc); 3297 3298 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) 3299 return; 3300 3301 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 3302 return; 3303 3304 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3305 3306 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3307 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3308 if (m_head == NULL) 3309 break; 3310 3311 if (dc_encap(sc, &m_head)) { 3312 if (m_head == NULL) 3313 break; 3314 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3315 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3316 break; 3317 } 3318 idx = sc->dc_cdata.dc_tx_prod; 3319 3320 queued++; 3321 /* 3322 * If there's a BPF listener, bounce a copy of this frame 3323 * to him. 3324 */ 3325 BPF_MTAP(ifp, m_head); 3326 3327 if (sc->dc_flags & DC_TX_ONE) { 3328 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3329 break; 3330 } 3331 } 3332 3333 if (queued > 0) { 3334 /* Transmit */ 3335 if (!(sc->dc_flags & DC_TX_POLL)) 3336 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3337 3338 /* 3339 * Set a timeout in case the chip goes out to lunch. 3340 */ 3341 sc->dc_wdog_timer = 5; 3342 } 3343} 3344 3345static void 3346dc_init(void *xsc) 3347{ 3348 struct dc_softc *sc = xsc; 3349 3350 DC_LOCK(sc); 3351 dc_init_locked(sc); 3352 DC_UNLOCK(sc); 3353} 3354 3355static void 3356dc_init_locked(struct dc_softc *sc) 3357{ 3358 struct ifnet *ifp = sc->dc_ifp; 3359 struct mii_data *mii; 3360 3361 DC_LOCK_ASSERT(sc); 3362 3363 mii = device_get_softc(sc->dc_miibus); 3364 3365 /* 3366 * Cancel pending I/O and free all RX/TX buffers. 3367 */ 3368 dc_stop(sc); 3369 dc_reset(sc); 3370 3371 /* 3372 * Set cache alignment and burst length. 3373 */ 3374 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3375 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3376 else 3377 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3378 /* 3379 * Evenly share the bus between receive and transmit process. 3380 */ 3381 if (DC_IS_INTEL(sc)) 3382 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3383 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3384 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3385 } else { 3386 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3387 } 3388 if (sc->dc_flags & DC_TX_POLL) 3389 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3390 switch(sc->dc_cachesize) { 3391 case 32: 3392 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3393 break; 3394 case 16: 3395 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3396 break; 3397 case 8: 3398 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3399 break; 3400 case 0: 3401 default: 3402 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3403 break; 3404 } 3405 3406 if (sc->dc_flags & DC_TX_STORENFWD) 3407 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3408 else { 3409 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3410 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3411 } else { 3412 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3413 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3414 } 3415 } 3416 3417 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3418 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3419 3420 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3421 /* 3422 * The app notes for the 98713 and 98715A say that 3423 * in order to have the chips operate properly, a magic 3424 * number must be written to CSR16. Macronix does not 3425 * document the meaning of these bits so there's no way 3426 * to know exactly what they do. The 98713 has a magic 3427 * number all its own; the rest all use a different one. 3428 */ 3429 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3430 if (sc->dc_type == DC_TYPE_98713) 3431 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3432 else 3433 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3434 } 3435 3436 if (DC_IS_XIRCOM(sc)) { 3437 /* 3438 * setup General Purpose Port mode and data so the tulip 3439 * can talk to the MII. 3440 */ 3441 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3442 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3443 DELAY(10); 3444 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3445 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3446 DELAY(10); 3447 } 3448 3449 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3450 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3451 3452 /* Init circular RX list. */ 3453 if (dc_list_rx_init(sc) == ENOBUFS) { 3454 device_printf(sc->dc_dev, 3455 "initialization failed: no memory for rx buffers\n"); 3456 dc_stop(sc); 3457 return; 3458 } 3459 3460 /* 3461 * Init TX descriptors. 3462 */ 3463 dc_list_tx_init(sc); 3464 3465 /* 3466 * Load the address of the RX list. 3467 */ 3468 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3469 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3470 3471 /* 3472 * Enable interrupts. 3473 */ 3474#ifdef DEVICE_POLLING 3475 /* 3476 * ... but only if we are not polling, and make sure they are off in 3477 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3478 * after a reset. 3479 */ 3480 if (ifp->if_capenable & IFCAP_POLLING) 3481 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3482 else 3483#endif 3484 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3485 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3486 3487 /* Enable transmitter. */ 3488 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3489 3490 /* 3491 * If this is an Intel 21143 and we're not using the 3492 * MII port, program the LED control pins so we get 3493 * link and activity indications. 3494 */ 3495 if (sc->dc_flags & DC_TULIP_LEDS) { 3496 CSR_WRITE_4(sc, DC_WATCHDOG, 3497 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3498 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3499 } 3500 3501 /* 3502 * Load the RX/multicast filter. We do this sort of late 3503 * because the filter programming scheme on the 21143 and 3504 * some clones requires DMAing a setup frame via the TX 3505 * engine, and we need the transmitter enabled for that. 3506 */ 3507 dc_setfilt(sc); 3508 3509 /* Enable receiver. */ 3510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3511 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3512 3513 mii_mediachg(mii); 3514 dc_setcfg(sc, sc->dc_if_media); 3515 3516 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3517 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3518 3519 /* Don't start the ticker if this is a homePNA link. */ 3520 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3521 sc->dc_link = 1; 3522 else { 3523 if (sc->dc_flags & DC_21143_NWAY) 3524 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3525 else 3526 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3527 } 3528 3529 sc->dc_wdog_timer = 0; 3530 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3531} 3532 3533/* 3534 * Set media options. 3535 */ 3536static int 3537dc_ifmedia_upd(struct ifnet *ifp) 3538{ 3539 struct dc_softc *sc; 3540 struct mii_data *mii; 3541 struct ifmedia *ifm; 3542 3543 sc = ifp->if_softc; 3544 mii = device_get_softc(sc->dc_miibus); 3545 DC_LOCK(sc); 3546 mii_mediachg(mii); 3547 ifm = &mii->mii_media; 3548 3549 if (DC_IS_DAVICOM(sc) && 3550 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3551 dc_setcfg(sc, ifm->ifm_media); 3552 else 3553 sc->dc_link = 0; 3554 DC_UNLOCK(sc); 3555 3556 return (0); 3557} 3558 3559/* 3560 * Report current media status. 3561 */ 3562static void 3563dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3564{ 3565 struct dc_softc *sc; 3566 struct mii_data *mii; 3567 struct ifmedia *ifm; 3568 3569 sc = ifp->if_softc; 3570 mii = device_get_softc(sc->dc_miibus); 3571 DC_LOCK(sc); 3572 mii_pollstat(mii); 3573 ifm = &mii->mii_media; 3574 if (DC_IS_DAVICOM(sc)) { 3575 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3576 ifmr->ifm_active = ifm->ifm_media; 3577 ifmr->ifm_status = 0; 3578 DC_UNLOCK(sc); 3579 return; 3580 } 3581 } 3582 ifmr->ifm_active = mii->mii_media_active; 3583 ifmr->ifm_status = mii->mii_media_status; 3584 DC_UNLOCK(sc); 3585} 3586 3587static int 3588dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3589{ 3590 struct dc_softc *sc = ifp->if_softc; 3591 struct ifreq *ifr = (struct ifreq *)data; 3592 struct mii_data *mii; 3593 int error = 0; 3594 3595 switch (command) { 3596 case SIOCSIFFLAGS: 3597 DC_LOCK(sc); 3598 if (ifp->if_flags & IFF_UP) { 3599 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3600 (IFF_PROMISC | IFF_ALLMULTI); 3601 3602 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3603 if (need_setfilt) 3604 dc_setfilt(sc); 3605 } else { 3606 sc->dc_txthresh = 0; 3607 dc_init_locked(sc); 3608 } 3609 } else { 3610 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3611 dc_stop(sc); 3612 } 3613 sc->dc_if_flags = ifp->if_flags; 3614 DC_UNLOCK(sc); 3615 error = 0; 3616 break; 3617 case SIOCADDMULTI: 3618 case SIOCDELMULTI: 3619 DC_LOCK(sc); 3620 dc_setfilt(sc); 3621 DC_UNLOCK(sc); 3622 error = 0; 3623 break; 3624 case SIOCGIFMEDIA: 3625 case SIOCSIFMEDIA: 3626 mii = device_get_softc(sc->dc_miibus); 3627 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3628 break; 3629 case SIOCSIFCAP: 3630#ifdef DEVICE_POLLING 3631 if (ifr->ifr_reqcap & IFCAP_POLLING && 3632 !(ifp->if_capenable & IFCAP_POLLING)) { 3633 error = ether_poll_register(dc_poll, ifp); 3634 if (error) 3635 return(error); 3636 DC_LOCK(sc); 3637 /* Disable interrupts */ 3638 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3639 ifp->if_capenable |= IFCAP_POLLING; 3640 DC_UNLOCK(sc); 3641 return (error); 3642 } 3643 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3644 ifp->if_capenable & IFCAP_POLLING) { 3645 error = ether_poll_deregister(ifp); 3646 /* Enable interrupts. */ 3647 DC_LOCK(sc); 3648 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3649 ifp->if_capenable &= ~IFCAP_POLLING; 3650 DC_UNLOCK(sc); 3651 return (error); 3652 } 3653#endif /* DEVICE_POLLING */ 3654 break; 3655 default: 3656 error = ether_ioctl(ifp, command, data); 3657 break; 3658 } 3659 3660 return (error); 3661} 3662 3663static void 3664dc_watchdog(void *xsc) 3665{ 3666 struct dc_softc *sc = xsc; 3667 struct ifnet *ifp; 3668 3669 DC_LOCK_ASSERT(sc); 3670 3671 if (sc->dc_wdog_timer == 0 || --sc->dc_wdog_timer != 0) { 3672 callout_reset(&sc->dc_wdog_ch, hz, dc_watchdog, sc); 3673 return; 3674 } 3675 3676 ifp = sc->dc_ifp; 3677 ifp->if_oerrors++; 3678 device_printf(sc->dc_dev, "watchdog timeout\n"); 3679 3680 dc_stop(sc); 3681 dc_reset(sc); 3682 dc_init_locked(sc); 3683 3684 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3685 dc_start_locked(ifp); 3686} 3687 3688/* 3689 * Stop the adapter and free any mbufs allocated to the 3690 * RX and TX lists. 3691 */ 3692static void 3693dc_stop(struct dc_softc *sc) 3694{ 3695 struct ifnet *ifp; 3696 struct dc_list_data *ld; 3697 struct dc_chain_data *cd; 3698 int i; 3699 u_int32_t ctl; 3700 3701 DC_LOCK_ASSERT(sc); 3702 3703 ifp = sc->dc_ifp; 3704 ld = sc->dc_ldata; 3705 cd = &sc->dc_cdata; 3706 3707 callout_stop(&sc->dc_stat_ch); 3708 callout_stop(&sc->dc_wdog_ch); 3709 sc->dc_wdog_timer = 0; 3710 3711 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3712 3713 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3714 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3715 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3716 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3717 sc->dc_link = 0; 3718 3719 /* 3720 * Free data in the RX lists. 3721 */ 3722 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3723 if (cd->dc_rx_chain[i] != NULL) { 3724 m_freem(cd->dc_rx_chain[i]); 3725 cd->dc_rx_chain[i] = NULL; 3726 } 3727 } 3728 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3729 3730 /* 3731 * Free the TX list buffers. 3732 */ 3733 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3734 if (cd->dc_tx_chain[i] != NULL) { 3735 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3736 if ((ctl & DC_TXCTL_SETUP) || 3737 !(ctl & DC_TXCTL_LASTFRAG)) { 3738 cd->dc_tx_chain[i] = NULL; 3739 continue; 3740 } 3741 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3742 m_freem(cd->dc_tx_chain[i]); 3743 cd->dc_tx_chain[i] = NULL; 3744 } 3745 } 3746 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3747} 3748 3749/* 3750 * Device suspend routine. Stop the interface and save some PCI 3751 * settings in case the BIOS doesn't restore them properly on 3752 * resume. 3753 */ 3754static int 3755dc_suspend(device_t dev) 3756{ 3757 struct dc_softc *sc; 3758 3759 sc = device_get_softc(dev); 3760 DC_LOCK(sc); 3761 dc_stop(sc); 3762 sc->suspended = 1; 3763 DC_UNLOCK(sc); 3764 3765 return (0); 3766} 3767 3768/* 3769 * Device resume routine. Restore some PCI settings in case the BIOS 3770 * doesn't, re-enable busmastering, and restart the interface if 3771 * appropriate. 3772 */ 3773static int 3774dc_resume(device_t dev) 3775{ 3776 struct dc_softc *sc; 3777 struct ifnet *ifp; 3778 3779 sc = device_get_softc(dev); 3780 ifp = sc->dc_ifp; 3781 3782 /* reinitialize interface if necessary */ 3783 DC_LOCK(sc); 3784 if (ifp->if_flags & IFF_UP) 3785 dc_init_locked(sc); 3786 3787 sc->suspended = 0; 3788 DC_UNLOCK(sc); 3789 3790 return (0); 3791} 3792 3793/* 3794 * Stop all chip I/O so that the kernel's probe routines don't 3795 * get confused by errant DMAs when rebooting. 3796 */ 3797static int 3798dc_shutdown(device_t dev) 3799{ 3800 struct dc_softc *sc; 3801 3802 sc = device_get_softc(dev); 3803 3804 DC_LOCK(sc); 3805 dc_stop(sc); 3806 DC_UNLOCK(sc); 3807 3808 return (0); 3809} 3810