if_dc.c revision 142398
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/dc/if_dc.c 142398 2005-02-24 21:32:56Z imp $"); 35 36/* 37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 38 * series chips and several workalikes including the following: 39 * 40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 42 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 43 * ASIX Electronics AX88140A (www.asix.com.tw) 44 * ASIX Electronics AX88141 (www.asix.com.tw) 45 * ADMtek AL981 (www.admtek.com.tw) 46 * ADMtek AN985 (www.admtek.com.tw) 47 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 48 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 49 * Accton EN1217 (www.accton.com) 50 * Xircom X3201 (www.xircom.com) 51 * Abocom FE2500 52 * Conexant LANfinity (www.conexant.com) 53 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 54 * 55 * Datasheets for the 21143 are available at developer.intel.com. 56 * Datasheets for the clone parts can be found at their respective sites. 57 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 58 * The PNIC II is essentially a Macronix 98715A chip; the only difference 59 * worth noting is that its multicast hash table is only 128 bits wide 60 * instead of 512. 61 * 62 * Written by Bill Paul <wpaul@ee.columbia.edu> 63 * Electrical Engineering Department 64 * Columbia University, New York City 65 */ 66/* 67 * The Intel 21143 is the successor to the DEC 21140. It is basically 68 * the same as the 21140 but with a few new features. The 21143 supports 69 * three kinds of media attachments: 70 * 71 * o MII port, for 10Mbps and 100Mbps support and NWAY 72 * autonegotiation provided by an external PHY. 73 * o SYM port, for symbol mode 100Mbps support. 74 * o 10baseT port. 75 * o AUI/BNC port. 76 * 77 * The 100Mbps SYM port and 10baseT port can be used together in 78 * combination with the internal NWAY support to create a 10/100 79 * autosensing configuration. 80 * 81 * Note that not all tulip workalikes are handled in this driver: we only 82 * deal with those which are relatively well behaved. The Winbond is 83 * handled separately due to its different register offsets and the 84 * special handling needed for its various bugs. The PNIC is handled 85 * here, but I'm not thrilled about it. 86 * 87 * All of the workalike chips use some form of MII transceiver support 88 * with the exception of the Macronix chips, which also have a SYM port. 89 * The ASIX AX88140A is also documented to have a SYM port, but all 90 * the cards I've seen use an MII transceiver, probably because the 91 * AX88140A doesn't support internal NWAY. 92 */ 93 94#include <sys/param.h> 95#include <sys/endian.h> 96#include <sys/systm.h> 97#include <sys/sockio.h> 98#include <sys/mbuf.h> 99#include <sys/malloc.h> 100#include <sys/kernel.h> 101#include <sys/module.h> 102#include <sys/socket.h> 103#include <sys/sysctl.h> 104 105#include <net/if.h> 106#include <net/if_arp.h> 107#include <net/ethernet.h> 108#include <net/if_dl.h> 109#include <net/if_media.h> 110#include <net/if_types.h> 111#include <net/if_vlan_var.h> 112 113#include <net/bpf.h> 114 115#include <machine/bus_pio.h> 116#include <machine/bus_memio.h> 117#include <machine/bus.h> 118#include <machine/resource.h> 119#include <sys/bus.h> 120#include <sys/rman.h> 121 122#include <dev/mii/mii.h> 123#include <dev/mii/miivar.h> 124 125#include <dev/pci/pcireg.h> 126#include <dev/pci/pcivar.h> 127 128#define DC_USEIOSPACE 129#ifdef __alpha__ 130#define SRM_MEDIA 131#endif 132 133#include <pci/if_dcreg.h> 134 135#ifdef __sparc64__ 136#include <dev/ofw/openfirm.h> 137#include <machine/ofw_machdep.h> 138#endif 139 140MODULE_DEPEND(dc, pci, 1, 1, 1); 141MODULE_DEPEND(dc, ether, 1, 1, 1); 142MODULE_DEPEND(dc, miibus, 1, 1, 1); 143 144/* "controller miibus0" required. See GENERIC if you get errors here. */ 145#include "miibus_if.h" 146 147/* 148 * Various supported device vendors/types and their names. 149 */ 150static struct dc_type dc_devs[] = { 151 { DC_VENDORID_DEC, DC_DEVICEID_21143, 152 "Intel 21143 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 154 "Davicom DM9009 10/100BaseTX" }, 155 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 156 "Davicom DM9100 10/100BaseTX" }, 157 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 158 "Davicom DM9102 10/100BaseTX" }, 159 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 160 "Davicom DM9102A 10/100BaseTX" }, 161 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 162 "ADMtek AL981 10/100BaseTX" }, 163 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 164 "ADMtek AN985 10/100BaseTX" }, 165 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 166 "ADMtek ADM9511 10/100BaseTX" }, 167 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 168 "ADMtek ADM9513 10/100BaseTX" }, 169 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 170 "Netgear FA511 10/100BaseTX" }, 171 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 172 "ASIX AX88140A 10/100BaseTX" }, 173 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 174 "ASIX AX88141 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_98713, 176 "Macronix 98713 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98713, 178 "Macronix 98713A 10/100BaseTX" }, 179 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 180 "Compex RL100-TX 10/100BaseTX" }, 181 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 182 "Compex RL100-TX 10/100BaseTX" }, 183 { DC_VENDORID_MX, DC_DEVICEID_987x5, 184 "Macronix 98715/98715A 10/100BaseTX" }, 185 { DC_VENDORID_MX, DC_DEVICEID_987x5, 186 "Macronix 98715AEC-C 10/100BaseTX" }, 187 { DC_VENDORID_MX, DC_DEVICEID_987x5, 188 "Macronix 98725 10/100BaseTX" }, 189 { DC_VENDORID_MX, DC_DEVICEID_98727, 190 "Macronix 98727/98732 10/100BaseTX" }, 191 { DC_VENDORID_LO, DC_DEVICEID_82C115, 192 "LC82C115 PNIC II 10/100BaseTX" }, 193 { DC_VENDORID_LO, DC_DEVICEID_82C168, 194 "82c168 PNIC 10/100BaseTX" }, 195 { DC_VENDORID_LO, DC_DEVICEID_82C168, 196 "82c169 PNIC 10/100BaseTX" }, 197 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 198 "Accton EN1217 10/100BaseTX" }, 199 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 200 "Accton EN2242 MiniPCI 10/100BaseTX" }, 201 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 202 "Xircom X3201 10/100BaseTX" }, 203 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 204 "Abocom FE2500 10/100BaseTX" }, 205 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500MX, 206 "Abocom FE2500MX 10/100BaseTX" }, 207 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 208 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 209 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 210 "Hawking CB102 CardBus 10/100" }, 211 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 212 "PlaneX FNW-3602-T CardBus 10/100" }, 213 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 214 "3Com OfficeConnect 10/100B" }, 215 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 216 "Microsoft MN-120 CardBus 10/100" }, 217 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 218 "Microsoft MN-130 10/100" }, 219 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 220 "Microsoft MN-130 10/100" }, 221 { 0, 0, NULL } 222}; 223 224static int dc_probe (device_t); 225static int dc_attach (device_t); 226static int dc_detach (device_t); 227static int dc_suspend (device_t); 228static int dc_resume (device_t); 229static struct dc_type *dc_devtype (device_t); 230static int dc_newbuf (struct dc_softc *, int, int); 231static int dc_encap (struct dc_softc *, struct mbuf **); 232static void dc_pnic_rx_bug_war (struct dc_softc *, int); 233static int dc_rx_resync (struct dc_softc *); 234static void dc_rxeof (struct dc_softc *); 235static void dc_txeof (struct dc_softc *); 236static void dc_tick (void *); 237static void dc_tx_underrun (struct dc_softc *); 238static void dc_intr (void *); 239static void dc_start (struct ifnet *); 240static int dc_ioctl (struct ifnet *, u_long, caddr_t); 241static void dc_init (void *); 242static void dc_stop (struct dc_softc *); 243static void dc_watchdog (struct ifnet *); 244static void dc_shutdown (device_t); 245static int dc_ifmedia_upd (struct ifnet *); 246static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 247 248static void dc_delay (struct dc_softc *); 249static void dc_eeprom_idle (struct dc_softc *); 250static void dc_eeprom_putbyte (struct dc_softc *, int); 251static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 252static void dc_eeprom_getword_pnic 253 (struct dc_softc *, int, u_int16_t *); 254static void dc_eeprom_getword_xircom 255 (struct dc_softc *, int, u_int16_t *); 256static void dc_eeprom_width (struct dc_softc *); 257static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 258 259static void dc_mii_writebit (struct dc_softc *, int); 260static int dc_mii_readbit (struct dc_softc *); 261static void dc_mii_sync (struct dc_softc *); 262static void dc_mii_send (struct dc_softc *, u_int32_t, int); 263static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 264static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 265static int dc_miibus_readreg (device_t, int, int); 266static int dc_miibus_writereg (device_t, int, int, int); 267static void dc_miibus_statchg (device_t); 268static void dc_miibus_mediainit (device_t); 269 270static void dc_setcfg (struct dc_softc *, int); 271static uint32_t dc_mchash_le (struct dc_softc *, const uint8_t *); 272static uint32_t dc_mchash_be (const uint8_t *); 273static void dc_setfilt_21143 (struct dc_softc *); 274static void dc_setfilt_asix (struct dc_softc *); 275static void dc_setfilt_admtek (struct dc_softc *); 276static void dc_setfilt_xircom (struct dc_softc *); 277 278static void dc_setfilt (struct dc_softc *); 279 280static void dc_reset (struct dc_softc *); 281static int dc_list_rx_init (struct dc_softc *); 282static int dc_list_tx_init (struct dc_softc *); 283 284static void dc_read_srom (struct dc_softc *, int); 285static void dc_parse_21143_srom (struct dc_softc *); 286static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 287static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 288static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 289static void dc_apply_fixup (struct dc_softc *, int); 290 291static void dc_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 292 int); 293static void dc_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 294 int); 295 296#ifdef DC_USEIOSPACE 297#define DC_RES SYS_RES_IOPORT 298#define DC_RID DC_PCI_CFBIO 299#else 300#define DC_RES SYS_RES_MEMORY 301#define DC_RID DC_PCI_CFBMA 302#endif 303 304static device_method_t dc_methods[] = { 305 /* Device interface */ 306 DEVMETHOD(device_probe, dc_probe), 307 DEVMETHOD(device_attach, dc_attach), 308 DEVMETHOD(device_detach, dc_detach), 309 DEVMETHOD(device_suspend, dc_suspend), 310 DEVMETHOD(device_resume, dc_resume), 311 DEVMETHOD(device_shutdown, dc_shutdown), 312 313 /* bus interface */ 314 DEVMETHOD(bus_print_child, bus_generic_print_child), 315 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 316 317 /* MII interface */ 318 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 319 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 320 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 321 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 322 323 { 0, 0 } 324}; 325 326static driver_t dc_driver = { 327 "dc", 328 dc_methods, 329 sizeof(struct dc_softc) 330}; 331 332static devclass_t dc_devclass; 333#ifdef __i386__ 334static int dc_quick = 1; 335SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 336 "do not m_devget() in dc driver"); 337#endif 338 339DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 340DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 341DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 342 343#define DC_SETBIT(sc, reg, x) \ 344 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 345 346#define DC_CLRBIT(sc, reg, x) \ 347 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 348 349#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 350#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 351 352#define IS_MPSAFE 0 353 354static void 355dc_delay(struct dc_softc *sc) 356{ 357 int idx; 358 359 for (idx = (300 / 33) + 1; idx > 0; idx--) 360 CSR_READ_4(sc, DC_BUSCTL); 361} 362 363static void 364dc_eeprom_width(struct dc_softc *sc) 365{ 366 int i; 367 368 /* Force EEPROM to idle state. */ 369 dc_eeprom_idle(sc); 370 371 /* Enter EEPROM access mode. */ 372 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 373 dc_delay(sc); 374 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 375 dc_delay(sc); 376 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 377 dc_delay(sc); 378 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 379 dc_delay(sc); 380 381 for (i = 3; i--;) { 382 if (6 & (1 << i)) 383 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 384 else 385 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 386 dc_delay(sc); 387 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 388 dc_delay(sc); 389 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 390 dc_delay(sc); 391 } 392 393 for (i = 1; i <= 12; i++) { 394 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 break; 400 } 401 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 402 dc_delay(sc); 403 } 404 405 /* Turn off EEPROM access mode. */ 406 dc_eeprom_idle(sc); 407 408 if (i < 4 || i > 12) 409 sc->dc_romwidth = 6; 410 else 411 sc->dc_romwidth = i; 412 413 /* Enter EEPROM access mode. */ 414 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 415 dc_delay(sc); 416 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 417 dc_delay(sc); 418 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 419 dc_delay(sc); 420 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 421 dc_delay(sc); 422 423 /* Turn off EEPROM access mode. */ 424 dc_eeprom_idle(sc); 425} 426 427static void 428dc_eeprom_idle(struct dc_softc *sc) 429{ 430 int i; 431 432 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 433 dc_delay(sc); 434 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 435 dc_delay(sc); 436 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 437 dc_delay(sc); 438 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 439 dc_delay(sc); 440 441 for (i = 0; i < 25; i++) { 442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 443 dc_delay(sc); 444 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 } 447 448 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 449 dc_delay(sc); 450 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 451 dc_delay(sc); 452 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 453} 454 455/* 456 * Send a read command and address to the EEPROM, check for ACK. 457 */ 458static void 459dc_eeprom_putbyte(struct dc_softc *sc, int addr) 460{ 461 int d, i; 462 463 d = DC_EECMD_READ >> 6; 464 for (i = 3; i--; ) { 465 if (d & (1 << i)) 466 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 467 else 468 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 469 dc_delay(sc); 470 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 471 dc_delay(sc); 472 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 473 dc_delay(sc); 474 } 475 476 /* 477 * Feed in each bit and strobe the clock. 478 */ 479 for (i = sc->dc_romwidth; i--;) { 480 if (addr & (1 << i)) { 481 SIO_SET(DC_SIO_EE_DATAIN); 482 } else { 483 SIO_CLR(DC_SIO_EE_DATAIN); 484 } 485 dc_delay(sc); 486 SIO_SET(DC_SIO_EE_CLK); 487 dc_delay(sc); 488 SIO_CLR(DC_SIO_EE_CLK); 489 dc_delay(sc); 490 } 491} 492 493/* 494 * Read a word of data stored in the EEPROM at address 'addr.' 495 * The PNIC 82c168/82c169 has its own non-standard way to read 496 * the EEPROM. 497 */ 498static void 499dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 500{ 501 int i; 502 u_int32_t r; 503 504 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 505 506 for (i = 0; i < DC_TIMEOUT; i++) { 507 DELAY(1); 508 r = CSR_READ_4(sc, DC_SIO); 509 if (!(r & DC_PN_SIOCTL_BUSY)) { 510 *dest = (u_int16_t)(r & 0xFFFF); 511 return; 512 } 513 } 514} 515 516/* 517 * Read a word of data stored in the EEPROM at address 'addr.' 518 * The Xircom X3201 has its own non-standard way to read 519 * the EEPROM, too. 520 */ 521static void 522dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 523{ 524 525 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 526 527 addr *= 2; 528 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 529 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 530 addr += 1; 531 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 532 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 533 534 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 535} 536 537/* 538 * Read a word of data stored in the EEPROM at address 'addr.' 539 */ 540static void 541dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 542{ 543 int i; 544 u_int16_t word = 0; 545 546 /* Force EEPROM to idle state. */ 547 dc_eeprom_idle(sc); 548 549 /* Enter EEPROM access mode. */ 550 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 551 dc_delay(sc); 552 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 553 dc_delay(sc); 554 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 555 dc_delay(sc); 556 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 557 dc_delay(sc); 558 559 /* 560 * Send address of word we want to read. 561 */ 562 dc_eeprom_putbyte(sc, addr); 563 564 /* 565 * Start reading bits from EEPROM. 566 */ 567 for (i = 0x8000; i; i >>= 1) { 568 SIO_SET(DC_SIO_EE_CLK); 569 dc_delay(sc); 570 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 571 word |= i; 572 dc_delay(sc); 573 SIO_CLR(DC_SIO_EE_CLK); 574 dc_delay(sc); 575 } 576 577 /* Turn off EEPROM access mode. */ 578 dc_eeprom_idle(sc); 579 580 *dest = word; 581} 582 583/* 584 * Read a sequence of words from the EEPROM. 585 */ 586static void 587dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int be) 588{ 589 int i; 590 u_int16_t word = 0, *ptr; 591 592 for (i = 0; i < cnt; i++) { 593 if (DC_IS_PNIC(sc)) 594 dc_eeprom_getword_pnic(sc, off + i, &word); 595 else if (DC_IS_XIRCOM(sc)) 596 dc_eeprom_getword_xircom(sc, off + i, &word); 597 else 598 dc_eeprom_getword(sc, off + i, &word); 599 ptr = (u_int16_t *)(dest + (i * 2)); 600 if (be) 601 *ptr = be16toh(word); 602 else 603 *ptr = le16toh(word); 604 } 605} 606 607/* 608 * The following two routines are taken from the Macronix 98713 609 * Application Notes pp.19-21. 610 */ 611/* 612 * Write a bit to the MII bus. 613 */ 614static void 615dc_mii_writebit(struct dc_softc *sc, int bit) 616{ 617 618 if (bit) 619 CSR_WRITE_4(sc, DC_SIO, 620 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 621 else 622 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 623 624 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 625 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 626} 627 628/* 629 * Read a bit from the MII bus. 630 */ 631static int 632dc_mii_readbit(struct dc_softc *sc) 633{ 634 635 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 636 CSR_READ_4(sc, DC_SIO); 637 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 638 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 639 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 640 return (1); 641 642 return (0); 643} 644 645/* 646 * Sync the PHYs by setting data bit and strobing the clock 32 times. 647 */ 648static void 649dc_mii_sync(struct dc_softc *sc) 650{ 651 int i; 652 653 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 654 655 for (i = 0; i < 32; i++) 656 dc_mii_writebit(sc, 1); 657} 658 659/* 660 * Clock a series of bits through the MII. 661 */ 662static void 663dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 664{ 665 int i; 666 667 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 668 dc_mii_writebit(sc, bits & i); 669} 670 671/* 672 * Read an PHY register through the MII. 673 */ 674static int 675dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 676{ 677 int i, ack; 678 679 DC_LOCK(sc); 680 681 /* 682 * Set up frame for RX. 683 */ 684 frame->mii_stdelim = DC_MII_STARTDELIM; 685 frame->mii_opcode = DC_MII_READOP; 686 frame->mii_turnaround = 0; 687 frame->mii_data = 0; 688 689 /* 690 * Sync the PHYs. 691 */ 692 dc_mii_sync(sc); 693 694 /* 695 * Send command/address info. 696 */ 697 dc_mii_send(sc, frame->mii_stdelim, 2); 698 dc_mii_send(sc, frame->mii_opcode, 2); 699 dc_mii_send(sc, frame->mii_phyaddr, 5); 700 dc_mii_send(sc, frame->mii_regaddr, 5); 701 702#ifdef notdef 703 /* Idle bit */ 704 dc_mii_writebit(sc, 1); 705 dc_mii_writebit(sc, 0); 706#endif 707 708 /* Check for ack. */ 709 ack = dc_mii_readbit(sc); 710 711 /* 712 * Now try reading data bits. If the ack failed, we still 713 * need to clock through 16 cycles to keep the PHY(s) in sync. 714 */ 715 if (ack) { 716 for (i = 0; i < 16; i++) 717 dc_mii_readbit(sc); 718 goto fail; 719 } 720 721 for (i = 0x8000; i; i >>= 1) { 722 if (!ack) { 723 if (dc_mii_readbit(sc)) 724 frame->mii_data |= i; 725 } 726 } 727 728fail: 729 730 dc_mii_writebit(sc, 0); 731 dc_mii_writebit(sc, 0); 732 733 DC_UNLOCK(sc); 734 735 if (ack) 736 return (1); 737 return (0); 738} 739 740/* 741 * Write to a PHY register through the MII. 742 */ 743static int 744dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 745{ 746 747 DC_LOCK(sc); 748 /* 749 * Set up frame for TX. 750 */ 751 752 frame->mii_stdelim = DC_MII_STARTDELIM; 753 frame->mii_opcode = DC_MII_WRITEOP; 754 frame->mii_turnaround = DC_MII_TURNAROUND; 755 756 /* 757 * Sync the PHYs. 758 */ 759 dc_mii_sync(sc); 760 761 dc_mii_send(sc, frame->mii_stdelim, 2); 762 dc_mii_send(sc, frame->mii_opcode, 2); 763 dc_mii_send(sc, frame->mii_phyaddr, 5); 764 dc_mii_send(sc, frame->mii_regaddr, 5); 765 dc_mii_send(sc, frame->mii_turnaround, 2); 766 dc_mii_send(sc, frame->mii_data, 16); 767 768 /* Idle bit. */ 769 dc_mii_writebit(sc, 0); 770 dc_mii_writebit(sc, 0); 771 772 DC_UNLOCK(sc); 773 774 return (0); 775} 776 777static int 778dc_miibus_readreg(device_t dev, int phy, int reg) 779{ 780 struct dc_mii_frame frame; 781 struct dc_softc *sc; 782 int i, rval, phy_reg = 0; 783 784 sc = device_get_softc(dev); 785 bzero(&frame, sizeof(frame)); 786 787 /* 788 * Note: both the AL981 and AN985 have internal PHYs, 789 * however the AL981 provides direct access to the PHY 790 * registers while the AN985 uses a serial MII interface. 791 * The AN985's MII interface is also buggy in that you 792 * can read from any MII address (0 to 31), but only address 1 793 * behaves normally. To deal with both cases, we pretend 794 * that the PHY is at MII address 1. 795 */ 796 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 797 return (0); 798 799 /* 800 * Note: the ukphy probes of the RS7112 report a PHY at 801 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 802 * so we only respond to correct one. 803 */ 804 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 805 return (0); 806 807 if (sc->dc_pmode != DC_PMODE_MII) { 808 if (phy == (MII_NPHY - 1)) { 809 switch (reg) { 810 case MII_BMSR: 811 /* 812 * Fake something to make the probe 813 * code think there's a PHY here. 814 */ 815 return (BMSR_MEDIAMASK); 816 break; 817 case MII_PHYIDR1: 818 if (DC_IS_PNIC(sc)) 819 return (DC_VENDORID_LO); 820 return (DC_VENDORID_DEC); 821 break; 822 case MII_PHYIDR2: 823 if (DC_IS_PNIC(sc)) 824 return (DC_DEVICEID_82C168); 825 return (DC_DEVICEID_21143); 826 break; 827 default: 828 return (0); 829 break; 830 } 831 } else 832 return (0); 833 } 834 835 if (DC_IS_PNIC(sc)) { 836 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 837 (phy << 23) | (reg << 18)); 838 for (i = 0; i < DC_TIMEOUT; i++) { 839 DELAY(1); 840 rval = CSR_READ_4(sc, DC_PN_MII); 841 if (!(rval & DC_PN_MII_BUSY)) { 842 rval &= 0xFFFF; 843 return (rval == 0xFFFF ? 0 : rval); 844 } 845 } 846 return (0); 847 } 848 849 if (DC_IS_COMET(sc)) { 850 switch (reg) { 851 case MII_BMCR: 852 phy_reg = DC_AL_BMCR; 853 break; 854 case MII_BMSR: 855 phy_reg = DC_AL_BMSR; 856 break; 857 case MII_PHYIDR1: 858 phy_reg = DC_AL_VENID; 859 break; 860 case MII_PHYIDR2: 861 phy_reg = DC_AL_DEVID; 862 break; 863 case MII_ANAR: 864 phy_reg = DC_AL_ANAR; 865 break; 866 case MII_ANLPAR: 867 phy_reg = DC_AL_LPAR; 868 break; 869 case MII_ANER: 870 phy_reg = DC_AL_ANER; 871 break; 872 default: 873 printf("dc%d: phy_read: bad phy register %x\n", 874 sc->dc_unit, reg); 875 return (0); 876 break; 877 } 878 879 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 880 881 if (rval == 0xFFFF) 882 return (0); 883 return (rval); 884 } 885 886 frame.mii_phyaddr = phy; 887 frame.mii_regaddr = reg; 888 if (sc->dc_type == DC_TYPE_98713) { 889 phy_reg = CSR_READ_4(sc, DC_NETCFG); 890 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 891 } 892 dc_mii_readreg(sc, &frame); 893 if (sc->dc_type == DC_TYPE_98713) 894 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 895 896 return (frame.mii_data); 897} 898 899static int 900dc_miibus_writereg(device_t dev, int phy, int reg, int data) 901{ 902 struct dc_softc *sc; 903 struct dc_mii_frame frame; 904 int i, phy_reg = 0; 905 906 sc = device_get_softc(dev); 907 bzero(&frame, sizeof(frame)); 908 909 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 910 return (0); 911 912 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 913 return (0); 914 915 if (DC_IS_PNIC(sc)) { 916 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 917 (phy << 23) | (reg << 10) | data); 918 for (i = 0; i < DC_TIMEOUT; i++) { 919 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 920 break; 921 } 922 return (0); 923 } 924 925 if (DC_IS_COMET(sc)) { 926 switch (reg) { 927 case MII_BMCR: 928 phy_reg = DC_AL_BMCR; 929 break; 930 case MII_BMSR: 931 phy_reg = DC_AL_BMSR; 932 break; 933 case MII_PHYIDR1: 934 phy_reg = DC_AL_VENID; 935 break; 936 case MII_PHYIDR2: 937 phy_reg = DC_AL_DEVID; 938 break; 939 case MII_ANAR: 940 phy_reg = DC_AL_ANAR; 941 break; 942 case MII_ANLPAR: 943 phy_reg = DC_AL_LPAR; 944 break; 945 case MII_ANER: 946 phy_reg = DC_AL_ANER; 947 break; 948 default: 949 printf("dc%d: phy_write: bad phy register %x\n", 950 sc->dc_unit, reg); 951 return (0); 952 break; 953 } 954 955 CSR_WRITE_4(sc, phy_reg, data); 956 return (0); 957 } 958 959 frame.mii_phyaddr = phy; 960 frame.mii_regaddr = reg; 961 frame.mii_data = data; 962 963 if (sc->dc_type == DC_TYPE_98713) { 964 phy_reg = CSR_READ_4(sc, DC_NETCFG); 965 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 966 } 967 dc_mii_writereg(sc, &frame); 968 if (sc->dc_type == DC_TYPE_98713) 969 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 970 971 return (0); 972} 973 974static void 975dc_miibus_statchg(device_t dev) 976{ 977 struct dc_softc *sc; 978 struct mii_data *mii; 979 struct ifmedia *ifm; 980 981 sc = device_get_softc(dev); 982 if (DC_IS_ADMTEK(sc)) 983 return; 984 985 mii = device_get_softc(sc->dc_miibus); 986 ifm = &mii->mii_media; 987 if (DC_IS_DAVICOM(sc) && 988 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 989 dc_setcfg(sc, ifm->ifm_media); 990 sc->dc_if_media = ifm->ifm_media; 991 } else { 992 dc_setcfg(sc, mii->mii_media_active); 993 sc->dc_if_media = mii->mii_media_active; 994 } 995} 996 997/* 998 * Special support for DM9102A cards with HomePNA PHYs. Note: 999 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1000 * to be impossible to talk to the management interface of the DM9801 1001 * PHY (its MDIO pin is not connected to anything). Consequently, 1002 * the driver has to just 'know' about the additional mode and deal 1003 * with it itself. *sigh* 1004 */ 1005static void 1006dc_miibus_mediainit(device_t dev) 1007{ 1008 struct dc_softc *sc; 1009 struct mii_data *mii; 1010 struct ifmedia *ifm; 1011 int rev; 1012 1013 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1014 1015 sc = device_get_softc(dev); 1016 mii = device_get_softc(sc->dc_miibus); 1017 ifm = &mii->mii_media; 1018 1019 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1020 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1021} 1022 1023#define DC_BITS_512 9 1024#define DC_BITS_128 7 1025#define DC_BITS_64 6 1026 1027static uint32_t 1028dc_mchash_le(struct dc_softc *sc, const uint8_t *addr) 1029{ 1030 uint32_t crc; 1031 1032 /* Compute CRC for the address value. */ 1033 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1034 1035 /* 1036 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1037 * chips is only 128 bits wide. 1038 */ 1039 if (sc->dc_flags & DC_128BIT_HASH) 1040 return (crc & ((1 << DC_BITS_128) - 1)); 1041 1042 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1043 if (sc->dc_flags & DC_64BIT_HASH) 1044 return (crc & ((1 << DC_BITS_64) - 1)); 1045 1046 /* Xircom's hash filtering table is different (read: weird) */ 1047 /* Xircom uses the LEAST significant bits */ 1048 if (DC_IS_XIRCOM(sc)) { 1049 if ((crc & 0x180) == 0x180) 1050 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1051 else 1052 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1053 (12 << 4)); 1054 } 1055 1056 return (crc & ((1 << DC_BITS_512) - 1)); 1057} 1058 1059/* 1060 * Calculate CRC of a multicast group address, return the lower 6 bits. 1061 */ 1062static uint32_t 1063dc_mchash_be(const uint8_t *addr) 1064{ 1065 uint32_t crc; 1066 1067 /* Compute CRC for the address value. */ 1068 crc = ether_crc32_be(addr, ETHER_ADDR_LEN); 1069 1070 /* Return the filter bit position. */ 1071 return ((crc >> 26) & 0x0000003F); 1072} 1073 1074/* 1075 * 21143-style RX filter setup routine. Filter programming is done by 1076 * downloading a special setup frame into the TX engine. 21143, Macronix, 1077 * PNIC, PNIC II and Davicom chips are programmed this way. 1078 * 1079 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1080 * address (our node address) and a 512-bit hash filter for multicast 1081 * frames. We also sneak the broadcast address into the hash filter since 1082 * we need that too. 1083 */ 1084static void 1085dc_setfilt_21143(struct dc_softc *sc) 1086{ 1087 struct dc_desc *sframe; 1088 u_int32_t h, *sp; 1089 struct ifmultiaddr *ifma; 1090 struct ifnet *ifp; 1091 int i; 1092 1093 ifp = &sc->arpcom.ac_if; 1094 1095 i = sc->dc_cdata.dc_tx_prod; 1096 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1097 sc->dc_cdata.dc_tx_cnt++; 1098 sframe = &sc->dc_ldata->dc_tx_list[i]; 1099 sp = sc->dc_cdata.dc_sbuf; 1100 bzero(sp, DC_SFRAME_LEN); 1101 1102 sframe->dc_data = htole32(sc->dc_saddr); 1103 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1104 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1105 1106 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1107 1108 /* If we want promiscuous mode, set the allframes bit. */ 1109 if (ifp->if_flags & IFF_PROMISC) 1110 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1111 else 1112 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1113 1114 if (ifp->if_flags & IFF_ALLMULTI) 1115 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1116 else 1117 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1118 1119 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1120 if (ifma->ifma_addr->sa_family != AF_LINK) 1121 continue; 1122 h = dc_mchash_le(sc, 1123 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1124 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1125 } 1126 1127 if (ifp->if_flags & IFF_BROADCAST) { 1128 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1129 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1130 } 1131 1132 /* Set our MAC address */ 1133 sp[39] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1134 sp[40] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1135 sp[41] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1136 1137 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1138 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1139 1140 /* 1141 * The PNIC takes an exceedingly long time to process its 1142 * setup frame; wait 10ms after posting the setup frame 1143 * before proceeding, just so it has time to swallow its 1144 * medicine. 1145 */ 1146 DELAY(10000); 1147 1148 ifp->if_timer = 5; 1149} 1150 1151static void 1152dc_setfilt_admtek(struct dc_softc *sc) 1153{ 1154 struct ifnet *ifp; 1155 struct ifmultiaddr *ifma; 1156 int h = 0; 1157 u_int32_t hashes[2] = { 0, 0 }; 1158 1159 ifp = &sc->arpcom.ac_if; 1160 1161 /* Init our MAC address. */ 1162 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1163 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1164 1165 /* If we want promiscuous mode, set the allframes bit. */ 1166 if (ifp->if_flags & IFF_PROMISC) 1167 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1168 else 1169 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1170 1171 if (ifp->if_flags & IFF_ALLMULTI) 1172 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1173 else 1174 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1175 1176 /* First, zot all the existing hash bits. */ 1177 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1178 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1179 1180 /* 1181 * If we're already in promisc or allmulti mode, we 1182 * don't have to bother programming the multicast filter. 1183 */ 1184 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1185 return; 1186 1187 /* Now program new ones. */ 1188 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1189 if (ifma->ifma_addr->sa_family != AF_LINK) 1190 continue; 1191 if (DC_IS_CENTAUR(sc)) 1192 h = dc_mchash_le(sc, 1193 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1194 else 1195 h = dc_mchash_be( 1196 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1197 if (h < 32) 1198 hashes[0] |= (1 << h); 1199 else 1200 hashes[1] |= (1 << (h - 32)); 1201 } 1202 1203 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1204 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1205} 1206 1207static void 1208dc_setfilt_asix(struct dc_softc *sc) 1209{ 1210 struct ifnet *ifp; 1211 struct ifmultiaddr *ifma; 1212 int h = 0; 1213 u_int32_t hashes[2] = { 0, 0 }; 1214 1215 ifp = &sc->arpcom.ac_if; 1216 1217 /* Init our MAC address */ 1218 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1219 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1220 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1221 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1222 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1223 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1224 1225 /* If we want promiscuous mode, set the allframes bit. */ 1226 if (ifp->if_flags & IFF_PROMISC) 1227 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1228 else 1229 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1230 1231 if (ifp->if_flags & IFF_ALLMULTI) 1232 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1233 else 1234 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1235 1236 /* 1237 * The ASIX chip has a special bit to enable reception 1238 * of broadcast frames. 1239 */ 1240 if (ifp->if_flags & IFF_BROADCAST) 1241 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1242 else 1243 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1244 1245 /* first, zot all the existing hash bits */ 1246 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1247 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1248 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1249 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1250 1251 /* 1252 * If we're already in promisc or allmulti mode, we 1253 * don't have to bother programming the multicast filter. 1254 */ 1255 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1256 return; 1257 1258 /* now program new ones */ 1259 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1260 if (ifma->ifma_addr->sa_family != AF_LINK) 1261 continue; 1262 h = dc_mchash_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1263 if (h < 32) 1264 hashes[0] |= (1 << h); 1265 else 1266 hashes[1] |= (1 << (h - 32)); 1267 } 1268 1269 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1270 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1271 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1272 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1273} 1274 1275static void 1276dc_setfilt_xircom(struct dc_softc *sc) 1277{ 1278 struct ifnet *ifp; 1279 struct ifmultiaddr *ifma; 1280 struct dc_desc *sframe; 1281 u_int32_t h, *sp; 1282 int i; 1283 1284 ifp = &sc->arpcom.ac_if; 1285 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1286 1287 i = sc->dc_cdata.dc_tx_prod; 1288 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1289 sc->dc_cdata.dc_tx_cnt++; 1290 sframe = &sc->dc_ldata->dc_tx_list[i]; 1291 sp = sc->dc_cdata.dc_sbuf; 1292 bzero(sp, DC_SFRAME_LEN); 1293 1294 sframe->dc_data = htole32(sc->dc_saddr); 1295 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1296 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1297 1298 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1299 1300 /* If we want promiscuous mode, set the allframes bit. */ 1301 if (ifp->if_flags & IFF_PROMISC) 1302 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1303 else 1304 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1305 1306 if (ifp->if_flags & IFF_ALLMULTI) 1307 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1308 else 1309 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1310 1311 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1312 if (ifma->ifma_addr->sa_family != AF_LINK) 1313 continue; 1314 h = dc_mchash_le(sc, 1315 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1316 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1317 } 1318 1319 if (ifp->if_flags & IFF_BROADCAST) { 1320 h = dc_mchash_le(sc, ifp->if_broadcastaddr); 1321 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1322 } 1323 1324 /* Set our MAC address */ 1325 sp[0] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1326 sp[1] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1327 sp[2] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1328 1329 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1330 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1331 ifp->if_flags |= IFF_RUNNING; 1332 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1333 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1334 1335 /* 1336 * Wait some time... 1337 */ 1338 DELAY(1000); 1339 1340 ifp->if_timer = 5; 1341} 1342 1343static void 1344dc_setfilt(struct dc_softc *sc) 1345{ 1346 1347 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1348 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1349 dc_setfilt_21143(sc); 1350 1351 if (DC_IS_ASIX(sc)) 1352 dc_setfilt_asix(sc); 1353 1354 if (DC_IS_ADMTEK(sc)) 1355 dc_setfilt_admtek(sc); 1356 1357 if (DC_IS_XIRCOM(sc)) 1358 dc_setfilt_xircom(sc); 1359} 1360 1361/* 1362 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1363 * the netconfig register, we first have to put the transmit and/or 1364 * receive logic in the idle state. 1365 */ 1366static void 1367dc_setcfg(struct dc_softc *sc, int media) 1368{ 1369 int i, restart = 0, watchdogreg; 1370 u_int32_t isr; 1371 1372 if (IFM_SUBTYPE(media) == IFM_NONE) 1373 return; 1374 1375 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1376 restart = 1; 1377 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1378 1379 for (i = 0; i < DC_TIMEOUT; i++) { 1380 isr = CSR_READ_4(sc, DC_ISR); 1381 if (isr & DC_ISR_TX_IDLE && 1382 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1383 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1384 break; 1385 DELAY(10); 1386 } 1387 1388 if (i == DC_TIMEOUT) 1389 printf("dc%d: failed to force tx and " 1390 "rx to idle state\n", sc->dc_unit); 1391 } 1392 1393 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1394 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1395 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1396 if (sc->dc_pmode == DC_PMODE_MII) { 1397 if (DC_IS_INTEL(sc)) { 1398 /* There's a write enable bit here that reads as 1. */ 1399 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1400 watchdogreg &= ~DC_WDOG_CTLWREN; 1401 watchdogreg |= DC_WDOG_JABBERDIS; 1402 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1403 } else { 1404 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1405 } 1406 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1407 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1408 if (sc->dc_type == DC_TYPE_98713) 1409 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1410 DC_NETCFG_SCRAMBLER)); 1411 if (!DC_IS_DAVICOM(sc)) 1412 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1413 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1414 if (DC_IS_INTEL(sc)) 1415 dc_apply_fixup(sc, IFM_AUTO); 1416 } else { 1417 if (DC_IS_PNIC(sc)) { 1418 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1419 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1420 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1421 } 1422 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1423 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1424 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1425 if (DC_IS_INTEL(sc)) 1426 dc_apply_fixup(sc, 1427 (media & IFM_GMASK) == IFM_FDX ? 1428 IFM_100_TX | IFM_FDX : IFM_100_TX); 1429 } 1430 } 1431 1432 if (IFM_SUBTYPE(media) == IFM_10_T) { 1433 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1434 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1435 if (sc->dc_pmode == DC_PMODE_MII) { 1436 /* There's a write enable bit here that reads as 1. */ 1437 if (DC_IS_INTEL(sc)) { 1438 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1439 watchdogreg &= ~DC_WDOG_CTLWREN; 1440 watchdogreg |= DC_WDOG_JABBERDIS; 1441 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1442 } else { 1443 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1444 } 1445 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1446 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1447 if (sc->dc_type == DC_TYPE_98713) 1448 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1449 if (!DC_IS_DAVICOM(sc)) 1450 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1451 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1452 if (DC_IS_INTEL(sc)) 1453 dc_apply_fixup(sc, IFM_AUTO); 1454 } else { 1455 if (DC_IS_PNIC(sc)) { 1456 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1457 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1458 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1459 } 1460 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1461 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1462 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1463 if (DC_IS_INTEL(sc)) { 1464 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1465 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1466 if ((media & IFM_GMASK) == IFM_FDX) 1467 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1468 else 1469 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1470 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1471 DC_CLRBIT(sc, DC_10BTCTRL, 1472 DC_TCTL_AUTONEGENBL); 1473 dc_apply_fixup(sc, 1474 (media & IFM_GMASK) == IFM_FDX ? 1475 IFM_10_T | IFM_FDX : IFM_10_T); 1476 DELAY(20000); 1477 } 1478 } 1479 } 1480 1481 /* 1482 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1483 * PHY and we want HomePNA mode, set the portsel bit to turn 1484 * on the external MII port. 1485 */ 1486 if (DC_IS_DAVICOM(sc)) { 1487 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1488 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1489 sc->dc_link = 1; 1490 } else { 1491 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1492 } 1493 } 1494 1495 if ((media & IFM_GMASK) == IFM_FDX) { 1496 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1497 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1498 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1499 } else { 1500 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1501 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1502 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1503 } 1504 1505 if (restart) 1506 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1507} 1508 1509static void 1510dc_reset(struct dc_softc *sc) 1511{ 1512 int i; 1513 1514 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1515 1516 for (i = 0; i < DC_TIMEOUT; i++) { 1517 DELAY(10); 1518 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1519 break; 1520 } 1521 1522 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1523 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1524 DELAY(10000); 1525 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1526 i = 0; 1527 } 1528 1529 if (i == DC_TIMEOUT) 1530 printf("dc%d: reset never completed!\n", sc->dc_unit); 1531 1532 /* Wait a little while for the chip to get its brains in order. */ 1533 DELAY(1000); 1534 1535 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1536 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1537 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1538 1539 /* 1540 * Bring the SIA out of reset. In some cases, it looks 1541 * like failing to unreset the SIA soon enough gets it 1542 * into a state where it will never come out of reset 1543 * until we reset the whole chip again. 1544 */ 1545 if (DC_IS_INTEL(sc)) { 1546 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1547 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1548 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1549 } 1550} 1551 1552static struct dc_type * 1553dc_devtype(device_t dev) 1554{ 1555 struct dc_type *t; 1556 u_int32_t rev; 1557 1558 t = dc_devs; 1559 1560 while (t->dc_name != NULL) { 1561 if ((pci_get_vendor(dev) == t->dc_vid) && 1562 (pci_get_device(dev) == t->dc_did)) { 1563 /* Check the PCI revision */ 1564 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1565 if (t->dc_did == DC_DEVICEID_98713 && 1566 rev >= DC_REVISION_98713A) 1567 t++; 1568 if (t->dc_did == DC_DEVICEID_98713_CP && 1569 rev >= DC_REVISION_98713A) 1570 t++; 1571 if (t->dc_did == DC_DEVICEID_987x5 && 1572 rev >= DC_REVISION_98715AEC_C) 1573 t++; 1574 if (t->dc_did == DC_DEVICEID_987x5 && 1575 rev >= DC_REVISION_98725) 1576 t++; 1577 if (t->dc_did == DC_DEVICEID_AX88140A && 1578 rev >= DC_REVISION_88141) 1579 t++; 1580 if (t->dc_did == DC_DEVICEID_82C168 && 1581 rev >= DC_REVISION_82C169) 1582 t++; 1583 if (t->dc_did == DC_DEVICEID_DM9102 && 1584 rev >= DC_REVISION_DM9102A) 1585 t++; 1586 /* 1587 * The Microsoft MN-130 has a device ID of 0x0002, 1588 * which happens to be the same as the PNIC 82c168. 1589 * To keep dc_attach() from getting confused, we 1590 * pretend its ID is something different. 1591 * XXX: ideally, dc_attach() should be checking 1592 * vendorid+deviceid together to avoid such 1593 * collisions. 1594 */ 1595 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1596 t->dc_did == DC_DEVICEID_MSMN130) 1597 t++; 1598 return (t); 1599 } 1600 t++; 1601 } 1602 1603 return (NULL); 1604} 1605 1606/* 1607 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1608 * IDs against our list and return a device name if we find a match. 1609 * We do a little bit of extra work to identify the exact type of 1610 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1611 * but different revision IDs. The same is true for 98715/98715A 1612 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1613 * cases, the exact chip revision affects driver behavior. 1614 */ 1615static int 1616dc_probe(device_t dev) 1617{ 1618 struct dc_type *t; 1619 1620 t = dc_devtype(dev); 1621 1622 if (t != NULL) { 1623 device_set_desc(dev, t->dc_name); 1624 return (BUS_PROBE_DEFAULT); 1625 } 1626 1627 return (ENXIO); 1628} 1629 1630static void 1631dc_apply_fixup(struct dc_softc *sc, int media) 1632{ 1633 struct dc_mediainfo *m; 1634 u_int8_t *p; 1635 int i; 1636 u_int32_t reg; 1637 1638 m = sc->dc_mi; 1639 1640 while (m != NULL) { 1641 if (m->dc_media == media) 1642 break; 1643 m = m->dc_next; 1644 } 1645 1646 if (m == NULL) 1647 return; 1648 1649 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1650 reg = (p[0] | (p[1] << 8)) << 16; 1651 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1652 } 1653 1654 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1655 reg = (p[0] | (p[1] << 8)) << 16; 1656 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1657 } 1658} 1659 1660static void 1661dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1662{ 1663 struct dc_mediainfo *m; 1664 1665 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1666 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1667 case DC_SIA_CODE_10BT: 1668 m->dc_media = IFM_10_T; 1669 break; 1670 case DC_SIA_CODE_10BT_FDX: 1671 m->dc_media = IFM_10_T | IFM_FDX; 1672 break; 1673 case DC_SIA_CODE_10B2: 1674 m->dc_media = IFM_10_2; 1675 break; 1676 case DC_SIA_CODE_10B5: 1677 m->dc_media = IFM_10_5; 1678 break; 1679 default: 1680 break; 1681 } 1682 1683 /* 1684 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1685 * Things apparently already work for cards that do 1686 * supply Media Specific Data. 1687 */ 1688 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1689 m->dc_gp_len = 2; 1690 m->dc_gp_ptr = 1691 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1692 } else { 1693 m->dc_gp_len = 2; 1694 m->dc_gp_ptr = 1695 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1696 } 1697 1698 m->dc_next = sc->dc_mi; 1699 sc->dc_mi = m; 1700 1701 sc->dc_pmode = DC_PMODE_SIA; 1702} 1703 1704static void 1705dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1706{ 1707 struct dc_mediainfo *m; 1708 1709 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1710 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1711 m->dc_media = IFM_100_TX; 1712 1713 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1714 m->dc_media = IFM_100_TX | IFM_FDX; 1715 1716 m->dc_gp_len = 2; 1717 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1718 1719 m->dc_next = sc->dc_mi; 1720 sc->dc_mi = m; 1721 1722 sc->dc_pmode = DC_PMODE_SYM; 1723} 1724 1725static void 1726dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1727{ 1728 struct dc_mediainfo *m; 1729 u_int8_t *p; 1730 1731 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1732 /* We abuse IFM_AUTO to represent MII. */ 1733 m->dc_media = IFM_AUTO; 1734 m->dc_gp_len = l->dc_gpr_len; 1735 1736 p = (u_int8_t *)l; 1737 p += sizeof(struct dc_eblock_mii); 1738 m->dc_gp_ptr = p; 1739 p += 2 * l->dc_gpr_len; 1740 m->dc_reset_len = *p; 1741 p++; 1742 m->dc_reset_ptr = p; 1743 1744 m->dc_next = sc->dc_mi; 1745 sc->dc_mi = m; 1746} 1747 1748static void 1749dc_read_srom(struct dc_softc *sc, int bits) 1750{ 1751 int size; 1752 1753 size = 2 << bits; 1754 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1755 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1756} 1757 1758static void 1759dc_parse_21143_srom(struct dc_softc *sc) 1760{ 1761 struct dc_leaf_hdr *lhdr; 1762 struct dc_eblock_hdr *hdr; 1763 int have_mii, i, loff; 1764 char *ptr; 1765 1766 have_mii = 0; 1767 loff = sc->dc_srom[27]; 1768 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1769 1770 ptr = (char *)lhdr; 1771 ptr += sizeof(struct dc_leaf_hdr) - 1; 1772 /* 1773 * Look if we got a MII media block. 1774 */ 1775 for (i = 0; i < lhdr->dc_mcnt; i++) { 1776 hdr = (struct dc_eblock_hdr *)ptr; 1777 if (hdr->dc_type == DC_EBLOCK_MII) 1778 have_mii++; 1779 1780 ptr += (hdr->dc_len & 0x7F); 1781 ptr++; 1782 } 1783 1784 /* 1785 * Do the same thing again. Only use SIA and SYM media 1786 * blocks if no MII media block is available. 1787 */ 1788 ptr = (char *)lhdr; 1789 ptr += sizeof(struct dc_leaf_hdr) - 1; 1790 for (i = 0; i < lhdr->dc_mcnt; i++) { 1791 hdr = (struct dc_eblock_hdr *)ptr; 1792 switch (hdr->dc_type) { 1793 case DC_EBLOCK_MII: 1794 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1795 break; 1796 case DC_EBLOCK_SIA: 1797 if (! have_mii) 1798 dc_decode_leaf_sia(sc, 1799 (struct dc_eblock_sia *)hdr); 1800 break; 1801 case DC_EBLOCK_SYM: 1802 if (! have_mii) 1803 dc_decode_leaf_sym(sc, 1804 (struct dc_eblock_sym *)hdr); 1805 break; 1806 default: 1807 /* Don't care. Yet. */ 1808 break; 1809 } 1810 ptr += (hdr->dc_len & 0x7F); 1811 ptr++; 1812 } 1813} 1814 1815static void 1816dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1817{ 1818 u_int32_t *paddr; 1819 1820 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1821 paddr = arg; 1822 *paddr = segs->ds_addr; 1823} 1824 1825/* 1826 * Attach the interface. Allocate softc structures, do ifmedia 1827 * setup and ethernet/BPF attach. 1828 */ 1829static int 1830dc_attach(device_t dev) 1831{ 1832 int tmp = 0; 1833 u_char eaddr[ETHER_ADDR_LEN]; 1834 u_int32_t command; 1835 struct dc_softc *sc; 1836 struct ifnet *ifp; 1837 u_int32_t revision; 1838 int unit, error = 0, rid, mac_offset; 1839 int i; 1840 u_int8_t *mac; 1841 1842 sc = device_get_softc(dev); 1843 unit = device_get_unit(dev); 1844 1845 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1846 MTX_DEF | MTX_RECURSE); 1847 1848 /* 1849 * Map control/status registers. 1850 */ 1851 pci_enable_busmaster(dev); 1852 1853 rid = DC_RID; 1854 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1855 1856 if (sc->dc_res == NULL) { 1857 printf("dc%d: couldn't map ports/memory\n", unit); 1858 error = ENXIO; 1859 goto fail; 1860 } 1861 1862 sc->dc_btag = rman_get_bustag(sc->dc_res); 1863 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1864 1865 /* Allocate interrupt. */ 1866 rid = 0; 1867 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1868 RF_SHAREABLE | RF_ACTIVE); 1869 1870 if (sc->dc_irq == NULL) { 1871 printf("dc%d: couldn't map interrupt\n", unit); 1872 error = ENXIO; 1873 goto fail; 1874 } 1875 1876 /* Need this info to decide on a chip type. */ 1877 sc->dc_info = dc_devtype(dev); 1878 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1879 1880 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1881 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1882 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1883 dc_eeprom_width(sc); 1884 1885 switch (sc->dc_info->dc_did) { 1886 case DC_DEVICEID_21143: 1887 sc->dc_type = DC_TYPE_21143; 1888 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1889 sc->dc_flags |= DC_REDUCED_MII_POLL; 1890 /* Save EEPROM contents so we can parse them later. */ 1891 dc_read_srom(sc, sc->dc_romwidth); 1892 break; 1893 case DC_DEVICEID_DM9009: 1894 case DC_DEVICEID_DM9100: 1895 case DC_DEVICEID_DM9102: 1896 sc->dc_type = DC_TYPE_DM9102; 1897 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1898 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1899 sc->dc_flags |= DC_TX_ALIGN; 1900 sc->dc_pmode = DC_PMODE_MII; 1901 /* Increase the latency timer value. */ 1902 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1903 command &= 0xFFFF00FF; 1904 command |= 0x00008000; 1905 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1906 break; 1907 case DC_DEVICEID_AL981: 1908 sc->dc_type = DC_TYPE_AL981; 1909 sc->dc_flags |= DC_TX_USE_TX_INTR; 1910 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1911 sc->dc_pmode = DC_PMODE_MII; 1912 dc_read_srom(sc, sc->dc_romwidth); 1913 break; 1914 case DC_DEVICEID_AN985: 1915 case DC_DEVICEID_ADM9511: 1916 case DC_DEVICEID_ADM9513: 1917 case DC_DEVICEID_FA511: 1918 case DC_DEVICEID_FE2500: 1919 case DC_DEVICEID_EN2242: 1920 case DC_DEVICEID_HAWKING_PN672TX: 1921 case DC_DEVICEID_3CSOHOB: 1922 case DC_DEVICEID_MSMN120: 1923 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1924 sc->dc_type = DC_TYPE_AN985; 1925 sc->dc_flags |= DC_64BIT_HASH; 1926 sc->dc_flags |= DC_TX_USE_TX_INTR; 1927 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1928 sc->dc_pmode = DC_PMODE_MII; 1929 /* Don't read SROM for - auto-loaded on reset */ 1930 break; 1931 case DC_DEVICEID_98713: 1932 case DC_DEVICEID_98713_CP: 1933 if (revision < DC_REVISION_98713A) { 1934 sc->dc_type = DC_TYPE_98713; 1935 } 1936 if (revision >= DC_REVISION_98713A) { 1937 sc->dc_type = DC_TYPE_98713A; 1938 sc->dc_flags |= DC_21143_NWAY; 1939 } 1940 sc->dc_flags |= DC_REDUCED_MII_POLL; 1941 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1942 break; 1943 case DC_DEVICEID_987x5: 1944 case DC_DEVICEID_EN1217: 1945 /* 1946 * Macronix MX98715AEC-C/D/E parts have only a 1947 * 128-bit hash table. We need to deal with these 1948 * in the same manner as the PNIC II so that we 1949 * get the right number of bits out of the 1950 * CRC routine. 1951 */ 1952 if (revision >= DC_REVISION_98715AEC_C && 1953 revision < DC_REVISION_98725) 1954 sc->dc_flags |= DC_128BIT_HASH; 1955 sc->dc_type = DC_TYPE_987x5; 1956 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1957 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1958 break; 1959 case DC_DEVICEID_98727: 1960 sc->dc_type = DC_TYPE_987x5; 1961 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1962 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1963 break; 1964 case DC_DEVICEID_82C115: 1965 sc->dc_type = DC_TYPE_PNICII; 1966 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 1967 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 1968 break; 1969 case DC_DEVICEID_82C168: 1970 sc->dc_type = DC_TYPE_PNIC; 1971 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 1972 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1973 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 1974 if (revision < DC_REVISION_82C169) 1975 sc->dc_pmode = DC_PMODE_SYM; 1976 break; 1977 case DC_DEVICEID_AX88140A: 1978 sc->dc_type = DC_TYPE_ASIX; 1979 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 1980 sc->dc_flags |= DC_REDUCED_MII_POLL; 1981 sc->dc_pmode = DC_PMODE_MII; 1982 break; 1983 case DC_DEVICEID_X3201: 1984 sc->dc_type = DC_TYPE_XIRCOM; 1985 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1986 DC_TX_ALIGN; 1987 /* 1988 * We don't actually need to coalesce, but we're doing 1989 * it to obtain a double word aligned buffer. 1990 * The DC_TX_COALESCE flag is required. 1991 */ 1992 sc->dc_pmode = DC_PMODE_MII; 1993 break; 1994 case DC_DEVICEID_RS7112: 1995 sc->dc_type = DC_TYPE_CONEXANT; 1996 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1997 sc->dc_flags |= DC_REDUCED_MII_POLL; 1998 sc->dc_pmode = DC_PMODE_MII; 1999 dc_read_srom(sc, sc->dc_romwidth); 2000 break; 2001 default: 2002 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2003 sc->dc_info->dc_did); 2004 break; 2005 } 2006 2007 /* Save the cache line size. */ 2008 if (DC_IS_DAVICOM(sc)) 2009 sc->dc_cachesize = 0; 2010 else 2011 sc->dc_cachesize = pci_read_config(dev, 2012 DC_PCI_CFLT, 4) & 0xFF; 2013 2014 /* Reset the adapter. */ 2015 dc_reset(sc); 2016 2017 /* Take 21143 out of snooze mode */ 2018 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2019 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2020 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2021 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2022 } 2023 2024 /* 2025 * Try to learn something about the supported media. 2026 * We know that ASIX and ADMtek and Davicom devices 2027 * will *always* be using MII media, so that's a no-brainer. 2028 * The tricky ones are the Macronix/PNIC II and the 2029 * Intel 21143. 2030 */ 2031 if (DC_IS_INTEL(sc)) 2032 dc_parse_21143_srom(sc); 2033 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2034 if (sc->dc_type == DC_TYPE_98713) 2035 sc->dc_pmode = DC_PMODE_MII; 2036 else 2037 sc->dc_pmode = DC_PMODE_SYM; 2038 } else if (!sc->dc_pmode) 2039 sc->dc_pmode = DC_PMODE_MII; 2040 2041 /* 2042 * Get station address from the EEPROM. 2043 */ 2044 switch(sc->dc_type) { 2045 case DC_TYPE_98713: 2046 case DC_TYPE_98713A: 2047 case DC_TYPE_987x5: 2048 case DC_TYPE_PNICII: 2049 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2050 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2051 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2052 break; 2053 case DC_TYPE_PNIC: 2054 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2055 break; 2056 case DC_TYPE_DM9102: 2057 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2058#ifdef __sparc64__ 2059 /* 2060 * If this is an onboard dc(4) the station address read from 2061 * the EEPROM is all zero and we have to get it from the fcode. 2062 */ 2063 for (i = 0; i < ETHER_ADDR_LEN; i++) 2064 if (eaddr[i] != 0x00) 2065 break; 2066 if (i >= ETHER_ADDR_LEN) 2067 OF_getetheraddr(dev, eaddr); 2068#endif 2069 break; 2070 case DC_TYPE_21143: 2071 case DC_TYPE_ASIX: 2072 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2073 break; 2074 case DC_TYPE_AL981: 2075 case DC_TYPE_AN985: 2076 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2077 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2078 break; 2079 case DC_TYPE_CONEXANT: 2080 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2081 ETHER_ADDR_LEN); 2082 break; 2083 case DC_TYPE_XIRCOM: 2084 /* The MAC comes from the CIS. */ 2085 mac = pci_get_ether(dev); 2086 if (!mac) { 2087 device_printf(dev, "No station address in CIS!\n"); 2088 error = ENXIO; 2089 goto fail; 2090 } 2091 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2092 break; 2093 default: 2094 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2095 break; 2096 } 2097 2098 sc->dc_unit = unit; 2099 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2100 2101 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2102 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2103 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2104 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2105 if (error) { 2106 printf("dc%d: failed to allocate busdma tag\n", unit); 2107 error = ENXIO; 2108 goto fail; 2109 } 2110 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2111 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2112 if (error) { 2113 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2114 error = ENXIO; 2115 goto fail; 2116 } 2117 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2118 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2119 BUS_DMA_NOWAIT); 2120 if (error) { 2121 printf("dc%d: cannot get address of the descriptors\n", unit); 2122 error = ENXIO; 2123 goto fail; 2124 } 2125 2126 /* 2127 * Allocate a busdma tag and DMA safe memory for the multicast 2128 * setup frame. 2129 */ 2130 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2131 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2132 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2133 if (error) { 2134 printf("dc%d: failed to allocate busdma tag\n", unit); 2135 error = ENXIO; 2136 goto fail; 2137 } 2138 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2139 BUS_DMA_NOWAIT, &sc->dc_smap); 2140 if (error) { 2141 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2142 error = ENXIO; 2143 goto fail; 2144 } 2145 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2146 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2147 if (error) { 2148 printf("dc%d: cannot get address of the descriptors\n", unit); 2149 error = ENXIO; 2150 goto fail; 2151 } 2152 2153 /* Allocate a busdma tag for mbufs. */ 2154 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2155 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * DC_TX_LIST_CNT, 2156 DC_TX_LIST_CNT, MCLBYTES, 0, NULL, NULL, &sc->dc_mtag); 2157 if (error) { 2158 printf("dc%d: failed to allocate busdma tag\n", unit); 2159 error = ENXIO; 2160 goto fail; 2161 } 2162 2163 /* Create the TX/RX busdma maps. */ 2164 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2165 error = bus_dmamap_create(sc->dc_mtag, 0, 2166 &sc->dc_cdata.dc_tx_map[i]); 2167 if (error) { 2168 printf("dc%d: failed to init TX ring\n", unit); 2169 error = ENXIO; 2170 goto fail; 2171 } 2172 } 2173 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2174 error = bus_dmamap_create(sc->dc_mtag, 0, 2175 &sc->dc_cdata.dc_rx_map[i]); 2176 if (error) { 2177 printf("dc%d: failed to init RX ring\n", unit); 2178 error = ENXIO; 2179 goto fail; 2180 } 2181 } 2182 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2183 if (error) { 2184 printf("dc%d: failed to init RX ring\n", unit); 2185 error = ENXIO; 2186 goto fail; 2187 } 2188 2189 ifp = &sc->arpcom.ac_if; 2190 ifp->if_softc = sc; 2191 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2192 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2193 ifp->if_mtu = ETHERMTU; 2194 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2195 if (!IS_MPSAFE) 2196 ifp->if_flags |= IFF_NEEDSGIANT; 2197 ifp->if_ioctl = dc_ioctl; 2198 ifp->if_start = dc_start; 2199 ifp->if_watchdog = dc_watchdog; 2200 ifp->if_init = dc_init; 2201 ifp->if_baudrate = 10000000; 2202 IFQ_SET_MAXLEN(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2203 ifp->if_snd.ifq_drv_maxlen = DC_TX_LIST_CNT - 1; 2204 IFQ_SET_READY(&ifp->if_snd); 2205 2206 /* 2207 * Do MII setup. If this is a 21143, check for a PHY on the 2208 * MII bus after applying any necessary fixups to twiddle the 2209 * GPIO bits. If we don't end up finding a PHY, restore the 2210 * old selection (SIA only or SIA/SYM) and attach the dcphy 2211 * driver instead. 2212 */ 2213 if (DC_IS_INTEL(sc)) { 2214 dc_apply_fixup(sc, IFM_AUTO); 2215 tmp = sc->dc_pmode; 2216 sc->dc_pmode = DC_PMODE_MII; 2217 } 2218 2219 error = mii_phy_probe(dev, &sc->dc_miibus, 2220 dc_ifmedia_upd, dc_ifmedia_sts); 2221 2222 if (error && DC_IS_INTEL(sc)) { 2223 sc->dc_pmode = tmp; 2224 if (sc->dc_pmode != DC_PMODE_SIA) 2225 sc->dc_pmode = DC_PMODE_SYM; 2226 sc->dc_flags |= DC_21143_NWAY; 2227 mii_phy_probe(dev, &sc->dc_miibus, 2228 dc_ifmedia_upd, dc_ifmedia_sts); 2229 /* 2230 * For non-MII cards, we need to have the 21143 2231 * drive the LEDs. Except there are some systems 2232 * like the NEC VersaPro NoteBook PC which have no 2233 * LEDs, and twiddling these bits has adverse effects 2234 * on them. (I.e. you suddenly can't get a link.) 2235 */ 2236 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2237 sc->dc_flags |= DC_TULIP_LEDS; 2238 error = 0; 2239 } 2240 2241 if (error) { 2242 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2243 goto fail; 2244 } 2245 2246 if (DC_IS_XIRCOM(sc)) { 2247 /* 2248 * setup General Purpose Port mode and data so the tulip 2249 * can talk to the MII. 2250 */ 2251 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2252 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2253 DELAY(10); 2254 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2255 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2256 DELAY(10); 2257 } 2258 2259 if (DC_IS_ADMTEK(sc)) { 2260 /* 2261 * Set automatic TX underrun recovery for the ADMtek chips 2262 */ 2263 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2264 } 2265 2266 /* 2267 * Tell the upper layer(s) we support long frames. 2268 */ 2269 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2270 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2271#ifdef DEVICE_POLLING 2272 ifp->if_capabilities |= IFCAP_POLLING; 2273#endif 2274 ifp->if_capenable = ifp->if_capabilities; 2275 2276 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0); 2277 2278#ifdef SRM_MEDIA 2279 sc->dc_srm_media = 0; 2280 2281 /* Remember the SRM console media setting */ 2282 if (DC_IS_INTEL(sc)) { 2283 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2284 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2285 switch ((command >> 8) & 0xff) { 2286 case 3: 2287 sc->dc_srm_media = IFM_10_T; 2288 break; 2289 case 4: 2290 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2291 break; 2292 case 5: 2293 sc->dc_srm_media = IFM_100_TX; 2294 break; 2295 case 6: 2296 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2297 break; 2298 } 2299 if (sc->dc_srm_media) 2300 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2301 } 2302#endif 2303 2304 /* 2305 * Call MI attach routine. 2306 */ 2307 ether_ifattach(ifp, eaddr); 2308 2309 /* Hook interrupt last to avoid having to lock softc */ 2310 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2311 (IS_MPSAFE ? INTR_MPSAFE : 0), 2312 dc_intr, sc, &sc->dc_intrhand); 2313 2314 if (error) { 2315 printf("dc%d: couldn't set up irq\n", unit); 2316 ether_ifdetach(ifp); 2317 goto fail; 2318 } 2319 2320fail: 2321 if (error) 2322 dc_detach(dev); 2323 return (error); 2324} 2325 2326/* 2327 * Shutdown hardware and free up resources. This can be called any 2328 * time after the mutex has been initialized. It is called in both 2329 * the error case in attach and the normal detach case so it needs 2330 * to be careful about only freeing resources that have actually been 2331 * allocated. 2332 */ 2333static int 2334dc_detach(device_t dev) 2335{ 2336 struct dc_softc *sc; 2337 struct ifnet *ifp; 2338 struct dc_mediainfo *m; 2339 int i; 2340 2341 sc = device_get_softc(dev); 2342 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2343 DC_LOCK(sc); 2344 2345 ifp = &sc->arpcom.ac_if; 2346 2347 /* These should only be active if attach succeeded */ 2348 if (device_is_attached(dev)) { 2349 dc_stop(sc); 2350 ether_ifdetach(ifp); 2351 } 2352 if (sc->dc_miibus) 2353 device_delete_child(dev, sc->dc_miibus); 2354 bus_generic_detach(dev); 2355 2356 if (sc->dc_intrhand) 2357 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2358 if (sc->dc_irq) 2359 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2360 if (sc->dc_res) 2361 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2362 2363 if (sc->dc_cdata.dc_sbuf != NULL) 2364 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2365 if (sc->dc_ldata != NULL) 2366 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2367 for (i = 0; i < DC_TX_LIST_CNT; i++) 2368 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 2369 for (i = 0; i < DC_RX_LIST_CNT; i++) 2370 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2371 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2372 if (sc->dc_stag) 2373 bus_dma_tag_destroy(sc->dc_stag); 2374 if (sc->dc_mtag) 2375 bus_dma_tag_destroy(sc->dc_mtag); 2376 if (sc->dc_ltag) 2377 bus_dma_tag_destroy(sc->dc_ltag); 2378 2379 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2380 2381 while (sc->dc_mi != NULL) { 2382 m = sc->dc_mi->dc_next; 2383 free(sc->dc_mi, M_DEVBUF); 2384 sc->dc_mi = m; 2385 } 2386 free(sc->dc_srom, M_DEVBUF); 2387 2388 DC_UNLOCK(sc); 2389 mtx_destroy(&sc->dc_mtx); 2390 2391 return (0); 2392} 2393 2394/* 2395 * Initialize the transmit descriptors. 2396 */ 2397static int 2398dc_list_tx_init(struct dc_softc *sc) 2399{ 2400 struct dc_chain_data *cd; 2401 struct dc_list_data *ld; 2402 int i, nexti; 2403 2404 cd = &sc->dc_cdata; 2405 ld = sc->dc_ldata; 2406 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2407 if (i == DC_TX_LIST_CNT - 1) 2408 nexti = 0; 2409 else 2410 nexti = i + 1; 2411 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2412 cd->dc_tx_chain[i] = NULL; 2413 ld->dc_tx_list[i].dc_data = 0; 2414 ld->dc_tx_list[i].dc_ctl = 0; 2415 } 2416 2417 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2418 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2420 return (0); 2421} 2422 2423 2424/* 2425 * Initialize the RX descriptors and allocate mbufs for them. Note that 2426 * we arrange the descriptors in a closed ring, so that the last descriptor 2427 * points back to the first. 2428 */ 2429static int 2430dc_list_rx_init(struct dc_softc *sc) 2431{ 2432 struct dc_chain_data *cd; 2433 struct dc_list_data *ld; 2434 int i, nexti; 2435 2436 cd = &sc->dc_cdata; 2437 ld = sc->dc_ldata; 2438 2439 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2440 if (dc_newbuf(sc, i, 1) != 0) 2441 return (ENOBUFS); 2442 if (i == DC_RX_LIST_CNT - 1) 2443 nexti = 0; 2444 else 2445 nexti = i + 1; 2446 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2447 } 2448 2449 cd->dc_rx_prod = 0; 2450 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2451 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2452 return (0); 2453} 2454 2455static void 2456dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2457 void *arg; 2458 bus_dma_segment_t *segs; 2459 int nseg; 2460 bus_size_t mapsize; 2461 int error; 2462{ 2463 struct dc_softc *sc; 2464 struct dc_desc *c; 2465 2466 sc = arg; 2467 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2468 if (error) { 2469 sc->dc_cdata.dc_rx_err = error; 2470 return; 2471 } 2472 2473 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2474 sc->dc_cdata.dc_rx_err = 0; 2475 c->dc_data = htole32(segs->ds_addr); 2476} 2477 2478/* 2479 * Initialize an RX descriptor and attach an MBUF cluster. 2480 */ 2481static int 2482dc_newbuf(struct dc_softc *sc, int i, int alloc) 2483{ 2484 struct mbuf *m_new; 2485 bus_dmamap_t tmp; 2486 int error; 2487 2488 if (alloc) { 2489 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2490 if (m_new == NULL) 2491 return (ENOBUFS); 2492 } else { 2493 m_new = sc->dc_cdata.dc_rx_chain[i]; 2494 m_new->m_data = m_new->m_ext.ext_buf; 2495 } 2496 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2497 m_adj(m_new, sizeof(u_int64_t)); 2498 2499 /* 2500 * If this is a PNIC chip, zero the buffer. This is part 2501 * of the workaround for the receive bug in the 82c168 and 2502 * 82c169 chips. 2503 */ 2504 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2505 bzero(mtod(m_new, char *), m_new->m_len); 2506 2507 /* No need to remap the mbuf if we're reusing it. */ 2508 if (alloc) { 2509 sc->dc_cdata.dc_rx_cur = i; 2510 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2511 m_new, dc_dma_map_rxbuf, sc, 0); 2512 if (error) { 2513 m_freem(m_new); 2514 return (error); 2515 } 2516 if (sc->dc_cdata.dc_rx_err != 0) { 2517 m_freem(m_new); 2518 return (sc->dc_cdata.dc_rx_err); 2519 } 2520 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2521 tmp = sc->dc_cdata.dc_rx_map[i]; 2522 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2523 sc->dc_sparemap = tmp; 2524 sc->dc_cdata.dc_rx_chain[i] = m_new; 2525 } 2526 2527 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2528 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2529 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2530 BUS_DMASYNC_PREREAD); 2531 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2532 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2533 return (0); 2534} 2535 2536/* 2537 * Grrrrr. 2538 * The PNIC chip has a terrible bug in it that manifests itself during 2539 * periods of heavy activity. The exact mode of failure if difficult to 2540 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2541 * will happen on slow machines. The bug is that sometimes instead of 2542 * uploading one complete frame during reception, it uploads what looks 2543 * like the entire contents of its FIFO memory. The frame we want is at 2544 * the end of the whole mess, but we never know exactly how much data has 2545 * been uploaded, so salvaging the frame is hard. 2546 * 2547 * There is only one way to do it reliably, and it's disgusting. 2548 * Here's what we know: 2549 * 2550 * - We know there will always be somewhere between one and three extra 2551 * descriptors uploaded. 2552 * 2553 * - We know the desired received frame will always be at the end of the 2554 * total data upload. 2555 * 2556 * - We know the size of the desired received frame because it will be 2557 * provided in the length field of the status word in the last descriptor. 2558 * 2559 * Here's what we do: 2560 * 2561 * - When we allocate buffers for the receive ring, we bzero() them. 2562 * This means that we know that the buffer contents should be all 2563 * zeros, except for data uploaded by the chip. 2564 * 2565 * - We also force the PNIC chip to upload frames that include the 2566 * ethernet CRC at the end. 2567 * 2568 * - We gather all of the bogus frame data into a single buffer. 2569 * 2570 * - We then position a pointer at the end of this buffer and scan 2571 * backwards until we encounter the first non-zero byte of data. 2572 * This is the end of the received frame. We know we will encounter 2573 * some data at the end of the frame because the CRC will always be 2574 * there, so even if the sender transmits a packet of all zeros, 2575 * we won't be fooled. 2576 * 2577 * - We know the size of the actual received frame, so we subtract 2578 * that value from the current pointer location. This brings us 2579 * to the start of the actual received packet. 2580 * 2581 * - We copy this into an mbuf and pass it on, along with the actual 2582 * frame length. 2583 * 2584 * The performance hit is tremendous, but it beats dropping frames all 2585 * the time. 2586 */ 2587 2588#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2589static void 2590dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2591{ 2592 struct dc_desc *cur_rx; 2593 struct dc_desc *c = NULL; 2594 struct mbuf *m = NULL; 2595 unsigned char *ptr; 2596 int i, total_len; 2597 u_int32_t rxstat = 0; 2598 2599 i = sc->dc_pnic_rx_bug_save; 2600 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2601 ptr = sc->dc_pnic_rx_buf; 2602 bzero(ptr, DC_RXLEN * 5); 2603 2604 /* Copy all the bytes from the bogus buffers. */ 2605 while (1) { 2606 c = &sc->dc_ldata->dc_rx_list[i]; 2607 rxstat = le32toh(c->dc_status); 2608 m = sc->dc_cdata.dc_rx_chain[i]; 2609 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2610 ptr += DC_RXLEN; 2611 /* If this is the last buffer, break out. */ 2612 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2613 break; 2614 dc_newbuf(sc, i, 0); 2615 DC_INC(i, DC_RX_LIST_CNT); 2616 } 2617 2618 /* Find the length of the actual receive frame. */ 2619 total_len = DC_RXBYTES(rxstat); 2620 2621 /* Scan backwards until we hit a non-zero byte. */ 2622 while (*ptr == 0x00) 2623 ptr--; 2624 2625 /* Round off. */ 2626 if ((uintptr_t)(ptr) & 0x3) 2627 ptr -= 1; 2628 2629 /* Now find the start of the frame. */ 2630 ptr -= total_len; 2631 if (ptr < sc->dc_pnic_rx_buf) 2632 ptr = sc->dc_pnic_rx_buf; 2633 2634 /* 2635 * Now copy the salvaged frame to the last mbuf and fake up 2636 * the status word to make it look like a successful 2637 * frame reception. 2638 */ 2639 dc_newbuf(sc, i, 0); 2640 bcopy(ptr, mtod(m, char *), total_len); 2641 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2642} 2643 2644/* 2645 * This routine searches the RX ring for dirty descriptors in the 2646 * event that the rxeof routine falls out of sync with the chip's 2647 * current descriptor pointer. This may happen sometimes as a result 2648 * of a "no RX buffer available" condition that happens when the chip 2649 * consumes all of the RX buffers before the driver has a chance to 2650 * process the RX ring. This routine may need to be called more than 2651 * once to bring the driver back in sync with the chip, however we 2652 * should still be getting RX DONE interrupts to drive the search 2653 * for new packets in the RX ring, so we should catch up eventually. 2654 */ 2655static int 2656dc_rx_resync(struct dc_softc *sc) 2657{ 2658 struct dc_desc *cur_rx; 2659 int i, pos; 2660 2661 pos = sc->dc_cdata.dc_rx_prod; 2662 2663 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2664 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2665 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2666 break; 2667 DC_INC(pos, DC_RX_LIST_CNT); 2668 } 2669 2670 /* If the ring really is empty, then just return. */ 2671 if (i == DC_RX_LIST_CNT) 2672 return (0); 2673 2674 /* We've fallen behing the chip: catch it. */ 2675 sc->dc_cdata.dc_rx_prod = pos; 2676 2677 return (EAGAIN); 2678} 2679 2680/* 2681 * A frame has been uploaded: pass the resulting mbuf chain up to 2682 * the higher level protocols. 2683 */ 2684static void 2685dc_rxeof(struct dc_softc *sc) 2686{ 2687 struct mbuf *m; 2688 struct ifnet *ifp; 2689 struct dc_desc *cur_rx; 2690 int i, total_len = 0; 2691 u_int32_t rxstat; 2692 2693 DC_LOCK_ASSERT(sc); 2694 2695 ifp = &sc->arpcom.ac_if; 2696 i = sc->dc_cdata.dc_rx_prod; 2697 2698 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2699 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2700 DC_RXSTAT_OWN)) { 2701#ifdef DEVICE_POLLING 2702 if (ifp->if_flags & IFF_POLLING) { 2703 if (sc->rxcycles <= 0) 2704 break; 2705 sc->rxcycles--; 2706 } 2707#endif 2708 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2709 rxstat = le32toh(cur_rx->dc_status); 2710 m = sc->dc_cdata.dc_rx_chain[i]; 2711 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2712 BUS_DMASYNC_POSTREAD); 2713 total_len = DC_RXBYTES(rxstat); 2714 2715 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2716 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2717 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2718 sc->dc_pnic_rx_bug_save = i; 2719 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2720 DC_INC(i, DC_RX_LIST_CNT); 2721 continue; 2722 } 2723 dc_pnic_rx_bug_war(sc, i); 2724 rxstat = le32toh(cur_rx->dc_status); 2725 total_len = DC_RXBYTES(rxstat); 2726 } 2727 } 2728 2729 /* 2730 * If an error occurs, update stats, clear the 2731 * status word and leave the mbuf cluster in place: 2732 * it should simply get re-used next time this descriptor 2733 * comes up in the ring. However, don't report long 2734 * frames as errors since they could be vlans. 2735 */ 2736 if ((rxstat & DC_RXSTAT_RXERR)) { 2737 if (!(rxstat & DC_RXSTAT_GIANT) || 2738 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2739 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2740 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2741 ifp->if_ierrors++; 2742 if (rxstat & DC_RXSTAT_COLLSEEN) 2743 ifp->if_collisions++; 2744 dc_newbuf(sc, i, 0); 2745 if (rxstat & DC_RXSTAT_CRCERR) { 2746 DC_INC(i, DC_RX_LIST_CNT); 2747 continue; 2748 } else { 2749 dc_init(sc); 2750 return; 2751 } 2752 } 2753 } 2754 2755 /* No errors; receive the packet. */ 2756 total_len -= ETHER_CRC_LEN; 2757#ifdef __i386__ 2758 /* 2759 * On the x86 we do not have alignment problems, so try to 2760 * allocate a new buffer for the receive ring, and pass up 2761 * the one where the packet is already, saving the expensive 2762 * copy done in m_devget(). 2763 * If we are on an architecture with alignment problems, or 2764 * if the allocation fails, then use m_devget and leave the 2765 * existing buffer in the receive ring. 2766 */ 2767 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2768 m->m_pkthdr.rcvif = ifp; 2769 m->m_pkthdr.len = m->m_len = total_len; 2770 DC_INC(i, DC_RX_LIST_CNT); 2771 } else 2772#endif 2773 { 2774 struct mbuf *m0; 2775 2776 m0 = m_devget(mtod(m, char *), total_len, 2777 ETHER_ALIGN, ifp, NULL); 2778 dc_newbuf(sc, i, 0); 2779 DC_INC(i, DC_RX_LIST_CNT); 2780 if (m0 == NULL) { 2781 ifp->if_ierrors++; 2782 continue; 2783 } 2784 m = m0; 2785 } 2786 2787 ifp->if_ipackets++; 2788 DC_UNLOCK(sc); 2789 (*ifp->if_input)(ifp, m); 2790 DC_LOCK(sc); 2791 } 2792 2793 sc->dc_cdata.dc_rx_prod = i; 2794} 2795 2796/* 2797 * A frame was downloaded to the chip. It's safe for us to clean up 2798 * the list buffers. 2799 */ 2800 2801static void 2802dc_txeof(struct dc_softc *sc) 2803{ 2804 struct dc_desc *cur_tx = NULL; 2805 struct ifnet *ifp; 2806 int idx; 2807 u_int32_t ctl, txstat; 2808 2809 ifp = &sc->arpcom.ac_if; 2810 2811 /* 2812 * Go through our tx list and free mbufs for those 2813 * frames that have been transmitted. 2814 */ 2815 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2816 idx = sc->dc_cdata.dc_tx_cons; 2817 while (idx != sc->dc_cdata.dc_tx_prod) { 2818 2819 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2820 txstat = le32toh(cur_tx->dc_status); 2821 ctl = le32toh(cur_tx->dc_ctl); 2822 2823 if (txstat & DC_TXSTAT_OWN) 2824 break; 2825 2826 if (!(ctl & DC_TXCTL_LASTFRAG) || ctl & DC_TXCTL_SETUP) { 2827 if (ctl & DC_TXCTL_SETUP) { 2828 /* 2829 * Yes, the PNIC is so brain damaged 2830 * that it will sometimes generate a TX 2831 * underrun error while DMAing the RX 2832 * filter setup frame. If we detect this, 2833 * we have to send the setup frame again, 2834 * or else the filter won't be programmed 2835 * correctly. 2836 */ 2837 if (DC_IS_PNIC(sc)) { 2838 if (txstat & DC_TXSTAT_ERRSUM) 2839 dc_setfilt(sc); 2840 } 2841 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2842 } 2843 sc->dc_cdata.dc_tx_cnt--; 2844 DC_INC(idx, DC_TX_LIST_CNT); 2845 continue; 2846 } 2847 2848 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2849 /* 2850 * XXX: Why does my Xircom taunt me so? 2851 * For some reason it likes setting the CARRLOST flag 2852 * even when the carrier is there. wtf?!? 2853 * Who knows, but Conexant chips have the 2854 * same problem. Maybe they took lessons 2855 * from Xircom. 2856 */ 2857 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2858 sc->dc_pmode == DC_PMODE_MII && 2859 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2860 DC_TXSTAT_NOCARRIER))) 2861 txstat &= ~DC_TXSTAT_ERRSUM; 2862 } else { 2863 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2864 sc->dc_pmode == DC_PMODE_MII && 2865 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2866 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2867 txstat &= ~DC_TXSTAT_ERRSUM; 2868 } 2869 2870 if (txstat & DC_TXSTAT_ERRSUM) { 2871 ifp->if_oerrors++; 2872 if (txstat & DC_TXSTAT_EXCESSCOLL) 2873 ifp->if_collisions++; 2874 if (txstat & DC_TXSTAT_LATECOLL) 2875 ifp->if_collisions++; 2876 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2877 dc_init(sc); 2878 return; 2879 } 2880 } 2881 2882 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2883 2884 ifp->if_opackets++; 2885 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2886 bus_dmamap_sync(sc->dc_mtag, 2887 sc->dc_cdata.dc_tx_map[idx], 2888 BUS_DMASYNC_POSTWRITE); 2889 bus_dmamap_unload(sc->dc_mtag, 2890 sc->dc_cdata.dc_tx_map[idx]); 2891 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2892 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2893 } 2894 2895 sc->dc_cdata.dc_tx_cnt--; 2896 DC_INC(idx, DC_TX_LIST_CNT); 2897 } 2898 2899 if (idx != sc->dc_cdata.dc_tx_cons) { 2900 /* Some buffers have been freed. */ 2901 sc->dc_cdata.dc_tx_cons = idx; 2902 ifp->if_flags &= ~IFF_OACTIVE; 2903 } 2904 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2905} 2906 2907static void 2908dc_tick(void *xsc) 2909{ 2910 struct dc_softc *sc; 2911 struct mii_data *mii; 2912 struct ifnet *ifp; 2913 u_int32_t r; 2914 2915 sc = xsc; 2916 DC_LOCK(sc); 2917 ifp = &sc->arpcom.ac_if; 2918 mii = device_get_softc(sc->dc_miibus); 2919 2920 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2921 if (sc->dc_flags & DC_21143_NWAY) { 2922 r = CSR_READ_4(sc, DC_10BTSTAT); 2923 if (IFM_SUBTYPE(mii->mii_media_active) == 2924 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2925 sc->dc_link = 0; 2926 mii_mediachg(mii); 2927 } 2928 if (IFM_SUBTYPE(mii->mii_media_active) == 2929 IFM_10_T && (r & DC_TSTAT_LS10)) { 2930 sc->dc_link = 0; 2931 mii_mediachg(mii); 2932 } 2933 if (sc->dc_link == 0) 2934 mii_tick(mii); 2935 } else { 2936 r = CSR_READ_4(sc, DC_ISR); 2937 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2938 sc->dc_cdata.dc_tx_cnt == 0) { 2939 mii_tick(mii); 2940 if (!(mii->mii_media_status & IFM_ACTIVE)) 2941 sc->dc_link = 0; 2942 } 2943 } 2944 } else 2945 mii_tick(mii); 2946 2947 /* 2948 * When the init routine completes, we expect to be able to send 2949 * packets right away, and in fact the network code will send a 2950 * gratuitous ARP the moment the init routine marks the interface 2951 * as running. However, even though the MAC may have been initialized, 2952 * there may be a delay of a few seconds before the PHY completes 2953 * autonegotiation and the link is brought up. Any transmissions 2954 * made during that delay will be lost. Dealing with this is tricky: 2955 * we can't just pause in the init routine while waiting for the 2956 * PHY to come ready since that would bring the whole system to 2957 * a screeching halt for several seconds. 2958 * 2959 * What we do here is prevent the TX start routine from sending 2960 * any packets until a link has been established. After the 2961 * interface has been initialized, the tick routine will poll 2962 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2963 * that time, packets will stay in the send queue, and once the 2964 * link comes up, they will be flushed out to the wire. 2965 */ 2966 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2967 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2968 sc->dc_link++; 2969 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2970 dc_start(ifp); 2971 } 2972 2973 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2974 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2975 else 2976 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2977 2978 DC_UNLOCK(sc); 2979} 2980 2981/* 2982 * A transmit underrun has occurred. Back off the transmit threshold, 2983 * or switch to store and forward mode if we have to. 2984 */ 2985static void 2986dc_tx_underrun(struct dc_softc *sc) 2987{ 2988 u_int32_t isr; 2989 int i; 2990 2991 if (DC_IS_DAVICOM(sc)) 2992 dc_init(sc); 2993 2994 if (DC_IS_INTEL(sc)) { 2995 /* 2996 * The real 21143 requires that the transmitter be idle 2997 * in order to change the transmit threshold or store 2998 * and forward state. 2999 */ 3000 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3001 3002 for (i = 0; i < DC_TIMEOUT; i++) { 3003 isr = CSR_READ_4(sc, DC_ISR); 3004 if (isr & DC_ISR_TX_IDLE) 3005 break; 3006 DELAY(10); 3007 } 3008 if (i == DC_TIMEOUT) { 3009 printf("dc%d: failed to force tx to idle state\n", 3010 sc->dc_unit); 3011 dc_init(sc); 3012 } 3013 } 3014 3015 printf("dc%d: TX underrun -- ", sc->dc_unit); 3016 sc->dc_txthresh += DC_TXTHRESH_INC; 3017 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3018 printf("using store and forward mode\n"); 3019 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3020 } else { 3021 printf("increasing TX threshold\n"); 3022 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3023 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3024 } 3025 3026 if (DC_IS_INTEL(sc)) 3027 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3028} 3029 3030#ifdef DEVICE_POLLING 3031static poll_handler_t dc_poll; 3032 3033static void 3034dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3035{ 3036 struct dc_softc *sc = ifp->if_softc; 3037 3038 if (!(ifp->if_capenable & IFCAP_POLLING)) { 3039 ether_poll_deregister(ifp); 3040 cmd = POLL_DEREGISTER; 3041 } 3042 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3043 /* Re-enable interrupts. */ 3044 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3045 return; 3046 } 3047 DC_LOCK(sc); 3048 sc->rxcycles = count; 3049 dc_rxeof(sc); 3050 dc_txeof(sc); 3051 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 3052 dc_start(ifp); 3053 3054 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3055 u_int32_t status; 3056 3057 status = CSR_READ_4(sc, DC_ISR); 3058 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3059 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3060 DC_ISR_BUS_ERR); 3061 if (!status) { 3062 DC_UNLOCK(sc); 3063 return; 3064 } 3065 /* ack what we have */ 3066 CSR_WRITE_4(sc, DC_ISR, status); 3067 3068 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3069 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3070 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3071 3072 if (dc_rx_resync(sc)) 3073 dc_rxeof(sc); 3074 } 3075 /* restart transmit unit if necessary */ 3076 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3077 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3078 3079 if (status & DC_ISR_TX_UNDERRUN) 3080 dc_tx_underrun(sc); 3081 3082 if (status & DC_ISR_BUS_ERR) { 3083 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3084 dc_reset(sc); 3085 dc_init(sc); 3086 } 3087 } 3088 DC_UNLOCK(sc); 3089} 3090#endif /* DEVICE_POLLING */ 3091 3092static void 3093dc_intr(void *arg) 3094{ 3095 struct dc_softc *sc; 3096 struct ifnet *ifp; 3097 u_int32_t status; 3098 3099 sc = arg; 3100 3101 if (sc->suspended) 3102 return; 3103 3104 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3105 return; 3106 3107 DC_LOCK(sc); 3108 ifp = &sc->arpcom.ac_if; 3109#ifdef DEVICE_POLLING 3110 if (ifp->if_flags & IFF_POLLING) 3111 goto done; 3112 if ((ifp->if_capenable & IFCAP_POLLING) && 3113 ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3114 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3115 goto done; 3116 } 3117#endif 3118 3119 /* Suppress unwanted interrupts */ 3120 if (!(ifp->if_flags & IFF_UP)) { 3121 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3122 dc_stop(sc); 3123 DC_UNLOCK(sc); 3124 return; 3125 } 3126 3127 /* Disable interrupts. */ 3128 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3129 3130 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3131 && status != 0xFFFFFFFF) { 3132 3133 CSR_WRITE_4(sc, DC_ISR, status); 3134 3135 if (status & DC_ISR_RX_OK) { 3136 int curpkts; 3137 curpkts = ifp->if_ipackets; 3138 dc_rxeof(sc); 3139 if (curpkts == ifp->if_ipackets) { 3140 while (dc_rx_resync(sc)) 3141 dc_rxeof(sc); 3142 } 3143 } 3144 3145 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3146 dc_txeof(sc); 3147 3148 if (status & DC_ISR_TX_IDLE) { 3149 dc_txeof(sc); 3150 if (sc->dc_cdata.dc_tx_cnt) { 3151 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3152 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3153 } 3154 } 3155 3156 if (status & DC_ISR_TX_UNDERRUN) 3157 dc_tx_underrun(sc); 3158 3159 if ((status & DC_ISR_RX_WATDOGTIMEO) 3160 || (status & DC_ISR_RX_NOBUF)) { 3161 int curpkts; 3162 curpkts = ifp->if_ipackets; 3163 dc_rxeof(sc); 3164 if (curpkts == ifp->if_ipackets) { 3165 while (dc_rx_resync(sc)) 3166 dc_rxeof(sc); 3167 } 3168 } 3169 3170 if (status & DC_ISR_BUS_ERR) { 3171 dc_reset(sc); 3172 dc_init(sc); 3173 } 3174 } 3175 3176 /* Re-enable interrupts. */ 3177 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3178 3179 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3180 dc_start(ifp); 3181 3182#ifdef DEVICE_POLLING 3183done: 3184#endif 3185 3186 DC_UNLOCK(sc); 3187} 3188 3189static void 3190dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3191 void *arg; 3192 bus_dma_segment_t *segs; 3193 int nseg; 3194 bus_size_t mapsize; 3195 int error; 3196{ 3197 struct dc_softc *sc; 3198 struct dc_desc *f; 3199 int cur, first, frag, i; 3200 3201 sc = arg; 3202 if (error) { 3203 sc->dc_cdata.dc_tx_err = error; 3204 return; 3205 } 3206 3207 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3208 for (i = 0; i < nseg; i++) { 3209 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3210 (frag == (DC_TX_LIST_CNT - 1)) && 3211 (first != sc->dc_cdata.dc_tx_first)) { 3212 bus_dmamap_unload(sc->dc_mtag, 3213 sc->dc_cdata.dc_tx_map[first]); 3214 sc->dc_cdata.dc_tx_err = ENOBUFS; 3215 return; 3216 } 3217 3218 f = &sc->dc_ldata->dc_tx_list[frag]; 3219 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3220 if (i == 0) { 3221 f->dc_status = 0; 3222 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3223 } else 3224 f->dc_status = htole32(DC_TXSTAT_OWN); 3225 f->dc_data = htole32(segs[i].ds_addr); 3226 cur = frag; 3227 DC_INC(frag, DC_TX_LIST_CNT); 3228 } 3229 3230 sc->dc_cdata.dc_tx_err = 0; 3231 sc->dc_cdata.dc_tx_prod = frag; 3232 sc->dc_cdata.dc_tx_cnt += nseg; 3233 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3234 sc->dc_cdata.dc_tx_chain[cur] = sc->dc_cdata.dc_tx_mapping; 3235 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3236 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3237 htole32(DC_TXCTL_FINT); 3238 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3239 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3240 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3241 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3242 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3243} 3244 3245/* 3246 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3247 * pointers to the fragment pointers. 3248 */ 3249static int 3250dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3251{ 3252 struct mbuf *m; 3253 int error, idx, chainlen = 0; 3254 3255 /* 3256 * If there's no way we can send any packets, return now. 3257 */ 3258 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3259 return (ENOBUFS); 3260 3261 /* 3262 * Count the number of frags in this chain to see if 3263 * we need to m_defrag. Since the descriptor list is shared 3264 * by all packets, we'll m_defrag long chains so that they 3265 * do not use up the entire list, even if they would fit. 3266 */ 3267 for (m = *m_head; m != NULL; m = m->m_next) 3268 chainlen++; 3269 3270 if ((chainlen > DC_TX_LIST_CNT / 4) || 3271 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3272 m = m_defrag(*m_head, M_DONTWAIT); 3273 if (m == NULL) 3274 return (ENOBUFS); 3275 *m_head = m; 3276 } 3277 3278 /* 3279 * Start packing the mbufs in this chain into 3280 * the fragment pointers. Stop when we run out 3281 * of fragments or hit the end of the mbuf chain. 3282 */ 3283 idx = sc->dc_cdata.dc_tx_prod; 3284 sc->dc_cdata.dc_tx_mapping = *m_head; 3285 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3286 *m_head, dc_dma_map_txbuf, sc, 0); 3287 if (error) 3288 return (error); 3289 if (sc->dc_cdata.dc_tx_err != 0) 3290 return (sc->dc_cdata.dc_tx_err); 3291 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3292 BUS_DMASYNC_PREWRITE); 3293 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3294 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3295 return (0); 3296} 3297 3298/* 3299 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3300 * to the mbuf data regions directly in the transmit lists. We also save a 3301 * copy of the pointers since the transmit list fragment pointers are 3302 * physical addresses. 3303 */ 3304 3305static void 3306dc_start(struct ifnet *ifp) 3307{ 3308 struct dc_softc *sc; 3309 struct mbuf *m_head = NULL, *m; 3310 unsigned int queued = 0; 3311 int idx; 3312 3313 sc = ifp->if_softc; 3314 3315 DC_LOCK(sc); 3316 3317 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3318 DC_UNLOCK(sc); 3319 return; 3320 } 3321 3322 if (ifp->if_flags & IFF_OACTIVE) { 3323 DC_UNLOCK(sc); 3324 return; 3325 } 3326 3327 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3328 3329 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3330 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3331 if (m_head == NULL) 3332 break; 3333 3334 if (sc->dc_flags & DC_TX_COALESCE && 3335 (m_head->m_next != NULL || 3336 sc->dc_flags & DC_TX_ALIGN)) { 3337 m = m_defrag(m_head, M_DONTWAIT); 3338 if (m == NULL) { 3339 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3340 ifp->if_flags |= IFF_OACTIVE; 3341 break; 3342 } else { 3343 m_head = m; 3344 } 3345 } 3346 3347 if (dc_encap(sc, &m_head)) { 3348 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3349 ifp->if_flags |= IFF_OACTIVE; 3350 break; 3351 } 3352 idx = sc->dc_cdata.dc_tx_prod; 3353 3354 queued++; 3355 /* 3356 * If there's a BPF listener, bounce a copy of this frame 3357 * to him. 3358 */ 3359 BPF_MTAP(ifp, m_head); 3360 3361 if (sc->dc_flags & DC_TX_ONE) { 3362 ifp->if_flags |= IFF_OACTIVE; 3363 break; 3364 } 3365 } 3366 3367 if (queued > 0) { 3368 /* Transmit */ 3369 if (!(sc->dc_flags & DC_TX_POLL)) 3370 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3371 3372 /* 3373 * Set a timeout in case the chip goes out to lunch. 3374 */ 3375 ifp->if_timer = 5; 3376 } 3377 3378 DC_UNLOCK(sc); 3379} 3380 3381static void 3382dc_init(void *xsc) 3383{ 3384 struct dc_softc *sc = xsc; 3385 struct ifnet *ifp = &sc->arpcom.ac_if; 3386 struct mii_data *mii; 3387 3388 DC_LOCK(sc); 3389 3390 mii = device_get_softc(sc->dc_miibus); 3391 3392 /* 3393 * Cancel pending I/O and free all RX/TX buffers. 3394 */ 3395 dc_stop(sc); 3396 dc_reset(sc); 3397 3398 /* 3399 * Set cache alignment and burst length. 3400 */ 3401 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3402 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3403 else 3404 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3405 /* 3406 * Evenly share the bus between receive and transmit process. 3407 */ 3408 if (DC_IS_INTEL(sc)) 3409 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3410 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3411 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3412 } else { 3413 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3414 } 3415 if (sc->dc_flags & DC_TX_POLL) 3416 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3417 switch(sc->dc_cachesize) { 3418 case 32: 3419 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3420 break; 3421 case 16: 3422 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3423 break; 3424 case 8: 3425 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3426 break; 3427 case 0: 3428 default: 3429 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3430 break; 3431 } 3432 3433 if (sc->dc_flags & DC_TX_STORENFWD) 3434 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3435 else { 3436 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3437 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3438 } else { 3439 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3440 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3441 } 3442 } 3443 3444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3445 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3446 3447 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3448 /* 3449 * The app notes for the 98713 and 98715A say that 3450 * in order to have the chips operate properly, a magic 3451 * number must be written to CSR16. Macronix does not 3452 * document the meaning of these bits so there's no way 3453 * to know exactly what they do. The 98713 has a magic 3454 * number all its own; the rest all use a different one. 3455 */ 3456 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3457 if (sc->dc_type == DC_TYPE_98713) 3458 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3459 else 3460 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3461 } 3462 3463 if (DC_IS_XIRCOM(sc)) { 3464 /* 3465 * setup General Purpose Port mode and data so the tulip 3466 * can talk to the MII. 3467 */ 3468 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3469 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3470 DELAY(10); 3471 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3472 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3473 DELAY(10); 3474 } 3475 3476 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3477 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3478 3479 /* Init circular RX list. */ 3480 if (dc_list_rx_init(sc) == ENOBUFS) { 3481 printf("dc%d: initialization failed: no " 3482 "memory for rx buffers\n", sc->dc_unit); 3483 dc_stop(sc); 3484 DC_UNLOCK(sc); 3485 return; 3486 } 3487 3488 /* 3489 * Init TX descriptors. 3490 */ 3491 dc_list_tx_init(sc); 3492 3493 /* 3494 * Load the address of the RX list. 3495 */ 3496 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3497 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3498 3499 /* 3500 * Enable interrupts. 3501 */ 3502#ifdef DEVICE_POLLING 3503 /* 3504 * ... but only if we are not polling, and make sure they are off in 3505 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3506 * after a reset. 3507 */ 3508 if (ifp->if_flags & IFF_POLLING) 3509 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3510 else 3511#endif 3512 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3513 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3514 3515 /* Enable transmitter. */ 3516 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3517 3518 /* 3519 * If this is an Intel 21143 and we're not using the 3520 * MII port, program the LED control pins so we get 3521 * link and activity indications. 3522 */ 3523 if (sc->dc_flags & DC_TULIP_LEDS) { 3524 CSR_WRITE_4(sc, DC_WATCHDOG, 3525 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3526 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3527 } 3528 3529 /* 3530 * Load the RX/multicast filter. We do this sort of late 3531 * because the filter programming scheme on the 21143 and 3532 * some clones requires DMAing a setup frame via the TX 3533 * engine, and we need the transmitter enabled for that. 3534 */ 3535 dc_setfilt(sc); 3536 3537 /* Enable receiver. */ 3538 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3539 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3540 3541 mii_mediachg(mii); 3542 dc_setcfg(sc, sc->dc_if_media); 3543 3544 ifp->if_flags |= IFF_RUNNING; 3545 ifp->if_flags &= ~IFF_OACTIVE; 3546 3547 /* Don't start the ticker if this is a homePNA link. */ 3548 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3549 sc->dc_link = 1; 3550 else { 3551 if (sc->dc_flags & DC_21143_NWAY) 3552 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3553 else 3554 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3555 } 3556 3557#ifdef SRM_MEDIA 3558 if(sc->dc_srm_media) { 3559 struct ifreq ifr; 3560 3561 ifr.ifr_media = sc->dc_srm_media; 3562 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3563 sc->dc_srm_media = 0; 3564 } 3565#endif 3566 DC_UNLOCK(sc); 3567} 3568 3569/* 3570 * Set media options. 3571 */ 3572static int 3573dc_ifmedia_upd(struct ifnet *ifp) 3574{ 3575 struct dc_softc *sc; 3576 struct mii_data *mii; 3577 struct ifmedia *ifm; 3578 3579 sc = ifp->if_softc; 3580 mii = device_get_softc(sc->dc_miibus); 3581 mii_mediachg(mii); 3582 ifm = &mii->mii_media; 3583 3584 if (DC_IS_DAVICOM(sc) && 3585 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3586 dc_setcfg(sc, ifm->ifm_media); 3587 else 3588 sc->dc_link = 0; 3589 3590 return (0); 3591} 3592 3593/* 3594 * Report current media status. 3595 */ 3596static void 3597dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3598{ 3599 struct dc_softc *sc; 3600 struct mii_data *mii; 3601 struct ifmedia *ifm; 3602 3603 sc = ifp->if_softc; 3604 mii = device_get_softc(sc->dc_miibus); 3605 mii_pollstat(mii); 3606 ifm = &mii->mii_media; 3607 if (DC_IS_DAVICOM(sc)) { 3608 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3609 ifmr->ifm_active = ifm->ifm_media; 3610 ifmr->ifm_status = 0; 3611 return; 3612 } 3613 } 3614 ifmr->ifm_active = mii->mii_media_active; 3615 ifmr->ifm_status = mii->mii_media_status; 3616} 3617 3618static int 3619dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3620{ 3621 struct dc_softc *sc = ifp->if_softc; 3622 struct ifreq *ifr = (struct ifreq *)data; 3623 struct mii_data *mii; 3624 int error = 0; 3625 3626 DC_LOCK(sc); 3627 3628 switch (command) { 3629 case SIOCSIFFLAGS: 3630 if (ifp->if_flags & IFF_UP) { 3631 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3632 (IFF_PROMISC | IFF_ALLMULTI); 3633 3634 if (ifp->if_flags & IFF_RUNNING) { 3635 if (need_setfilt) 3636 dc_setfilt(sc); 3637 } else { 3638 sc->dc_txthresh = 0; 3639 dc_init(sc); 3640 } 3641 } else { 3642 if (ifp->if_flags & IFF_RUNNING) 3643 dc_stop(sc); 3644 } 3645 sc->dc_if_flags = ifp->if_flags; 3646 error = 0; 3647 break; 3648 case SIOCADDMULTI: 3649 case SIOCDELMULTI: 3650 dc_setfilt(sc); 3651 error = 0; 3652 break; 3653 case SIOCGIFMEDIA: 3654 case SIOCSIFMEDIA: 3655 mii = device_get_softc(sc->dc_miibus); 3656 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3657#ifdef SRM_MEDIA 3658 if (sc->dc_srm_media) 3659 sc->dc_srm_media = 0; 3660#endif 3661 break; 3662 case SIOCSIFCAP: 3663 ifp->if_capenable &= ~IFCAP_POLLING; 3664 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 3665 break; 3666 default: 3667 error = ether_ioctl(ifp, command, data); 3668 break; 3669 } 3670 3671 DC_UNLOCK(sc); 3672 3673 return (error); 3674} 3675 3676static void 3677dc_watchdog(struct ifnet *ifp) 3678{ 3679 struct dc_softc *sc; 3680 3681 sc = ifp->if_softc; 3682 3683 DC_LOCK(sc); 3684 3685 ifp->if_oerrors++; 3686 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3687 3688 dc_stop(sc); 3689 dc_reset(sc); 3690 dc_init(sc); 3691 3692 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3693 dc_start(ifp); 3694 3695 DC_UNLOCK(sc); 3696} 3697 3698/* 3699 * Stop the adapter and free any mbufs allocated to the 3700 * RX and TX lists. 3701 */ 3702static void 3703dc_stop(struct dc_softc *sc) 3704{ 3705 struct ifnet *ifp; 3706 struct dc_list_data *ld; 3707 struct dc_chain_data *cd; 3708 int i; 3709 u_int32_t ctl; 3710 3711 DC_LOCK(sc); 3712 3713 ifp = &sc->arpcom.ac_if; 3714 ifp->if_timer = 0; 3715 ld = sc->dc_ldata; 3716 cd = &sc->dc_cdata; 3717 3718 callout_stop(&sc->dc_stat_ch); 3719 3720 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3721#ifdef DEVICE_POLLING 3722 ether_poll_deregister(ifp); 3723#endif 3724 3725 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3726 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3727 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3728 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3729 sc->dc_link = 0; 3730 3731 /* 3732 * Free data in the RX lists. 3733 */ 3734 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3735 if (cd->dc_rx_chain[i] != NULL) { 3736 m_freem(cd->dc_rx_chain[i]); 3737 cd->dc_rx_chain[i] = NULL; 3738 } 3739 } 3740 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3741 3742 /* 3743 * Free the TX list buffers. 3744 */ 3745 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3746 if (cd->dc_tx_chain[i] != NULL) { 3747 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3748 if ((ctl & DC_TXCTL_SETUP) || 3749 !(ctl & DC_TXCTL_LASTFRAG)) { 3750 cd->dc_tx_chain[i] = NULL; 3751 continue; 3752 } 3753 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3754 m_freem(cd->dc_tx_chain[i]); 3755 cd->dc_tx_chain[i] = NULL; 3756 } 3757 } 3758 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3759 3760 DC_UNLOCK(sc); 3761} 3762 3763/* 3764 * Device suspend routine. Stop the interface and save some PCI 3765 * settings in case the BIOS doesn't restore them properly on 3766 * resume. 3767 */ 3768static int 3769dc_suspend(device_t dev) 3770{ 3771 struct dc_softc *sc; 3772 int s; 3773 3774 s = splimp(); 3775 3776 sc = device_get_softc(dev); 3777 dc_stop(sc); 3778 sc->suspended = 1; 3779 3780 splx(s); 3781 return (0); 3782} 3783 3784/* 3785 * Device resume routine. Restore some PCI settings in case the BIOS 3786 * doesn't, re-enable busmastering, and restart the interface if 3787 * appropriate. 3788 */ 3789static int 3790dc_resume(device_t dev) 3791{ 3792 struct dc_softc *sc; 3793 struct ifnet *ifp; 3794 int s; 3795 3796 s = splimp(); 3797 3798 sc = device_get_softc(dev); 3799 ifp = &sc->arpcom.ac_if; 3800 3801 /* reinitialize interface if necessary */ 3802 if (ifp->if_flags & IFF_UP) 3803 dc_init(sc); 3804 3805 sc->suspended = 0; 3806 3807 splx(s); 3808 return (0); 3809} 3810 3811/* 3812 * Stop all chip I/O so that the kernel's probe routines don't 3813 * get confused by errant DMAs when rebooting. 3814 */ 3815static void 3816dc_shutdown(device_t dev) 3817{ 3818 struct dc_softc *sc; 3819 3820 sc = device_get_softc(dev); 3821 3822 dc_stop(sc); 3823} 3824