if_dc.c revision 121433
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 35 * series chips and several workalikes including the following: 36 * 37 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 38 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 39 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 40 * ASIX Electronics AX88140A (www.asix.com.tw) 41 * ASIX Electronics AX88141 (www.asix.com.tw) 42 * ADMtek AL981 (www.admtek.com.tw) 43 * ADMtek AN985 (www.admtek.com.tw) 44 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 45 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 46 * Accton EN1217 (www.accton.com) 47 * Xircom X3201 (www.xircom.com) 48 * Abocom FE2500 49 * Conexant LANfinity (www.conexant.com) 50 * 3Com OfficeConnect 10/100B 3CSOHO100B (www.3com.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64/* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92#include <sys/cdefs.h> 93__FBSDID("$FreeBSD: head/sys/dev/dc/if_dc.c 121433 2003-10-23 16:57:38Z imp $"); 94 95#include <sys/param.h> 96#include <sys/endian.h> 97#include <sys/systm.h> 98#include <sys/sockio.h> 99#include <sys/mbuf.h> 100#include <sys/malloc.h> 101#include <sys/kernel.h> 102#include <sys/socket.h> 103#include <sys/sysctl.h> 104 105#include <net/if.h> 106#include <net/if_arp.h> 107#include <net/ethernet.h> 108#include <net/if_dl.h> 109#include <net/if_media.h> 110#include <net/if_types.h> 111#include <net/if_vlan_var.h> 112 113#include <net/bpf.h> 114 115#include <machine/bus_pio.h> 116#include <machine/bus_memio.h> 117#include <machine/bus.h> 118#include <machine/resource.h> 119#include <sys/bus.h> 120#include <sys/rman.h> 121 122#include <dev/mii/mii.h> 123#include <dev/mii/miivar.h> 124 125#include <dev/pci/pcireg.h> 126#include <dev/pci/pcivar.h> 127 128#define DC_USEIOSPACE 129#ifdef __alpha__ 130#define SRM_MEDIA 131#endif 132 133#include <pci/if_dcreg.h> 134 135MODULE_DEPEND(dc, pci, 1, 1, 1); 136MODULE_DEPEND(dc, ether, 1, 1, 1); 137MODULE_DEPEND(dc, miibus, 1, 1, 1); 138 139/* "controller miibus0" required. See GENERIC if you get errors here. */ 140#include "miibus_if.h" 141 142/* 143 * Various supported device vendors/types and their names. 144 */ 145static struct dc_type dc_devs[] = { 146 { DC_VENDORID_DEC, DC_DEVICEID_21143, 147 "Intel 21143 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 149 "Davicom DM9009 10/100BaseTX" }, 150 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 151 "Davicom DM9100 10/100BaseTX" }, 152 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 153 "Davicom DM9102 10/100BaseTX" }, 154 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 155 "Davicom DM9102A 10/100BaseTX" }, 156 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 157 "ADMtek AL981 10/100BaseTX" }, 158 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 159 "ADMtek AN985 10/100BaseTX" }, 160 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 161 "ADMtek ADM9511 10/100BaseTX" }, 162 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 163 "ADMtek ADM9513 10/100BaseTX" }, 164 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 165 "Netgear FA511 10/100BaseTX" }, 166 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 167 "ASIX AX88140A 10/100BaseTX" }, 168 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 169 "ASIX AX88141 10/100BaseTX" }, 170 { DC_VENDORID_MX, DC_DEVICEID_98713, 171 "Macronix 98713 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_98713, 173 "Macronix 98713A 10/100BaseTX" }, 174 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 175 "Compex RL100-TX 10/100BaseTX" }, 176 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 177 "Compex RL100-TX 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_987x5, 179 "Macronix 98715/98715A 10/100BaseTX" }, 180 { DC_VENDORID_MX, DC_DEVICEID_987x5, 181 "Macronix 98715AEC-C 10/100BaseTX" }, 182 { DC_VENDORID_MX, DC_DEVICEID_987x5, 183 "Macronix 98725 10/100BaseTX" }, 184 { DC_VENDORID_MX, DC_DEVICEID_98727, 185 "Macronix 98727/98732 10/100BaseTX" }, 186 { DC_VENDORID_LO, DC_DEVICEID_82C115, 187 "LC82C115 PNIC II 10/100BaseTX" }, 188 { DC_VENDORID_LO, DC_DEVICEID_82C168, 189 "82c168 PNIC 10/100BaseTX" }, 190 { DC_VENDORID_LO, DC_DEVICEID_82C168, 191 "82c169 PNIC 10/100BaseTX" }, 192 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 193 "Accton EN1217 10/100BaseTX" }, 194 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 195 "Accton EN2242 MiniPCI 10/100BaseTX" }, 196 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 197 "Xircom X3201 10/100BaseTX" }, 198 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 199 "Abocom FE2500 10/100BaseTX" }, 200 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 201 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 202 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 203 "Hawking CB102 CardBus 10/100" }, 204 { DC_VENDORID_PLANEX, DC_DEVICEID_FNW3602T, 205 "PlaneX FNW-3602-T CardBus 10/100" }, 206 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 207 "3Com OfficeConnect 10/100B" }, 208 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN120, 209 "Microsoft MN-120 CardBus 10/100" }, 210 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130, 211 "Microsoft MN-130 10/100" }, 212 { DC_VENDORID_MICROSOFT, DC_DEVICEID_MSMN130_FAKE, 213 "Microsoft MN-130 10/100" }, 214 { 0, 0, NULL } 215}; 216 217static int dc_probe (device_t); 218static int dc_attach (device_t); 219static int dc_detach (device_t); 220static int dc_suspend (device_t); 221static int dc_resume (device_t); 222#ifndef BURN_BRIDGES 223static void dc_acpi (device_t); 224#endif 225static struct dc_type *dc_devtype (device_t); 226static int dc_newbuf (struct dc_softc *, int, int); 227static int dc_encap (struct dc_softc *, struct mbuf **); 228static void dc_pnic_rx_bug_war (struct dc_softc *, int); 229static int dc_rx_resync (struct dc_softc *); 230static void dc_rxeof (struct dc_softc *); 231static void dc_txeof (struct dc_softc *); 232static void dc_tick (void *); 233static void dc_tx_underrun (struct dc_softc *); 234static void dc_intr (void *); 235static void dc_start (struct ifnet *); 236static int dc_ioctl (struct ifnet *, u_long, caddr_t); 237static void dc_init (void *); 238static void dc_stop (struct dc_softc *); 239static void dc_watchdog (struct ifnet *); 240static void dc_shutdown (device_t); 241static int dc_ifmedia_upd (struct ifnet *); 242static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 243 244static void dc_delay (struct dc_softc *); 245static void dc_eeprom_idle (struct dc_softc *); 246static void dc_eeprom_putbyte (struct dc_softc *, int); 247static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 248static void dc_eeprom_getword_pnic 249 (struct dc_softc *, int, u_int16_t *); 250static void dc_eeprom_getword_xircom 251 (struct dc_softc *, int, u_int16_t *); 252static void dc_eeprom_width (struct dc_softc *); 253static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 254 255static void dc_mii_writebit (struct dc_softc *, int); 256static int dc_mii_readbit (struct dc_softc *); 257static void dc_mii_sync (struct dc_softc *); 258static void dc_mii_send (struct dc_softc *, u_int32_t, int); 259static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 260static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 261static int dc_miibus_readreg (device_t, int, int); 262static int dc_miibus_writereg (device_t, int, int, int); 263static void dc_miibus_statchg (device_t); 264static void dc_miibus_mediainit (device_t); 265 266static void dc_setcfg (struct dc_softc *, int); 267static u_int32_t dc_crc_le (struct dc_softc *, const uint8_t *); 268static u_int32_t dc_crc_be (const uint8_t *); 269static void dc_setfilt_21143 (struct dc_softc *); 270static void dc_setfilt_asix (struct dc_softc *); 271static void dc_setfilt_admtek (struct dc_softc *); 272static void dc_setfilt_xircom (struct dc_softc *); 273 274static void dc_setfilt (struct dc_softc *); 275 276static void dc_reset (struct dc_softc *); 277static int dc_list_rx_init (struct dc_softc *); 278static int dc_list_tx_init (struct dc_softc *); 279 280static void dc_read_srom (struct dc_softc *, int); 281static void dc_parse_21143_srom (struct dc_softc *); 282static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 283static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 284static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 285static void dc_apply_fixup (struct dc_softc *, int); 286 287static void dc_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t, 288 int); 289static void dc_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t, 290 int); 291 292#ifdef DC_USEIOSPACE 293#define DC_RES SYS_RES_IOPORT 294#define DC_RID DC_PCI_CFBIO 295#else 296#define DC_RES SYS_RES_MEMORY 297#define DC_RID DC_PCI_CFBMA 298#endif 299 300static device_method_t dc_methods[] = { 301 /* Device interface */ 302 DEVMETHOD(device_probe, dc_probe), 303 DEVMETHOD(device_attach, dc_attach), 304 DEVMETHOD(device_detach, dc_detach), 305 DEVMETHOD(device_suspend, dc_suspend), 306 DEVMETHOD(device_resume, dc_resume), 307 DEVMETHOD(device_shutdown, dc_shutdown), 308 309 /* bus interface */ 310 DEVMETHOD(bus_print_child, bus_generic_print_child), 311 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 312 313 /* MII interface */ 314 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 315 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 316 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 317 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 318 319 { 0, 0 } 320}; 321 322static driver_t dc_driver = { 323 "dc", 324 dc_methods, 325 sizeof(struct dc_softc) 326}; 327 328static devclass_t dc_devclass; 329#ifdef __i386__ 330static int dc_quick = 1; 331SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, &dc_quick, 0, 332 "do not mdevget in dc driver"); 333#endif 334 335DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 336DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 337DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 338 339#define DC_SETBIT(sc, reg, x) \ 340 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 341 342#define DC_CLRBIT(sc, reg, x) \ 343 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 344 345#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 346#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 347 348#define IS_MPSAFE 0 349 350static void 351dc_delay(struct dc_softc *sc) 352{ 353 int idx; 354 355 for (idx = (300 / 33) + 1; idx > 0; idx--) 356 CSR_READ_4(sc, DC_BUSCTL); 357} 358 359static void 360dc_eeprom_width(struct dc_softc *sc) 361{ 362 int i; 363 364 /* Force EEPROM to idle state. */ 365 dc_eeprom_idle(sc); 366 367 /* Enter EEPROM access mode. */ 368 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 369 dc_delay(sc); 370 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 371 dc_delay(sc); 372 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 373 dc_delay(sc); 374 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 375 dc_delay(sc); 376 377 for (i = 3; i--;) { 378 if (6 & (1 << i)) 379 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 380 else 381 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 382 dc_delay(sc); 383 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 384 dc_delay(sc); 385 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 386 dc_delay(sc); 387 } 388 389 for (i = 1; i <= 12; i++) { 390 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 393 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 394 dc_delay(sc); 395 break; 396 } 397 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 398 dc_delay(sc); 399 } 400 401 /* Turn off EEPROM access mode. */ 402 dc_eeprom_idle(sc); 403 404 if (i < 4 || i > 12) 405 sc->dc_romwidth = 6; 406 else 407 sc->dc_romwidth = i; 408 409 /* Enter EEPROM access mode. */ 410 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 411 dc_delay(sc); 412 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 413 dc_delay(sc); 414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 415 dc_delay(sc); 416 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 417 dc_delay(sc); 418 419 /* Turn off EEPROM access mode. */ 420 dc_eeprom_idle(sc); 421} 422 423static void 424dc_eeprom_idle(struct dc_softc *sc) 425{ 426 int i; 427 428 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 429 dc_delay(sc); 430 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 431 dc_delay(sc); 432 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 433 dc_delay(sc); 434 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 435 dc_delay(sc); 436 437 for (i = 0; i < 25; i++) { 438 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 439 dc_delay(sc); 440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 441 dc_delay(sc); 442 } 443 444 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 445 dc_delay(sc); 446 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 447 dc_delay(sc); 448 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 449} 450 451/* 452 * Send a read command and address to the EEPROM, check for ACK. 453 */ 454static void 455dc_eeprom_putbyte(struct dc_softc *sc, int addr) 456{ 457 int d, i; 458 459 d = DC_EECMD_READ >> 6; 460 for (i = 3; i--; ) { 461 if (d & (1 << i)) 462 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 463 else 464 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 465 dc_delay(sc); 466 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 467 dc_delay(sc); 468 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 469 dc_delay(sc); 470 } 471 472 /* 473 * Feed in each bit and strobe the clock. 474 */ 475 for (i = sc->dc_romwidth; i--;) { 476 if (addr & (1 << i)) { 477 SIO_SET(DC_SIO_EE_DATAIN); 478 } else { 479 SIO_CLR(DC_SIO_EE_DATAIN); 480 } 481 dc_delay(sc); 482 SIO_SET(DC_SIO_EE_CLK); 483 dc_delay(sc); 484 SIO_CLR(DC_SIO_EE_CLK); 485 dc_delay(sc); 486 } 487} 488 489/* 490 * Read a word of data stored in the EEPROM at address 'addr.' 491 * The PNIC 82c168/82c169 has its own non-standard way to read 492 * the EEPROM. 493 */ 494static void 495dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 496{ 497 int i; 498 u_int32_t r; 499 500 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ | addr); 501 502 for (i = 0; i < DC_TIMEOUT; i++) { 503 DELAY(1); 504 r = CSR_READ_4(sc, DC_SIO); 505 if (!(r & DC_PN_SIOCTL_BUSY)) { 506 *dest = (u_int16_t)(r & 0xFFFF); 507 return; 508 } 509 } 510} 511 512/* 513 * Read a word of data stored in the EEPROM at address 'addr.' 514 * The Xircom X3201 has its own non-standard way to read 515 * the EEPROM, too. 516 */ 517static void 518dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 519{ 520 521 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 522 523 addr *= 2; 524 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 525 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; 526 addr += 1; 527 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 528 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; 529 530 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 531} 532 533/* 534 * Read a word of data stored in the EEPROM at address 'addr.' 535 */ 536static void 537dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 538{ 539 int i; 540 u_int16_t word = 0; 541 542 /* Force EEPROM to idle state. */ 543 dc_eeprom_idle(sc); 544 545 /* Enter EEPROM access mode. */ 546 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 547 dc_delay(sc); 548 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 549 dc_delay(sc); 550 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 551 dc_delay(sc); 552 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 553 dc_delay(sc); 554 555 /* 556 * Send address of word we want to read. 557 */ 558 dc_eeprom_putbyte(sc, addr); 559 560 /* 561 * Start reading bits from EEPROM. 562 */ 563 for (i = 0x8000; i; i >>= 1) { 564 SIO_SET(DC_SIO_EE_CLK); 565 dc_delay(sc); 566 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 567 word |= i; 568 dc_delay(sc); 569 SIO_CLR(DC_SIO_EE_CLK); 570 dc_delay(sc); 571 } 572 573 /* Turn off EEPROM access mode. */ 574 dc_eeprom_idle(sc); 575 576 *dest = word; 577} 578 579/* 580 * Read a sequence of words from the EEPROM. 581 */ 582static void 583dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 584{ 585 int i; 586 u_int16_t word = 0, *ptr; 587 588 for (i = 0; i < cnt; i++) { 589 if (DC_IS_PNIC(sc)) 590 dc_eeprom_getword_pnic(sc, off + i, &word); 591 else if (DC_IS_XIRCOM(sc)) 592 dc_eeprom_getword_xircom(sc, off + i, &word); 593 else 594 dc_eeprom_getword(sc, off + i, &word); 595 ptr = (u_int16_t *)(dest + (i * 2)); 596 if (swap) 597 *ptr = ntohs(word); 598 else 599 *ptr = word; 600 } 601} 602 603/* 604 * The following two routines are taken from the Macronix 98713 605 * Application Notes pp.19-21. 606 */ 607/* 608 * Write a bit to the MII bus. 609 */ 610static void 611dc_mii_writebit(struct dc_softc *sc, int bit) 612{ 613 614 if (bit) 615 CSR_WRITE_4(sc, DC_SIO, 616 DC_SIO_ROMCTL_WRITE | DC_SIO_MII_DATAOUT); 617 else 618 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 619 620 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 621 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 622} 623 624/* 625 * Read a bit from the MII bus. 626 */ 627static int 628dc_mii_readbit(struct dc_softc *sc) 629{ 630 631 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ | DC_SIO_MII_DIR); 632 CSR_READ_4(sc, DC_SIO); 633 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 634 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 635 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 636 return (1); 637 638 return (0); 639} 640 641/* 642 * Sync the PHYs by setting data bit and strobing the clock 32 times. 643 */ 644static void 645dc_mii_sync(struct dc_softc *sc) 646{ 647 int i; 648 649 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 650 651 for (i = 0; i < 32; i++) 652 dc_mii_writebit(sc, 1); 653} 654 655/* 656 * Clock a series of bits through the MII. 657 */ 658static void 659dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 660{ 661 int i; 662 663 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 664 dc_mii_writebit(sc, bits & i); 665} 666 667/* 668 * Read an PHY register through the MII. 669 */ 670static int 671dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 672{ 673 int i, ack; 674 675 DC_LOCK(sc); 676 677 /* 678 * Set up frame for RX. 679 */ 680 frame->mii_stdelim = DC_MII_STARTDELIM; 681 frame->mii_opcode = DC_MII_READOP; 682 frame->mii_turnaround = 0; 683 frame->mii_data = 0; 684 685 /* 686 * Sync the PHYs. 687 */ 688 dc_mii_sync(sc); 689 690 /* 691 * Send command/address info. 692 */ 693 dc_mii_send(sc, frame->mii_stdelim, 2); 694 dc_mii_send(sc, frame->mii_opcode, 2); 695 dc_mii_send(sc, frame->mii_phyaddr, 5); 696 dc_mii_send(sc, frame->mii_regaddr, 5); 697 698#ifdef notdef 699 /* Idle bit */ 700 dc_mii_writebit(sc, 1); 701 dc_mii_writebit(sc, 0); 702#endif 703 704 /* Check for ack. */ 705 ack = dc_mii_readbit(sc); 706 707 /* 708 * Now try reading data bits. If the ack failed, we still 709 * need to clock through 16 cycles to keep the PHY(s) in sync. 710 */ 711 if (ack) { 712 for (i = 0; i < 16; i++) 713 dc_mii_readbit(sc); 714 goto fail; 715 } 716 717 for (i = 0x8000; i; i >>= 1) { 718 if (!ack) { 719 if (dc_mii_readbit(sc)) 720 frame->mii_data |= i; 721 } 722 } 723 724fail: 725 726 dc_mii_writebit(sc, 0); 727 dc_mii_writebit(sc, 0); 728 729 DC_UNLOCK(sc); 730 731 if (ack) 732 return (1); 733 return (0); 734} 735 736/* 737 * Write to a PHY register through the MII. 738 */ 739static int 740dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 741{ 742 743 DC_LOCK(sc); 744 /* 745 * Set up frame for TX. 746 */ 747 748 frame->mii_stdelim = DC_MII_STARTDELIM; 749 frame->mii_opcode = DC_MII_WRITEOP; 750 frame->mii_turnaround = DC_MII_TURNAROUND; 751 752 /* 753 * Sync the PHYs. 754 */ 755 dc_mii_sync(sc); 756 757 dc_mii_send(sc, frame->mii_stdelim, 2); 758 dc_mii_send(sc, frame->mii_opcode, 2); 759 dc_mii_send(sc, frame->mii_phyaddr, 5); 760 dc_mii_send(sc, frame->mii_regaddr, 5); 761 dc_mii_send(sc, frame->mii_turnaround, 2); 762 dc_mii_send(sc, frame->mii_data, 16); 763 764 /* Idle bit. */ 765 dc_mii_writebit(sc, 0); 766 dc_mii_writebit(sc, 0); 767 768 DC_UNLOCK(sc); 769 770 return (0); 771} 772 773static int 774dc_miibus_readreg(device_t dev, int phy, int reg) 775{ 776 struct dc_mii_frame frame; 777 struct dc_softc *sc; 778 int i, rval, phy_reg = 0; 779 780 sc = device_get_softc(dev); 781 bzero(&frame, sizeof(frame)); 782 783 /* 784 * Note: both the AL981 and AN985 have internal PHYs, 785 * however the AL981 provides direct access to the PHY 786 * registers while the AN985 uses a serial MII interface. 787 * The AN985's MII interface is also buggy in that you 788 * can read from any MII address (0 to 31), but only address 1 789 * behaves normally. To deal with both cases, we pretend 790 * that the PHY is at MII address 1. 791 */ 792 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 793 return (0); 794 795 /* 796 * Note: the ukphy probes of the RS7112 report a PHY at 797 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 798 * so we only respond to correct one. 799 */ 800 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 801 return (0); 802 803 if (sc->dc_pmode != DC_PMODE_MII) { 804 if (phy == (MII_NPHY - 1)) { 805 switch (reg) { 806 case MII_BMSR: 807 /* 808 * Fake something to make the probe 809 * code think there's a PHY here. 810 */ 811 return (BMSR_MEDIAMASK); 812 break; 813 case MII_PHYIDR1: 814 if (DC_IS_PNIC(sc)) 815 return (DC_VENDORID_LO); 816 return (DC_VENDORID_DEC); 817 break; 818 case MII_PHYIDR2: 819 if (DC_IS_PNIC(sc)) 820 return (DC_DEVICEID_82C168); 821 return (DC_DEVICEID_21143); 822 break; 823 default: 824 return (0); 825 break; 826 } 827 } else 828 return (0); 829 } 830 831 if (DC_IS_PNIC(sc)) { 832 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 833 (phy << 23) | (reg << 18)); 834 for (i = 0; i < DC_TIMEOUT; i++) { 835 DELAY(1); 836 rval = CSR_READ_4(sc, DC_PN_MII); 837 if (!(rval & DC_PN_MII_BUSY)) { 838 rval &= 0xFFFF; 839 return (rval == 0xFFFF ? 0 : rval); 840 } 841 } 842 return (0); 843 } 844 845 if (DC_IS_COMET(sc)) { 846 switch (reg) { 847 case MII_BMCR: 848 phy_reg = DC_AL_BMCR; 849 break; 850 case MII_BMSR: 851 phy_reg = DC_AL_BMSR; 852 break; 853 case MII_PHYIDR1: 854 phy_reg = DC_AL_VENID; 855 break; 856 case MII_PHYIDR2: 857 phy_reg = DC_AL_DEVID; 858 break; 859 case MII_ANAR: 860 phy_reg = DC_AL_ANAR; 861 break; 862 case MII_ANLPAR: 863 phy_reg = DC_AL_LPAR; 864 break; 865 case MII_ANER: 866 phy_reg = DC_AL_ANER; 867 break; 868 default: 869 printf("dc%d: phy_read: bad phy register %x\n", 870 sc->dc_unit, reg); 871 return (0); 872 break; 873 } 874 875 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 876 877 if (rval == 0xFFFF) 878 return (0); 879 return (rval); 880 } 881 882 frame.mii_phyaddr = phy; 883 frame.mii_regaddr = reg; 884 if (sc->dc_type == DC_TYPE_98713) { 885 phy_reg = CSR_READ_4(sc, DC_NETCFG); 886 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 887 } 888 dc_mii_readreg(sc, &frame); 889 if (sc->dc_type == DC_TYPE_98713) 890 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 891 892 return (frame.mii_data); 893} 894 895static int 896dc_miibus_writereg(device_t dev, int phy, int reg, int data) 897{ 898 struct dc_softc *sc; 899 struct dc_mii_frame frame; 900 int i, phy_reg = 0; 901 902 sc = device_get_softc(dev); 903 bzero(&frame, sizeof(frame)); 904 905 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 906 return (0); 907 908 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 909 return (0); 910 911 if (DC_IS_PNIC(sc)) { 912 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 913 (phy << 23) | (reg << 10) | data); 914 for (i = 0; i < DC_TIMEOUT; i++) { 915 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 916 break; 917 } 918 return (0); 919 } 920 921 if (DC_IS_COMET(sc)) { 922 switch (reg) { 923 case MII_BMCR: 924 phy_reg = DC_AL_BMCR; 925 break; 926 case MII_BMSR: 927 phy_reg = DC_AL_BMSR; 928 break; 929 case MII_PHYIDR1: 930 phy_reg = DC_AL_VENID; 931 break; 932 case MII_PHYIDR2: 933 phy_reg = DC_AL_DEVID; 934 break; 935 case MII_ANAR: 936 phy_reg = DC_AL_ANAR; 937 break; 938 case MII_ANLPAR: 939 phy_reg = DC_AL_LPAR; 940 break; 941 case MII_ANER: 942 phy_reg = DC_AL_ANER; 943 break; 944 default: 945 printf("dc%d: phy_write: bad phy register %x\n", 946 sc->dc_unit, reg); 947 return (0); 948 break; 949 } 950 951 CSR_WRITE_4(sc, phy_reg, data); 952 return (0); 953 } 954 955 frame.mii_phyaddr = phy; 956 frame.mii_regaddr = reg; 957 frame.mii_data = data; 958 959 if (sc->dc_type == DC_TYPE_98713) { 960 phy_reg = CSR_READ_4(sc, DC_NETCFG); 961 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 962 } 963 dc_mii_writereg(sc, &frame); 964 if (sc->dc_type == DC_TYPE_98713) 965 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 966 967 return (0); 968} 969 970static void 971dc_miibus_statchg(device_t dev) 972{ 973 struct dc_softc *sc; 974 struct mii_data *mii; 975 struct ifmedia *ifm; 976 977 sc = device_get_softc(dev); 978 if (DC_IS_ADMTEK(sc)) 979 return; 980 981 mii = device_get_softc(sc->dc_miibus); 982 ifm = &mii->mii_media; 983 if (DC_IS_DAVICOM(sc) && 984 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 985 dc_setcfg(sc, ifm->ifm_media); 986 sc->dc_if_media = ifm->ifm_media; 987 } else { 988 dc_setcfg(sc, mii->mii_media_active); 989 sc->dc_if_media = mii->mii_media_active; 990 } 991} 992 993/* 994 * Special support for DM9102A cards with HomePNA PHYs. Note: 995 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 996 * to be impossible to talk to the management interface of the DM9801 997 * PHY (its MDIO pin is not connected to anything). Consequently, 998 * the driver has to just 'know' about the additional mode and deal 999 * with it itself. *sigh* 1000 */ 1001static void 1002dc_miibus_mediainit(device_t dev) 1003{ 1004 struct dc_softc *sc; 1005 struct mii_data *mii; 1006 struct ifmedia *ifm; 1007 int rev; 1008 1009 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1010 1011 sc = device_get_softc(dev); 1012 mii = device_get_softc(sc->dc_miibus); 1013 ifm = &mii->mii_media; 1014 1015 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1016 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1017} 1018 1019#define DC_POLY 0xEDB88320 1020#define DC_BITS_512 9 1021#define DC_BITS_128 7 1022#define DC_BITS_64 6 1023 1024static u_int32_t 1025dc_crc_le(struct dc_softc *sc, const uint8_t *addr) 1026{ 1027 uint32_t idx, bit, data, crc; 1028 1029 /* Compute CRC for the address value. */ 1030 crc = 0xFFFFFFFF; /* initial value */ 1031 1032 for (idx = 0; idx < 6; idx++) { 1033 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1034 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1035 } 1036 1037 /* 1038 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1039 * chips is only 128 bits wide. 1040 */ 1041 if (sc->dc_flags & DC_128BIT_HASH) 1042 return (crc & ((1 << DC_BITS_128) - 1)); 1043 1044 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1045 if (sc->dc_flags & DC_64BIT_HASH) 1046 return (crc & ((1 << DC_BITS_64) - 1)); 1047 1048 /* Xircom's hash filtering table is different (read: weird) */ 1049 /* Xircom uses the LEAST significant bits */ 1050 if (DC_IS_XIRCOM(sc)) { 1051 if ((crc & 0x180) == 0x180) 1052 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 1053 else 1054 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + 1055 (12 << 4)); 1056 } 1057 1058 return (crc & ((1 << DC_BITS_512) - 1)); 1059} 1060 1061/* 1062 * Calculate CRC of a multicast group address, return the lower 6 bits. 1063 */ 1064static u_int32_t 1065dc_crc_be(const uint8_t *addr) 1066{ 1067 uint32_t crc, carry; 1068 int i, j; 1069 uint8_t c; 1070 1071 /* Compute CRC for the address value. */ 1072 crc = 0xFFFFFFFF; /* initial value */ 1073 1074 for (i = 0; i < 6; i++) { 1075 c = *(addr + i); 1076 for (j = 0; j < 8; j++) { 1077 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1078 crc <<= 1; 1079 c >>= 1; 1080 if (carry) 1081 crc = (crc ^ 0x04c11db6) | carry; 1082 } 1083 } 1084 1085 /* Return the filter bit position. */ 1086 return ((crc >> 26) & 0x0000003F); 1087} 1088 1089/* 1090 * 21143-style RX filter setup routine. Filter programming is done by 1091 * downloading a special setup frame into the TX engine. 21143, Macronix, 1092 * PNIC, PNIC II and Davicom chips are programmed this way. 1093 * 1094 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1095 * address (our node address) and a 512-bit hash filter for multicast 1096 * frames. We also sneak the broadcast address into the hash filter since 1097 * we need that too. 1098 */ 1099static void 1100dc_setfilt_21143(struct dc_softc *sc) 1101{ 1102 struct dc_desc *sframe; 1103 u_int32_t h, *sp; 1104 struct ifmultiaddr *ifma; 1105 struct ifnet *ifp; 1106 int i; 1107 1108 ifp = &sc->arpcom.ac_if; 1109 1110 i = sc->dc_cdata.dc_tx_prod; 1111 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1112 sc->dc_cdata.dc_tx_cnt++; 1113 sframe = &sc->dc_ldata->dc_tx_list[i]; 1114 sp = sc->dc_cdata.dc_sbuf; 1115 bzero(sp, DC_SFRAME_LEN); 1116 1117 sframe->dc_data = htole32(sc->dc_saddr); 1118 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1119 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1120 1121 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1122 1123 /* If we want promiscuous mode, set the allframes bit. */ 1124 if (ifp->if_flags & IFF_PROMISC) 1125 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1126 else 1127 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1128 1129 if (ifp->if_flags & IFF_ALLMULTI) 1130 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1131 else 1132 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1133 1134 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1135 if (ifma->ifma_addr->sa_family != AF_LINK) 1136 continue; 1137 h = dc_crc_le(sc, 1138 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1139 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1140 } 1141 1142 if (ifp->if_flags & IFF_BROADCAST) { 1143 h = dc_crc_le(sc, ifp->if_broadcastaddr); 1144 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1145 } 1146 1147 /* Set our MAC address */ 1148 sp[39] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1149 sp[40] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1150 sp[41] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1151 1152 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1153 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1154 1155 /* 1156 * The PNIC takes an exceedingly long time to process its 1157 * setup frame; wait 10ms after posting the setup frame 1158 * before proceeding, just so it has time to swallow its 1159 * medicine. 1160 */ 1161 DELAY(10000); 1162 1163 ifp->if_timer = 5; 1164} 1165 1166static void 1167dc_setfilt_admtek(struct dc_softc *sc) 1168{ 1169 struct ifnet *ifp; 1170 struct ifmultiaddr *ifma; 1171 int h = 0; 1172 u_int32_t hashes[2] = { 0, 0 }; 1173 1174 ifp = &sc->arpcom.ac_if; 1175 1176 /* Init our MAC address. */ 1177 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1178 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1179 1180 /* If we want promiscuous mode, set the allframes bit. */ 1181 if (ifp->if_flags & IFF_PROMISC) 1182 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1183 else 1184 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1185 1186 if (ifp->if_flags & IFF_ALLMULTI) 1187 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1188 else 1189 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1190 1191 /* First, zot all the existing hash bits. */ 1192 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1193 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1194 1195 /* 1196 * If we're already in promisc or allmulti mode, we 1197 * don't have to bother programming the multicast filter. 1198 */ 1199 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1200 return; 1201 1202 /* Now program new ones. */ 1203 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1204 if (ifma->ifma_addr->sa_family != AF_LINK) 1205 continue; 1206 if (DC_IS_CENTAUR(sc)) 1207 h = dc_crc_le(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1208 else 1209 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1210 if (h < 32) 1211 hashes[0] |= (1 << h); 1212 else 1213 hashes[1] |= (1 << (h - 32)); 1214 } 1215 1216 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1217 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1218} 1219 1220static void 1221dc_setfilt_asix(struct dc_softc *sc) 1222{ 1223 struct ifnet *ifp; 1224 struct ifmultiaddr *ifma; 1225 int h = 0; 1226 u_int32_t hashes[2] = { 0, 0 }; 1227 1228 ifp = &sc->arpcom.ac_if; 1229 1230 /* Init our MAC address */ 1231 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1232 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1233 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1234 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1235 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1236 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1237 1238 /* If we want promiscuous mode, set the allframes bit. */ 1239 if (ifp->if_flags & IFF_PROMISC) 1240 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1241 else 1242 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1243 1244 if (ifp->if_flags & IFF_ALLMULTI) 1245 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1246 else 1247 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1248 1249 /* 1250 * The ASIX chip has a special bit to enable reception 1251 * of broadcast frames. 1252 */ 1253 if (ifp->if_flags & IFF_BROADCAST) 1254 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1255 else 1256 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1257 1258 /* first, zot all the existing hash bits */ 1259 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1260 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1261 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1262 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1263 1264 /* 1265 * If we're already in promisc or allmulti mode, we 1266 * don't have to bother programming the multicast filter. 1267 */ 1268 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) 1269 return; 1270 1271 /* now program new ones */ 1272 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1273 if (ifma->ifma_addr->sa_family != AF_LINK) 1274 continue; 1275 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1276 if (h < 32) 1277 hashes[0] |= (1 << h); 1278 else 1279 hashes[1] |= (1 << (h - 32)); 1280 } 1281 1282 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1283 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1284 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1285 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1286} 1287 1288static void 1289dc_setfilt_xircom(struct dc_softc *sc) 1290{ 1291 struct ifnet *ifp; 1292 struct ifmultiaddr *ifma; 1293 struct dc_desc *sframe; 1294 u_int32_t h, *sp; 1295 int i; 1296 1297 ifp = &sc->arpcom.ac_if; 1298 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1299 1300 i = sc->dc_cdata.dc_tx_prod; 1301 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1302 sc->dc_cdata.dc_tx_cnt++; 1303 sframe = &sc->dc_ldata->dc_tx_list[i]; 1304 sp = sc->dc_cdata.dc_sbuf; 1305 bzero(sp, DC_SFRAME_LEN); 1306 1307 sframe->dc_data = htole32(sc->dc_saddr); 1308 sframe->dc_ctl = htole32(DC_SFRAME_LEN | DC_TXCTL_SETUP | 1309 DC_TXCTL_TLINK | DC_FILTER_HASHPERF | DC_TXCTL_FINT); 1310 1311 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)sc->dc_cdata.dc_sbuf; 1312 1313 /* If we want promiscuous mode, set the allframes bit. */ 1314 if (ifp->if_flags & IFF_PROMISC) 1315 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1316 else 1317 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1318 1319 if (ifp->if_flags & IFF_ALLMULTI) 1320 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1321 else 1322 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1323 1324 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1325 if (ifma->ifma_addr->sa_family != AF_LINK) 1326 continue; 1327 h = dc_crc_le(sc, 1328 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1329 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1330 } 1331 1332 if (ifp->if_flags & IFF_BROADCAST) { 1333 h = dc_crc_le(sc, ifp->if_broadcastaddr); 1334 sp[h >> 4] |= htole32(1 << (h & 0xF)); 1335 } 1336 1337 /* Set our MAC address */ 1338 sp[0] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1339 sp[1] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1340 sp[2] = DC_SP_MAC(((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1341 1342 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1343 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1344 ifp->if_flags |= IFF_RUNNING; 1345 sframe->dc_status = htole32(DC_TXSTAT_OWN); 1346 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1347 1348 /* 1349 * Wait some time... 1350 */ 1351 DELAY(1000); 1352 1353 ifp->if_timer = 5; 1354} 1355 1356static void 1357dc_setfilt(struct dc_softc *sc) 1358{ 1359 1360 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1361 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1362 dc_setfilt_21143(sc); 1363 1364 if (DC_IS_ASIX(sc)) 1365 dc_setfilt_asix(sc); 1366 1367 if (DC_IS_ADMTEK(sc)) 1368 dc_setfilt_admtek(sc); 1369 1370 if (DC_IS_XIRCOM(sc)) 1371 dc_setfilt_xircom(sc); 1372} 1373 1374/* 1375 * In order to fiddle with the 'full-duplex' and '100Mbps' bits in 1376 * the netconfig register, we first have to put the transmit and/or 1377 * receive logic in the idle state. 1378 */ 1379static void 1380dc_setcfg(struct dc_softc *sc, int media) 1381{ 1382 int i, restart = 0, watchdogreg; 1383 u_int32_t isr; 1384 1385 if (IFM_SUBTYPE(media) == IFM_NONE) 1386 return; 1387 1388 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)) { 1389 restart = 1; 1390 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON | DC_NETCFG_RX_ON)); 1391 1392 for (i = 0; i < DC_TIMEOUT; i++) { 1393 isr = CSR_READ_4(sc, DC_ISR); 1394 if (isr & DC_ISR_TX_IDLE && 1395 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1396 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1397 break; 1398 DELAY(10); 1399 } 1400 1401 if (i == DC_TIMEOUT) 1402 printf("dc%d: failed to force tx and " 1403 "rx to idle state\n", sc->dc_unit); 1404 } 1405 1406 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1407 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1408 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1409 if (sc->dc_pmode == DC_PMODE_MII) { 1410 if (DC_IS_INTEL(sc)) { 1411 /* There's a write enable bit here that reads as 1. */ 1412 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1413 watchdogreg &= ~DC_WDOG_CTLWREN; 1414 watchdogreg |= DC_WDOG_JABBERDIS; 1415 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1416 } else { 1417 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1418 } 1419 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1420 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1421 if (sc->dc_type == DC_TYPE_98713) 1422 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1423 DC_NETCFG_SCRAMBLER)); 1424 if (!DC_IS_DAVICOM(sc)) 1425 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1426 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1427 if (DC_IS_INTEL(sc)) 1428 dc_apply_fixup(sc, IFM_AUTO); 1429 } else { 1430 if (DC_IS_PNIC(sc)) { 1431 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1432 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1433 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1434 } 1435 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1437 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1438 if (DC_IS_INTEL(sc)) 1439 dc_apply_fixup(sc, 1440 (media & IFM_GMASK) == IFM_FDX ? 1441 IFM_100_TX | IFM_FDX : IFM_100_TX); 1442 } 1443 } 1444 1445 if (IFM_SUBTYPE(media) == IFM_10_T) { 1446 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1447 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1448 if (sc->dc_pmode == DC_PMODE_MII) { 1449 /* There's a write enable bit here that reads as 1. */ 1450 if (DC_IS_INTEL(sc)) { 1451 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1452 watchdogreg &= ~DC_WDOG_CTLWREN; 1453 watchdogreg |= DC_WDOG_JABBERDIS; 1454 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1455 } else { 1456 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1457 } 1458 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS | 1459 DC_NETCFG_PORTSEL | DC_NETCFG_SCRAMBLER)); 1460 if (sc->dc_type == DC_TYPE_98713) 1461 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1462 if (!DC_IS_DAVICOM(sc)) 1463 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1464 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1465 if (DC_IS_INTEL(sc)) 1466 dc_apply_fixup(sc, IFM_AUTO); 1467 } else { 1468 if (DC_IS_PNIC(sc)) { 1469 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1470 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1471 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1472 } 1473 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1474 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1475 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1476 if (DC_IS_INTEL(sc)) { 1477 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1478 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1479 if ((media & IFM_GMASK) == IFM_FDX) 1480 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1481 else 1482 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1483 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1484 DC_CLRBIT(sc, DC_10BTCTRL, 1485 DC_TCTL_AUTONEGENBL); 1486 dc_apply_fixup(sc, 1487 (media & IFM_GMASK) == IFM_FDX ? 1488 IFM_10_T | IFM_FDX : IFM_10_T); 1489 DELAY(20000); 1490 } 1491 } 1492 } 1493 1494 /* 1495 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1496 * PHY and we want HomePNA mode, set the portsel bit to turn 1497 * on the external MII port. 1498 */ 1499 if (DC_IS_DAVICOM(sc)) { 1500 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1501 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1502 sc->dc_link = 1; 1503 } else { 1504 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1505 } 1506 } 1507 1508 if ((media & IFM_GMASK) == IFM_FDX) { 1509 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1510 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1511 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1512 } else { 1513 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1514 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1515 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1516 } 1517 1518 if (restart) 1519 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON | DC_NETCFG_RX_ON); 1520} 1521 1522static void 1523dc_reset(struct dc_softc *sc) 1524{ 1525 int i; 1526 1527 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1528 1529 for (i = 0; i < DC_TIMEOUT; i++) { 1530 DELAY(10); 1531 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1532 break; 1533 } 1534 1535 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1536 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1537 DELAY(10000); 1538 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1539 i = 0; 1540 } 1541 1542 if (i == DC_TIMEOUT) 1543 printf("dc%d: reset never completed!\n", sc->dc_unit); 1544 1545 /* Wait a little while for the chip to get its brains in order. */ 1546 DELAY(1000); 1547 1548 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1549 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1550 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1551 1552 /* 1553 * Bring the SIA out of reset. In some cases, it looks 1554 * like failing to unreset the SIA soon enough gets it 1555 * into a state where it will never come out of reset 1556 * until we reset the whole chip again. 1557 */ 1558 if (DC_IS_INTEL(sc)) { 1559 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1560 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1561 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1562 } 1563} 1564 1565static struct dc_type * 1566dc_devtype(device_t dev) 1567{ 1568 struct dc_type *t; 1569 u_int32_t rev; 1570 1571 t = dc_devs; 1572 1573 while (t->dc_name != NULL) { 1574 if ((pci_get_vendor(dev) == t->dc_vid) && 1575 (pci_get_device(dev) == t->dc_did)) { 1576 /* Check the PCI revision */ 1577 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1578 if (t->dc_did == DC_DEVICEID_98713 && 1579 rev >= DC_REVISION_98713A) 1580 t++; 1581 if (t->dc_did == DC_DEVICEID_98713_CP && 1582 rev >= DC_REVISION_98713A) 1583 t++; 1584 if (t->dc_did == DC_DEVICEID_987x5 && 1585 rev >= DC_REVISION_98715AEC_C) 1586 t++; 1587 if (t->dc_did == DC_DEVICEID_987x5 && 1588 rev >= DC_REVISION_98725) 1589 t++; 1590 if (t->dc_did == DC_DEVICEID_AX88140A && 1591 rev >= DC_REVISION_88141) 1592 t++; 1593 if (t->dc_did == DC_DEVICEID_82C168 && 1594 rev >= DC_REVISION_82C169) 1595 t++; 1596 if (t->dc_did == DC_DEVICEID_DM9102 && 1597 rev >= DC_REVISION_DM9102A) 1598 t++; 1599 /* 1600 * The Microsoft MN-130 has a device ID of 0x0002, 1601 * which happens to be the same as the PNIC 82c168. 1602 * To keep dc_attach() from getting confused, we 1603 * pretend its ID is something different. 1604 * XXX: ideally, dc_attach() should be checking 1605 * vendorid+deviceid together to avoid such 1606 * collisions. 1607 */ 1608 if (t->dc_vid == DC_VENDORID_MICROSOFT && 1609 t->dc_did == DC_DEVICEID_MSMN130) 1610 t++; 1611 return (t); 1612 } 1613 t++; 1614 } 1615 1616 return (NULL); 1617} 1618 1619/* 1620 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1621 * IDs against our list and return a device name if we find a match. 1622 * We do a little bit of extra work to identify the exact type of 1623 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1624 * but different revision IDs. The same is true for 98715/98715A 1625 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1626 * cases, the exact chip revision affects driver behavior. 1627 */ 1628static int 1629dc_probe(device_t dev) 1630{ 1631 struct dc_type *t; 1632 1633 t = dc_devtype(dev); 1634 1635 if (t != NULL) { 1636 device_set_desc(dev, t->dc_name); 1637 return (0); 1638 } 1639 1640 return (ENXIO); 1641} 1642 1643#ifndef BURN_BRIDGES 1644static void 1645dc_acpi(device_t dev) 1646{ 1647 int unit; 1648 u_int32_t iobase, membase, irq; 1649 1650 unit = device_get_unit(dev); 1651 1652 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1653 /* Save important PCI config data. */ 1654 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1655 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1656 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1657 1658 /* Reset the power state. */ 1659 printf("dc%d: chip is in D%d power mode " 1660 "-- setting to D0\n", unit, 1661 pci_get_powerstate(dev)); 1662 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1663 1664 /* Restore PCI config data. */ 1665 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1666 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1667 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1668 } 1669} 1670#endif 1671 1672static void 1673dc_apply_fixup(struct dc_softc *sc, int media) 1674{ 1675 struct dc_mediainfo *m; 1676 u_int8_t *p; 1677 int i; 1678 u_int32_t reg; 1679 1680 m = sc->dc_mi; 1681 1682 while (m != NULL) { 1683 if (m->dc_media == media) 1684 break; 1685 m = m->dc_next; 1686 } 1687 1688 if (m == NULL) 1689 return; 1690 1691 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1692 reg = (p[0] | (p[1] << 8)) << 16; 1693 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1694 } 1695 1696 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1697 reg = (p[0] | (p[1] << 8)) << 16; 1698 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1699 } 1700} 1701 1702static void 1703dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1704{ 1705 struct dc_mediainfo *m; 1706 1707 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1708 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT) { 1709 case DC_SIA_CODE_10BT: 1710 m->dc_media = IFM_10_T; 1711 break; 1712 case DC_SIA_CODE_10BT_FDX: 1713 m->dc_media = IFM_10_T | IFM_FDX; 1714 break; 1715 case DC_SIA_CODE_10B2: 1716 m->dc_media = IFM_10_2; 1717 break; 1718 case DC_SIA_CODE_10B5: 1719 m->dc_media = IFM_10_5; 1720 break; 1721 default: 1722 break; 1723 } 1724 1725 /* 1726 * We need to ignore CSR13, CSR14, CSR15 for SIA mode. 1727 * Things apparently already work for cards that do 1728 * supply Media Specific Data. 1729 */ 1730 if (l->dc_sia_code & DC_SIA_CODE_EXT) { 1731 m->dc_gp_len = 2; 1732 m->dc_gp_ptr = 1733 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1734 } else { 1735 m->dc_gp_len = 2; 1736 m->dc_gp_ptr = 1737 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1738 } 1739 1740 m->dc_next = sc->dc_mi; 1741 sc->dc_mi = m; 1742 1743 sc->dc_pmode = DC_PMODE_SIA; 1744} 1745 1746static void 1747dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1748{ 1749 struct dc_mediainfo *m; 1750 1751 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1752 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1753 m->dc_media = IFM_100_TX; 1754 1755 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1756 m->dc_media = IFM_100_TX | IFM_FDX; 1757 1758 m->dc_gp_len = 2; 1759 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1760 1761 m->dc_next = sc->dc_mi; 1762 sc->dc_mi = m; 1763 1764 sc->dc_pmode = DC_PMODE_SYM; 1765} 1766 1767static void 1768dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1769{ 1770 struct dc_mediainfo *m; 1771 u_int8_t *p; 1772 1773 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT | M_ZERO); 1774 /* We abuse IFM_AUTO to represent MII. */ 1775 m->dc_media = IFM_AUTO; 1776 m->dc_gp_len = l->dc_gpr_len; 1777 1778 p = (u_int8_t *)l; 1779 p += sizeof(struct dc_eblock_mii); 1780 m->dc_gp_ptr = p; 1781 p += 2 * l->dc_gpr_len; 1782 m->dc_reset_len = *p; 1783 p++; 1784 m->dc_reset_ptr = p; 1785 1786 m->dc_next = sc->dc_mi; 1787 sc->dc_mi = m; 1788} 1789 1790static void 1791dc_read_srom(struct dc_softc *sc, int bits) 1792{ 1793 int size; 1794 1795 size = 2 << bits; 1796 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1797 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1798} 1799 1800static void 1801dc_parse_21143_srom(struct dc_softc *sc) 1802{ 1803 struct dc_leaf_hdr *lhdr; 1804 struct dc_eblock_hdr *hdr; 1805 int have_mii, i, loff; 1806 char *ptr; 1807 1808 have_mii = 0; 1809 loff = sc->dc_srom[27]; 1810 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1811 1812 ptr = (char *)lhdr; 1813 ptr += sizeof(struct dc_leaf_hdr) - 1; 1814 /* 1815 * Look if we got a MII media block. 1816 */ 1817 for (i = 0; i < lhdr->dc_mcnt; i++) { 1818 hdr = (struct dc_eblock_hdr *)ptr; 1819 if (hdr->dc_type == DC_EBLOCK_MII) 1820 have_mii++; 1821 1822 ptr += (hdr->dc_len & 0x7F); 1823 ptr++; 1824 } 1825 1826 /* 1827 * Do the same thing again. Only use SIA and SYM media 1828 * blocks if no MII media block is available. 1829 */ 1830 ptr = (char *)lhdr; 1831 ptr += sizeof(struct dc_leaf_hdr) - 1; 1832 for (i = 0; i < lhdr->dc_mcnt; i++) { 1833 hdr = (struct dc_eblock_hdr *)ptr; 1834 switch (hdr->dc_type) { 1835 case DC_EBLOCK_MII: 1836 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1837 break; 1838 case DC_EBLOCK_SIA: 1839 if (! have_mii) 1840 dc_decode_leaf_sia(sc, 1841 (struct dc_eblock_sia *)hdr); 1842 break; 1843 case DC_EBLOCK_SYM: 1844 if (! have_mii) 1845 dc_decode_leaf_sym(sc, 1846 (struct dc_eblock_sym *)hdr); 1847 break; 1848 default: 1849 /* Don't care. Yet. */ 1850 break; 1851 } 1852 ptr += (hdr->dc_len & 0x7F); 1853 ptr++; 1854 } 1855} 1856 1857static void 1858dc_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1859{ 1860 u_int32_t *paddr; 1861 1862 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1863 paddr = arg; 1864 *paddr = segs->ds_addr; 1865} 1866 1867/* 1868 * Attach the interface. Allocate softc structures, do ifmedia 1869 * setup and ethernet/BPF attach. 1870 */ 1871static int 1872dc_attach(device_t dev) 1873{ 1874 int tmp = 0; 1875 u_char eaddr[ETHER_ADDR_LEN]; 1876 u_int32_t command; 1877 struct dc_softc *sc; 1878 struct ifnet *ifp; 1879 u_int32_t revision; 1880 int unit, error = 0, rid, mac_offset; 1881 int i; 1882 u_int8_t *mac; 1883 1884 sc = device_get_softc(dev); 1885 unit = device_get_unit(dev); 1886 1887 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1888 MTX_DEF | MTX_RECURSE); 1889#ifndef BURN_BRIDGES 1890 /* 1891 * Handle power management nonsense. 1892 */ 1893 dc_acpi(dev); 1894#endif 1895 /* 1896 * Map control/status registers. 1897 */ 1898 pci_enable_busmaster(dev); 1899 1900 rid = DC_RID; 1901 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1902 0, ~0, 1, RF_ACTIVE); 1903 1904 if (sc->dc_res == NULL) { 1905 printf("dc%d: couldn't map ports/memory\n", unit); 1906 error = ENXIO; 1907 goto fail; 1908 } 1909 1910 sc->dc_btag = rman_get_bustag(sc->dc_res); 1911 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1912 1913 /* Allocate interrupt. */ 1914 rid = 0; 1915 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1916 RF_SHAREABLE | RF_ACTIVE); 1917 1918 if (sc->dc_irq == NULL) { 1919 printf("dc%d: couldn't map interrupt\n", unit); 1920 error = ENXIO; 1921 goto fail; 1922 } 1923 1924 /* Need this info to decide on a chip type. */ 1925 sc->dc_info = dc_devtype(dev); 1926 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1927 1928 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1929 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1930 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1931 dc_eeprom_width(sc); 1932 1933 switch (sc->dc_info->dc_did) { 1934 case DC_DEVICEID_21143: 1935 sc->dc_type = DC_TYPE_21143; 1936 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1937 sc->dc_flags |= DC_REDUCED_MII_POLL; 1938 /* Save EEPROM contents so we can parse them later. */ 1939 dc_read_srom(sc, sc->dc_romwidth); 1940 break; 1941 case DC_DEVICEID_DM9009: 1942 case DC_DEVICEID_DM9100: 1943 case DC_DEVICEID_DM9102: 1944 sc->dc_type = DC_TYPE_DM9102; 1945 sc->dc_flags |= DC_TX_COALESCE | DC_TX_INTR_ALWAYS; 1946 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_TX_STORENFWD; 1947 sc->dc_flags |= DC_TX_ALIGN; 1948 sc->dc_pmode = DC_PMODE_MII; 1949 /* Increase the latency timer value. */ 1950 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1951 command &= 0xFFFF00FF; 1952 command |= 0x00008000; 1953 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1954 break; 1955 case DC_DEVICEID_AL981: 1956 sc->dc_type = DC_TYPE_AL981; 1957 sc->dc_flags |= DC_TX_USE_TX_INTR; 1958 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1959 sc->dc_pmode = DC_PMODE_MII; 1960 dc_read_srom(sc, sc->dc_romwidth); 1961 break; 1962 case DC_DEVICEID_AN985: 1963 case DC_DEVICEID_ADM9511: 1964 case DC_DEVICEID_ADM9513: 1965 case DC_DEVICEID_FA511: 1966 case DC_DEVICEID_FE2500: 1967 case DC_DEVICEID_EN2242: 1968 case DC_DEVICEID_HAWKING_PN672TX: 1969 case DC_DEVICEID_3CSOHOB: 1970 case DC_DEVICEID_MSMN120: 1971 case DC_DEVICEID_MSMN130_FAKE: /* XXX avoid collision with PNIC*/ 1972 sc->dc_type = DC_TYPE_AN985; 1973 sc->dc_flags |= DC_64BIT_HASH; 1974 sc->dc_flags |= DC_TX_USE_TX_INTR; 1975 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1976 sc->dc_pmode = DC_PMODE_MII; 1977 /* Don't read SROM for - auto-loaded on reset */ 1978 break; 1979 case DC_DEVICEID_98713: 1980 case DC_DEVICEID_98713_CP: 1981 if (revision < DC_REVISION_98713A) { 1982 sc->dc_type = DC_TYPE_98713; 1983 } 1984 if (revision >= DC_REVISION_98713A) { 1985 sc->dc_type = DC_TYPE_98713A; 1986 sc->dc_flags |= DC_21143_NWAY; 1987 } 1988 sc->dc_flags |= DC_REDUCED_MII_POLL; 1989 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 1990 break; 1991 case DC_DEVICEID_987x5: 1992 case DC_DEVICEID_EN1217: 1993 /* 1994 * Macronix MX98715AEC-C/D/E parts have only a 1995 * 128-bit hash table. We need to deal with these 1996 * in the same manner as the PNIC II so that we 1997 * get the right number of bits out of the 1998 * CRC routine. 1999 */ 2000 if (revision >= DC_REVISION_98715AEC_C && 2001 revision < DC_REVISION_98725) 2002 sc->dc_flags |= DC_128BIT_HASH; 2003 sc->dc_type = DC_TYPE_987x5; 2004 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2005 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2006 break; 2007 case DC_DEVICEID_98727: 2008 sc->dc_type = DC_TYPE_987x5; 2009 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR; 2010 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2011 break; 2012 case DC_DEVICEID_82C115: 2013 sc->dc_type = DC_TYPE_PNICII; 2014 sc->dc_flags |= DC_TX_POLL | DC_TX_USE_TX_INTR | DC_128BIT_HASH; 2015 sc->dc_flags |= DC_REDUCED_MII_POLL | DC_21143_NWAY; 2016 break; 2017 case DC_DEVICEID_82C168: 2018 sc->dc_type = DC_TYPE_PNIC; 2019 sc->dc_flags |= DC_TX_STORENFWD | DC_TX_INTR_ALWAYS; 2020 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2021 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2022 if (revision < DC_REVISION_82C169) 2023 sc->dc_pmode = DC_PMODE_SYM; 2024 break; 2025 case DC_DEVICEID_AX88140A: 2026 sc->dc_type = DC_TYPE_ASIX; 2027 sc->dc_flags |= DC_TX_USE_TX_INTR | DC_TX_INTR_FIRSTFRAG; 2028 sc->dc_flags |= DC_REDUCED_MII_POLL; 2029 sc->dc_pmode = DC_PMODE_MII; 2030 break; 2031 case DC_DEVICEID_X3201: 2032 sc->dc_type = DC_TYPE_XIRCOM; 2033 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2034 DC_TX_ALIGN; 2035 /* 2036 * We don't actually need to coalesce, but we're doing 2037 * it to obtain a double word aligned buffer. 2038 * The DC_TX_COALESCE flag is required. 2039 */ 2040 sc->dc_pmode = DC_PMODE_MII; 2041 break; 2042 case DC_DEVICEID_RS7112: 2043 sc->dc_type = DC_TYPE_CONEXANT; 2044 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2045 sc->dc_flags |= DC_REDUCED_MII_POLL; 2046 sc->dc_pmode = DC_PMODE_MII; 2047 dc_read_srom(sc, sc->dc_romwidth); 2048 break; 2049 default: 2050 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2051 sc->dc_info->dc_did); 2052 break; 2053 } 2054 2055 /* Save the cache line size. */ 2056 if (DC_IS_DAVICOM(sc)) 2057 sc->dc_cachesize = 0; 2058 else 2059 sc->dc_cachesize = pci_read_config(dev, 2060 DC_PCI_CFLT, 4) & 0xFF; 2061 2062 /* Reset the adapter. */ 2063 dc_reset(sc); 2064 2065 /* Take 21143 out of snooze mode */ 2066 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2067 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2068 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2069 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2070 } 2071 2072 /* 2073 * Try to learn something about the supported media. 2074 * We know that ASIX and ADMtek and Davicom devices 2075 * will *always* be using MII media, so that's a no-brainer. 2076 * The tricky ones are the Macronix/PNIC II and the 2077 * Intel 21143. 2078 */ 2079 if (DC_IS_INTEL(sc)) 2080 dc_parse_21143_srom(sc); 2081 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2082 if (sc->dc_type == DC_TYPE_98713) 2083 sc->dc_pmode = DC_PMODE_MII; 2084 else 2085 sc->dc_pmode = DC_PMODE_SYM; 2086 } else if (!sc->dc_pmode) 2087 sc->dc_pmode = DC_PMODE_MII; 2088 2089 /* 2090 * Get station address from the EEPROM. 2091 */ 2092 switch(sc->dc_type) { 2093 case DC_TYPE_98713: 2094 case DC_TYPE_98713A: 2095 case DC_TYPE_987x5: 2096 case DC_TYPE_PNICII: 2097 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2098 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2099 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2100 break; 2101 case DC_TYPE_PNIC: 2102 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2103 break; 2104 case DC_TYPE_DM9102: 2105 case DC_TYPE_21143: 2106 case DC_TYPE_ASIX: 2107 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2108 break; 2109 case DC_TYPE_AL981: 2110 case DC_TYPE_AN985: 2111 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc, DC_AL_PAR0); 2112 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc, DC_AL_PAR1); 2113 break; 2114 case DC_TYPE_CONEXANT: 2115 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 2116 ETHER_ADDR_LEN); 2117 break; 2118 case DC_TYPE_XIRCOM: 2119 /* The MAC comes from the CIS. */ 2120 mac = pci_get_ether(dev); 2121 if (!mac) { 2122 device_printf(dev, "No station address in CIS!\n"); 2123 error = ENXIO; 2124 goto fail; 2125 } 2126 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2127 break; 2128 default: 2129 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2130 break; 2131 } 2132 2133 /* 2134 * A 21143 or clone chip was detected. Inform the world. 2135 */ 2136 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2137 2138 sc->dc_unit = unit; 2139 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2140 2141 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 2142 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2143 BUS_SPACE_MAXADDR, NULL, NULL, sizeof(struct dc_list_data), 1, 2144 sizeof(struct dc_list_data), 0, NULL, NULL, &sc->dc_ltag); 2145 if (error) { 2146 printf("dc%d: failed to allocate busdma tag\n", unit); 2147 error = ENXIO; 2148 goto fail; 2149 } 2150 error = bus_dmamem_alloc(sc->dc_ltag, (void **)&sc->dc_ldata, 2151 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->dc_lmap); 2152 if (error) { 2153 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2154 error = ENXIO; 2155 goto fail; 2156 } 2157 error = bus_dmamap_load(sc->dc_ltag, sc->dc_lmap, sc->dc_ldata, 2158 sizeof(struct dc_list_data), dc_dma_map_addr, &sc->dc_laddr, 2159 BUS_DMA_NOWAIT); 2160 if (error) { 2161 printf("dc%d: cannot get address of the descriptors\n", unit); 2162 error = ENXIO; 2163 goto fail; 2164 } 2165 2166 /* 2167 * Allocate a busdma tag and DMA safe memory for the multicast 2168 * setup frame. 2169 */ 2170 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2171 BUS_SPACE_MAXADDR, NULL, NULL, DC_SFRAME_LEN + DC_MIN_FRAMELEN, 1, 2172 DC_SFRAME_LEN + DC_MIN_FRAMELEN, 0, NULL, NULL, &sc->dc_stag); 2173 if (error) { 2174 printf("dc%d: failed to allocate busdma tag\n", unit); 2175 error = ENXIO; 2176 goto fail; 2177 } 2178 error = bus_dmamem_alloc(sc->dc_stag, (void **)&sc->dc_cdata.dc_sbuf, 2179 BUS_DMA_NOWAIT, &sc->dc_smap); 2180 if (error) { 2181 printf("dc%d: failed to allocate DMA safe memory\n", unit); 2182 error = ENXIO; 2183 goto fail; 2184 } 2185 error = bus_dmamap_load(sc->dc_stag, sc->dc_smap, sc->dc_cdata.dc_sbuf, 2186 DC_SFRAME_LEN, dc_dma_map_addr, &sc->dc_saddr, BUS_DMA_NOWAIT); 2187 if (error) { 2188 printf("dc%d: cannot get address of the descriptors\n", unit); 2189 error = ENXIO; 2190 goto fail; 2191 } 2192 2193 /* Allocate a busdma tag for mbufs. */ 2194 error = bus_dma_tag_create(NULL, PAGE_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, 2195 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * DC_TX_LIST_CNT, 2196 DC_TX_LIST_CNT, MCLBYTES, 0, NULL, NULL, &sc->dc_mtag); 2197 if (error) { 2198 printf("dc%d: failed to allocate busdma tag\n", unit); 2199 error = ENXIO; 2200 goto fail; 2201 } 2202 2203 /* Create the TX/RX busdma maps. */ 2204 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2205 error = bus_dmamap_create(sc->dc_mtag, 0, 2206 &sc->dc_cdata.dc_tx_map[i]); 2207 if (error) { 2208 printf("dc%d: failed to init TX ring\n", unit); 2209 error = ENXIO; 2210 goto fail; 2211 } 2212 } 2213 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2214 error = bus_dmamap_create(sc->dc_mtag, 0, 2215 &sc->dc_cdata.dc_rx_map[i]); 2216 if (error) { 2217 printf("dc%d: failed to init RX ring\n", unit); 2218 error = ENXIO; 2219 goto fail; 2220 } 2221 } 2222 error = bus_dmamap_create(sc->dc_mtag, 0, &sc->dc_sparemap); 2223 if (error) { 2224 printf("dc%d: failed to init RX ring\n", unit); 2225 error = ENXIO; 2226 goto fail; 2227 } 2228 2229 ifp = &sc->arpcom.ac_if; 2230 ifp->if_softc = sc; 2231 ifp->if_unit = unit; 2232 ifp->if_name = "dc"; 2233 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2234 ifp->if_mtu = ETHERMTU; 2235 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2236 ifp->if_ioctl = dc_ioctl; 2237 ifp->if_start = dc_start; 2238 ifp->if_watchdog = dc_watchdog; 2239 ifp->if_init = dc_init; 2240 ifp->if_baudrate = 10000000; 2241 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2242 2243 /* 2244 * Do MII setup. If this is a 21143, check for a PHY on the 2245 * MII bus after applying any necessary fixups to twiddle the 2246 * GPIO bits. If we don't end up finding a PHY, restore the 2247 * old selection (SIA only or SIA/SYM) and attach the dcphy 2248 * driver instead. 2249 */ 2250 if (DC_IS_INTEL(sc)) { 2251 dc_apply_fixup(sc, IFM_AUTO); 2252 tmp = sc->dc_pmode; 2253 sc->dc_pmode = DC_PMODE_MII; 2254 } 2255 2256 error = mii_phy_probe(dev, &sc->dc_miibus, 2257 dc_ifmedia_upd, dc_ifmedia_sts); 2258 2259 if (error && DC_IS_INTEL(sc)) { 2260 sc->dc_pmode = tmp; 2261 if (sc->dc_pmode != DC_PMODE_SIA) 2262 sc->dc_pmode = DC_PMODE_SYM; 2263 sc->dc_flags |= DC_21143_NWAY; 2264 mii_phy_probe(dev, &sc->dc_miibus, 2265 dc_ifmedia_upd, dc_ifmedia_sts); 2266 /* 2267 * For non-MII cards, we need to have the 21143 2268 * drive the LEDs. Except there are some systems 2269 * like the NEC VersaPro NoteBook PC which have no 2270 * LEDs, and twiddling these bits has adverse effects 2271 * on them. (I.e. you suddenly can't get a link.) 2272 */ 2273 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2274 sc->dc_flags |= DC_TULIP_LEDS; 2275 error = 0; 2276 } 2277 2278 if (error) { 2279 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2280 goto fail; 2281 } 2282 2283 if (DC_IS_XIRCOM(sc)) { 2284 /* 2285 * setup General Purpose Port mode and data so the tulip 2286 * can talk to the MII. 2287 */ 2288 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2289 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2290 DELAY(10); 2291 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2292 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2293 DELAY(10); 2294 } 2295 2296 if (DC_IS_ADMTEK(sc)) { 2297 /* 2298 * Set automatic TX underrun recovery for the ADMtek chips 2299 */ 2300 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2301 } 2302 2303 /* 2304 * Tell the upper layer(s) we support long frames. 2305 */ 2306 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2307 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2308 2309 callout_init(&sc->dc_stat_ch, IS_MPSAFE ? CALLOUT_MPSAFE : 0); 2310 2311#ifdef SRM_MEDIA 2312 sc->dc_srm_media = 0; 2313 2314 /* Remember the SRM console media setting */ 2315 if (DC_IS_INTEL(sc)) { 2316 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2317 command &= ~(DC_CFDD_SNOOZE_MODE | DC_CFDD_SLEEP_MODE); 2318 switch ((command >> 8) & 0xff) { 2319 case 3: 2320 sc->dc_srm_media = IFM_10_T; 2321 break; 2322 case 4: 2323 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2324 break; 2325 case 5: 2326 sc->dc_srm_media = IFM_100_TX; 2327 break; 2328 case 6: 2329 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2330 break; 2331 } 2332 if (sc->dc_srm_media) 2333 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2334 } 2335#endif 2336 2337 /* 2338 * Call MI attach routine. 2339 */ 2340 ether_ifattach(ifp, eaddr); 2341 2342 /* Hook interrupt last to avoid having to lock softc */ 2343 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2344 (IS_MPSAFE ? INTR_MPSAFE : 0), 2345 dc_intr, sc, &sc->dc_intrhand); 2346 2347 if (error) { 2348 printf("dc%d: couldn't set up irq\n", unit); 2349 ether_ifdetach(ifp); 2350 goto fail; 2351 } 2352 2353fail: 2354 if (error) 2355 dc_detach(dev); 2356 return (error); 2357} 2358 2359/* 2360 * Shutdown hardware and free up resources. This can be called any 2361 * time after the mutex has been initialized. It is called in both 2362 * the error case in attach and the normal detach case so it needs 2363 * to be careful about only freeing resources that have actually been 2364 * allocated. 2365 */ 2366static int 2367dc_detach(device_t dev) 2368{ 2369 struct dc_softc *sc; 2370 struct ifnet *ifp; 2371 struct dc_mediainfo *m; 2372 int i; 2373 2374 sc = device_get_softc(dev); 2375 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2376 DC_LOCK(sc); 2377 2378 ifp = &sc->arpcom.ac_if; 2379 2380 /* These should only be active if attach succeeded */ 2381 if (device_is_attached(dev)) { 2382 dc_stop(sc); 2383 ether_ifdetach(ifp); 2384 } 2385 if (sc->dc_miibus) 2386 device_delete_child(dev, sc->dc_miibus); 2387 bus_generic_detach(dev); 2388 2389 if (sc->dc_intrhand) 2390 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2391 if (sc->dc_irq) 2392 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2393 if (sc->dc_res) 2394 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2395 2396 if (sc->dc_cdata.dc_sbuf != NULL) 2397 bus_dmamem_free(sc->dc_stag, sc->dc_cdata.dc_sbuf, sc->dc_smap); 2398 if (sc->dc_ldata != NULL) 2399 bus_dmamem_free(sc->dc_ltag, sc->dc_ldata, sc->dc_lmap); 2400 for (i = 0; i < DC_TX_LIST_CNT; i++) 2401 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_tx_map[i]); 2402 for (i = 0; i < DC_RX_LIST_CNT; i++) 2403 bus_dmamap_destroy(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2404 bus_dmamap_destroy(sc->dc_mtag, sc->dc_sparemap); 2405 if (sc->dc_stag) 2406 bus_dma_tag_destroy(sc->dc_stag); 2407 if (sc->dc_mtag) 2408 bus_dma_tag_destroy(sc->dc_mtag); 2409 if (sc->dc_ltag) 2410 bus_dma_tag_destroy(sc->dc_ltag); 2411 2412 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2413 2414 while (sc->dc_mi != NULL) { 2415 m = sc->dc_mi->dc_next; 2416 free(sc->dc_mi, M_DEVBUF); 2417 sc->dc_mi = m; 2418 } 2419 free(sc->dc_srom, M_DEVBUF); 2420 2421 DC_UNLOCK(sc); 2422 mtx_destroy(&sc->dc_mtx); 2423 2424 return (0); 2425} 2426 2427/* 2428 * Initialize the transmit descriptors. 2429 */ 2430static int 2431dc_list_tx_init(struct dc_softc *sc) 2432{ 2433 struct dc_chain_data *cd; 2434 struct dc_list_data *ld; 2435 int i, nexti; 2436 2437 cd = &sc->dc_cdata; 2438 ld = sc->dc_ldata; 2439 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2440 if (i == DC_TX_LIST_CNT - 1) 2441 nexti = 0; 2442 else 2443 nexti = i + 1; 2444 ld->dc_tx_list[i].dc_next = htole32(DC_TXDESC(sc, nexti)); 2445 cd->dc_tx_chain[i] = NULL; 2446 ld->dc_tx_list[i].dc_data = 0; 2447 ld->dc_tx_list[i].dc_ctl = 0; 2448 } 2449 2450 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2451 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2452 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2453 return (0); 2454} 2455 2456 2457/* 2458 * Initialize the RX descriptors and allocate mbufs for them. Note that 2459 * we arrange the descriptors in a closed ring, so that the last descriptor 2460 * points back to the first. 2461 */ 2462static int 2463dc_list_rx_init(struct dc_softc *sc) 2464{ 2465 struct dc_chain_data *cd; 2466 struct dc_list_data *ld; 2467 int i, nexti; 2468 2469 cd = &sc->dc_cdata; 2470 ld = sc->dc_ldata; 2471 2472 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2473 if (dc_newbuf(sc, i, 1) != 0) 2474 return (ENOBUFS); 2475 if (i == DC_RX_LIST_CNT - 1) 2476 nexti = 0; 2477 else 2478 nexti = i + 1; 2479 ld->dc_rx_list[i].dc_next = htole32(DC_RXDESC(sc, nexti)); 2480 } 2481 2482 cd->dc_rx_prod = 0; 2483 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2484 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2485 return (0); 2486} 2487 2488static void 2489dc_dma_map_rxbuf(arg, segs, nseg, mapsize, error) 2490 void *arg; 2491 bus_dma_segment_t *segs; 2492 int nseg; 2493 bus_size_t mapsize; 2494 int error; 2495{ 2496 struct dc_softc *sc; 2497 struct dc_desc *c; 2498 2499 sc = arg; 2500 c = &sc->dc_ldata->dc_rx_list[sc->dc_cdata.dc_rx_cur]; 2501 if (error) { 2502 sc->dc_cdata.dc_rx_err = error; 2503 return; 2504 } 2505 2506 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 2507 sc->dc_cdata.dc_rx_err = 0; 2508 c->dc_data = htole32(segs->ds_addr); 2509} 2510 2511/* 2512 * Initialize an RX descriptor and attach an MBUF cluster. 2513 */ 2514static int 2515dc_newbuf(struct dc_softc *sc, int i, int alloc) 2516{ 2517 struct mbuf *m_new; 2518 bus_dmamap_t tmp; 2519 int error; 2520 2521 if (alloc) { 2522 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2523 if (m_new == NULL) 2524 return (ENOBUFS); 2525 } else { 2526 m_new = sc->dc_cdata.dc_rx_chain[i]; 2527 m_new->m_data = m_new->m_ext.ext_buf; 2528 } 2529 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2530 m_adj(m_new, sizeof(u_int64_t)); 2531 2532 /* 2533 * If this is a PNIC chip, zero the buffer. This is part 2534 * of the workaround for the receive bug in the 82c168 and 2535 * 82c169 chips. 2536 */ 2537 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2538 bzero(mtod(m_new, char *), m_new->m_len); 2539 2540 /* No need to remap the mbuf if we're reusing it. */ 2541 if (alloc) { 2542 sc->dc_cdata.dc_rx_cur = i; 2543 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_sparemap, 2544 m_new, dc_dma_map_rxbuf, sc, 0); 2545 if (error) { 2546 m_freem(m_new); 2547 return (error); 2548 } 2549 if (sc->dc_cdata.dc_rx_err != 0) { 2550 m_freem(m_new); 2551 return (sc->dc_cdata.dc_rx_err); 2552 } 2553 bus_dmamap_unload(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i]); 2554 tmp = sc->dc_cdata.dc_rx_map[i]; 2555 sc->dc_cdata.dc_rx_map[i] = sc->dc_sparemap; 2556 sc->dc_sparemap = tmp; 2557 sc->dc_cdata.dc_rx_chain[i] = m_new; 2558 } 2559 2560 sc->dc_ldata->dc_rx_list[i].dc_ctl = htole32(DC_RXCTL_RLINK | DC_RXLEN); 2561 sc->dc_ldata->dc_rx_list[i].dc_status = htole32(DC_RXSTAT_OWN); 2562 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2563 BUS_DMASYNC_PREREAD); 2564 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 2565 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2566 return (0); 2567} 2568 2569/* 2570 * Grrrrr. 2571 * The PNIC chip has a terrible bug in it that manifests itself during 2572 * periods of heavy activity. The exact mode of failure if difficult to 2573 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2574 * will happen on slow machines. The bug is that sometimes instead of 2575 * uploading one complete frame during reception, it uploads what looks 2576 * like the entire contents of its FIFO memory. The frame we want is at 2577 * the end of the whole mess, but we never know exactly how much data has 2578 * been uploaded, so salvaging the frame is hard. 2579 * 2580 * There is only one way to do it reliably, and it's disgusting. 2581 * Here's what we know: 2582 * 2583 * - We know there will always be somewhere between one and three extra 2584 * descriptors uploaded. 2585 * 2586 * - We know the desired received frame will always be at the end of the 2587 * total data upload. 2588 * 2589 * - We know the size of the desired received frame because it will be 2590 * provided in the length field of the status word in the last descriptor. 2591 * 2592 * Here's what we do: 2593 * 2594 * - When we allocate buffers for the receive ring, we bzero() them. 2595 * This means that we know that the buffer contents should be all 2596 * zeros, except for data uploaded by the chip. 2597 * 2598 * - We also force the PNIC chip to upload frames that include the 2599 * ethernet CRC at the end. 2600 * 2601 * - We gather all of the bogus frame data into a single buffer. 2602 * 2603 * - We then position a pointer at the end of this buffer and scan 2604 * backwards until we encounter the first non-zero byte of data. 2605 * This is the end of the received frame. We know we will encounter 2606 * some data at the end of the frame because the CRC will always be 2607 * there, so even if the sender transmits a packet of all zeros, 2608 * we won't be fooled. 2609 * 2610 * - We know the size of the actual received frame, so we subtract 2611 * that value from the current pointer location. This brings us 2612 * to the start of the actual received packet. 2613 * 2614 * - We copy this into an mbuf and pass it on, along with the actual 2615 * frame length. 2616 * 2617 * The performance hit is tremendous, but it beats dropping frames all 2618 * the time. 2619 */ 2620 2621#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG | DC_RXSTAT_LASTFRAG) 2622static void 2623dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2624{ 2625 struct dc_desc *cur_rx; 2626 struct dc_desc *c = NULL; 2627 struct mbuf *m = NULL; 2628 unsigned char *ptr; 2629 int i, total_len; 2630 u_int32_t rxstat = 0; 2631 2632 i = sc->dc_pnic_rx_bug_save; 2633 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2634 ptr = sc->dc_pnic_rx_buf; 2635 bzero(ptr, DC_RXLEN * 5); 2636 2637 /* Copy all the bytes from the bogus buffers. */ 2638 while (1) { 2639 c = &sc->dc_ldata->dc_rx_list[i]; 2640 rxstat = le32toh(c->dc_status); 2641 m = sc->dc_cdata.dc_rx_chain[i]; 2642 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2643 ptr += DC_RXLEN; 2644 /* If this is the last buffer, break out. */ 2645 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2646 break; 2647 dc_newbuf(sc, i, 0); 2648 DC_INC(i, DC_RX_LIST_CNT); 2649 } 2650 2651 /* Find the length of the actual receive frame. */ 2652 total_len = DC_RXBYTES(rxstat); 2653 2654 /* Scan backwards until we hit a non-zero byte. */ 2655 while (*ptr == 0x00) 2656 ptr--; 2657 2658 /* Round off. */ 2659 if ((uintptr_t)(ptr) & 0x3) 2660 ptr -= 1; 2661 2662 /* Now find the start of the frame. */ 2663 ptr -= total_len; 2664 if (ptr < sc->dc_pnic_rx_buf) 2665 ptr = sc->dc_pnic_rx_buf; 2666 2667 /* 2668 * Now copy the salvaged frame to the last mbuf and fake up 2669 * the status word to make it look like a successful 2670 * frame reception. 2671 */ 2672 dc_newbuf(sc, i, 0); 2673 bcopy(ptr, mtod(m, char *), total_len); 2674 cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG); 2675} 2676 2677/* 2678 * This routine searches the RX ring for dirty descriptors in the 2679 * event that the rxeof routine falls out of sync with the chip's 2680 * current descriptor pointer. This may happen sometimes as a result 2681 * of a "no RX buffer available" condition that happens when the chip 2682 * consumes all of the RX buffers before the driver has a chance to 2683 * process the RX ring. This routine may need to be called more than 2684 * once to bring the driver back in sync with the chip, however we 2685 * should still be getting RX DONE interrupts to drive the search 2686 * for new packets in the RX ring, so we should catch up eventually. 2687 */ 2688static int 2689dc_rx_resync(struct dc_softc *sc) 2690{ 2691 struct dc_desc *cur_rx; 2692 int i, pos; 2693 2694 pos = sc->dc_cdata.dc_rx_prod; 2695 2696 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2697 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2698 if (!(le32toh(cur_rx->dc_status) & DC_RXSTAT_OWN)) 2699 break; 2700 DC_INC(pos, DC_RX_LIST_CNT); 2701 } 2702 2703 /* If the ring really is empty, then just return. */ 2704 if (i == DC_RX_LIST_CNT) 2705 return (0); 2706 2707 /* We've fallen behing the chip: catch it. */ 2708 sc->dc_cdata.dc_rx_prod = pos; 2709 2710 return (EAGAIN); 2711} 2712 2713/* 2714 * A frame has been uploaded: pass the resulting mbuf chain up to 2715 * the higher level protocols. 2716 */ 2717static void 2718dc_rxeof(struct dc_softc *sc) 2719{ 2720 struct mbuf *m; 2721 struct ifnet *ifp; 2722 struct dc_desc *cur_rx; 2723 int i, total_len = 0; 2724 u_int32_t rxstat; 2725 2726 ifp = &sc->arpcom.ac_if; 2727 i = sc->dc_cdata.dc_rx_prod; 2728 2729 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2730 while (!(le32toh(sc->dc_ldata->dc_rx_list[i].dc_status) & 2731 DC_RXSTAT_OWN)) { 2732#ifdef DEVICE_POLLING 2733 if (ifp->if_flags & IFF_POLLING) { 2734 if (sc->rxcycles <= 0) 2735 break; 2736 sc->rxcycles--; 2737 } 2738#endif 2739 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2740 rxstat = le32toh(cur_rx->dc_status); 2741 m = sc->dc_cdata.dc_rx_chain[i]; 2742 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_rx_map[i], 2743 BUS_DMASYNC_POSTREAD); 2744 total_len = DC_RXBYTES(rxstat); 2745 2746 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2747 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2748 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2749 sc->dc_pnic_rx_bug_save = i; 2750 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2751 DC_INC(i, DC_RX_LIST_CNT); 2752 continue; 2753 } 2754 dc_pnic_rx_bug_war(sc, i); 2755 rxstat = le32toh(cur_rx->dc_status); 2756 total_len = DC_RXBYTES(rxstat); 2757 } 2758 } 2759 2760 /* 2761 * If an error occurs, update stats, clear the 2762 * status word and leave the mbuf cluster in place: 2763 * it should simply get re-used next time this descriptor 2764 * comes up in the ring. However, don't report long 2765 * frames as errors since they could be vlans. 2766 */ 2767 if ((rxstat & DC_RXSTAT_RXERR)) { 2768 if (!(rxstat & DC_RXSTAT_GIANT) || 2769 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2770 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2771 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2772 ifp->if_ierrors++; 2773 if (rxstat & DC_RXSTAT_COLLSEEN) 2774 ifp->if_collisions++; 2775 dc_newbuf(sc, i, 0); 2776 if (rxstat & DC_RXSTAT_CRCERR) { 2777 DC_INC(i, DC_RX_LIST_CNT); 2778 continue; 2779 } else { 2780 dc_init(sc); 2781 return; 2782 } 2783 } 2784 } 2785 2786 /* No errors; receive the packet. */ 2787 total_len -= ETHER_CRC_LEN; 2788#ifdef __i386__ 2789 /* 2790 * On the x86 we do not have alignment problems, so try to 2791 * allocate a new buffer for the receive ring, and pass up 2792 * the one where the packet is already, saving the expensive 2793 * copy done in m_devget(). 2794 * If we are on an architecture with alignment problems, or 2795 * if the allocation fails, then use m_devget and leave the 2796 * existing buffer in the receive ring. 2797 */ 2798 if (dc_quick && dc_newbuf(sc, i, 1) == 0) { 2799 m->m_pkthdr.rcvif = ifp; 2800 m->m_pkthdr.len = m->m_len = total_len; 2801 DC_INC(i, DC_RX_LIST_CNT); 2802 } else 2803#endif 2804 { 2805 struct mbuf *m0; 2806 2807 m0 = m_devget(mtod(m, char *), total_len, 2808 ETHER_ALIGN, ifp, NULL); 2809 dc_newbuf(sc, i, 0); 2810 DC_INC(i, DC_RX_LIST_CNT); 2811 if (m0 == NULL) { 2812 ifp->if_ierrors++; 2813 continue; 2814 } 2815 m = m0; 2816 } 2817 2818 ifp->if_ipackets++; 2819 (*ifp->if_input)(ifp, m); 2820 } 2821 2822 sc->dc_cdata.dc_rx_prod = i; 2823} 2824 2825/* 2826 * A frame was downloaded to the chip. It's safe for us to clean up 2827 * the list buffers. 2828 */ 2829 2830static void 2831dc_txeof(struct dc_softc *sc) 2832{ 2833 struct dc_desc *cur_tx = NULL; 2834 struct ifnet *ifp; 2835 int idx; 2836 u_int32_t ctl, txstat; 2837 2838 ifp = &sc->arpcom.ac_if; 2839 2840 /* 2841 * Go through our tx list and free mbufs for those 2842 * frames that have been transmitted. 2843 */ 2844 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, BUS_DMASYNC_POSTREAD); 2845 idx = sc->dc_cdata.dc_tx_cons; 2846 while (idx != sc->dc_cdata.dc_tx_prod) { 2847 2848 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2849 txstat = le32toh(cur_tx->dc_status); 2850 ctl = le32toh(cur_tx->dc_ctl); 2851 2852 if (txstat & DC_TXSTAT_OWN) 2853 break; 2854 2855 if (!(ctl & DC_TXCTL_FIRSTFRAG) || ctl & DC_TXCTL_SETUP) { 2856 if (ctl & DC_TXCTL_SETUP) { 2857 /* 2858 * Yes, the PNIC is so brain damaged 2859 * that it will sometimes generate a TX 2860 * underrun error while DMAing the RX 2861 * filter setup frame. If we detect this, 2862 * we have to send the setup frame again, 2863 * or else the filter won't be programmed 2864 * correctly. 2865 */ 2866 if (DC_IS_PNIC(sc)) { 2867 if (txstat & DC_TXSTAT_ERRSUM) 2868 dc_setfilt(sc); 2869 } 2870 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2871 } 2872 sc->dc_cdata.dc_tx_cnt--; 2873 DC_INC(idx, DC_TX_LIST_CNT); 2874 continue; 2875 } 2876 2877 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2878 /* 2879 * XXX: Why does my Xircom taunt me so? 2880 * For some reason it likes setting the CARRLOST flag 2881 * even when the carrier is there. wtf?!? 2882 * Who knows, but Conexant chips have the 2883 * same problem. Maybe they took lessons 2884 * from Xircom. 2885 */ 2886 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2887 sc->dc_pmode == DC_PMODE_MII && 2888 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2889 DC_TXSTAT_NOCARRIER))) 2890 txstat &= ~DC_TXSTAT_ERRSUM; 2891 } else { 2892 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2893 sc->dc_pmode == DC_PMODE_MII && 2894 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM | 2895 DC_TXSTAT_NOCARRIER | DC_TXSTAT_CARRLOST))) 2896 txstat &= ~DC_TXSTAT_ERRSUM; 2897 } 2898 2899 if (txstat & DC_TXSTAT_ERRSUM) { 2900 ifp->if_oerrors++; 2901 if (txstat & DC_TXSTAT_EXCESSCOLL) 2902 ifp->if_collisions++; 2903 if (txstat & DC_TXSTAT_LATECOLL) 2904 ifp->if_collisions++; 2905 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2906 dc_init(sc); 2907 return; 2908 } 2909 } 2910 2911 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2912 2913 ifp->if_opackets++; 2914 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2915 bus_dmamap_sync(sc->dc_mtag, 2916 sc->dc_cdata.dc_tx_map[idx], 2917 BUS_DMASYNC_POSTWRITE); 2918 bus_dmamap_unload(sc->dc_mtag, 2919 sc->dc_cdata.dc_tx_map[idx]); 2920 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2921 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2922 } 2923 2924 sc->dc_cdata.dc_tx_cnt--; 2925 DC_INC(idx, DC_TX_LIST_CNT); 2926 } 2927 2928 if (idx != sc->dc_cdata.dc_tx_cons) { 2929 /* Some buffers have been freed. */ 2930 sc->dc_cdata.dc_tx_cons = idx; 2931 ifp->if_flags &= ~IFF_OACTIVE; 2932 } 2933 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2934} 2935 2936static void 2937dc_tick(void *xsc) 2938{ 2939 struct dc_softc *sc; 2940 struct mii_data *mii; 2941 struct ifnet *ifp; 2942 u_int32_t r; 2943 2944 sc = xsc; 2945 DC_LOCK(sc); 2946 ifp = &sc->arpcom.ac_if; 2947 mii = device_get_softc(sc->dc_miibus); 2948 2949 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2950 if (sc->dc_flags & DC_21143_NWAY) { 2951 r = CSR_READ_4(sc, DC_10BTSTAT); 2952 if (IFM_SUBTYPE(mii->mii_media_active) == 2953 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2954 sc->dc_link = 0; 2955 mii_mediachg(mii); 2956 } 2957 if (IFM_SUBTYPE(mii->mii_media_active) == 2958 IFM_10_T && (r & DC_TSTAT_LS10)) { 2959 sc->dc_link = 0; 2960 mii_mediachg(mii); 2961 } 2962 if (sc->dc_link == 0) 2963 mii_tick(mii); 2964 } else { 2965 r = CSR_READ_4(sc, DC_ISR); 2966 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2967 sc->dc_cdata.dc_tx_cnt == 0) { 2968 mii_tick(mii); 2969 if (!(mii->mii_media_status & IFM_ACTIVE)) 2970 sc->dc_link = 0; 2971 } 2972 } 2973 } else 2974 mii_tick(mii); 2975 2976 /* 2977 * When the init routine completes, we expect to be able to send 2978 * packets right away, and in fact the network code will send a 2979 * gratuitous ARP the moment the init routine marks the interface 2980 * as running. However, even though the MAC may have been initialized, 2981 * there may be a delay of a few seconds before the PHY completes 2982 * autonegotiation and the link is brought up. Any transmissions 2983 * made during that delay will be lost. Dealing with this is tricky: 2984 * we can't just pause in the init routine while waiting for the 2985 * PHY to come ready since that would bring the whole system to 2986 * a screeching halt for several seconds. 2987 * 2988 * What we do here is prevent the TX start routine from sending 2989 * any packets until a link has been established. After the 2990 * interface has been initialized, the tick routine will poll 2991 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2992 * that time, packets will stay in the send queue, and once the 2993 * link comes up, they will be flushed out to the wire. 2994 */ 2995 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2996 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2997 sc->dc_link++; 2998 if (ifp->if_snd.ifq_head != NULL) 2999 dc_start(ifp); 3000 } 3001 3002 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 3003 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3004 else 3005 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3006 3007 DC_UNLOCK(sc); 3008} 3009 3010/* 3011 * A transmit underrun has occurred. Back off the transmit threshold, 3012 * or switch to store and forward mode if we have to. 3013 */ 3014static void 3015dc_tx_underrun(struct dc_softc *sc) 3016{ 3017 u_int32_t isr; 3018 int i; 3019 3020 if (DC_IS_DAVICOM(sc)) 3021 dc_init(sc); 3022 3023 if (DC_IS_INTEL(sc)) { 3024 /* 3025 * The real 21143 requires that the transmitter be idle 3026 * in order to change the transmit threshold or store 3027 * and forward state. 3028 */ 3029 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3030 3031 for (i = 0; i < DC_TIMEOUT; i++) { 3032 isr = CSR_READ_4(sc, DC_ISR); 3033 if (isr & DC_ISR_TX_IDLE) 3034 break; 3035 DELAY(10); 3036 } 3037 if (i == DC_TIMEOUT) { 3038 printf("dc%d: failed to force tx to idle state\n", 3039 sc->dc_unit); 3040 dc_init(sc); 3041 } 3042 } 3043 3044 printf("dc%d: TX underrun -- ", sc->dc_unit); 3045 sc->dc_txthresh += DC_TXTHRESH_INC; 3046 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3047 printf("using store and forward mode\n"); 3048 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3049 } else { 3050 printf("increasing TX threshold\n"); 3051 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3052 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3053 } 3054 3055 if (DC_IS_INTEL(sc)) 3056 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3057} 3058 3059#ifdef DEVICE_POLLING 3060static poll_handler_t dc_poll; 3061 3062static void 3063dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3064{ 3065 struct dc_softc *sc = ifp->if_softc; 3066 3067 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 3068 /* Re-enable interrupts. */ 3069 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3070 return; 3071 } 3072 sc->rxcycles = count; 3073 dc_rxeof(sc); 3074 dc_txeof(sc); 3075 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 3076 dc_start(ifp); 3077 3078 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 3079 u_int32_t status; 3080 3081 status = CSR_READ_4(sc, DC_ISR); 3082 status &= (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF | 3083 DC_ISR_TX_NOBUF | DC_ISR_TX_IDLE | DC_ISR_TX_UNDERRUN | 3084 DC_ISR_BUS_ERR); 3085 if (!status) 3086 return; 3087 /* ack what we have */ 3088 CSR_WRITE_4(sc, DC_ISR, status); 3089 3090 if (status & (DC_ISR_RX_WATDOGTIMEO | DC_ISR_RX_NOBUF)) { 3091 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 3092 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 3093 3094 if (dc_rx_resync(sc)) 3095 dc_rxeof(sc); 3096 } 3097 /* restart transmit unit if necessary */ 3098 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3099 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3100 3101 if (status & DC_ISR_TX_UNDERRUN) 3102 dc_tx_underrun(sc); 3103 3104 if (status & DC_ISR_BUS_ERR) { 3105 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3106 dc_reset(sc); 3107 dc_init(sc); 3108 } 3109 } 3110} 3111#endif /* DEVICE_POLLING */ 3112 3113static void 3114dc_intr(void *arg) 3115{ 3116 struct dc_softc *sc; 3117 struct ifnet *ifp; 3118 u_int32_t status; 3119 3120 sc = arg; 3121 3122 if (sc->suspended) 3123 return; 3124 3125 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3126 return; 3127 3128 DC_LOCK(sc); 3129 ifp = &sc->arpcom.ac_if; 3130#ifdef DEVICE_POLLING 3131 if (ifp->if_flags & IFF_POLLING) 3132 goto done; 3133 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3134 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3135 goto done; 3136 } 3137#endif 3138 3139 /* Suppress unwanted interrupts */ 3140 if (!(ifp->if_flags & IFF_UP)) { 3141 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3142 dc_stop(sc); 3143 DC_UNLOCK(sc); 3144 return; 3145 } 3146 3147 /* Disable interrupts. */ 3148 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3149 3150 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3151 && status != 0xFFFFFFFF) { 3152 3153 CSR_WRITE_4(sc, DC_ISR, status); 3154 3155 if (status & DC_ISR_RX_OK) { 3156 int curpkts; 3157 curpkts = ifp->if_ipackets; 3158 dc_rxeof(sc); 3159 if (curpkts == ifp->if_ipackets) { 3160 while (dc_rx_resync(sc)) 3161 dc_rxeof(sc); 3162 } 3163 } 3164 3165 if (status & (DC_ISR_TX_OK | DC_ISR_TX_NOBUF)) 3166 dc_txeof(sc); 3167 3168 if (status & DC_ISR_TX_IDLE) { 3169 dc_txeof(sc); 3170 if (sc->dc_cdata.dc_tx_cnt) { 3171 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3172 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3173 } 3174 } 3175 3176 if (status & DC_ISR_TX_UNDERRUN) 3177 dc_tx_underrun(sc); 3178 3179 if ((status & DC_ISR_RX_WATDOGTIMEO) 3180 || (status & DC_ISR_RX_NOBUF)) { 3181 int curpkts; 3182 curpkts = ifp->if_ipackets; 3183 dc_rxeof(sc); 3184 if (curpkts == ifp->if_ipackets) { 3185 while (dc_rx_resync(sc)) 3186 dc_rxeof(sc); 3187 } 3188 } 3189 3190 if (status & DC_ISR_BUS_ERR) { 3191 dc_reset(sc); 3192 dc_init(sc); 3193 } 3194 } 3195 3196 /* Re-enable interrupts. */ 3197 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3198 3199 if (ifp->if_snd.ifq_head != NULL) 3200 dc_start(ifp); 3201 3202#ifdef DEVICE_POLLING 3203done: 3204#endif 3205 3206 DC_UNLOCK(sc); 3207} 3208 3209static void 3210dc_dma_map_txbuf(arg, segs, nseg, mapsize, error) 3211 void *arg; 3212 bus_dma_segment_t *segs; 3213 int nseg; 3214 bus_size_t mapsize; 3215 int error; 3216{ 3217 struct dc_softc *sc; 3218 struct dc_desc *f; 3219 int cur, first, frag, i; 3220 3221 sc = arg; 3222 if (error) { 3223 sc->dc_cdata.dc_tx_err = error; 3224 return; 3225 } 3226 3227 first = cur = frag = sc->dc_cdata.dc_tx_prod; 3228 for (i = 0; i < nseg; i++) { 3229 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3230 (frag == (DC_TX_LIST_CNT - 1)) && 3231 (first != sc->dc_cdata.dc_tx_first)) { 3232 bus_dmamap_unload(sc->dc_mtag, 3233 sc->dc_cdata.dc_tx_map[first]); 3234 sc->dc_cdata.dc_tx_err = ENOBUFS; 3235 return; 3236 } 3237 3238 f = &sc->dc_ldata->dc_tx_list[frag]; 3239 f->dc_ctl = htole32(DC_TXCTL_TLINK | segs[i].ds_len); 3240 if (i == 0) { 3241 f->dc_status = 0; 3242 f->dc_ctl |= htole32(DC_TXCTL_FIRSTFRAG); 3243 } else 3244 f->dc_status = htole32(DC_TXSTAT_OWN); 3245 f->dc_data = htole32(segs[i].ds_addr); 3246 cur = frag; 3247 DC_INC(frag, DC_TX_LIST_CNT); 3248 } 3249 3250 sc->dc_cdata.dc_tx_err = 0; 3251 sc->dc_cdata.dc_tx_prod = frag; 3252 sc->dc_cdata.dc_tx_cnt += nseg; 3253 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG); 3254 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3255 sc->dc_ldata->dc_tx_list[first].dc_ctl |= 3256 htole32(DC_TXCTL_FINT); 3257 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3258 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3259 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3260 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_FINT); 3261 sc->dc_ldata->dc_tx_list[first].dc_status = htole32(DC_TXSTAT_OWN); 3262} 3263 3264/* 3265 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3266 * pointers to the fragment pointers. 3267 */ 3268static int 3269dc_encap(struct dc_softc *sc, struct mbuf **m_head) 3270{ 3271 struct mbuf *m; 3272 int error, idx, chainlen = 0; 3273 3274 /* 3275 * If there's no way we can send any packets, return now. 3276 */ 3277 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3278 return (ENOBUFS); 3279 3280 /* 3281 * Count the number of frags in this chain to see if 3282 * we need to m_defrag. Since the descriptor list is shared 3283 * by all packets, we'll m_defrag long chains so that they 3284 * do not use up the entire list, even if they would fit. 3285 */ 3286 for (m = *m_head; m != NULL; m = m->m_next) 3287 chainlen++; 3288 3289 if ((chainlen > DC_TX_LIST_CNT / 4) || 3290 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3291 m = m_defrag(*m_head, M_DONTWAIT); 3292 if (m == NULL) 3293 return (ENOBUFS); 3294 *m_head = m; 3295 } 3296 3297 /* 3298 * Start packing the mbufs in this chain into 3299 * the fragment pointers. Stop when we run out 3300 * of fragments or hit the end of the mbuf chain. 3301 */ 3302 idx = sc->dc_cdata.dc_tx_prod; 3303 error = bus_dmamap_load_mbuf(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3304 *m_head, dc_dma_map_txbuf, sc, 0); 3305 if (error) 3306 return (error); 3307 if (sc->dc_cdata.dc_tx_err != 0) 3308 return (sc->dc_cdata.dc_tx_err); 3309 sc->dc_cdata.dc_tx_chain[idx] = *m_head; 3310 bus_dmamap_sync(sc->dc_mtag, sc->dc_cdata.dc_tx_map[idx], 3311 BUS_DMASYNC_PREWRITE); 3312 bus_dmamap_sync(sc->dc_ltag, sc->dc_lmap, 3313 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3314 return (0); 3315} 3316 3317/* 3318 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3319 * to the mbuf data regions directly in the transmit lists. We also save a 3320 * copy of the pointers since the transmit list fragment pointers are 3321 * physical addresses. 3322 */ 3323 3324static void 3325dc_start(struct ifnet *ifp) 3326{ 3327 struct dc_softc *sc; 3328 struct mbuf *m_head = NULL, *m; 3329 int idx; 3330 3331 sc = ifp->if_softc; 3332 3333 DC_LOCK(sc); 3334 3335 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3336 DC_UNLOCK(sc); 3337 return; 3338 } 3339 3340 if (ifp->if_flags & IFF_OACTIVE) { 3341 DC_UNLOCK(sc); 3342 return; 3343 } 3344 3345 idx = sc->dc_cdata.dc_tx_first = sc->dc_cdata.dc_tx_prod; 3346 3347 while (sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3348 IF_DEQUEUE(&ifp->if_snd, m_head); 3349 if (m_head == NULL) 3350 break; 3351 3352 if (sc->dc_flags & DC_TX_COALESCE && 3353 (m_head->m_next != NULL || 3354 sc->dc_flags & DC_TX_ALIGN)) { 3355 m = m_defrag(m_head, M_DONTWAIT); 3356 if (m == NULL) { 3357 IF_PREPEND(&ifp->if_snd, m_head); 3358 ifp->if_flags |= IFF_OACTIVE; 3359 break; 3360 } else { 3361 m_head = m; 3362 } 3363 } 3364 3365 if (dc_encap(sc, &m_head)) { 3366 IF_PREPEND(&ifp->if_snd, m_head); 3367 ifp->if_flags |= IFF_OACTIVE; 3368 break; 3369 } 3370 idx = sc->dc_cdata.dc_tx_prod; 3371 3372 /* 3373 * If there's a BPF listener, bounce a copy of this frame 3374 * to him. 3375 */ 3376 BPF_MTAP(ifp, m_head); 3377 3378 if (sc->dc_flags & DC_TX_ONE) { 3379 ifp->if_flags |= IFF_OACTIVE; 3380 break; 3381 } 3382 } 3383 3384 /* Transmit */ 3385 if (!(sc->dc_flags & DC_TX_POLL)) 3386 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3387 3388 /* 3389 * Set a timeout in case the chip goes out to lunch. 3390 */ 3391 ifp->if_timer = 5; 3392 3393 DC_UNLOCK(sc); 3394} 3395 3396static void 3397dc_init(void *xsc) 3398{ 3399 struct dc_softc *sc = xsc; 3400 struct ifnet *ifp = &sc->arpcom.ac_if; 3401 struct mii_data *mii; 3402 3403 DC_LOCK(sc); 3404 3405 mii = device_get_softc(sc->dc_miibus); 3406 3407 /* 3408 * Cancel pending I/O and free all RX/TX buffers. 3409 */ 3410 dc_stop(sc); 3411 dc_reset(sc); 3412 3413 /* 3414 * Set cache alignment and burst length. 3415 */ 3416 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3417 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3418 else 3419 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME | DC_BUSCTL_MRLE); 3420 /* 3421 * Evenly share the bus between receive and transmit process. 3422 */ 3423 if (DC_IS_INTEL(sc)) 3424 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3425 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3426 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3427 } else { 3428 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3429 } 3430 if (sc->dc_flags & DC_TX_POLL) 3431 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3432 switch(sc->dc_cachesize) { 3433 case 32: 3434 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3435 break; 3436 case 16: 3437 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3438 break; 3439 case 8: 3440 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3441 break; 3442 case 0: 3443 default: 3444 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3445 break; 3446 } 3447 3448 if (sc->dc_flags & DC_TX_STORENFWD) 3449 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3450 else { 3451 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3452 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3453 } else { 3454 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3455 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3456 } 3457 } 3458 3459 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3460 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3461 3462 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3463 /* 3464 * The app notes for the 98713 and 98715A say that 3465 * in order to have the chips operate properly, a magic 3466 * number must be written to CSR16. Macronix does not 3467 * document the meaning of these bits so there's no way 3468 * to know exactly what they do. The 98713 has a magic 3469 * number all its own; the rest all use a different one. 3470 */ 3471 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3472 if (sc->dc_type == DC_TYPE_98713) 3473 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3474 else 3475 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3476 } 3477 3478 if (DC_IS_XIRCOM(sc)) { 3479 /* 3480 * setup General Purpose Port mode and data so the tulip 3481 * can talk to the MII. 3482 */ 3483 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3484 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3485 DELAY(10); 3486 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3487 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3488 DELAY(10); 3489 } 3490 3491 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3492 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3493 3494 /* Init circular RX list. */ 3495 if (dc_list_rx_init(sc) == ENOBUFS) { 3496 printf("dc%d: initialization failed: no " 3497 "memory for rx buffers\n", sc->dc_unit); 3498 dc_stop(sc); 3499 DC_UNLOCK(sc); 3500 return; 3501 } 3502 3503 /* 3504 * Init TX descriptors. 3505 */ 3506 dc_list_tx_init(sc); 3507 3508 /* 3509 * Load the address of the RX list. 3510 */ 3511 CSR_WRITE_4(sc, DC_RXADDR, DC_RXDESC(sc, 0)); 3512 CSR_WRITE_4(sc, DC_TXADDR, DC_TXDESC(sc, 0)); 3513 3514 /* 3515 * Enable interrupts. 3516 */ 3517#ifdef DEVICE_POLLING 3518 /* 3519 * ... but only if we are not polling, and make sure they are off in 3520 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3521 * after a reset. 3522 */ 3523 if (ifp->if_flags & IFF_POLLING) 3524 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3525 else 3526#endif 3527 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3528 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3529 3530 /* Enable transmitter. */ 3531 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3532 3533 /* 3534 * If this is an Intel 21143 and we're not using the 3535 * MII port, program the LED control pins so we get 3536 * link and activity indications. 3537 */ 3538 if (sc->dc_flags & DC_TULIP_LEDS) { 3539 CSR_WRITE_4(sc, DC_WATCHDOG, 3540 DC_WDOG_CTLWREN | DC_WDOG_LINK | DC_WDOG_ACTIVITY); 3541 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3542 } 3543 3544 /* 3545 * Load the RX/multicast filter. We do this sort of late 3546 * because the filter programming scheme on the 21143 and 3547 * some clones requires DMAing a setup frame via the TX 3548 * engine, and we need the transmitter enabled for that. 3549 */ 3550 dc_setfilt(sc); 3551 3552 /* Enable receiver. */ 3553 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3554 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3555 3556 mii_mediachg(mii); 3557 dc_setcfg(sc, sc->dc_if_media); 3558 3559 ifp->if_flags |= IFF_RUNNING; 3560 ifp->if_flags &= ~IFF_OACTIVE; 3561 3562 /* Don't start the ticker if this is a homePNA link. */ 3563 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3564 sc->dc_link = 1; 3565 else { 3566 if (sc->dc_flags & DC_21143_NWAY) 3567 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3568 else 3569 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3570 } 3571 3572#ifdef SRM_MEDIA 3573 if(sc->dc_srm_media) { 3574 struct ifreq ifr; 3575 3576 ifr.ifr_media = sc->dc_srm_media; 3577 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3578 sc->dc_srm_media = 0; 3579 } 3580#endif 3581 DC_UNLOCK(sc); 3582} 3583 3584/* 3585 * Set media options. 3586 */ 3587static int 3588dc_ifmedia_upd(struct ifnet *ifp) 3589{ 3590 struct dc_softc *sc; 3591 struct mii_data *mii; 3592 struct ifmedia *ifm; 3593 3594 sc = ifp->if_softc; 3595 mii = device_get_softc(sc->dc_miibus); 3596 mii_mediachg(mii); 3597 ifm = &mii->mii_media; 3598 3599 if (DC_IS_DAVICOM(sc) && 3600 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3601 dc_setcfg(sc, ifm->ifm_media); 3602 else 3603 sc->dc_link = 0; 3604 3605 return (0); 3606} 3607 3608/* 3609 * Report current media status. 3610 */ 3611static void 3612dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3613{ 3614 struct dc_softc *sc; 3615 struct mii_data *mii; 3616 struct ifmedia *ifm; 3617 3618 sc = ifp->if_softc; 3619 mii = device_get_softc(sc->dc_miibus); 3620 mii_pollstat(mii); 3621 ifm = &mii->mii_media; 3622 if (DC_IS_DAVICOM(sc)) { 3623 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3624 ifmr->ifm_active = ifm->ifm_media; 3625 ifmr->ifm_status = 0; 3626 return; 3627 } 3628 } 3629 ifmr->ifm_active = mii->mii_media_active; 3630 ifmr->ifm_status = mii->mii_media_status; 3631} 3632 3633static int 3634dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3635{ 3636 struct dc_softc *sc = ifp->if_softc; 3637 struct ifreq *ifr = (struct ifreq *)data; 3638 struct mii_data *mii; 3639 int error = 0; 3640 3641 DC_LOCK(sc); 3642 3643 switch (command) { 3644 case SIOCSIFFLAGS: 3645 if (ifp->if_flags & IFF_UP) { 3646 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3647 (IFF_PROMISC | IFF_ALLMULTI); 3648 3649 if (ifp->if_flags & IFF_RUNNING) { 3650 if (need_setfilt) 3651 dc_setfilt(sc); 3652 } else { 3653 sc->dc_txthresh = 0; 3654 dc_init(sc); 3655 } 3656 } else { 3657 if (ifp->if_flags & IFF_RUNNING) 3658 dc_stop(sc); 3659 } 3660 sc->dc_if_flags = ifp->if_flags; 3661 error = 0; 3662 break; 3663 case SIOCADDMULTI: 3664 case SIOCDELMULTI: 3665 dc_setfilt(sc); 3666 error = 0; 3667 break; 3668 case SIOCGIFMEDIA: 3669 case SIOCSIFMEDIA: 3670 mii = device_get_softc(sc->dc_miibus); 3671 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3672#ifdef SRM_MEDIA 3673 if (sc->dc_srm_media) 3674 sc->dc_srm_media = 0; 3675#endif 3676 break; 3677 default: 3678 error = ether_ioctl(ifp, command, data); 3679 break; 3680 } 3681 3682 DC_UNLOCK(sc); 3683 3684 return (error); 3685} 3686 3687static void 3688dc_watchdog(struct ifnet *ifp) 3689{ 3690 struct dc_softc *sc; 3691 3692 sc = ifp->if_softc; 3693 3694 DC_LOCK(sc); 3695 3696 ifp->if_oerrors++; 3697 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3698 3699 dc_stop(sc); 3700 dc_reset(sc); 3701 dc_init(sc); 3702 3703 if (ifp->if_snd.ifq_head != NULL) 3704 dc_start(ifp); 3705 3706 DC_UNLOCK(sc); 3707} 3708 3709/* 3710 * Stop the adapter and free any mbufs allocated to the 3711 * RX and TX lists. 3712 */ 3713static void 3714dc_stop(struct dc_softc *sc) 3715{ 3716 struct ifnet *ifp; 3717 struct dc_list_data *ld; 3718 struct dc_chain_data *cd; 3719 int i; 3720 u_int32_t ctl; 3721 3722 DC_LOCK(sc); 3723 3724 ifp = &sc->arpcom.ac_if; 3725 ifp->if_timer = 0; 3726 ld = sc->dc_ldata; 3727 cd = &sc->dc_cdata; 3728 3729 callout_stop(&sc->dc_stat_ch); 3730 3731 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3732#ifdef DEVICE_POLLING 3733 ether_poll_deregister(ifp); 3734#endif 3735 3736 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON | DC_NETCFG_TX_ON)); 3737 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3738 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3739 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3740 sc->dc_link = 0; 3741 3742 /* 3743 * Free data in the RX lists. 3744 */ 3745 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3746 if (cd->dc_rx_chain[i] != NULL) { 3747 m_freem(cd->dc_rx_chain[i]); 3748 cd->dc_rx_chain[i] = NULL; 3749 } 3750 } 3751 bzero(&ld->dc_rx_list, sizeof(ld->dc_rx_list)); 3752 3753 /* 3754 * Free the TX list buffers. 3755 */ 3756 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3757 if (cd->dc_tx_chain[i] != NULL) { 3758 ctl = le32toh(ld->dc_tx_list[i].dc_ctl); 3759 if ((ctl & DC_TXCTL_SETUP) || 3760 !(ctl & DC_TXCTL_FIRSTFRAG)) { 3761 cd->dc_tx_chain[i] = NULL; 3762 continue; 3763 } 3764 bus_dmamap_unload(sc->dc_mtag, cd->dc_tx_map[i]); 3765 m_freem(cd->dc_tx_chain[i]); 3766 cd->dc_tx_chain[i] = NULL; 3767 } 3768 } 3769 bzero(&ld->dc_tx_list, sizeof(ld->dc_tx_list)); 3770 3771 DC_UNLOCK(sc); 3772} 3773 3774/* 3775 * Device suspend routine. Stop the interface and save some PCI 3776 * settings in case the BIOS doesn't restore them properly on 3777 * resume. 3778 */ 3779static int 3780dc_suspend(device_t dev) 3781{ 3782 struct dc_softc *sc; 3783 int i, s; 3784 3785 s = splimp(); 3786 3787 sc = device_get_softc(dev); 3788 3789 dc_stop(sc); 3790 3791 for (i = 0; i < 5; i++) 3792 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4); 3793 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3794 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3795 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3796 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3797 3798 sc->suspended = 1; 3799 3800 splx(s); 3801 return (0); 3802} 3803 3804/* 3805 * Device resume routine. Restore some PCI settings in case the BIOS 3806 * doesn't, re-enable busmastering, and restart the interface if 3807 * appropriate. 3808 */ 3809static int 3810dc_resume(device_t dev) 3811{ 3812 struct dc_softc *sc; 3813 struct ifnet *ifp; 3814 int i, s; 3815 3816 s = splimp(); 3817 3818 sc = device_get_softc(dev); 3819 ifp = &sc->arpcom.ac_if; 3820#ifndef BURN_BRIDGES 3821 dc_acpi(dev); 3822#endif 3823 /* better way to do this? */ 3824 for (i = 0; i < 5; i++) 3825 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4); 3826 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3827 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3828 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3829 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3830 3831 /* reenable busmastering */ 3832 pci_enable_busmaster(dev); 3833 pci_enable_io(dev, DC_RES); 3834 3835 /* reinitialize interface if necessary */ 3836 if (ifp->if_flags & IFF_UP) 3837 dc_init(sc); 3838 3839 sc->suspended = 0; 3840 3841 splx(s); 3842 return (0); 3843} 3844 3845/* 3846 * Stop all chip I/O so that the kernel's probe routines don't 3847 * get confused by errant DMAs when rebooting. 3848 */ 3849static void 3850dc_shutdown(device_t dev) 3851{ 3852 struct dc_softc *sc; 3853 3854 sc = device_get_softc(dev); 3855 3856 dc_stop(sc); 3857} 3858