if_dc.c revision 113545
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 35 * series chips and several workalikes including the following: 36 * 37 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 38 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 39 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 40 * ASIX Electronics AX88140A (www.asix.com.tw) 41 * ASIX Electronics AX88141 (www.asix.com.tw) 42 * ADMtek AL981 (www.admtek.com.tw) 43 * ADMtek AN985 (www.admtek.com.tw) 44 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 45 * Accton EN1217 (www.accton.com) 46 * Xircom X3201 (www.xircom.com) 47 * Abocom FE2500 48 * Conexant LANfinity (www.conexant.com) 49 * 50 * Datasheets for the 21143 are available at developer.intel.com. 51 * Datasheets for the clone parts can be found at their respective sites. 52 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 53 * The PNIC II is essentially a Macronix 98715A chip; the only difference 54 * worth noting is that its multicast hash table is only 128 bits wide 55 * instead of 512. 56 * 57 * Written by Bill Paul <wpaul@ee.columbia.edu> 58 * Electrical Engineering Department 59 * Columbia University, New York City 60 */ 61 62/* 63 * The Intel 21143 is the successor to the DEC 21140. It is basically 64 * the same as the 21140 but with a few new features. The 21143 supports 65 * three kinds of media attachments: 66 * 67 * o MII port, for 10Mbps and 100Mbps support and NWAY 68 * autonegotiation provided by an external PHY. 69 * o SYM port, for symbol mode 100Mbps support. 70 * o 10baseT port. 71 * o AUI/BNC port. 72 * 73 * The 100Mbps SYM port and 10baseT port can be used together in 74 * combination with the internal NWAY support to create a 10/100 75 * autosensing configuration. 76 * 77 * Note that not all tulip workalikes are handled in this driver: we only 78 * deal with those which are relatively well behaved. The Winbond is 79 * handled separately due to its different register offsets and the 80 * special handling needed for its various bugs. The PNIC is handled 81 * here, but I'm not thrilled about it. 82 * 83 * All of the workalike chips use some form of MII transceiver support 84 * with the exception of the Macronix chips, which also have a SYM port. 85 * The ASIX AX88140A is also documented to have a SYM port, but all 86 * the cards I've seen use an MII transceiver, probably because the 87 * AX88140A doesn't support internal NWAY. 88 */ 89 90#include <sys/cdefs.h> 91__FBSDID("$FreeBSD: head/sys/dev/dc/if_dc.c 113545 2003-04-16 03:16:57Z mdodd $"); 92 93#include <sys/param.h> 94#include <sys/systm.h> 95#include <sys/sockio.h> 96#include <sys/mbuf.h> 97#include <sys/malloc.h> 98#include <sys/kernel.h> 99#include <sys/socket.h> 100#include <sys/sysctl.h> 101 102#include <net/if.h> 103#include <net/if_arp.h> 104#include <net/ethernet.h> 105#include <net/if_dl.h> 106#include <net/if_media.h> 107#include <net/if_types.h> 108#include <net/if_vlan_var.h> 109 110#include <net/bpf.h> 111 112#include <vm/vm.h> /* for vtophys */ 113#include <vm/pmap.h> /* for vtophys */ 114#include <machine/bus_pio.h> 115#include <machine/bus_memio.h> 116#include <machine/bus.h> 117#include <machine/resource.h> 118#include <sys/bus.h> 119#include <sys/rman.h> 120 121#include <dev/mii/mii.h> 122#include <dev/mii/miivar.h> 123 124#include <pci/pcireg.h> 125#include <pci/pcivar.h> 126 127#define DC_USEIOSPACE 128#ifdef __alpha__ 129#define SRM_MEDIA 130#endif 131 132#include <pci/if_dcreg.h> 133 134MODULE_DEPEND(dc, pci, 1, 1, 1); 135MODULE_DEPEND(dc, ether, 1, 1, 1); 136MODULE_DEPEND(dc, miibus, 1, 1, 1); 137 138/* "controller miibus0" required. See GENERIC if you get errors here. */ 139#include "miibus_if.h" 140 141/* 142 * Various supported device vendors/types and their names. 143 */ 144static struct dc_type dc_devs[] = { 145 { DC_VENDORID_DEC, DC_DEVICEID_21143, 146 "Intel 21143 10/100BaseTX" }, 147 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 148 "Davicom DM9009 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 150 "Davicom DM9100 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154 "Davicom DM9102A 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 156 "ADMtek AL981 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 158 "ADMtek AN985 10/100BaseTX" }, 159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160 "ASIX AX88140A 10/100BaseTX" }, 161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 162 "ASIX AX88141 10/100BaseTX" }, 163 { DC_VENDORID_MX, DC_DEVICEID_98713, 164 "Macronix 98713 10/100BaseTX" }, 165 { DC_VENDORID_MX, DC_DEVICEID_98713, 166 "Macronix 98713A 10/100BaseTX" }, 167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168 "Compex RL100-TX 10/100BaseTX" }, 169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 170 "Compex RL100-TX 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98715/98715A 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98715AEC-C 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_987x5, 176 "Macronix 98725 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98727, 178 "Macronix 98727/98732 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C115, 180 "LC82C115 PNIC II 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C168, 182 "82c168 PNIC 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C168, 184 "82c169 PNIC 10/100BaseTX" }, 185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 186 "Accton EN1217 10/100BaseTX" }, 187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 188 "Accton EN2242 MiniPCI 10/100BaseTX" }, 189 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 190 "Xircom X3201 10/100BaseTX" }, 191 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 192 "Abocom FE2500 10/100BaseTX" }, 193 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 194 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 195 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 196 "Hawking CB102 CardBus 10/100" }, 197 { 0, 0, NULL } 198}; 199 200static int dc_probe (device_t); 201static int dc_attach (device_t); 202static int dc_detach (device_t); 203static int dc_suspend (device_t); 204static int dc_resume (device_t); 205static void dc_acpi (device_t); 206static struct dc_type *dc_devtype (device_t); 207static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 208static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 209static void dc_pnic_rx_bug_war (struct dc_softc *, int); 210static int dc_rx_resync (struct dc_softc *); 211static void dc_rxeof (struct dc_softc *); 212static void dc_txeof (struct dc_softc *); 213static void dc_tick (void *); 214static void dc_tx_underrun (struct dc_softc *); 215static void dc_intr (void *); 216static void dc_start (struct ifnet *); 217static int dc_ioctl (struct ifnet *, u_long, caddr_t); 218static void dc_init (void *); 219static void dc_stop (struct dc_softc *); 220static void dc_watchdog (struct ifnet *); 221static void dc_shutdown (device_t); 222static int dc_ifmedia_upd (struct ifnet *); 223static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 224 225static void dc_delay (struct dc_softc *); 226static void dc_eeprom_idle (struct dc_softc *); 227static void dc_eeprom_putbyte (struct dc_softc *, int); 228static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 229static void dc_eeprom_getword_pnic 230 (struct dc_softc *, int, u_int16_t *); 231static void dc_eeprom_getword_xircom 232 (struct dc_softc *, int, u_int16_t *); 233static void dc_eeprom_width (struct dc_softc *); 234static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 235 236static void dc_mii_writebit (struct dc_softc *, int); 237static int dc_mii_readbit (struct dc_softc *); 238static void dc_mii_sync (struct dc_softc *); 239static void dc_mii_send (struct dc_softc *, u_int32_t, int); 240static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 241static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 242static int dc_miibus_readreg (device_t, int, int); 243static int dc_miibus_writereg (device_t, int, int, int); 244static void dc_miibus_statchg (device_t); 245static void dc_miibus_mediainit (device_t); 246 247static void dc_setcfg (struct dc_softc *, int); 248static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 249static u_int32_t dc_crc_be (caddr_t); 250static void dc_setfilt_21143 (struct dc_softc *); 251static void dc_setfilt_asix (struct dc_softc *); 252static void dc_setfilt_admtek (struct dc_softc *); 253static void dc_setfilt_xircom (struct dc_softc *); 254 255static void dc_setfilt (struct dc_softc *); 256 257static void dc_reset (struct dc_softc *); 258static int dc_list_rx_init (struct dc_softc *); 259static int dc_list_tx_init (struct dc_softc *); 260 261static void dc_read_srom (struct dc_softc *, int); 262static void dc_parse_21143_srom (struct dc_softc *); 263static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 264static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 265static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 266static void dc_apply_fixup (struct dc_softc *, int); 267 268#ifdef DC_USEIOSPACE 269#define DC_RES SYS_RES_IOPORT 270#define DC_RID DC_PCI_CFBIO 271#else 272#define DC_RES SYS_RES_MEMORY 273#define DC_RID DC_PCI_CFBMA 274#endif 275 276static device_method_t dc_methods[] = { 277 /* Device interface */ 278 DEVMETHOD(device_probe, dc_probe), 279 DEVMETHOD(device_attach, dc_attach), 280 DEVMETHOD(device_detach, dc_detach), 281 DEVMETHOD(device_suspend, dc_suspend), 282 DEVMETHOD(device_resume, dc_resume), 283 DEVMETHOD(device_shutdown, dc_shutdown), 284 285 /* bus interface */ 286 DEVMETHOD(bus_print_child, bus_generic_print_child), 287 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 288 289 /* MII interface */ 290 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 291 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 292 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 293 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 294 295 { 0, 0 } 296}; 297 298static driver_t dc_driver = { 299 "dc", 300 dc_methods, 301 sizeof(struct dc_softc) 302}; 303 304static devclass_t dc_devclass; 305#ifdef __i386__ 306static int dc_quick=1; 307SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 308 &dc_quick,0,"do not mdevget in dc driver"); 309#endif 310 311DRIVER_MODULE(dc, cardbus, dc_driver, dc_devclass, 0, 0); 312DRIVER_MODULE(dc, pci, dc_driver, dc_devclass, 0, 0); 313DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 314 315#define DC_SETBIT(sc, reg, x) \ 316 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 317 318#define DC_CLRBIT(sc, reg, x) \ 319 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 320 321#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 322#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 323 324#define IS_MPSAFE 0 325 326static void 327dc_delay(sc) 328 struct dc_softc *sc; 329{ 330 int idx; 331 332 for (idx = (300 / 33) + 1; idx > 0; idx--) 333 CSR_READ_4(sc, DC_BUSCTL); 334} 335 336static void 337dc_eeprom_width(sc) 338 struct dc_softc *sc; 339{ 340 int i; 341 342 /* Force EEPROM to idle state. */ 343 dc_eeprom_idle(sc); 344 345 /* Enter EEPROM access mode. */ 346 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 347 dc_delay(sc); 348 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 349 dc_delay(sc); 350 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 351 dc_delay(sc); 352 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 353 dc_delay(sc); 354 355 for (i = 3; i--;) { 356 if (6 & (1 << i)) 357 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 358 else 359 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 360 dc_delay(sc); 361 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 362 dc_delay(sc); 363 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 364 dc_delay(sc); 365 } 366 367 for (i = 1; i <= 12; i++) { 368 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 369 dc_delay(sc); 370 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 371 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 372 dc_delay(sc); 373 break; 374 } 375 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 376 dc_delay(sc); 377 } 378 379 /* Turn off EEPROM access mode. */ 380 dc_eeprom_idle(sc); 381 382 if (i < 4 || i > 12) 383 sc->dc_romwidth = 6; 384 else 385 sc->dc_romwidth = i; 386 387 /* Enter EEPROM access mode. */ 388 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 389 dc_delay(sc); 390 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 391 dc_delay(sc); 392 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 393 dc_delay(sc); 394 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 395 dc_delay(sc); 396 397 /* Turn off EEPROM access mode. */ 398 dc_eeprom_idle(sc); 399} 400 401static void 402dc_eeprom_idle(sc) 403 struct dc_softc *sc; 404{ 405 register int i; 406 407 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 408 dc_delay(sc); 409 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 410 dc_delay(sc); 411 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 412 dc_delay(sc); 413 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 414 dc_delay(sc); 415 416 for (i = 0; i < 25; i++) { 417 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 418 dc_delay(sc); 419 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 420 dc_delay(sc); 421 } 422 423 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 424 dc_delay(sc); 425 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 426 dc_delay(sc); 427 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 428 429 return; 430} 431 432/* 433 * Send a read command and address to the EEPROM, check for ACK. 434 */ 435static void 436dc_eeprom_putbyte(sc, addr) 437 struct dc_softc *sc; 438 int addr; 439{ 440 register int d, i; 441 442 d = DC_EECMD_READ >> 6; 443 for (i = 3; i--; ) { 444 if (d & (1 << i)) 445 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 446 else 447 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 448 dc_delay(sc); 449 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 450 dc_delay(sc); 451 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 452 dc_delay(sc); 453 } 454 455 /* 456 * Feed in each bit and strobe the clock. 457 */ 458 for (i = sc->dc_romwidth; i--;) { 459 if (addr & (1 << i)) { 460 SIO_SET(DC_SIO_EE_DATAIN); 461 } else { 462 SIO_CLR(DC_SIO_EE_DATAIN); 463 } 464 dc_delay(sc); 465 SIO_SET(DC_SIO_EE_CLK); 466 dc_delay(sc); 467 SIO_CLR(DC_SIO_EE_CLK); 468 dc_delay(sc); 469 } 470 471 return; 472} 473 474/* 475 * Read a word of data stored in the EEPROM at address 'addr.' 476 * The PNIC 82c168/82c169 has its own non-standard way to read 477 * the EEPROM. 478 */ 479static void 480dc_eeprom_getword_pnic(sc, addr, dest) 481 struct dc_softc *sc; 482 int addr; 483 u_int16_t *dest; 484{ 485 register int i; 486 u_int32_t r; 487 488 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 489 490 for (i = 0; i < DC_TIMEOUT; i++) { 491 DELAY(1); 492 r = CSR_READ_4(sc, DC_SIO); 493 if (!(r & DC_PN_SIOCTL_BUSY)) { 494 *dest = (u_int16_t)(r & 0xFFFF); 495 return; 496 } 497 } 498 499 return; 500} 501 502/* 503 * Read a word of data stored in the EEPROM at address 'addr.' 504 * The Xircom X3201 has its own non-standard way to read 505 * the EEPROM, too. 506 */ 507static void 508dc_eeprom_getword_xircom(sc, addr, dest) 509 struct dc_softc *sc; 510 int addr; 511 u_int16_t *dest; 512{ 513 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 514 515 addr *= 2; 516 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 517 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 518 addr += 1; 519 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 520 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 521 522 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 523 return; 524} 525 526/* 527 * Read a word of data stored in the EEPROM at address 'addr.' 528 */ 529static void 530dc_eeprom_getword(sc, addr, dest) 531 struct dc_softc *sc; 532 int addr; 533 u_int16_t *dest; 534{ 535 register int i; 536 u_int16_t word = 0; 537 538 /* Force EEPROM to idle state. */ 539 dc_eeprom_idle(sc); 540 541 /* Enter EEPROM access mode. */ 542 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 543 dc_delay(sc); 544 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 545 dc_delay(sc); 546 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 547 dc_delay(sc); 548 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 549 dc_delay(sc); 550 551 /* 552 * Send address of word we want to read. 553 */ 554 dc_eeprom_putbyte(sc, addr); 555 556 /* 557 * Start reading bits from EEPROM. 558 */ 559 for (i = 0x8000; i; i >>= 1) { 560 SIO_SET(DC_SIO_EE_CLK); 561 dc_delay(sc); 562 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 563 word |= i; 564 dc_delay(sc); 565 SIO_CLR(DC_SIO_EE_CLK); 566 dc_delay(sc); 567 } 568 569 /* Turn off EEPROM access mode. */ 570 dc_eeprom_idle(sc); 571 572 *dest = word; 573 574 return; 575} 576 577/* 578 * Read a sequence of words from the EEPROM. 579 */ 580static void 581dc_read_eeprom(sc, dest, off, cnt, swap) 582 struct dc_softc *sc; 583 caddr_t dest; 584 int off; 585 int cnt; 586 int swap; 587{ 588 int i; 589 u_int16_t word = 0, *ptr; 590 591 for (i = 0; i < cnt; i++) { 592 if (DC_IS_PNIC(sc)) 593 dc_eeprom_getword_pnic(sc, off + i, &word); 594 else if (DC_IS_XIRCOM(sc)) 595 dc_eeprom_getword_xircom(sc, off + i, &word); 596 else 597 dc_eeprom_getword(sc, off + i, &word); 598 ptr = (u_int16_t *)(dest + (i * 2)); 599 if (swap) 600 *ptr = ntohs(word); 601 else 602 *ptr = word; 603 } 604 605 return; 606} 607 608/* 609 * The following two routines are taken from the Macronix 98713 610 * Application Notes pp.19-21. 611 */ 612/* 613 * Write a bit to the MII bus. 614 */ 615static void 616dc_mii_writebit(sc, bit) 617 struct dc_softc *sc; 618 int bit; 619{ 620 if (bit) 621 CSR_WRITE_4(sc, DC_SIO, 622 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 623 else 624 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 625 626 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 627 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 628 629 return; 630} 631 632/* 633 * Read a bit from the MII bus. 634 */ 635static int 636dc_mii_readbit(sc) 637 struct dc_softc *sc; 638{ 639 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 640 CSR_READ_4(sc, DC_SIO); 641 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 642 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 643 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 644 return(1); 645 646 return(0); 647} 648 649/* 650 * Sync the PHYs by setting data bit and strobing the clock 32 times. 651 */ 652static void 653dc_mii_sync(sc) 654 struct dc_softc *sc; 655{ 656 register int i; 657 658 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 659 660 for (i = 0; i < 32; i++) 661 dc_mii_writebit(sc, 1); 662 663 return; 664} 665 666/* 667 * Clock a series of bits through the MII. 668 */ 669static void 670dc_mii_send(sc, bits, cnt) 671 struct dc_softc *sc; 672 u_int32_t bits; 673 int cnt; 674{ 675 int i; 676 677 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 678 dc_mii_writebit(sc, bits & i); 679} 680 681/* 682 * Read an PHY register through the MII. 683 */ 684static int 685dc_mii_readreg(sc, frame) 686 struct dc_softc *sc; 687 struct dc_mii_frame *frame; 688 689{ 690 int i, ack; 691 692 DC_LOCK(sc); 693 694 /* 695 * Set up frame for RX. 696 */ 697 frame->mii_stdelim = DC_MII_STARTDELIM; 698 frame->mii_opcode = DC_MII_READOP; 699 frame->mii_turnaround = 0; 700 frame->mii_data = 0; 701 702 /* 703 * Sync the PHYs. 704 */ 705 dc_mii_sync(sc); 706 707 /* 708 * Send command/address info. 709 */ 710 dc_mii_send(sc, frame->mii_stdelim, 2); 711 dc_mii_send(sc, frame->mii_opcode, 2); 712 dc_mii_send(sc, frame->mii_phyaddr, 5); 713 dc_mii_send(sc, frame->mii_regaddr, 5); 714 715#ifdef notdef 716 /* Idle bit */ 717 dc_mii_writebit(sc, 1); 718 dc_mii_writebit(sc, 0); 719#endif 720 721 /* Check for ack */ 722 ack = dc_mii_readbit(sc); 723 724 /* 725 * Now try reading data bits. If the ack failed, we still 726 * need to clock through 16 cycles to keep the PHY(s) in sync. 727 */ 728 if (ack) { 729 for(i = 0; i < 16; i++) { 730 dc_mii_readbit(sc); 731 } 732 goto fail; 733 } 734 735 for (i = 0x8000; i; i >>= 1) { 736 if (!ack) { 737 if (dc_mii_readbit(sc)) 738 frame->mii_data |= i; 739 } 740 } 741 742fail: 743 744 dc_mii_writebit(sc, 0); 745 dc_mii_writebit(sc, 0); 746 747 DC_UNLOCK(sc); 748 749 if (ack) 750 return(1); 751 return(0); 752} 753 754/* 755 * Write to a PHY register through the MII. 756 */ 757static int 758dc_mii_writereg(sc, frame) 759 struct dc_softc *sc; 760 struct dc_mii_frame *frame; 761 762{ 763 DC_LOCK(sc); 764 /* 765 * Set up frame for TX. 766 */ 767 768 frame->mii_stdelim = DC_MII_STARTDELIM; 769 frame->mii_opcode = DC_MII_WRITEOP; 770 frame->mii_turnaround = DC_MII_TURNAROUND; 771 772 /* 773 * Sync the PHYs. 774 */ 775 dc_mii_sync(sc); 776 777 dc_mii_send(sc, frame->mii_stdelim, 2); 778 dc_mii_send(sc, frame->mii_opcode, 2); 779 dc_mii_send(sc, frame->mii_phyaddr, 5); 780 dc_mii_send(sc, frame->mii_regaddr, 5); 781 dc_mii_send(sc, frame->mii_turnaround, 2); 782 dc_mii_send(sc, frame->mii_data, 16); 783 784 /* Idle bit. */ 785 dc_mii_writebit(sc, 0); 786 dc_mii_writebit(sc, 0); 787 788 DC_UNLOCK(sc); 789 790 return(0); 791} 792 793static int 794dc_miibus_readreg(dev, phy, reg) 795 device_t dev; 796 int phy, reg; 797{ 798 struct dc_mii_frame frame; 799 struct dc_softc *sc; 800 int i, rval, phy_reg = 0; 801 802 sc = device_get_softc(dev); 803 bzero((char *)&frame, sizeof(frame)); 804 805 /* 806 * Note: both the AL981 and AN985 have internal PHYs, 807 * however the AL981 provides direct access to the PHY 808 * registers while the AN985 uses a serial MII interface. 809 * The AN985's MII interface is also buggy in that you 810 * can read from any MII address (0 to 31), but only address 1 811 * behaves normally. To deal with both cases, we pretend 812 * that the PHY is at MII address 1. 813 */ 814 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 815 return(0); 816 817 /* 818 * Note: the ukphy probes of the RS7112 report a PHY at 819 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 820 * so we only respond to correct one. 821 */ 822 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 823 return(0); 824 825 if (sc->dc_pmode != DC_PMODE_MII) { 826 if (phy == (MII_NPHY - 1)) { 827 switch(reg) { 828 case MII_BMSR: 829 /* 830 * Fake something to make the probe 831 * code think there's a PHY here. 832 */ 833 return(BMSR_MEDIAMASK); 834 break; 835 case MII_PHYIDR1: 836 if (DC_IS_PNIC(sc)) 837 return(DC_VENDORID_LO); 838 return(DC_VENDORID_DEC); 839 break; 840 case MII_PHYIDR2: 841 if (DC_IS_PNIC(sc)) 842 return(DC_DEVICEID_82C168); 843 return(DC_DEVICEID_21143); 844 break; 845 default: 846 return(0); 847 break; 848 } 849 } else 850 return(0); 851 } 852 853 if (DC_IS_PNIC(sc)) { 854 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 855 (phy << 23) | (reg << 18)); 856 for (i = 0; i < DC_TIMEOUT; i++) { 857 DELAY(1); 858 rval = CSR_READ_4(sc, DC_PN_MII); 859 if (!(rval & DC_PN_MII_BUSY)) { 860 rval &= 0xFFFF; 861 return(rval == 0xFFFF ? 0 : rval); 862 } 863 } 864 return(0); 865 } 866 867 if (DC_IS_COMET(sc)) { 868 switch(reg) { 869 case MII_BMCR: 870 phy_reg = DC_AL_BMCR; 871 break; 872 case MII_BMSR: 873 phy_reg = DC_AL_BMSR; 874 break; 875 case MII_PHYIDR1: 876 phy_reg = DC_AL_VENID; 877 break; 878 case MII_PHYIDR2: 879 phy_reg = DC_AL_DEVID; 880 break; 881 case MII_ANAR: 882 phy_reg = DC_AL_ANAR; 883 break; 884 case MII_ANLPAR: 885 phy_reg = DC_AL_LPAR; 886 break; 887 case MII_ANER: 888 phy_reg = DC_AL_ANER; 889 break; 890 default: 891 printf("dc%d: phy_read: bad phy register %x\n", 892 sc->dc_unit, reg); 893 return(0); 894 break; 895 } 896 897 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 898 899 if (rval == 0xFFFF) 900 return(0); 901 return(rval); 902 } 903 904 frame.mii_phyaddr = phy; 905 frame.mii_regaddr = reg; 906 if (sc->dc_type == DC_TYPE_98713) { 907 phy_reg = CSR_READ_4(sc, DC_NETCFG); 908 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 909 } 910 dc_mii_readreg(sc, &frame); 911 if (sc->dc_type == DC_TYPE_98713) 912 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 913 914 return(frame.mii_data); 915} 916 917static int 918dc_miibus_writereg(dev, phy, reg, data) 919 device_t dev; 920 int phy, reg, data; 921{ 922 struct dc_softc *sc; 923 struct dc_mii_frame frame; 924 int i, phy_reg = 0; 925 926 sc = device_get_softc(dev); 927 bzero((char *)&frame, sizeof(frame)); 928 929 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 930 return(0); 931 932 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 933 return(0); 934 935 if (DC_IS_PNIC(sc)) { 936 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 937 (phy << 23) | (reg << 10) | data); 938 for (i = 0; i < DC_TIMEOUT; i++) { 939 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 940 break; 941 } 942 return(0); 943 } 944 945 if (DC_IS_COMET(sc)) { 946 switch(reg) { 947 case MII_BMCR: 948 phy_reg = DC_AL_BMCR; 949 break; 950 case MII_BMSR: 951 phy_reg = DC_AL_BMSR; 952 break; 953 case MII_PHYIDR1: 954 phy_reg = DC_AL_VENID; 955 break; 956 case MII_PHYIDR2: 957 phy_reg = DC_AL_DEVID; 958 break; 959 case MII_ANAR: 960 phy_reg = DC_AL_ANAR; 961 break; 962 case MII_ANLPAR: 963 phy_reg = DC_AL_LPAR; 964 break; 965 case MII_ANER: 966 phy_reg = DC_AL_ANER; 967 break; 968 default: 969 printf("dc%d: phy_write: bad phy register %x\n", 970 sc->dc_unit, reg); 971 return(0); 972 break; 973 } 974 975 CSR_WRITE_4(sc, phy_reg, data); 976 return(0); 977 } 978 979 frame.mii_phyaddr = phy; 980 frame.mii_regaddr = reg; 981 frame.mii_data = data; 982 983 if (sc->dc_type == DC_TYPE_98713) { 984 phy_reg = CSR_READ_4(sc, DC_NETCFG); 985 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 986 } 987 dc_mii_writereg(sc, &frame); 988 if (sc->dc_type == DC_TYPE_98713) 989 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 990 991 return(0); 992} 993 994static void 995dc_miibus_statchg(dev) 996 device_t dev; 997{ 998 struct dc_softc *sc; 999 struct mii_data *mii; 1000 struct ifmedia *ifm; 1001 1002 sc = device_get_softc(dev); 1003 if (DC_IS_ADMTEK(sc)) 1004 return; 1005 1006 mii = device_get_softc(sc->dc_miibus); 1007 ifm = &mii->mii_media; 1008 if (DC_IS_DAVICOM(sc) && 1009 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 1010 dc_setcfg(sc, ifm->ifm_media); 1011 sc->dc_if_media = ifm->ifm_media; 1012 } else { 1013 dc_setcfg(sc, mii->mii_media_active); 1014 sc->dc_if_media = mii->mii_media_active; 1015 } 1016 1017 return; 1018} 1019 1020/* 1021 * Special support for DM9102A cards with HomePNA PHYs. Note: 1022 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1023 * to be impossible to talk to the management interface of the DM9801 1024 * PHY (its MDIO pin is not connected to anything). Consequently, 1025 * the driver has to just 'know' about the additional mode and deal 1026 * with it itself. *sigh* 1027 */ 1028static void 1029dc_miibus_mediainit(dev) 1030 device_t dev; 1031{ 1032 struct dc_softc *sc; 1033 struct mii_data *mii; 1034 struct ifmedia *ifm; 1035 int rev; 1036 1037 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1038 1039 sc = device_get_softc(dev); 1040 mii = device_get_softc(sc->dc_miibus); 1041 ifm = &mii->mii_media; 1042 1043 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1044 ifmedia_add(ifm, IFM_ETHER|IFM_HPNA_1, 0, NULL); 1045 1046 return; 1047} 1048 1049#define DC_POLY 0xEDB88320 1050#define DC_BITS_512 9 1051#define DC_BITS_128 7 1052#define DC_BITS_64 6 1053 1054static u_int32_t 1055dc_crc_le(sc, addr) 1056 struct dc_softc *sc; 1057 caddr_t addr; 1058{ 1059 u_int32_t idx, bit, data, crc; 1060 1061 /* Compute CRC for the address value. */ 1062 crc = 0xFFFFFFFF; /* initial value */ 1063 1064 for (idx = 0; idx < 6; idx++) { 1065 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1066 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1067 } 1068 1069 /* 1070 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1071 * chips is only 128 bits wide. 1072 */ 1073 if (sc->dc_flags & DC_128BIT_HASH) 1074 return (crc & ((1 << DC_BITS_128) - 1)); 1075 1076 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1077 if (sc->dc_flags & DC_64BIT_HASH) 1078 return (crc & ((1 << DC_BITS_64) - 1)); 1079 1080 /* Xircom's hash filtering table is different (read: weird) */ 1081 /* Xircom uses the LEAST significant bits */ 1082 if (DC_IS_XIRCOM(sc)) { 1083 if ((crc & 0x180) == 0x180) 1084 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 1085 else 1086 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 1087 } 1088 1089 return (crc & ((1 << DC_BITS_512) - 1)); 1090} 1091 1092/* 1093 * Calculate CRC of a multicast group address, return the lower 6 bits. 1094 */ 1095static u_int32_t 1096dc_crc_be(addr) 1097 caddr_t addr; 1098{ 1099 u_int32_t crc, carry; 1100 int i, j; 1101 u_int8_t c; 1102 1103 /* Compute CRC for the address value. */ 1104 crc = 0xFFFFFFFF; /* initial value */ 1105 1106 for (i = 0; i < 6; i++) { 1107 c = *(addr + i); 1108 for (j = 0; j < 8; j++) { 1109 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1110 crc <<= 1; 1111 c >>= 1; 1112 if (carry) 1113 crc = (crc ^ 0x04c11db6) | carry; 1114 } 1115 } 1116 1117 /* return the filter bit position */ 1118 return((crc >> 26) & 0x0000003F); 1119} 1120 1121/* 1122 * 21143-style RX filter setup routine. Filter programming is done by 1123 * downloading a special setup frame into the TX engine. 21143, Macronix, 1124 * PNIC, PNIC II and Davicom chips are programmed this way. 1125 * 1126 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1127 * address (our node address) and a 512-bit hash filter for multicast 1128 * frames. We also sneak the broadcast address into the hash filter since 1129 * we need that too. 1130 */ 1131static void 1132dc_setfilt_21143(sc) 1133 struct dc_softc *sc; 1134{ 1135 struct dc_desc *sframe; 1136 u_int32_t h, *sp; 1137 struct ifmultiaddr *ifma; 1138 struct ifnet *ifp; 1139 int i; 1140 1141 ifp = &sc->arpcom.ac_if; 1142 1143 i = sc->dc_cdata.dc_tx_prod; 1144 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1145 sc->dc_cdata.dc_tx_cnt++; 1146 sframe = &sc->dc_ldata->dc_tx_list[i]; 1147 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1148 bzero((char *)sp, DC_SFRAME_LEN); 1149 1150 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1151 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1152 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1153 1154 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1155 1156 /* If we want promiscuous mode, set the allframes bit. */ 1157 if (ifp->if_flags & IFF_PROMISC) 1158 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1159 else 1160 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1161 1162 if (ifp->if_flags & IFF_ALLMULTI) 1163 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1164 else 1165 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1166 1167 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1168 if (ifma->ifma_addr->sa_family != AF_LINK) 1169 continue; 1170 h = dc_crc_le(sc, 1171 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1172 sp[h >> 4] |= 1 << (h & 0xF); 1173 } 1174 1175 if (ifp->if_flags & IFF_BROADCAST) { 1176 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1177 sp[h >> 4] |= 1 << (h & 0xF); 1178 } 1179 1180 /* Set our MAC address */ 1181 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1182 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1183 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1184 1185 sframe->dc_status = DC_TXSTAT_OWN; 1186 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1187 1188 /* 1189 * The PNIC takes an exceedingly long time to process its 1190 * setup frame; wait 10ms after posting the setup frame 1191 * before proceeding, just so it has time to swallow its 1192 * medicine. 1193 */ 1194 DELAY(10000); 1195 1196 ifp->if_timer = 5; 1197 1198 return; 1199} 1200 1201static void 1202dc_setfilt_admtek(sc) 1203 struct dc_softc *sc; 1204{ 1205 struct ifnet *ifp; 1206 int h = 0; 1207 u_int32_t hashes[2] = { 0, 0 }; 1208 struct ifmultiaddr *ifma; 1209 1210 ifp = &sc->arpcom.ac_if; 1211 1212 /* Init our MAC address */ 1213 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1214 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1215 1216 /* If we want promiscuous mode, set the allframes bit. */ 1217 if (ifp->if_flags & IFF_PROMISC) 1218 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1219 else 1220 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1221 1222 if (ifp->if_flags & IFF_ALLMULTI) 1223 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1224 else 1225 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1226 1227 /* first, zot all the existing hash bits */ 1228 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1229 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1230 1231 /* 1232 * If we're already in promisc or allmulti mode, we 1233 * don't have to bother programming the multicast filter. 1234 */ 1235 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1236 return; 1237 1238 /* now program new ones */ 1239 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1240 if (ifma->ifma_addr->sa_family != AF_LINK) 1241 continue; 1242 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1243 if (h < 32) 1244 hashes[0] |= (1 << h); 1245 else 1246 hashes[1] |= (1 << (h - 32)); 1247 } 1248 1249 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1250 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1251 1252 return; 1253} 1254 1255static void 1256dc_setfilt_asix(sc) 1257 struct dc_softc *sc; 1258{ 1259 struct ifnet *ifp; 1260 int h = 0; 1261 u_int32_t hashes[2] = { 0, 0 }; 1262 struct ifmultiaddr *ifma; 1263 1264 ifp = &sc->arpcom.ac_if; 1265 1266 /* Init our MAC address */ 1267 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1268 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1269 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1270 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1271 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1272 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1273 1274 /* If we want promiscuous mode, set the allframes bit. */ 1275 if (ifp->if_flags & IFF_PROMISC) 1276 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1277 else 1278 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1279 1280 if (ifp->if_flags & IFF_ALLMULTI) 1281 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1282 else 1283 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1284 1285 /* 1286 * The ASIX chip has a special bit to enable reception 1287 * of broadcast frames. 1288 */ 1289 if (ifp->if_flags & IFF_BROADCAST) 1290 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1291 else 1292 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1293 1294 /* first, zot all the existing hash bits */ 1295 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1296 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1297 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1298 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1299 1300 /* 1301 * If we're already in promisc or allmulti mode, we 1302 * don't have to bother programming the multicast filter. 1303 */ 1304 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1305 return; 1306 1307 /* now program new ones */ 1308 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1309 if (ifma->ifma_addr->sa_family != AF_LINK) 1310 continue; 1311 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1312 if (h < 32) 1313 hashes[0] |= (1 << h); 1314 else 1315 hashes[1] |= (1 << (h - 32)); 1316 } 1317 1318 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1319 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1320 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1321 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1322 1323 return; 1324} 1325 1326static void 1327dc_setfilt_xircom(sc) 1328 struct dc_softc *sc; 1329{ 1330 struct dc_desc *sframe; 1331 u_int32_t h, *sp; 1332 struct ifmultiaddr *ifma; 1333 struct ifnet *ifp; 1334 int i; 1335 1336 ifp = &sc->arpcom.ac_if; 1337 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1338 1339 i = sc->dc_cdata.dc_tx_prod; 1340 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1341 sc->dc_cdata.dc_tx_cnt++; 1342 sframe = &sc->dc_ldata->dc_tx_list[i]; 1343 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1344 bzero((char *)sp, DC_SFRAME_LEN); 1345 1346 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1347 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1348 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1349 1350 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1351 1352 /* If we want promiscuous mode, set the allframes bit. */ 1353 if (ifp->if_flags & IFF_PROMISC) 1354 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1355 else 1356 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1357 1358 if (ifp->if_flags & IFF_ALLMULTI) 1359 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1360 else 1361 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1362 1363 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1364 if (ifma->ifma_addr->sa_family != AF_LINK) 1365 continue; 1366 h = dc_crc_le(sc, 1367 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1368 sp[h >> 4] |= 1 << (h & 0xF); 1369 } 1370 1371 if (ifp->if_flags & IFF_BROADCAST) { 1372 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1373 sp[h >> 4] |= 1 << (h & 0xF); 1374 } 1375 1376 /* Set our MAC address */ 1377 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1378 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1379 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1380 1381 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1382 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1383 ifp->if_flags |= IFF_RUNNING; 1384 sframe->dc_status = DC_TXSTAT_OWN; 1385 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1386 1387 /* 1388 * wait some time... 1389 */ 1390 DELAY(1000); 1391 1392 ifp->if_timer = 5; 1393 1394 return; 1395} 1396 1397static void 1398dc_setfilt(sc) 1399 struct dc_softc *sc; 1400{ 1401 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1402 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1403 dc_setfilt_21143(sc); 1404 1405 if (DC_IS_ASIX(sc)) 1406 dc_setfilt_asix(sc); 1407 1408 if (DC_IS_ADMTEK(sc)) 1409 dc_setfilt_admtek(sc); 1410 1411 if (DC_IS_XIRCOM(sc)) 1412 dc_setfilt_xircom(sc); 1413 1414 return; 1415} 1416 1417/* 1418 * In order to fiddle with the 1419 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1420 * first have to put the transmit and/or receive logic in the idle state. 1421 */ 1422static void 1423dc_setcfg(sc, media) 1424 struct dc_softc *sc; 1425 int media; 1426{ 1427 int i, restart = 0; 1428 u_int32_t isr; 1429 1430 if (IFM_SUBTYPE(media) == IFM_NONE) 1431 return; 1432 1433 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1434 restart = 1; 1435 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1436 1437 for (i = 0; i < DC_TIMEOUT; i++) { 1438 isr = CSR_READ_4(sc, DC_ISR); 1439 if (isr & DC_ISR_TX_IDLE && 1440 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1441 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1442 break; 1443 DELAY(10); 1444 } 1445 1446 if (i == DC_TIMEOUT) 1447 printf("dc%d: failed to force tx and " 1448 "rx to idle state\n", sc->dc_unit); 1449 } 1450 1451 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1452 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1453 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1454 if (sc->dc_pmode == DC_PMODE_MII) { 1455 int watchdogreg; 1456 1457 if (DC_IS_INTEL(sc)) { 1458 /* there's a write enable bit here that reads as 1 */ 1459 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1460 watchdogreg &= ~DC_WDOG_CTLWREN; 1461 watchdogreg |= DC_WDOG_JABBERDIS; 1462 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1463 } else { 1464 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1465 } 1466 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1467 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1468 if (sc->dc_type == DC_TYPE_98713) 1469 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1470 DC_NETCFG_SCRAMBLER)); 1471 if (!DC_IS_DAVICOM(sc)) 1472 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1473 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1474 if (DC_IS_INTEL(sc)) 1475 dc_apply_fixup(sc, IFM_AUTO); 1476 } else { 1477 if (DC_IS_PNIC(sc)) { 1478 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1479 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1480 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1481 } 1482 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1483 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1484 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1485 if (DC_IS_INTEL(sc)) 1486 dc_apply_fixup(sc, 1487 (media & IFM_GMASK) == IFM_FDX ? 1488 IFM_100_TX|IFM_FDX : IFM_100_TX); 1489 } 1490 } 1491 1492 if (IFM_SUBTYPE(media) == IFM_10_T) { 1493 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1494 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1495 if (sc->dc_pmode == DC_PMODE_MII) { 1496 int watchdogreg; 1497 1498 /* there's a write enable bit here that reads as 1 */ 1499 if (DC_IS_INTEL(sc)) { 1500 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1501 watchdogreg &= ~DC_WDOG_CTLWREN; 1502 watchdogreg |= DC_WDOG_JABBERDIS; 1503 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1504 } else { 1505 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1506 } 1507 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1508 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1509 if (sc->dc_type == DC_TYPE_98713) 1510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1511 if (!DC_IS_DAVICOM(sc)) 1512 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1513 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1514 if (DC_IS_INTEL(sc)) 1515 dc_apply_fixup(sc, IFM_AUTO); 1516 } else { 1517 if (DC_IS_PNIC(sc)) { 1518 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1519 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1520 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1521 } 1522 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1523 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1524 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1525 if (DC_IS_INTEL(sc)) { 1526 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1527 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1528 if ((media & IFM_GMASK) == IFM_FDX) 1529 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1530 else 1531 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1532 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1533 DC_CLRBIT(sc, DC_10BTCTRL, 1534 DC_TCTL_AUTONEGENBL); 1535 dc_apply_fixup(sc, 1536 (media & IFM_GMASK) == IFM_FDX ? 1537 IFM_10_T|IFM_FDX : IFM_10_T); 1538 DELAY(20000); 1539 } 1540 } 1541 } 1542 1543 /* 1544 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1545 * PHY and we want HomePNA mode, set the portsel bit to turn 1546 * on the external MII port. 1547 */ 1548 if (DC_IS_DAVICOM(sc)) { 1549 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1550 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1551 sc->dc_link = 1; 1552 } else { 1553 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1554 } 1555 } 1556 1557 if ((media & IFM_GMASK) == IFM_FDX) { 1558 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1559 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1560 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1561 } else { 1562 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1563 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1564 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1565 } 1566 1567 if (restart) 1568 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1569 1570 return; 1571} 1572 1573static void 1574dc_reset(sc) 1575 struct dc_softc *sc; 1576{ 1577 register int i; 1578 1579 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1580 1581 for (i = 0; i < DC_TIMEOUT; i++) { 1582 DELAY(10); 1583 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1584 break; 1585 } 1586 1587 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1588 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1589 DELAY(10000); 1590 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1591 i = 0; 1592 } 1593 1594 if (i == DC_TIMEOUT) 1595 printf("dc%d: reset never completed!\n", sc->dc_unit); 1596 1597 /* Wait a little while for the chip to get its brains in order. */ 1598 DELAY(1000); 1599 1600 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1601 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1602 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1603 1604 /* 1605 * Bring the SIA out of reset. In some cases, it looks 1606 * like failing to unreset the SIA soon enough gets it 1607 * into a state where it will never come out of reset 1608 * until we reset the whole chip again. 1609 */ 1610 if (DC_IS_INTEL(sc)) { 1611 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1612 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1613 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1614 } 1615 1616 return; 1617} 1618 1619static struct dc_type * 1620dc_devtype(dev) 1621 device_t dev; 1622{ 1623 struct dc_type *t; 1624 u_int32_t rev; 1625 1626 t = dc_devs; 1627 1628 while(t->dc_name != NULL) { 1629 if ((pci_get_vendor(dev) == t->dc_vid) && 1630 (pci_get_device(dev) == t->dc_did)) { 1631 /* Check the PCI revision */ 1632 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1633 if (t->dc_did == DC_DEVICEID_98713 && 1634 rev >= DC_REVISION_98713A) 1635 t++; 1636 if (t->dc_did == DC_DEVICEID_98713_CP && 1637 rev >= DC_REVISION_98713A) 1638 t++; 1639 if (t->dc_did == DC_DEVICEID_987x5 && 1640 rev >= DC_REVISION_98715AEC_C) 1641 t++; 1642 if (t->dc_did == DC_DEVICEID_987x5 && 1643 rev >= DC_REVISION_98725) 1644 t++; 1645 if (t->dc_did == DC_DEVICEID_AX88140A && 1646 rev >= DC_REVISION_88141) 1647 t++; 1648 if (t->dc_did == DC_DEVICEID_82C168 && 1649 rev >= DC_REVISION_82C169) 1650 t++; 1651 if (t->dc_did == DC_DEVICEID_DM9102 && 1652 rev >= DC_REVISION_DM9102A) 1653 t++; 1654 return(t); 1655 } 1656 t++; 1657 } 1658 1659 return(NULL); 1660} 1661 1662/* 1663 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1664 * IDs against our list and return a device name if we find a match. 1665 * We do a little bit of extra work to identify the exact type of 1666 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1667 * but different revision IDs. The same is true for 98715/98715A 1668 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1669 * cases, the exact chip revision affects driver behavior. 1670 */ 1671static int 1672dc_probe(dev) 1673 device_t dev; 1674{ 1675 struct dc_type *t; 1676 1677 t = dc_devtype(dev); 1678 1679 if (t != NULL) { 1680 device_set_desc(dev, t->dc_name); 1681 return(0); 1682 } 1683 1684 return(ENXIO); 1685} 1686 1687static void 1688dc_acpi(dev) 1689 device_t dev; 1690{ 1691 int unit; 1692 1693 unit = device_get_unit(dev); 1694 1695 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1696 u_int32_t iobase, membase, irq; 1697 1698 /* Save important PCI config data. */ 1699 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1700 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1701 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1702 1703 /* Reset the power state. */ 1704 printf("dc%d: chip is in D%d power mode " 1705 "-- setting to D0\n", unit, 1706 pci_get_powerstate(dev)); 1707 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1708 1709 /* Restore PCI config data. */ 1710 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1711 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1712 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1713 } 1714 1715 return; 1716} 1717 1718static void 1719dc_apply_fixup(sc, media) 1720 struct dc_softc *sc; 1721 int media; 1722{ 1723 struct dc_mediainfo *m; 1724 u_int8_t *p; 1725 int i; 1726 u_int32_t reg; 1727 1728 m = sc->dc_mi; 1729 1730 while (m != NULL) { 1731 if (m->dc_media == media) 1732 break; 1733 m = m->dc_next; 1734 } 1735 1736 if (m == NULL) 1737 return; 1738 1739 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1740 reg = (p[0] | (p[1] << 8)) << 16; 1741 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1742 } 1743 1744 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1745 reg = (p[0] | (p[1] << 8)) << 16; 1746 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1747 } 1748 1749 return; 1750} 1751 1752static void 1753dc_decode_leaf_sia(sc, l) 1754 struct dc_softc *sc; 1755 struct dc_eblock_sia *l; 1756{ 1757 struct dc_mediainfo *m; 1758 1759 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1760 bzero(m, sizeof(struct dc_mediainfo)); 1761 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1762 m->dc_media = IFM_10_T; 1763 1764 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1765 m->dc_media = IFM_10_T|IFM_FDX; 1766 1767 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1768 m->dc_media = IFM_10_2; 1769 1770 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1771 m->dc_media = IFM_10_5; 1772 1773 m->dc_gp_len = 2; 1774 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1775 1776 m->dc_next = sc->dc_mi; 1777 sc->dc_mi = m; 1778 1779 sc->dc_pmode = DC_PMODE_SIA; 1780 1781 return; 1782} 1783 1784static void 1785dc_decode_leaf_sym(sc, l) 1786 struct dc_softc *sc; 1787 struct dc_eblock_sym *l; 1788{ 1789 struct dc_mediainfo *m; 1790 1791 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1792 bzero(m, sizeof(struct dc_mediainfo)); 1793 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1794 m->dc_media = IFM_100_TX; 1795 1796 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1797 m->dc_media = IFM_100_TX|IFM_FDX; 1798 1799 m->dc_gp_len = 2; 1800 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1801 1802 m->dc_next = sc->dc_mi; 1803 sc->dc_mi = m; 1804 1805 sc->dc_pmode = DC_PMODE_SYM; 1806 1807 return; 1808} 1809 1810static void 1811dc_decode_leaf_mii(sc, l) 1812 struct dc_softc *sc; 1813 struct dc_eblock_mii *l; 1814{ 1815 u_int8_t *p; 1816 struct dc_mediainfo *m; 1817 1818 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1819 bzero(m, sizeof(struct dc_mediainfo)); 1820 /* We abuse IFM_AUTO to represent MII. */ 1821 m->dc_media = IFM_AUTO; 1822 m->dc_gp_len = l->dc_gpr_len; 1823 1824 p = (u_int8_t *)l; 1825 p += sizeof(struct dc_eblock_mii); 1826 m->dc_gp_ptr = p; 1827 p += 2 * l->dc_gpr_len; 1828 m->dc_reset_len = *p; 1829 p++; 1830 m->dc_reset_ptr = p; 1831 1832 m->dc_next = sc->dc_mi; 1833 sc->dc_mi = m; 1834 1835 return; 1836} 1837 1838static void 1839dc_read_srom(sc, bits) 1840 struct dc_softc *sc; 1841 int bits; 1842{ 1843 int size; 1844 1845 size = 2 << bits; 1846 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1847 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1848} 1849 1850static void 1851dc_parse_21143_srom(sc) 1852 struct dc_softc *sc; 1853{ 1854 struct dc_leaf_hdr *lhdr; 1855 struct dc_eblock_hdr *hdr; 1856 int i, loff; 1857 char *ptr; 1858 1859 loff = sc->dc_srom[27]; 1860 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1861 1862 ptr = (char *)lhdr; 1863 ptr += sizeof(struct dc_leaf_hdr) - 1; 1864 for (i = 0; i < lhdr->dc_mcnt; i++) { 1865 hdr = (struct dc_eblock_hdr *)ptr; 1866 switch(hdr->dc_type) { 1867 case DC_EBLOCK_MII: 1868 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1869 break; 1870 case DC_EBLOCK_SIA: 1871 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1872 break; 1873 case DC_EBLOCK_SYM: 1874 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1875 break; 1876 default: 1877 /* Don't care. Yet. */ 1878 break; 1879 } 1880 ptr += (hdr->dc_len & 0x7F); 1881 ptr++; 1882 } 1883 1884 return; 1885} 1886 1887/* 1888 * Attach the interface. Allocate softc structures, do ifmedia 1889 * setup and ethernet/BPF attach. 1890 */ 1891static int 1892dc_attach(dev) 1893 device_t dev; 1894{ 1895 int tmp = 0; 1896 u_char eaddr[ETHER_ADDR_LEN]; 1897 u_int32_t command; 1898 struct dc_softc *sc; 1899 struct ifnet *ifp; 1900 u_int32_t revision; 1901 int unit, error = 0, rid, mac_offset; 1902 u_int8_t *mac; 1903 1904 sc = device_get_softc(dev); 1905 unit = device_get_unit(dev); 1906 1907 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1908 MTX_DEF | MTX_RECURSE); 1909 1910 /* 1911 * Handle power management nonsense. 1912 */ 1913 dc_acpi(dev); 1914 1915 /* 1916 * Map control/status registers. 1917 */ 1918 pci_enable_busmaster(dev); 1919 1920 rid = DC_RID; 1921 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1922 0, ~0, 1, RF_ACTIVE); 1923 1924 if (sc->dc_res == NULL) { 1925 printf("dc%d: couldn't map ports/memory\n", unit); 1926 error = ENXIO; 1927 goto fail; 1928 } 1929 1930 sc->dc_btag = rman_get_bustag(sc->dc_res); 1931 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1932 1933 /* Allocate interrupt */ 1934 rid = 0; 1935 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1936 RF_SHAREABLE | RF_ACTIVE); 1937 1938 if (sc->dc_irq == NULL) { 1939 printf("dc%d: couldn't map interrupt\n", unit); 1940 error = ENXIO; 1941 goto fail; 1942 } 1943 1944 /* Need this info to decide on a chip type. */ 1945 sc->dc_info = dc_devtype(dev); 1946 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1947 1948 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1949 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1950 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1951 dc_eeprom_width(sc); 1952 1953 switch(sc->dc_info->dc_did) { 1954 case DC_DEVICEID_21143: 1955 sc->dc_type = DC_TYPE_21143; 1956 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1957 sc->dc_flags |= DC_REDUCED_MII_POLL; 1958 /* Save EEPROM contents so we can parse them later. */ 1959 dc_read_srom(sc, sc->dc_romwidth); 1960 break; 1961 case DC_DEVICEID_DM9009: 1962 case DC_DEVICEID_DM9100: 1963 case DC_DEVICEID_DM9102: 1964 sc->dc_type = DC_TYPE_DM9102; 1965 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1966 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1967 sc->dc_pmode = DC_PMODE_MII; 1968 /* Increase the latency timer value. */ 1969 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1970 command &= 0xFFFF00FF; 1971 command |= 0x00008000; 1972 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1973 break; 1974 case DC_DEVICEID_AL981: 1975 sc->dc_type = DC_TYPE_AL981; 1976 sc->dc_flags |= DC_TX_USE_TX_INTR; 1977 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1978 sc->dc_pmode = DC_PMODE_MII; 1979 dc_read_srom(sc, sc->dc_romwidth); 1980 break; 1981 case DC_DEVICEID_AN985: 1982 case DC_DEVICEID_FE2500: 1983 case DC_DEVICEID_EN2242: 1984 case DC_DEVICEID_HAWKING_PN672TX: 1985 sc->dc_type = DC_TYPE_AN985; 1986 sc->dc_flags |= DC_TX_USE_TX_INTR; 1987 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1988 sc->dc_pmode = DC_PMODE_MII; 1989 dc_read_srom(sc, sc->dc_romwidth); 1990 break; 1991 case DC_DEVICEID_98713: 1992 case DC_DEVICEID_98713_CP: 1993 if (revision < DC_REVISION_98713A) { 1994 sc->dc_type = DC_TYPE_98713; 1995 } 1996 if (revision >= DC_REVISION_98713A) { 1997 sc->dc_type = DC_TYPE_98713A; 1998 sc->dc_flags |= DC_21143_NWAY; 1999 } 2000 sc->dc_flags |= DC_REDUCED_MII_POLL; 2001 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2002 break; 2003 case DC_DEVICEID_987x5: 2004 case DC_DEVICEID_EN1217: 2005 /* 2006 * Macronix MX98715AEC-C/D/E parts have only a 2007 * 128-bit hash table. We need to deal with these 2008 * in the same manner as the PNIC II so that we 2009 * get the right number of bits out of the 2010 * CRC routine. 2011 */ 2012 if (revision >= DC_REVISION_98715AEC_C && 2013 revision < DC_REVISION_98725) 2014 sc->dc_flags |= DC_128BIT_HASH; 2015 sc->dc_type = DC_TYPE_987x5; 2016 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2017 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2018 break; 2019 case DC_DEVICEID_98727: 2020 sc->dc_type = DC_TYPE_987x5; 2021 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2022 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2023 break; 2024 case DC_DEVICEID_82C115: 2025 sc->dc_type = DC_TYPE_PNICII; 2026 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 2027 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2028 break; 2029 case DC_DEVICEID_82C168: 2030 sc->dc_type = DC_TYPE_PNIC; 2031 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 2032 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2033 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2034 if (revision < DC_REVISION_82C169) 2035 sc->dc_pmode = DC_PMODE_SYM; 2036 break; 2037 case DC_DEVICEID_AX88140A: 2038 sc->dc_type = DC_TYPE_ASIX; 2039 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 2040 sc->dc_flags |= DC_REDUCED_MII_POLL; 2041 sc->dc_pmode = DC_PMODE_MII; 2042 break; 2043 case DC_DEVICEID_X3201: 2044 sc->dc_type = DC_TYPE_XIRCOM; 2045 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2046 DC_TX_ALIGN; 2047 /* 2048 * We don't actually need to coalesce, but we're doing 2049 * it to obtain a double word aligned buffer. 2050 * The DC_TX_COALESCE flag is required. 2051 */ 2052 sc->dc_pmode = DC_PMODE_MII; 2053 break; 2054 case DC_DEVICEID_RS7112: 2055 sc->dc_type = DC_TYPE_CONEXANT; 2056 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2057 sc->dc_flags |= DC_REDUCED_MII_POLL; 2058 sc->dc_pmode = DC_PMODE_MII; 2059 dc_read_srom(sc, sc->dc_romwidth); 2060 break; 2061 default: 2062 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2063 sc->dc_info->dc_did); 2064 break; 2065 } 2066 2067 /* Save the cache line size. */ 2068 if (DC_IS_DAVICOM(sc)) 2069 sc->dc_cachesize = 0; 2070 else 2071 sc->dc_cachesize = pci_read_config(dev, 2072 DC_PCI_CFLT, 4) & 0xFF; 2073 2074 /* Reset the adapter. */ 2075 dc_reset(sc); 2076 2077 /* Take 21143 out of snooze mode */ 2078 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2079 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2080 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2081 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2082 } 2083 2084 /* 2085 * Try to learn something about the supported media. 2086 * We know that ASIX and ADMtek and Davicom devices 2087 * will *always* be using MII media, so that's a no-brainer. 2088 * The tricky ones are the Macronix/PNIC II and the 2089 * Intel 21143. 2090 */ 2091 if (DC_IS_INTEL(sc)) 2092 dc_parse_21143_srom(sc); 2093 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2094 if (sc->dc_type == DC_TYPE_98713) 2095 sc->dc_pmode = DC_PMODE_MII; 2096 else 2097 sc->dc_pmode = DC_PMODE_SYM; 2098 } else if (!sc->dc_pmode) 2099 sc->dc_pmode = DC_PMODE_MII; 2100 2101 /* 2102 * Get station address from the EEPROM. 2103 */ 2104 switch(sc->dc_type) { 2105 case DC_TYPE_98713: 2106 case DC_TYPE_98713A: 2107 case DC_TYPE_987x5: 2108 case DC_TYPE_PNICII: 2109 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2110 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2111 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2112 break; 2113 case DC_TYPE_PNIC: 2114 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2115 break; 2116 case DC_TYPE_DM9102: 2117 case DC_TYPE_21143: 2118 case DC_TYPE_ASIX: 2119 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2120 break; 2121 case DC_TYPE_AL981: 2122 case DC_TYPE_AN985: 2123 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 2124 ETHER_ADDR_LEN); 2125 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2126 break; 2127 case DC_TYPE_CONEXANT: 2128 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2129 break; 2130 case DC_TYPE_XIRCOM: 2131 /* The MAC comes from the CIS */ 2132 mac = pci_get_ether(dev); 2133 if (!mac) { 2134 device_printf(dev, "No station address in CIS!\n"); 2135 error = ENXIO; 2136 goto fail; 2137 } 2138 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2139 break; 2140 default: 2141 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2142 break; 2143 } 2144 2145 /* 2146 * A 21143 or clone chip was detected. Inform the world. 2147 */ 2148 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2149 2150 sc->dc_unit = unit; 2151 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2152 2153 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2154 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2155 2156 if (sc->dc_ldata == NULL) { 2157 printf("dc%d: no memory for list buffers!\n", unit); 2158 error = ENXIO; 2159 goto fail; 2160 } 2161 2162 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2163 2164 ifp = &sc->arpcom.ac_if; 2165 ifp->if_softc = sc; 2166 ifp->if_unit = unit; 2167 ifp->if_name = "dc"; 2168 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2169 ifp->if_mtu = ETHERMTU; 2170 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2171 ifp->if_ioctl = dc_ioctl; 2172 ifp->if_output = ether_output; 2173 ifp->if_start = dc_start; 2174 ifp->if_watchdog = dc_watchdog; 2175 ifp->if_init = dc_init; 2176 ifp->if_baudrate = 10000000; 2177 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2178 2179 /* 2180 * Do MII setup. If this is a 21143, check for a PHY on the 2181 * MII bus after applying any necessary fixups to twiddle the 2182 * GPIO bits. If we don't end up finding a PHY, restore the 2183 * old selection (SIA only or SIA/SYM) and attach the dcphy 2184 * driver instead. 2185 */ 2186 if (DC_IS_INTEL(sc)) { 2187 dc_apply_fixup(sc, IFM_AUTO); 2188 tmp = sc->dc_pmode; 2189 sc->dc_pmode = DC_PMODE_MII; 2190 } 2191 2192 error = mii_phy_probe(dev, &sc->dc_miibus, 2193 dc_ifmedia_upd, dc_ifmedia_sts); 2194 2195 if (error && DC_IS_INTEL(sc)) { 2196 sc->dc_pmode = tmp; 2197 if (sc->dc_pmode != DC_PMODE_SIA) 2198 sc->dc_pmode = DC_PMODE_SYM; 2199 sc->dc_flags |= DC_21143_NWAY; 2200 mii_phy_probe(dev, &sc->dc_miibus, 2201 dc_ifmedia_upd, dc_ifmedia_sts); 2202 /* 2203 * For non-MII cards, we need to have the 21143 2204 * drive the LEDs. Except there are some systems 2205 * like the NEC VersaPro NoteBook PC which have no 2206 * LEDs, and twiddling these bits has adverse effects 2207 * on them. (I.e. you suddenly can't get a link.) 2208 */ 2209 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2210 sc->dc_flags |= DC_TULIP_LEDS; 2211 error = 0; 2212 } 2213 2214 if (error) { 2215 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2216 goto fail; 2217 } 2218 2219 if (DC_IS_XIRCOM(sc)) { 2220 /* 2221 * setup General Purpose Port mode and data so the tulip 2222 * can talk to the MII. 2223 */ 2224 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2225 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2226 DELAY(10); 2227 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2228 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2229 DELAY(10); 2230 } 2231 2232 if (DC_IS_ADMTEK(sc)) { 2233 /* 2234 * Set automatic TX underrun recovery for the ADMtek chips 2235 */ 2236 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2237 } 2238 2239 /* 2240 * Tell the upper layer(s) we support long frames. 2241 */ 2242 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2243 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2244 2245 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2246 2247#ifdef SRM_MEDIA 2248 sc->dc_srm_media = 0; 2249 2250 /* Remember the SRM console media setting */ 2251 if (DC_IS_INTEL(sc)) { 2252 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2253 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2254 switch ((command >> 8) & 0xff) { 2255 case 3: 2256 sc->dc_srm_media = IFM_10_T; 2257 break; 2258 case 4: 2259 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2260 break; 2261 case 5: 2262 sc->dc_srm_media = IFM_100_TX; 2263 break; 2264 case 6: 2265 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2266 break; 2267 } 2268 if (sc->dc_srm_media) 2269 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2270 } 2271#endif 2272 2273 /* 2274 * Call MI attach routine. 2275 */ 2276 ether_ifattach(ifp, eaddr); 2277 2278 /* Hook interrupt last to avoid having to lock softc */ 2279 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2280 (IS_MPSAFE ? INTR_MPSAFE : 0), 2281 dc_intr, sc, &sc->dc_intrhand); 2282 2283 if (error) { 2284 printf("dc%d: couldn't set up irq\n", unit); 2285 goto fail; 2286 } 2287 2288fail: 2289 if (error) 2290 dc_detach(dev); 2291 return (error); 2292} 2293 2294static int 2295dc_detach(dev) 2296 device_t dev; 2297{ 2298 struct dc_softc *sc; 2299 struct ifnet *ifp; 2300 struct dc_mediainfo *m; 2301 2302 sc = device_get_softc(dev); 2303 KASSERT(mtx_initialized(&sc->dc_mtx), ("dc mutex not initialized")); 2304 DC_LOCK(sc); 2305 2306 ifp = &sc->arpcom.ac_if; 2307 2308 if (device_is_alive(dev)) { 2309 if (bus_child_present(dev)) 2310 dc_stop(sc); 2311 ether_ifdetach(ifp); 2312 device_delete_child(dev, sc->dc_miibus); 2313 bus_generic_detach(dev); 2314 } 2315 2316 if (sc->dc_intrhand) 2317 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2318 if (sc->dc_irq) 2319 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2320 if (sc->dc_res) 2321 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2322 2323 if (sc->dc_ldata) 2324 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2325 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2326 2327 while(sc->dc_mi != NULL) { 2328 m = sc->dc_mi->dc_next; 2329 free(sc->dc_mi, M_DEVBUF); 2330 sc->dc_mi = m; 2331 } 2332 free(sc->dc_srom, M_DEVBUF); 2333 2334 DC_UNLOCK(sc); 2335 mtx_destroy(&sc->dc_mtx); 2336 2337 return(0); 2338} 2339 2340/* 2341 * Initialize the transmit descriptors. 2342 */ 2343static int 2344dc_list_tx_init(sc) 2345 struct dc_softc *sc; 2346{ 2347 struct dc_chain_data *cd; 2348 struct dc_list_data *ld; 2349 int i, nexti; 2350 2351 cd = &sc->dc_cdata; 2352 ld = sc->dc_ldata; 2353 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2354 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2355 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2356 cd->dc_tx_chain[i] = NULL; 2357 ld->dc_tx_list[i].dc_data = 0; 2358 ld->dc_tx_list[i].dc_ctl = 0; 2359 } 2360 2361 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2362 2363 return(0); 2364} 2365 2366 2367/* 2368 * Initialize the RX descriptors and allocate mbufs for them. Note that 2369 * we arrange the descriptors in a closed ring, so that the last descriptor 2370 * points back to the first. 2371 */ 2372static int 2373dc_list_rx_init(sc) 2374 struct dc_softc *sc; 2375{ 2376 struct dc_chain_data *cd; 2377 struct dc_list_data *ld; 2378 int i, nexti; 2379 2380 cd = &sc->dc_cdata; 2381 ld = sc->dc_ldata; 2382 2383 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2384 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2385 return(ENOBUFS); 2386 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2387 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2388 } 2389 2390 cd->dc_rx_prod = 0; 2391 2392 return(0); 2393} 2394 2395/* 2396 * Initialize an RX descriptor and attach an MBUF cluster. 2397 */ 2398static int 2399dc_newbuf(sc, i, m) 2400 struct dc_softc *sc; 2401 int i; 2402 struct mbuf *m; 2403{ 2404 struct mbuf *m_new = NULL; 2405 struct dc_desc *c; 2406 2407 c = &sc->dc_ldata->dc_rx_list[i]; 2408 2409 if (m == NULL) { 2410 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2411 if (m_new == NULL) 2412 return(ENOBUFS); 2413 2414 MCLGET(m_new, M_DONTWAIT); 2415 if (!(m_new->m_flags & M_EXT)) { 2416 m_freem(m_new); 2417 return(ENOBUFS); 2418 } 2419 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2420 } else { 2421 m_new = m; 2422 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2423 m_new->m_data = m_new->m_ext.ext_buf; 2424 } 2425 2426 m_adj(m_new, sizeof(u_int64_t)); 2427 2428 /* 2429 * If this is a PNIC chip, zero the buffer. This is part 2430 * of the workaround for the receive bug in the 82c168 and 2431 * 82c169 chips. 2432 */ 2433 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2434 bzero((char *)mtod(m_new, char *), m_new->m_len); 2435 2436 sc->dc_cdata.dc_rx_chain[i] = m_new; 2437 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2438 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2439 c->dc_status = DC_RXSTAT_OWN; 2440 2441 return(0); 2442} 2443 2444/* 2445 * Grrrrr. 2446 * The PNIC chip has a terrible bug in it that manifests itself during 2447 * periods of heavy activity. The exact mode of failure if difficult to 2448 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2449 * will happen on slow machines. The bug is that sometimes instead of 2450 * uploading one complete frame during reception, it uploads what looks 2451 * like the entire contents of its FIFO memory. The frame we want is at 2452 * the end of the whole mess, but we never know exactly how much data has 2453 * been uploaded, so salvaging the frame is hard. 2454 * 2455 * There is only one way to do it reliably, and it's disgusting. 2456 * Here's what we know: 2457 * 2458 * - We know there will always be somewhere between one and three extra 2459 * descriptors uploaded. 2460 * 2461 * - We know the desired received frame will always be at the end of the 2462 * total data upload. 2463 * 2464 * - We know the size of the desired received frame because it will be 2465 * provided in the length field of the status word in the last descriptor. 2466 * 2467 * Here's what we do: 2468 * 2469 * - When we allocate buffers for the receive ring, we bzero() them. 2470 * This means that we know that the buffer contents should be all 2471 * zeros, except for data uploaded by the chip. 2472 * 2473 * - We also force the PNIC chip to upload frames that include the 2474 * ethernet CRC at the end. 2475 * 2476 * - We gather all of the bogus frame data into a single buffer. 2477 * 2478 * - We then position a pointer at the end of this buffer and scan 2479 * backwards until we encounter the first non-zero byte of data. 2480 * This is the end of the received frame. We know we will encounter 2481 * some data at the end of the frame because the CRC will always be 2482 * there, so even if the sender transmits a packet of all zeros, 2483 * we won't be fooled. 2484 * 2485 * - We know the size of the actual received frame, so we subtract 2486 * that value from the current pointer location. This brings us 2487 * to the start of the actual received packet. 2488 * 2489 * - We copy this into an mbuf and pass it on, along with the actual 2490 * frame length. 2491 * 2492 * The performance hit is tremendous, but it beats dropping frames all 2493 * the time. 2494 */ 2495 2496#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2497static void 2498dc_pnic_rx_bug_war(sc, idx) 2499 struct dc_softc *sc; 2500 int idx; 2501{ 2502 struct dc_desc *cur_rx; 2503 struct dc_desc *c = NULL; 2504 struct mbuf *m = NULL; 2505 unsigned char *ptr; 2506 int i, total_len; 2507 u_int32_t rxstat = 0; 2508 2509 i = sc->dc_pnic_rx_bug_save; 2510 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2511 ptr = sc->dc_pnic_rx_buf; 2512 bzero(ptr, sizeof(DC_RXLEN * 5)); 2513 2514 /* Copy all the bytes from the bogus buffers. */ 2515 while (1) { 2516 c = &sc->dc_ldata->dc_rx_list[i]; 2517 rxstat = c->dc_status; 2518 m = sc->dc_cdata.dc_rx_chain[i]; 2519 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2520 ptr += DC_RXLEN; 2521 /* If this is the last buffer, break out. */ 2522 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2523 break; 2524 dc_newbuf(sc, i, m); 2525 DC_INC(i, DC_RX_LIST_CNT); 2526 } 2527 2528 /* Find the length of the actual receive frame. */ 2529 total_len = DC_RXBYTES(rxstat); 2530 2531 /* Scan backwards until we hit a non-zero byte. */ 2532 while(*ptr == 0x00) 2533 ptr--; 2534 2535 /* Round off. */ 2536 if ((uintptr_t)(ptr) & 0x3) 2537 ptr -= 1; 2538 2539 /* Now find the start of the frame. */ 2540 ptr -= total_len; 2541 if (ptr < sc->dc_pnic_rx_buf) 2542 ptr = sc->dc_pnic_rx_buf; 2543 2544 /* 2545 * Now copy the salvaged frame to the last mbuf and fake up 2546 * the status word to make it look like a successful 2547 * frame reception. 2548 */ 2549 dc_newbuf(sc, i, m); 2550 bcopy(ptr, mtod(m, char *), total_len); 2551 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2552 2553 return; 2554} 2555 2556/* 2557 * This routine searches the RX ring for dirty descriptors in the 2558 * event that the rxeof routine falls out of sync with the chip's 2559 * current descriptor pointer. This may happen sometimes as a result 2560 * of a "no RX buffer available" condition that happens when the chip 2561 * consumes all of the RX buffers before the driver has a chance to 2562 * process the RX ring. This routine may need to be called more than 2563 * once to bring the driver back in sync with the chip, however we 2564 * should still be getting RX DONE interrupts to drive the search 2565 * for new packets in the RX ring, so we should catch up eventually. 2566 */ 2567static int 2568dc_rx_resync(sc) 2569 struct dc_softc *sc; 2570{ 2571 int i, pos; 2572 struct dc_desc *cur_rx; 2573 2574 pos = sc->dc_cdata.dc_rx_prod; 2575 2576 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2577 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2578 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2579 break; 2580 DC_INC(pos, DC_RX_LIST_CNT); 2581 } 2582 2583 /* If the ring really is empty, then just return. */ 2584 if (i == DC_RX_LIST_CNT) 2585 return(0); 2586 2587 /* We've fallen behing the chip: catch it. */ 2588 sc->dc_cdata.dc_rx_prod = pos; 2589 2590 return(EAGAIN); 2591} 2592 2593/* 2594 * A frame has been uploaded: pass the resulting mbuf chain up to 2595 * the higher level protocols. 2596 */ 2597static void 2598dc_rxeof(sc) 2599 struct dc_softc *sc; 2600{ 2601 struct mbuf *m; 2602 struct ifnet *ifp; 2603 struct dc_desc *cur_rx; 2604 int i, total_len = 0; 2605 u_int32_t rxstat; 2606 2607 ifp = &sc->arpcom.ac_if; 2608 i = sc->dc_cdata.dc_rx_prod; 2609 2610 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2611 2612#ifdef DEVICE_POLLING 2613 if (ifp->if_flags & IFF_POLLING) { 2614 if (sc->rxcycles <= 0) 2615 break; 2616 sc->rxcycles--; 2617 } 2618#endif /* DEVICE_POLLING */ 2619 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2620 rxstat = cur_rx->dc_status; 2621 m = sc->dc_cdata.dc_rx_chain[i]; 2622 total_len = DC_RXBYTES(rxstat); 2623 2624 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2625 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2626 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2627 sc->dc_pnic_rx_bug_save = i; 2628 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2629 DC_INC(i, DC_RX_LIST_CNT); 2630 continue; 2631 } 2632 dc_pnic_rx_bug_war(sc, i); 2633 rxstat = cur_rx->dc_status; 2634 total_len = DC_RXBYTES(rxstat); 2635 } 2636 } 2637 2638 sc->dc_cdata.dc_rx_chain[i] = NULL; 2639 2640 /* 2641 * If an error occurs, update stats, clear the 2642 * status word and leave the mbuf cluster in place: 2643 * it should simply get re-used next time this descriptor 2644 * comes up in the ring. However, don't report long 2645 * frames as errors since they could be vlans 2646 */ 2647 if ((rxstat & DC_RXSTAT_RXERR)){ 2648 if (!(rxstat & DC_RXSTAT_GIANT) || 2649 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2650 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2651 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2652 ifp->if_ierrors++; 2653 if (rxstat & DC_RXSTAT_COLLSEEN) 2654 ifp->if_collisions++; 2655 dc_newbuf(sc, i, m); 2656 if (rxstat & DC_RXSTAT_CRCERR) { 2657 DC_INC(i, DC_RX_LIST_CNT); 2658 continue; 2659 } else { 2660 dc_init(sc); 2661 return; 2662 } 2663 } 2664 } 2665 2666 /* No errors; receive the packet. */ 2667 total_len -= ETHER_CRC_LEN; 2668#ifdef __i386__ 2669 /* 2670 * On the x86 we do not have alignment problems, so try to 2671 * allocate a new buffer for the receive ring, and pass up 2672 * the one where the packet is already, saving the expensive 2673 * copy done in m_devget(). 2674 * If we are on an architecture with alignment problems, or 2675 * if the allocation fails, then use m_devget and leave the 2676 * existing buffer in the receive ring. 2677 */ 2678 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2679 m->m_pkthdr.rcvif = ifp; 2680 m->m_pkthdr.len = m->m_len = total_len; 2681 DC_INC(i, DC_RX_LIST_CNT); 2682 } else 2683#endif 2684 { 2685 struct mbuf *m0; 2686 2687 m0 = m_devget(mtod(m, char *), total_len, 2688 ETHER_ALIGN, ifp, NULL); 2689 dc_newbuf(sc, i, m); 2690 DC_INC(i, DC_RX_LIST_CNT); 2691 if (m0 == NULL) { 2692 ifp->if_ierrors++; 2693 continue; 2694 } 2695 m = m0; 2696 } 2697 2698 ifp->if_ipackets++; 2699 (*ifp->if_input)(ifp, m); 2700 } 2701 2702 sc->dc_cdata.dc_rx_prod = i; 2703} 2704 2705/* 2706 * A frame was downloaded to the chip. It's safe for us to clean up 2707 * the list buffers. 2708 */ 2709 2710static void 2711dc_txeof(sc) 2712 struct dc_softc *sc; 2713{ 2714 struct dc_desc *cur_tx = NULL; 2715 struct ifnet *ifp; 2716 int idx; 2717 2718 ifp = &sc->arpcom.ac_if; 2719 2720 /* 2721 * Go through our tx list and free mbufs for those 2722 * frames that have been transmitted. 2723 */ 2724 idx = sc->dc_cdata.dc_tx_cons; 2725 while(idx != sc->dc_cdata.dc_tx_prod) { 2726 u_int32_t txstat; 2727 2728 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2729 txstat = cur_tx->dc_status; 2730 2731 if (txstat & DC_TXSTAT_OWN) 2732 break; 2733 2734 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2735 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2736 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2737 /* 2738 * Yes, the PNIC is so brain damaged 2739 * that it will sometimes generate a TX 2740 * underrun error while DMAing the RX 2741 * filter setup frame. If we detect this, 2742 * we have to send the setup frame again, 2743 * or else the filter won't be programmed 2744 * correctly. 2745 */ 2746 if (DC_IS_PNIC(sc)) { 2747 if (txstat & DC_TXSTAT_ERRSUM) 2748 dc_setfilt(sc); 2749 } 2750 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2751 } 2752 sc->dc_cdata.dc_tx_cnt--; 2753 DC_INC(idx, DC_TX_LIST_CNT); 2754 continue; 2755 } 2756 2757 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2758 /* 2759 * XXX: Why does my Xircom taunt me so? 2760 * For some reason it likes setting the CARRLOST flag 2761 * even when the carrier is there. wtf?!? 2762 * Who knows, but Conexant chips have the 2763 * same problem. Maybe they took lessons 2764 * from Xircom. 2765 */ 2766 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2767 sc->dc_pmode == DC_PMODE_MII && 2768 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2769 DC_TXSTAT_NOCARRIER))) 2770 txstat &= ~DC_TXSTAT_ERRSUM; 2771 } else { 2772 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2773 sc->dc_pmode == DC_PMODE_MII && 2774 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2775 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2776 txstat &= ~DC_TXSTAT_ERRSUM; 2777 } 2778 2779 if (txstat & DC_TXSTAT_ERRSUM) { 2780 ifp->if_oerrors++; 2781 if (txstat & DC_TXSTAT_EXCESSCOLL) 2782 ifp->if_collisions++; 2783 if (txstat & DC_TXSTAT_LATECOLL) 2784 ifp->if_collisions++; 2785 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2786 dc_init(sc); 2787 return; 2788 } 2789 } 2790 2791 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2792 2793 ifp->if_opackets++; 2794 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2795 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2796 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2797 } 2798 2799 sc->dc_cdata.dc_tx_cnt--; 2800 DC_INC(idx, DC_TX_LIST_CNT); 2801 } 2802 2803 if (idx != sc->dc_cdata.dc_tx_cons) { 2804 /* some buffers have been freed */ 2805 sc->dc_cdata.dc_tx_cons = idx; 2806 ifp->if_flags &= ~IFF_OACTIVE; 2807 } 2808 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2809 2810 return; 2811} 2812 2813static void 2814dc_tick(xsc) 2815 void *xsc; 2816{ 2817 struct dc_softc *sc; 2818 struct mii_data *mii; 2819 struct ifnet *ifp; 2820 u_int32_t r; 2821 2822 sc = xsc; 2823 DC_LOCK(sc); 2824 ifp = &sc->arpcom.ac_if; 2825 mii = device_get_softc(sc->dc_miibus); 2826 2827 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2828 if (sc->dc_flags & DC_21143_NWAY) { 2829 r = CSR_READ_4(sc, DC_10BTSTAT); 2830 if (IFM_SUBTYPE(mii->mii_media_active) == 2831 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2832 sc->dc_link = 0; 2833 mii_mediachg(mii); 2834 } 2835 if (IFM_SUBTYPE(mii->mii_media_active) == 2836 IFM_10_T && (r & DC_TSTAT_LS10)) { 2837 sc->dc_link = 0; 2838 mii_mediachg(mii); 2839 } 2840 if (sc->dc_link == 0) 2841 mii_tick(mii); 2842 } else { 2843 r = CSR_READ_4(sc, DC_ISR); 2844 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2845 sc->dc_cdata.dc_tx_cnt == 0) { 2846 mii_tick(mii); 2847 if (!(mii->mii_media_status & IFM_ACTIVE)) 2848 sc->dc_link = 0; 2849 } 2850 } 2851 } else 2852 mii_tick(mii); 2853 2854 /* 2855 * When the init routine completes, we expect to be able to send 2856 * packets right away, and in fact the network code will send a 2857 * gratuitous ARP the moment the init routine marks the interface 2858 * as running. However, even though the MAC may have been initialized, 2859 * there may be a delay of a few seconds before the PHY completes 2860 * autonegotiation and the link is brought up. Any transmissions 2861 * made during that delay will be lost. Dealing with this is tricky: 2862 * we can't just pause in the init routine while waiting for the 2863 * PHY to come ready since that would bring the whole system to 2864 * a screeching halt for several seconds. 2865 * 2866 * What we do here is prevent the TX start routine from sending 2867 * any packets until a link has been established. After the 2868 * interface has been initialized, the tick routine will poll 2869 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2870 * that time, packets will stay in the send queue, and once the 2871 * link comes up, they will be flushed out to the wire. 2872 */ 2873 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2874 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2875 sc->dc_link++; 2876 if (ifp->if_snd.ifq_head != NULL) 2877 dc_start(ifp); 2878 } 2879 2880 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2881 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2882 else 2883 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2884 2885 DC_UNLOCK(sc); 2886 2887 return; 2888} 2889 2890/* 2891 * A transmit underrun has occurred. Back off the transmit threshold, 2892 * or switch to store and forward mode if we have to. 2893 */ 2894static void 2895dc_tx_underrun(sc) 2896 struct dc_softc *sc; 2897{ 2898 u_int32_t isr; 2899 int i; 2900 2901 if (DC_IS_DAVICOM(sc)) 2902 dc_init(sc); 2903 2904 if (DC_IS_INTEL(sc)) { 2905 /* 2906 * The real 21143 requires that the transmitter be idle 2907 * in order to change the transmit threshold or store 2908 * and forward state. 2909 */ 2910 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2911 2912 for (i = 0; i < DC_TIMEOUT; i++) { 2913 isr = CSR_READ_4(sc, DC_ISR); 2914 if (isr & DC_ISR_TX_IDLE) 2915 break; 2916 DELAY(10); 2917 } 2918 if (i == DC_TIMEOUT) { 2919 printf("dc%d: failed to force tx to idle state\n", 2920 sc->dc_unit); 2921 dc_init(sc); 2922 } 2923 } 2924 2925 printf("dc%d: TX underrun -- ", sc->dc_unit); 2926 sc->dc_txthresh += DC_TXTHRESH_INC; 2927 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2928 printf("using store and forward mode\n"); 2929 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2930 } else { 2931 printf("increasing TX threshold\n"); 2932 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2933 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2934 } 2935 2936 if (DC_IS_INTEL(sc)) 2937 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2938 2939 return; 2940} 2941 2942#ifdef DEVICE_POLLING 2943static poll_handler_t dc_poll; 2944 2945static void 2946dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2947{ 2948 struct dc_softc *sc = ifp->if_softc; 2949 2950 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2951 /* Re-enable interrupts. */ 2952 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2953 return; 2954 } 2955 sc->rxcycles = count; 2956 dc_rxeof(sc); 2957 dc_txeof(sc); 2958 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2959 dc_start(ifp); 2960 2961 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2962 u_int32_t status; 2963 2964 status = CSR_READ_4(sc, DC_ISR); 2965 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2966 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2967 DC_ISR_BUS_ERR); 2968 if (!status) 2969 return; 2970 /* ack what we have */ 2971 CSR_WRITE_4(sc, DC_ISR, status); 2972 2973 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 2974 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2975 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2976 2977 if (dc_rx_resync(sc)) 2978 dc_rxeof(sc); 2979 } 2980 /* restart transmit unit if necessary */ 2981 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2982 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2983 2984 if (status & DC_ISR_TX_UNDERRUN) 2985 dc_tx_underrun(sc); 2986 2987 if (status & DC_ISR_BUS_ERR) { 2988 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 2989 dc_reset(sc); 2990 dc_init(sc); 2991 } 2992 } 2993} 2994#endif /* DEVICE_POLLING */ 2995 2996static void 2997dc_intr(arg) 2998 void *arg; 2999{ 3000 struct dc_softc *sc; 3001 struct ifnet *ifp; 3002 u_int32_t status; 3003 3004 sc = arg; 3005 3006 if (sc->suspended) { 3007 return; 3008 } 3009 3010 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3011 return; 3012 3013 DC_LOCK(sc); 3014 ifp = &sc->arpcom.ac_if; 3015#ifdef DEVICE_POLLING 3016 if (ifp->if_flags & IFF_POLLING) 3017 goto done; 3018 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3019 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3020 goto done; 3021 } 3022#endif /* DEVICE_POLLING */ 3023 3024 /* Suppress unwanted interrupts */ 3025 if (!(ifp->if_flags & IFF_UP)) { 3026 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3027 dc_stop(sc); 3028 DC_UNLOCK(sc); 3029 return; 3030 } 3031 3032 /* Disable interrupts. */ 3033 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3034 3035 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3036 && status != 0xFFFFFFFF) { 3037 3038 CSR_WRITE_4(sc, DC_ISR, status); 3039 3040 if (status & DC_ISR_RX_OK) { 3041 int curpkts; 3042 curpkts = ifp->if_ipackets; 3043 dc_rxeof(sc); 3044 if (curpkts == ifp->if_ipackets) { 3045 while(dc_rx_resync(sc)) 3046 dc_rxeof(sc); 3047 } 3048 } 3049 3050 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 3051 dc_txeof(sc); 3052 3053 if (status & DC_ISR_TX_IDLE) { 3054 dc_txeof(sc); 3055 if (sc->dc_cdata.dc_tx_cnt) { 3056 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3057 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3058 } 3059 } 3060 3061 if (status & DC_ISR_TX_UNDERRUN) 3062 dc_tx_underrun(sc); 3063 3064 if ((status & DC_ISR_RX_WATDOGTIMEO) 3065 || (status & DC_ISR_RX_NOBUF)) { 3066 int curpkts; 3067 curpkts = ifp->if_ipackets; 3068 dc_rxeof(sc); 3069 if (curpkts == ifp->if_ipackets) { 3070 while(dc_rx_resync(sc)) 3071 dc_rxeof(sc); 3072 } 3073 } 3074 3075 if (status & DC_ISR_BUS_ERR) { 3076 dc_reset(sc); 3077 dc_init(sc); 3078 } 3079 } 3080 3081 /* Re-enable interrupts. */ 3082 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3083 3084 if (ifp->if_snd.ifq_head != NULL) 3085 dc_start(ifp); 3086 3087#ifdef DEVICE_POLLING 3088done: 3089#endif /* DEVICE_POLLING */ 3090 3091 DC_UNLOCK(sc); 3092 3093 return; 3094} 3095 3096/* 3097 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3098 * pointers to the fragment pointers. 3099 */ 3100static int 3101dc_encap(sc, m_head, txidx) 3102 struct dc_softc *sc; 3103 struct mbuf *m_head; 3104 u_int32_t *txidx; 3105{ 3106 struct dc_desc *f = NULL; 3107 struct mbuf *m; 3108 int frag, cur, cnt = 0, chainlen = 0; 3109 3110 /* 3111 * If there's no way we can send any packets, return now. 3112 */ 3113 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3114 return (ENOBUFS); 3115 3116 /* 3117 * Count the number of frags in this chain to see if 3118 * we need to m_defrag. Since the descriptor list is shared 3119 * by all packets, we'll m_defrag long chains so that they 3120 * do not use up the entire list, even if they would fit. 3121 */ 3122 3123 for (m = m_head; m != NULL; m = m->m_next) 3124 chainlen++; 3125 3126 if ((chainlen > DC_TX_LIST_CNT / 4) || 3127 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3128 m = m_defrag(m_head, M_DONTWAIT); 3129 if (m == NULL) 3130 return (ENOBUFS); 3131 m_head = m; 3132 } 3133 3134 /* 3135 * Start packing the mbufs in this chain into 3136 * the fragment pointers. Stop when we run out 3137 * of fragments or hit the end of the mbuf chain. 3138 */ 3139 m = m_head; 3140 cur = frag = *txidx; 3141 3142 for (m = m_head; m != NULL; m = m->m_next) { 3143 if (m->m_len != 0) { 3144 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3145 if (*txidx != sc->dc_cdata.dc_tx_prod && 3146 frag == (DC_TX_LIST_CNT - 1)) 3147 return(ENOBUFS); 3148 } 3149 if ((DC_TX_LIST_CNT - 3150 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3151 return(ENOBUFS); 3152 3153 f = &sc->dc_ldata->dc_tx_list[frag]; 3154 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3155 if (cnt == 0) { 3156 f->dc_status = 0; 3157 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3158 } else 3159 f->dc_status = DC_TXSTAT_OWN; 3160 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3161 cur = frag; 3162 DC_INC(frag, DC_TX_LIST_CNT); 3163 cnt++; 3164 } 3165 } 3166 3167 if (m != NULL) 3168 return(ENOBUFS); 3169 3170 sc->dc_cdata.dc_tx_cnt += cnt; 3171 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3172 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3173 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3174 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3175 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3176 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3177 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3178 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3179 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3180 *txidx = frag; 3181 3182 return(0); 3183} 3184 3185/* 3186 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3187 * to the mbuf data regions directly in the transmit lists. We also save a 3188 * copy of the pointers since the transmit list fragment pointers are 3189 * physical addresses. 3190 */ 3191 3192static void 3193dc_start(ifp) 3194 struct ifnet *ifp; 3195{ 3196 struct dc_softc *sc; 3197 struct mbuf *m_head = NULL, *m; 3198 int idx; 3199 3200 sc = ifp->if_softc; 3201 3202 DC_LOCK(sc); 3203 3204 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3205 DC_UNLOCK(sc); 3206 return; 3207 } 3208 3209 if (ifp->if_flags & IFF_OACTIVE) { 3210 DC_UNLOCK(sc); 3211 return; 3212 } 3213 3214 idx = sc->dc_cdata.dc_tx_prod; 3215 3216 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3217 IF_DEQUEUE(&ifp->if_snd, m_head); 3218 if (m_head == NULL) 3219 break; 3220 3221 if (sc->dc_flags & DC_TX_COALESCE && 3222 (m_head->m_next != NULL || 3223 sc->dc_flags & DC_TX_ALIGN)) { 3224 m = m_defrag(m_head, M_DONTWAIT); 3225 if (m == NULL) { 3226 IF_PREPEND(&ifp->if_snd, m_head); 3227 ifp->if_flags |= IFF_OACTIVE; 3228 break; 3229 } else { 3230 m_head = m; 3231 } 3232 } 3233 3234 if (dc_encap(sc, m_head, &idx)) { 3235 IF_PREPEND(&ifp->if_snd, m_head); 3236 ifp->if_flags |= IFF_OACTIVE; 3237 break; 3238 } 3239 3240 /* 3241 * If there's a BPF listener, bounce a copy of this frame 3242 * to him. 3243 */ 3244 BPF_MTAP(ifp, m_head); 3245 3246 if (sc->dc_flags & DC_TX_ONE) { 3247 ifp->if_flags |= IFF_OACTIVE; 3248 break; 3249 } 3250 } 3251 3252 /* Transmit */ 3253 sc->dc_cdata.dc_tx_prod = idx; 3254 if (!(sc->dc_flags & DC_TX_POLL)) 3255 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3256 3257 /* 3258 * Set a timeout in case the chip goes out to lunch. 3259 */ 3260 ifp->if_timer = 5; 3261 3262 DC_UNLOCK(sc); 3263 3264 return; 3265} 3266 3267static void 3268dc_init(xsc) 3269 void *xsc; 3270{ 3271 struct dc_softc *sc = xsc; 3272 struct ifnet *ifp = &sc->arpcom.ac_if; 3273 struct mii_data *mii; 3274 3275 DC_LOCK(sc); 3276 3277 mii = device_get_softc(sc->dc_miibus); 3278 3279 /* 3280 * Cancel pending I/O and free all RX/TX buffers. 3281 */ 3282 dc_stop(sc); 3283 dc_reset(sc); 3284 3285 /* 3286 * Set cache alignment and burst length. 3287 */ 3288 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3289 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3290 else 3291 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3292 /* 3293 * Evenly share the bus between receive and transmit process. 3294 */ 3295 if (DC_IS_INTEL(sc)) 3296 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3297 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3298 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3299 } else { 3300 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3301 } 3302 if (sc->dc_flags & DC_TX_POLL) 3303 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3304 switch(sc->dc_cachesize) { 3305 case 32: 3306 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3307 break; 3308 case 16: 3309 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3310 break; 3311 case 8: 3312 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3313 break; 3314 case 0: 3315 default: 3316 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3317 break; 3318 } 3319 3320 if (sc->dc_flags & DC_TX_STORENFWD) 3321 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3322 else { 3323 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3324 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3325 } else { 3326 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3327 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3328 } 3329 } 3330 3331 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3332 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3333 3334 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3335 /* 3336 * The app notes for the 98713 and 98715A say that 3337 * in order to have the chips operate properly, a magic 3338 * number must be written to CSR16. Macronix does not 3339 * document the meaning of these bits so there's no way 3340 * to know exactly what they do. The 98713 has a magic 3341 * number all its own; the rest all use a different one. 3342 */ 3343 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3344 if (sc->dc_type == DC_TYPE_98713) 3345 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3346 else 3347 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3348 } 3349 3350 if (DC_IS_XIRCOM(sc)) { 3351 /* 3352 * setup General Purpose Port mode and data so the tulip 3353 * can talk to the MII. 3354 */ 3355 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3356 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3357 DELAY(10); 3358 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3359 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3360 DELAY(10); 3361 } 3362 3363 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3364 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3365 3366 /* Init circular RX list. */ 3367 if (dc_list_rx_init(sc) == ENOBUFS) { 3368 printf("dc%d: initialization failed: no " 3369 "memory for rx buffers\n", sc->dc_unit); 3370 dc_stop(sc); 3371 DC_UNLOCK(sc); 3372 return; 3373 } 3374 3375 /* 3376 * Init tx descriptors. 3377 */ 3378 dc_list_tx_init(sc); 3379 3380 /* 3381 * Load the address of the RX list. 3382 */ 3383 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3384 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3385 3386 /* 3387 * Enable interrupts. 3388 */ 3389#ifdef DEVICE_POLLING 3390 /* 3391 * ... but only if we are not polling, and make sure they are off in 3392 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3393 * after a reset. 3394 */ 3395 if (ifp->if_flags & IFF_POLLING) 3396 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3397 else 3398#endif 3399 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3400 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3401 3402 /* Enable transmitter. */ 3403 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3404 3405 /* 3406 * If this is an Intel 21143 and we're not using the 3407 * MII port, program the LED control pins so we get 3408 * link and activity indications. 3409 */ 3410 if (sc->dc_flags & DC_TULIP_LEDS) { 3411 CSR_WRITE_4(sc, DC_WATCHDOG, 3412 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3413 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3414 } 3415 3416 /* 3417 * Load the RX/multicast filter. We do this sort of late 3418 * because the filter programming scheme on the 21143 and 3419 * some clones requires DMAing a setup frame via the TX 3420 * engine, and we need the transmitter enabled for that. 3421 */ 3422 dc_setfilt(sc); 3423 3424 /* Enable receiver. */ 3425 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3426 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3427 3428 mii_mediachg(mii); 3429 dc_setcfg(sc, sc->dc_if_media); 3430 3431 ifp->if_flags |= IFF_RUNNING; 3432 ifp->if_flags &= ~IFF_OACTIVE; 3433 3434 /* Don't start the ticker if this is a homePNA link. */ 3435 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3436 sc->dc_link = 1; 3437 else { 3438 if (sc->dc_flags & DC_21143_NWAY) 3439 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3440 else 3441 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3442 } 3443 3444#ifdef SRM_MEDIA 3445 if(sc->dc_srm_media) { 3446 struct ifreq ifr; 3447 3448 ifr.ifr_media = sc->dc_srm_media; 3449 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3450 sc->dc_srm_media = 0; 3451 } 3452#endif 3453 DC_UNLOCK(sc); 3454 return; 3455} 3456 3457/* 3458 * Set media options. 3459 */ 3460static int 3461dc_ifmedia_upd(ifp) 3462 struct ifnet *ifp; 3463{ 3464 struct dc_softc *sc; 3465 struct mii_data *mii; 3466 struct ifmedia *ifm; 3467 3468 sc = ifp->if_softc; 3469 mii = device_get_softc(sc->dc_miibus); 3470 mii_mediachg(mii); 3471 ifm = &mii->mii_media; 3472 3473 if (DC_IS_DAVICOM(sc) && 3474 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3475 dc_setcfg(sc, ifm->ifm_media); 3476 else 3477 sc->dc_link = 0; 3478 3479 return(0); 3480} 3481 3482/* 3483 * Report current media status. 3484 */ 3485static void 3486dc_ifmedia_sts(ifp, ifmr) 3487 struct ifnet *ifp; 3488 struct ifmediareq *ifmr; 3489{ 3490 struct dc_softc *sc; 3491 struct mii_data *mii; 3492 struct ifmedia *ifm; 3493 3494 sc = ifp->if_softc; 3495 mii = device_get_softc(sc->dc_miibus); 3496 mii_pollstat(mii); 3497 ifm = &mii->mii_media; 3498 if (DC_IS_DAVICOM(sc)) { 3499 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3500 ifmr->ifm_active = ifm->ifm_media; 3501 ifmr->ifm_status = 0; 3502 return; 3503 } 3504 } 3505 ifmr->ifm_active = mii->mii_media_active; 3506 ifmr->ifm_status = mii->mii_media_status; 3507 3508 return; 3509} 3510 3511static int 3512dc_ioctl(ifp, command, data) 3513 struct ifnet *ifp; 3514 u_long command; 3515 caddr_t data; 3516{ 3517 struct dc_softc *sc = ifp->if_softc; 3518 struct ifreq *ifr = (struct ifreq *) data; 3519 struct mii_data *mii; 3520 int error = 0; 3521 3522 DC_LOCK(sc); 3523 3524 switch(command) { 3525 case SIOCSIFFLAGS: 3526 if (ifp->if_flags & IFF_UP) { 3527 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3528 (IFF_PROMISC | IFF_ALLMULTI); 3529 3530 if (ifp->if_flags & IFF_RUNNING) { 3531 if (need_setfilt) 3532 dc_setfilt(sc); 3533 } else { 3534 sc->dc_txthresh = 0; 3535 dc_init(sc); 3536 } 3537 } else { 3538 if (ifp->if_flags & IFF_RUNNING) 3539 dc_stop(sc); 3540 } 3541 sc->dc_if_flags = ifp->if_flags; 3542 error = 0; 3543 break; 3544 case SIOCADDMULTI: 3545 case SIOCDELMULTI: 3546 dc_setfilt(sc); 3547 error = 0; 3548 break; 3549 case SIOCGIFMEDIA: 3550 case SIOCSIFMEDIA: 3551 mii = device_get_softc(sc->dc_miibus); 3552 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3553#ifdef SRM_MEDIA 3554 if (sc->dc_srm_media) 3555 sc->dc_srm_media = 0; 3556#endif 3557 break; 3558 default: 3559 error = ether_ioctl(ifp, command, data); 3560 break; 3561 } 3562 3563 DC_UNLOCK(sc); 3564 3565 return(error); 3566} 3567 3568static void 3569dc_watchdog(ifp) 3570 struct ifnet *ifp; 3571{ 3572 struct dc_softc *sc; 3573 3574 sc = ifp->if_softc; 3575 3576 DC_LOCK(sc); 3577 3578 ifp->if_oerrors++; 3579 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3580 3581 dc_stop(sc); 3582 dc_reset(sc); 3583 dc_init(sc); 3584 3585 if (ifp->if_snd.ifq_head != NULL) 3586 dc_start(ifp); 3587 3588 DC_UNLOCK(sc); 3589 3590 return; 3591} 3592 3593/* 3594 * Stop the adapter and free any mbufs allocated to the 3595 * RX and TX lists. 3596 */ 3597static void 3598dc_stop(sc) 3599 struct dc_softc *sc; 3600{ 3601 register int i; 3602 struct ifnet *ifp; 3603 3604 DC_LOCK(sc); 3605 3606 ifp = &sc->arpcom.ac_if; 3607 ifp->if_timer = 0; 3608 3609 callout_stop(&sc->dc_stat_ch); 3610 3611 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3612#ifdef DEVICE_POLLING 3613 ether_poll_deregister(ifp); 3614#endif 3615 3616 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3617 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3618 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3619 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3620 sc->dc_link = 0; 3621 3622 /* 3623 * Free data in the RX lists. 3624 */ 3625 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3626 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3627 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3628 sc->dc_cdata.dc_rx_chain[i] = NULL; 3629 } 3630 } 3631 bzero((char *)&sc->dc_ldata->dc_rx_list, 3632 sizeof(sc->dc_ldata->dc_rx_list)); 3633 3634 /* 3635 * Free the TX list buffers. 3636 */ 3637 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3638 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3639 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3640 DC_TXCTL_SETUP) { 3641 sc->dc_cdata.dc_tx_chain[i] = NULL; 3642 continue; 3643 } 3644 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3645 sc->dc_cdata.dc_tx_chain[i] = NULL; 3646 } 3647 } 3648 3649 bzero((char *)&sc->dc_ldata->dc_tx_list, 3650 sizeof(sc->dc_ldata->dc_tx_list)); 3651 3652 DC_UNLOCK(sc); 3653 3654 return; 3655} 3656 3657/* 3658 * Device suspend routine. Stop the interface and save some PCI 3659 * settings in case the BIOS doesn't restore them properly on 3660 * resume. 3661 */ 3662static int 3663dc_suspend(dev) 3664 device_t dev; 3665{ 3666 register int i; 3667 int s; 3668 struct dc_softc *sc; 3669 3670 s = splimp(); 3671 3672 sc = device_get_softc(dev); 3673 3674 dc_stop(sc); 3675 3676 for (i = 0; i < 5; i++) 3677 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3678 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3679 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3680 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3681 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3682 3683 sc->suspended = 1; 3684 3685 splx(s); 3686 return (0); 3687} 3688 3689/* 3690 * Device resume routine. Restore some PCI settings in case the BIOS 3691 * doesn't, re-enable busmastering, and restart the interface if 3692 * appropriate. 3693 */ 3694static int 3695dc_resume(dev) 3696 device_t dev; 3697{ 3698 register int i; 3699 int s; 3700 struct dc_softc *sc; 3701 struct ifnet *ifp; 3702 3703 s = splimp(); 3704 3705 sc = device_get_softc(dev); 3706 ifp = &sc->arpcom.ac_if; 3707 3708 dc_acpi(dev); 3709 3710 /* better way to do this? */ 3711 for (i = 0; i < 5; i++) 3712 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3713 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3714 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3715 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3716 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3717 3718 /* reenable busmastering */ 3719 pci_enable_busmaster(dev); 3720 pci_enable_io(dev, DC_RES); 3721 3722 /* reinitialize interface if necessary */ 3723 if (ifp->if_flags & IFF_UP) 3724 dc_init(sc); 3725 3726 sc->suspended = 0; 3727 3728 splx(s); 3729 return (0); 3730} 3731 3732/* 3733 * Stop all chip I/O so that the kernel's probe routines don't 3734 * get confused by errant DMAs when rebooting. 3735 */ 3736static void 3737dc_shutdown(dev) 3738 device_t dev; 3739{ 3740 struct dc_softc *sc; 3741 3742 sc = device_get_softc(dev); 3743 3744 dc_stop(sc); 3745 3746 return; 3747} 3748