if_dc.c revision 112872
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/dc/if_dc.c 112872 2003-03-31 17:29:43Z njl $ 33 */ 34 35/* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * Conexant LANfinity (www.conexant.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64/* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92#include <sys/param.h> 93#include <sys/systm.h> 94#include <sys/sockio.h> 95#include <sys/mbuf.h> 96#include <sys/malloc.h> 97#include <sys/kernel.h> 98#include <sys/socket.h> 99#include <sys/sysctl.h> 100 101#include <net/if.h> 102#include <net/if_arp.h> 103#include <net/ethernet.h> 104#include <net/if_dl.h> 105#include <net/if_media.h> 106#include <net/if_types.h> 107#include <net/if_vlan_var.h> 108 109#include <net/bpf.h> 110 111#include <vm/vm.h> /* for vtophys */ 112#include <vm/pmap.h> /* for vtophys */ 113#include <machine/bus_pio.h> 114#include <machine/bus_memio.h> 115#include <machine/bus.h> 116#include <machine/resource.h> 117#include <sys/bus.h> 118#include <sys/rman.h> 119 120#include <dev/mii/mii.h> 121#include <dev/mii/miivar.h> 122 123#include <pci/pcireg.h> 124#include <pci/pcivar.h> 125 126#define DC_USEIOSPACE 127#ifdef __alpha__ 128#define SRM_MEDIA 129#endif 130 131#include <pci/if_dcreg.h> 132 133MODULE_DEPEND(dc, miibus, 1, 1, 1); 134 135/* "controller miibus0" required. See GENERIC if you get errors here. */ 136#include "miibus_if.h" 137 138#ifndef lint 139static const char rcsid[] = 140 "$FreeBSD: head/sys/dev/dc/if_dc.c 112872 2003-03-31 17:29:43Z njl $"; 141#endif 142 143/* 144 * Various supported device vendors/types and their names. 145 */ 146static struct dc_type dc_devs[] = { 147 { DC_VENDORID_DEC, DC_DEVICEID_21143, 148 "Intel 21143 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 150 "Davicom DM9009 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 152 "Davicom DM9100 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154 "Davicom DM9102 10/100BaseTX" }, 155 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 156 "Davicom DM9102A 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 158 "ADMtek AL981 10/100BaseTX" }, 159 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 160 "ADMtek AN985 10/100BaseTX" }, 161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 162 "ASIX AX88140A 10/100BaseTX" }, 163 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 164 "ASIX AX88141 10/100BaseTX" }, 165 { DC_VENDORID_MX, DC_DEVICEID_98713, 166 "Macronix 98713 10/100BaseTX" }, 167 { DC_VENDORID_MX, DC_DEVICEID_98713, 168 "Macronix 98713A 10/100BaseTX" }, 169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 170 "Compex RL100-TX 10/100BaseTX" }, 171 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 172 "Compex RL100-TX 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98715/98715A 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_987x5, 176 "Macronix 98715AEC-C 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_987x5, 178 "Macronix 98725 10/100BaseTX" }, 179 { DC_VENDORID_MX, DC_DEVICEID_98727, 180 "Macronix 98727/98732 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C115, 182 "LC82C115 PNIC II 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C168, 184 "82c168 PNIC 10/100BaseTX" }, 185 { DC_VENDORID_LO, DC_DEVICEID_82C168, 186 "82c169 PNIC 10/100BaseTX" }, 187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 188 "Accton EN1217 10/100BaseTX" }, 189 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 190 "Accton EN2242 MiniPCI 10/100BaseTX" }, 191 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 192 "Xircom X3201 10/100BaseTX" }, 193 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 194 "Abocom FE2500 10/100BaseTX" }, 195 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 196 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 197 { DC_VENDORID_HAWKING, DC_DEVICEID_HAWKING_PN672TX, 198 "Hawking CB102 CardBus 10/100" }, 199 { 0, 0, NULL } 200}; 201 202static int dc_probe (device_t); 203static int dc_attach (device_t); 204static int dc_detach (device_t); 205static int dc_suspend (device_t); 206static int dc_resume (device_t); 207static void dc_acpi (device_t); 208static struct dc_type *dc_devtype (device_t); 209static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 210static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 211static void dc_pnic_rx_bug_war (struct dc_softc *, int); 212static int dc_rx_resync (struct dc_softc *); 213static void dc_rxeof (struct dc_softc *); 214static void dc_txeof (struct dc_softc *); 215static void dc_tick (void *); 216static void dc_tx_underrun (struct dc_softc *); 217static void dc_intr (void *); 218static void dc_start (struct ifnet *); 219static int dc_ioctl (struct ifnet *, u_long, caddr_t); 220static void dc_init (void *); 221static void dc_stop (struct dc_softc *); 222static void dc_watchdog (struct ifnet *); 223static void dc_shutdown (device_t); 224static int dc_ifmedia_upd (struct ifnet *); 225static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 226 227static void dc_delay (struct dc_softc *); 228static void dc_eeprom_idle (struct dc_softc *); 229static void dc_eeprom_putbyte (struct dc_softc *, int); 230static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 231static void dc_eeprom_getword_pnic 232 (struct dc_softc *, int, u_int16_t *); 233static void dc_eeprom_getword_xircom 234 (struct dc_softc *, int, u_int16_t *); 235static void dc_eeprom_width (struct dc_softc *); 236static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 237 238static void dc_mii_writebit (struct dc_softc *, int); 239static int dc_mii_readbit (struct dc_softc *); 240static void dc_mii_sync (struct dc_softc *); 241static void dc_mii_send (struct dc_softc *, u_int32_t, int); 242static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 243static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 244static int dc_miibus_readreg (device_t, int, int); 245static int dc_miibus_writereg (device_t, int, int, int); 246static void dc_miibus_statchg (device_t); 247static void dc_miibus_mediainit (device_t); 248 249static void dc_setcfg (struct dc_softc *, int); 250static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 251static u_int32_t dc_crc_be (caddr_t); 252static void dc_setfilt_21143 (struct dc_softc *); 253static void dc_setfilt_asix (struct dc_softc *); 254static void dc_setfilt_admtek (struct dc_softc *); 255static void dc_setfilt_xircom (struct dc_softc *); 256 257static void dc_setfilt (struct dc_softc *); 258 259static void dc_reset (struct dc_softc *); 260static int dc_list_rx_init (struct dc_softc *); 261static int dc_list_tx_init (struct dc_softc *); 262 263static void dc_read_srom (struct dc_softc *, int); 264static void dc_parse_21143_srom (struct dc_softc *); 265static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 266static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 267static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 268static void dc_apply_fixup (struct dc_softc *, int); 269 270#ifdef DC_USEIOSPACE 271#define DC_RES SYS_RES_IOPORT 272#define DC_RID DC_PCI_CFBIO 273#else 274#define DC_RES SYS_RES_MEMORY 275#define DC_RID DC_PCI_CFBMA 276#endif 277 278static device_method_t dc_methods[] = { 279 /* Device interface */ 280 DEVMETHOD(device_probe, dc_probe), 281 DEVMETHOD(device_attach, dc_attach), 282 DEVMETHOD(device_detach, dc_detach), 283 DEVMETHOD(device_suspend, dc_suspend), 284 DEVMETHOD(device_resume, dc_resume), 285 DEVMETHOD(device_shutdown, dc_shutdown), 286 287 /* bus interface */ 288 DEVMETHOD(bus_print_child, bus_generic_print_child), 289 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 290 291 /* MII interface */ 292 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 293 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 294 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 295 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 296 297 { 0, 0 } 298}; 299 300static driver_t dc_driver = { 301 "dc", 302 dc_methods, 303 sizeof(struct dc_softc) 304}; 305 306static devclass_t dc_devclass; 307#ifdef __i386__ 308static int dc_quick=1; 309SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 310 &dc_quick,0,"do not mdevget in dc driver"); 311#endif 312 313DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 314DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 315DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 316 317#define DC_SETBIT(sc, reg, x) \ 318 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 319 320#define DC_CLRBIT(sc, reg, x) \ 321 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 322 323#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 324#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 325 326#define IS_MPSAFE 0 327 328static void 329dc_delay(sc) 330 struct dc_softc *sc; 331{ 332 int idx; 333 334 for (idx = (300 / 33) + 1; idx > 0; idx--) 335 CSR_READ_4(sc, DC_BUSCTL); 336} 337 338static void 339dc_eeprom_width(sc) 340 struct dc_softc *sc; 341{ 342 int i; 343 344 /* Force EEPROM to idle state. */ 345 dc_eeprom_idle(sc); 346 347 /* Enter EEPROM access mode. */ 348 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 349 dc_delay(sc); 350 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 351 dc_delay(sc); 352 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 353 dc_delay(sc); 354 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 355 dc_delay(sc); 356 357 for (i = 3; i--;) { 358 if (6 & (1 << i)) 359 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 360 else 361 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 362 dc_delay(sc); 363 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 364 dc_delay(sc); 365 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 366 dc_delay(sc); 367 } 368 369 for (i = 1; i <= 12; i++) { 370 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 371 dc_delay(sc); 372 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 373 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 374 dc_delay(sc); 375 break; 376 } 377 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 378 dc_delay(sc); 379 } 380 381 /* Turn off EEPROM access mode. */ 382 dc_eeprom_idle(sc); 383 384 if (i < 4 || i > 12) 385 sc->dc_romwidth = 6; 386 else 387 sc->dc_romwidth = i; 388 389 /* Enter EEPROM access mode. */ 390 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 391 dc_delay(sc); 392 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 393 dc_delay(sc); 394 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 395 dc_delay(sc); 396 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 397 dc_delay(sc); 398 399 /* Turn off EEPROM access mode. */ 400 dc_eeprom_idle(sc); 401} 402 403static void 404dc_eeprom_idle(sc) 405 struct dc_softc *sc; 406{ 407 register int i; 408 409 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 410 dc_delay(sc); 411 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 412 dc_delay(sc); 413 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 414 dc_delay(sc); 415 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 416 dc_delay(sc); 417 418 for (i = 0; i < 25; i++) { 419 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 420 dc_delay(sc); 421 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 422 dc_delay(sc); 423 } 424 425 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 426 dc_delay(sc); 427 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 428 dc_delay(sc); 429 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 430 431 return; 432} 433 434/* 435 * Send a read command and address to the EEPROM, check for ACK. 436 */ 437static void 438dc_eeprom_putbyte(sc, addr) 439 struct dc_softc *sc; 440 int addr; 441{ 442 register int d, i; 443 444 d = DC_EECMD_READ >> 6; 445 for (i = 3; i--; ) { 446 if (d & (1 << i)) 447 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 448 else 449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 450 dc_delay(sc); 451 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 452 dc_delay(sc); 453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 454 dc_delay(sc); 455 } 456 457 /* 458 * Feed in each bit and strobe the clock. 459 */ 460 for (i = sc->dc_romwidth; i--;) { 461 if (addr & (1 << i)) { 462 SIO_SET(DC_SIO_EE_DATAIN); 463 } else { 464 SIO_CLR(DC_SIO_EE_DATAIN); 465 } 466 dc_delay(sc); 467 SIO_SET(DC_SIO_EE_CLK); 468 dc_delay(sc); 469 SIO_CLR(DC_SIO_EE_CLK); 470 dc_delay(sc); 471 } 472 473 return; 474} 475 476/* 477 * Read a word of data stored in the EEPROM at address 'addr.' 478 * The PNIC 82c168/82c169 has its own non-standard way to read 479 * the EEPROM. 480 */ 481static void 482dc_eeprom_getword_pnic(sc, addr, dest) 483 struct dc_softc *sc; 484 int addr; 485 u_int16_t *dest; 486{ 487 register int i; 488 u_int32_t r; 489 490 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 491 492 for (i = 0; i < DC_TIMEOUT; i++) { 493 DELAY(1); 494 r = CSR_READ_4(sc, DC_SIO); 495 if (!(r & DC_PN_SIOCTL_BUSY)) { 496 *dest = (u_int16_t)(r & 0xFFFF); 497 return; 498 } 499 } 500 501 return; 502} 503 504/* 505 * Read a word of data stored in the EEPROM at address 'addr.' 506 * The Xircom X3201 has its own non-standard way to read 507 * the EEPROM, too. 508 */ 509static void 510dc_eeprom_getword_xircom(sc, addr, dest) 511 struct dc_softc *sc; 512 int addr; 513 u_int16_t *dest; 514{ 515 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 516 517 addr *= 2; 518 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 519 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 520 addr += 1; 521 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 522 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 523 524 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 525 return; 526} 527 528/* 529 * Read a word of data stored in the EEPROM at address 'addr.' 530 */ 531static void 532dc_eeprom_getword(sc, addr, dest) 533 struct dc_softc *sc; 534 int addr; 535 u_int16_t *dest; 536{ 537 register int i; 538 u_int16_t word = 0; 539 540 /* Force EEPROM to idle state. */ 541 dc_eeprom_idle(sc); 542 543 /* Enter EEPROM access mode. */ 544 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 545 dc_delay(sc); 546 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 547 dc_delay(sc); 548 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 549 dc_delay(sc); 550 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 551 dc_delay(sc); 552 553 /* 554 * Send address of word we want to read. 555 */ 556 dc_eeprom_putbyte(sc, addr); 557 558 /* 559 * Start reading bits from EEPROM. 560 */ 561 for (i = 0x8000; i; i >>= 1) { 562 SIO_SET(DC_SIO_EE_CLK); 563 dc_delay(sc); 564 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 565 word |= i; 566 dc_delay(sc); 567 SIO_CLR(DC_SIO_EE_CLK); 568 dc_delay(sc); 569 } 570 571 /* Turn off EEPROM access mode. */ 572 dc_eeprom_idle(sc); 573 574 *dest = word; 575 576 return; 577} 578 579/* 580 * Read a sequence of words from the EEPROM. 581 */ 582static void 583dc_read_eeprom(sc, dest, off, cnt, swap) 584 struct dc_softc *sc; 585 caddr_t dest; 586 int off; 587 int cnt; 588 int swap; 589{ 590 int i; 591 u_int16_t word = 0, *ptr; 592 593 for (i = 0; i < cnt; i++) { 594 if (DC_IS_PNIC(sc)) 595 dc_eeprom_getword_pnic(sc, off + i, &word); 596 else if (DC_IS_XIRCOM(sc)) 597 dc_eeprom_getword_xircom(sc, off + i, &word); 598 else 599 dc_eeprom_getword(sc, off + i, &word); 600 ptr = (u_int16_t *)(dest + (i * 2)); 601 if (swap) 602 *ptr = ntohs(word); 603 else 604 *ptr = word; 605 } 606 607 return; 608} 609 610/* 611 * The following two routines are taken from the Macronix 98713 612 * Application Notes pp.19-21. 613 */ 614/* 615 * Write a bit to the MII bus. 616 */ 617static void 618dc_mii_writebit(sc, bit) 619 struct dc_softc *sc; 620 int bit; 621{ 622 if (bit) 623 CSR_WRITE_4(sc, DC_SIO, 624 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 625 else 626 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 627 628 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 629 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 630 631 return; 632} 633 634/* 635 * Read a bit from the MII bus. 636 */ 637static int 638dc_mii_readbit(sc) 639 struct dc_softc *sc; 640{ 641 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 642 CSR_READ_4(sc, DC_SIO); 643 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 644 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 645 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 646 return(1); 647 648 return(0); 649} 650 651/* 652 * Sync the PHYs by setting data bit and strobing the clock 32 times. 653 */ 654static void 655dc_mii_sync(sc) 656 struct dc_softc *sc; 657{ 658 register int i; 659 660 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 661 662 for (i = 0; i < 32; i++) 663 dc_mii_writebit(sc, 1); 664 665 return; 666} 667 668/* 669 * Clock a series of bits through the MII. 670 */ 671static void 672dc_mii_send(sc, bits, cnt) 673 struct dc_softc *sc; 674 u_int32_t bits; 675 int cnt; 676{ 677 int i; 678 679 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 680 dc_mii_writebit(sc, bits & i); 681} 682 683/* 684 * Read an PHY register through the MII. 685 */ 686static int 687dc_mii_readreg(sc, frame) 688 struct dc_softc *sc; 689 struct dc_mii_frame *frame; 690 691{ 692 int i, ack; 693 694 DC_LOCK(sc); 695 696 /* 697 * Set up frame for RX. 698 */ 699 frame->mii_stdelim = DC_MII_STARTDELIM; 700 frame->mii_opcode = DC_MII_READOP; 701 frame->mii_turnaround = 0; 702 frame->mii_data = 0; 703 704 /* 705 * Sync the PHYs. 706 */ 707 dc_mii_sync(sc); 708 709 /* 710 * Send command/address info. 711 */ 712 dc_mii_send(sc, frame->mii_stdelim, 2); 713 dc_mii_send(sc, frame->mii_opcode, 2); 714 dc_mii_send(sc, frame->mii_phyaddr, 5); 715 dc_mii_send(sc, frame->mii_regaddr, 5); 716 717#ifdef notdef 718 /* Idle bit */ 719 dc_mii_writebit(sc, 1); 720 dc_mii_writebit(sc, 0); 721#endif 722 723 /* Check for ack */ 724 ack = dc_mii_readbit(sc); 725 726 /* 727 * Now try reading data bits. If the ack failed, we still 728 * need to clock through 16 cycles to keep the PHY(s) in sync. 729 */ 730 if (ack) { 731 for(i = 0; i < 16; i++) { 732 dc_mii_readbit(sc); 733 } 734 goto fail; 735 } 736 737 for (i = 0x8000; i; i >>= 1) { 738 if (!ack) { 739 if (dc_mii_readbit(sc)) 740 frame->mii_data |= i; 741 } 742 } 743 744fail: 745 746 dc_mii_writebit(sc, 0); 747 dc_mii_writebit(sc, 0); 748 749 DC_UNLOCK(sc); 750 751 if (ack) 752 return(1); 753 return(0); 754} 755 756/* 757 * Write to a PHY register through the MII. 758 */ 759static int 760dc_mii_writereg(sc, frame) 761 struct dc_softc *sc; 762 struct dc_mii_frame *frame; 763 764{ 765 DC_LOCK(sc); 766 /* 767 * Set up frame for TX. 768 */ 769 770 frame->mii_stdelim = DC_MII_STARTDELIM; 771 frame->mii_opcode = DC_MII_WRITEOP; 772 frame->mii_turnaround = DC_MII_TURNAROUND; 773 774 /* 775 * Sync the PHYs. 776 */ 777 dc_mii_sync(sc); 778 779 dc_mii_send(sc, frame->mii_stdelim, 2); 780 dc_mii_send(sc, frame->mii_opcode, 2); 781 dc_mii_send(sc, frame->mii_phyaddr, 5); 782 dc_mii_send(sc, frame->mii_regaddr, 5); 783 dc_mii_send(sc, frame->mii_turnaround, 2); 784 dc_mii_send(sc, frame->mii_data, 16); 785 786 /* Idle bit. */ 787 dc_mii_writebit(sc, 0); 788 dc_mii_writebit(sc, 0); 789 790 DC_UNLOCK(sc); 791 792 return(0); 793} 794 795static int 796dc_miibus_readreg(dev, phy, reg) 797 device_t dev; 798 int phy, reg; 799{ 800 struct dc_mii_frame frame; 801 struct dc_softc *sc; 802 int i, rval, phy_reg = 0; 803 804 sc = device_get_softc(dev); 805 bzero((char *)&frame, sizeof(frame)); 806 807 /* 808 * Note: both the AL981 and AN985 have internal PHYs, 809 * however the AL981 provides direct access to the PHY 810 * registers while the AN985 uses a serial MII interface. 811 * The AN985's MII interface is also buggy in that you 812 * can read from any MII address (0 to 31), but only address 1 813 * behaves normally. To deal with both cases, we pretend 814 * that the PHY is at MII address 1. 815 */ 816 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 817 return(0); 818 819 /* 820 * Note: the ukphy probes of the RS7112 report a PHY at 821 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 822 * so we only respond to correct one. 823 */ 824 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 825 return(0); 826 827 if (sc->dc_pmode != DC_PMODE_MII) { 828 if (phy == (MII_NPHY - 1)) { 829 switch(reg) { 830 case MII_BMSR: 831 /* 832 * Fake something to make the probe 833 * code think there's a PHY here. 834 */ 835 return(BMSR_MEDIAMASK); 836 break; 837 case MII_PHYIDR1: 838 if (DC_IS_PNIC(sc)) 839 return(DC_VENDORID_LO); 840 return(DC_VENDORID_DEC); 841 break; 842 case MII_PHYIDR2: 843 if (DC_IS_PNIC(sc)) 844 return(DC_DEVICEID_82C168); 845 return(DC_DEVICEID_21143); 846 break; 847 default: 848 return(0); 849 break; 850 } 851 } else 852 return(0); 853 } 854 855 if (DC_IS_PNIC(sc)) { 856 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 857 (phy << 23) | (reg << 18)); 858 for (i = 0; i < DC_TIMEOUT; i++) { 859 DELAY(1); 860 rval = CSR_READ_4(sc, DC_PN_MII); 861 if (!(rval & DC_PN_MII_BUSY)) { 862 rval &= 0xFFFF; 863 return(rval == 0xFFFF ? 0 : rval); 864 } 865 } 866 return(0); 867 } 868 869 if (DC_IS_COMET(sc)) { 870 switch(reg) { 871 case MII_BMCR: 872 phy_reg = DC_AL_BMCR; 873 break; 874 case MII_BMSR: 875 phy_reg = DC_AL_BMSR; 876 break; 877 case MII_PHYIDR1: 878 phy_reg = DC_AL_VENID; 879 break; 880 case MII_PHYIDR2: 881 phy_reg = DC_AL_DEVID; 882 break; 883 case MII_ANAR: 884 phy_reg = DC_AL_ANAR; 885 break; 886 case MII_ANLPAR: 887 phy_reg = DC_AL_LPAR; 888 break; 889 case MII_ANER: 890 phy_reg = DC_AL_ANER; 891 break; 892 default: 893 printf("dc%d: phy_read: bad phy register %x\n", 894 sc->dc_unit, reg); 895 return(0); 896 break; 897 } 898 899 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 900 901 if (rval == 0xFFFF) 902 return(0); 903 return(rval); 904 } 905 906 frame.mii_phyaddr = phy; 907 frame.mii_regaddr = reg; 908 if (sc->dc_type == DC_TYPE_98713) { 909 phy_reg = CSR_READ_4(sc, DC_NETCFG); 910 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 911 } 912 dc_mii_readreg(sc, &frame); 913 if (sc->dc_type == DC_TYPE_98713) 914 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 915 916 return(frame.mii_data); 917} 918 919static int 920dc_miibus_writereg(dev, phy, reg, data) 921 device_t dev; 922 int phy, reg, data; 923{ 924 struct dc_softc *sc; 925 struct dc_mii_frame frame; 926 int i, phy_reg = 0; 927 928 sc = device_get_softc(dev); 929 bzero((char *)&frame, sizeof(frame)); 930 931 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 932 return(0); 933 934 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 935 return(0); 936 937 if (DC_IS_PNIC(sc)) { 938 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 939 (phy << 23) | (reg << 10) | data); 940 for (i = 0; i < DC_TIMEOUT; i++) { 941 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 942 break; 943 } 944 return(0); 945 } 946 947 if (DC_IS_COMET(sc)) { 948 switch(reg) { 949 case MII_BMCR: 950 phy_reg = DC_AL_BMCR; 951 break; 952 case MII_BMSR: 953 phy_reg = DC_AL_BMSR; 954 break; 955 case MII_PHYIDR1: 956 phy_reg = DC_AL_VENID; 957 break; 958 case MII_PHYIDR2: 959 phy_reg = DC_AL_DEVID; 960 break; 961 case MII_ANAR: 962 phy_reg = DC_AL_ANAR; 963 break; 964 case MII_ANLPAR: 965 phy_reg = DC_AL_LPAR; 966 break; 967 case MII_ANER: 968 phy_reg = DC_AL_ANER; 969 break; 970 default: 971 printf("dc%d: phy_write: bad phy register %x\n", 972 sc->dc_unit, reg); 973 return(0); 974 break; 975 } 976 977 CSR_WRITE_4(sc, phy_reg, data); 978 return(0); 979 } 980 981 frame.mii_phyaddr = phy; 982 frame.mii_regaddr = reg; 983 frame.mii_data = data; 984 985 if (sc->dc_type == DC_TYPE_98713) { 986 phy_reg = CSR_READ_4(sc, DC_NETCFG); 987 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 988 } 989 dc_mii_writereg(sc, &frame); 990 if (sc->dc_type == DC_TYPE_98713) 991 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 992 993 return(0); 994} 995 996static void 997dc_miibus_statchg(dev) 998 device_t dev; 999{ 1000 struct dc_softc *sc; 1001 struct mii_data *mii; 1002 struct ifmedia *ifm; 1003 1004 sc = device_get_softc(dev); 1005 if (DC_IS_ADMTEK(sc)) 1006 return; 1007 1008 mii = device_get_softc(sc->dc_miibus); 1009 ifm = &mii->mii_media; 1010 if (DC_IS_DAVICOM(sc) && 1011 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 1012 dc_setcfg(sc, ifm->ifm_media); 1013 sc->dc_if_media = ifm->ifm_media; 1014 } else { 1015 dc_setcfg(sc, mii->mii_media_active); 1016 sc->dc_if_media = mii->mii_media_active; 1017 } 1018 1019 return; 1020} 1021 1022/* 1023 * Special support for DM9102A cards with HomePNA PHYs. Note: 1024 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1025 * to be impossible to talk to the management interface of the DM9801 1026 * PHY (its MDIO pin is not connected to anything). Consequently, 1027 * the driver has to just 'know' about the additional mode and deal 1028 * with it itself. *sigh* 1029 */ 1030static void 1031dc_miibus_mediainit(dev) 1032 device_t dev; 1033{ 1034 struct dc_softc *sc; 1035 struct mii_data *mii; 1036 struct ifmedia *ifm; 1037 int rev; 1038 1039 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1040 1041 sc = device_get_softc(dev); 1042 mii = device_get_softc(sc->dc_miibus); 1043 ifm = &mii->mii_media; 1044 1045 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1046 ifmedia_add(ifm, IFM_ETHER|IFM_HPNA_1, 0, NULL); 1047 1048 return; 1049} 1050 1051#define DC_POLY 0xEDB88320 1052#define DC_BITS_512 9 1053#define DC_BITS_128 7 1054#define DC_BITS_64 6 1055 1056static u_int32_t 1057dc_crc_le(sc, addr) 1058 struct dc_softc *sc; 1059 caddr_t addr; 1060{ 1061 u_int32_t idx, bit, data, crc; 1062 1063 /* Compute CRC for the address value. */ 1064 crc = 0xFFFFFFFF; /* initial value */ 1065 1066 for (idx = 0; idx < 6; idx++) { 1067 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1068 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1069 } 1070 1071 /* 1072 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1073 * chips is only 128 bits wide. 1074 */ 1075 if (sc->dc_flags & DC_128BIT_HASH) 1076 return (crc & ((1 << DC_BITS_128) - 1)); 1077 1078 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1079 if (sc->dc_flags & DC_64BIT_HASH) 1080 return (crc & ((1 << DC_BITS_64) - 1)); 1081 1082 /* Xircom's hash filtering table is different (read: weird) */ 1083 /* Xircom uses the LEAST significant bits */ 1084 if (DC_IS_XIRCOM(sc)) { 1085 if ((crc & 0x180) == 0x180) 1086 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 1087 else 1088 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 1089 } 1090 1091 return (crc & ((1 << DC_BITS_512) - 1)); 1092} 1093 1094/* 1095 * Calculate CRC of a multicast group address, return the lower 6 bits. 1096 */ 1097static u_int32_t 1098dc_crc_be(addr) 1099 caddr_t addr; 1100{ 1101 u_int32_t crc, carry; 1102 int i, j; 1103 u_int8_t c; 1104 1105 /* Compute CRC for the address value. */ 1106 crc = 0xFFFFFFFF; /* initial value */ 1107 1108 for (i = 0; i < 6; i++) { 1109 c = *(addr + i); 1110 for (j = 0; j < 8; j++) { 1111 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1112 crc <<= 1; 1113 c >>= 1; 1114 if (carry) 1115 crc = (crc ^ 0x04c11db6) | carry; 1116 } 1117 } 1118 1119 /* return the filter bit position */ 1120 return((crc >> 26) & 0x0000003F); 1121} 1122 1123/* 1124 * 21143-style RX filter setup routine. Filter programming is done by 1125 * downloading a special setup frame into the TX engine. 21143, Macronix, 1126 * PNIC, PNIC II and Davicom chips are programmed this way. 1127 * 1128 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1129 * address (our node address) and a 512-bit hash filter for multicast 1130 * frames. We also sneak the broadcast address into the hash filter since 1131 * we need that too. 1132 */ 1133static void 1134dc_setfilt_21143(sc) 1135 struct dc_softc *sc; 1136{ 1137 struct dc_desc *sframe; 1138 u_int32_t h, *sp; 1139 struct ifmultiaddr *ifma; 1140 struct ifnet *ifp; 1141 int i; 1142 1143 ifp = &sc->arpcom.ac_if; 1144 1145 i = sc->dc_cdata.dc_tx_prod; 1146 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1147 sc->dc_cdata.dc_tx_cnt++; 1148 sframe = &sc->dc_ldata->dc_tx_list[i]; 1149 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1150 bzero((char *)sp, DC_SFRAME_LEN); 1151 1152 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1153 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1154 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1155 1156 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1157 1158 /* If we want promiscuous mode, set the allframes bit. */ 1159 if (ifp->if_flags & IFF_PROMISC) 1160 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1161 else 1162 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1163 1164 if (ifp->if_flags & IFF_ALLMULTI) 1165 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1166 else 1167 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1168 1169 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1170 if (ifma->ifma_addr->sa_family != AF_LINK) 1171 continue; 1172 h = dc_crc_le(sc, 1173 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1174 sp[h >> 4] |= 1 << (h & 0xF); 1175 } 1176 1177 if (ifp->if_flags & IFF_BROADCAST) { 1178 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1179 sp[h >> 4] |= 1 << (h & 0xF); 1180 } 1181 1182 /* Set our MAC address */ 1183 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1184 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1185 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1186 1187 sframe->dc_status = DC_TXSTAT_OWN; 1188 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1189 1190 /* 1191 * The PNIC takes an exceedingly long time to process its 1192 * setup frame; wait 10ms after posting the setup frame 1193 * before proceeding, just so it has time to swallow its 1194 * medicine. 1195 */ 1196 DELAY(10000); 1197 1198 ifp->if_timer = 5; 1199 1200 return; 1201} 1202 1203static void 1204dc_setfilt_admtek(sc) 1205 struct dc_softc *sc; 1206{ 1207 struct ifnet *ifp; 1208 int h = 0; 1209 u_int32_t hashes[2] = { 0, 0 }; 1210 struct ifmultiaddr *ifma; 1211 1212 ifp = &sc->arpcom.ac_if; 1213 1214 /* Init our MAC address */ 1215 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1216 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1217 1218 /* If we want promiscuous mode, set the allframes bit. */ 1219 if (ifp->if_flags & IFF_PROMISC) 1220 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1221 else 1222 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1223 1224 if (ifp->if_flags & IFF_ALLMULTI) 1225 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1226 else 1227 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1228 1229 /* first, zot all the existing hash bits */ 1230 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1231 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1232 1233 /* 1234 * If we're already in promisc or allmulti mode, we 1235 * don't have to bother programming the multicast filter. 1236 */ 1237 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1238 return; 1239 1240 /* now program new ones */ 1241 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1242 if (ifma->ifma_addr->sa_family != AF_LINK) 1243 continue; 1244 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1245 if (h < 32) 1246 hashes[0] |= (1 << h); 1247 else 1248 hashes[1] |= (1 << (h - 32)); 1249 } 1250 1251 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1252 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1253 1254 return; 1255} 1256 1257static void 1258dc_setfilt_asix(sc) 1259 struct dc_softc *sc; 1260{ 1261 struct ifnet *ifp; 1262 int h = 0; 1263 u_int32_t hashes[2] = { 0, 0 }; 1264 struct ifmultiaddr *ifma; 1265 1266 ifp = &sc->arpcom.ac_if; 1267 1268 /* Init our MAC address */ 1269 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1270 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1271 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1272 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1273 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1274 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1275 1276 /* If we want promiscuous mode, set the allframes bit. */ 1277 if (ifp->if_flags & IFF_PROMISC) 1278 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1279 else 1280 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1281 1282 if (ifp->if_flags & IFF_ALLMULTI) 1283 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1284 else 1285 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1286 1287 /* 1288 * The ASIX chip has a special bit to enable reception 1289 * of broadcast frames. 1290 */ 1291 if (ifp->if_flags & IFF_BROADCAST) 1292 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1293 else 1294 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1295 1296 /* first, zot all the existing hash bits */ 1297 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1298 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1299 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1300 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1301 1302 /* 1303 * If we're already in promisc or allmulti mode, we 1304 * don't have to bother programming the multicast filter. 1305 */ 1306 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1307 return; 1308 1309 /* now program new ones */ 1310 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1311 if (ifma->ifma_addr->sa_family != AF_LINK) 1312 continue; 1313 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1314 if (h < 32) 1315 hashes[0] |= (1 << h); 1316 else 1317 hashes[1] |= (1 << (h - 32)); 1318 } 1319 1320 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1321 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1322 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1323 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1324 1325 return; 1326} 1327 1328static void 1329dc_setfilt_xircom(sc) 1330 struct dc_softc *sc; 1331{ 1332 struct dc_desc *sframe; 1333 u_int32_t h, *sp; 1334 struct ifmultiaddr *ifma; 1335 struct ifnet *ifp; 1336 int i; 1337 1338 ifp = &sc->arpcom.ac_if; 1339 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1340 1341 i = sc->dc_cdata.dc_tx_prod; 1342 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1343 sc->dc_cdata.dc_tx_cnt++; 1344 sframe = &sc->dc_ldata->dc_tx_list[i]; 1345 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1346 bzero((char *)sp, DC_SFRAME_LEN); 1347 1348 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1349 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1350 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1351 1352 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1353 1354 /* If we want promiscuous mode, set the allframes bit. */ 1355 if (ifp->if_flags & IFF_PROMISC) 1356 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1357 else 1358 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1359 1360 if (ifp->if_flags & IFF_ALLMULTI) 1361 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1362 else 1363 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1364 1365 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1366 if (ifma->ifma_addr->sa_family != AF_LINK) 1367 continue; 1368 h = dc_crc_le(sc, 1369 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1370 sp[h >> 4] |= 1 << (h & 0xF); 1371 } 1372 1373 if (ifp->if_flags & IFF_BROADCAST) { 1374 h = dc_crc_le(sc, (caddr_t)ifp->if_broadcastaddr); 1375 sp[h >> 4] |= 1 << (h & 0xF); 1376 } 1377 1378 /* Set our MAC address */ 1379 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1380 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1381 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1382 1383 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1384 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1385 ifp->if_flags |= IFF_RUNNING; 1386 sframe->dc_status = DC_TXSTAT_OWN; 1387 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1388 1389 /* 1390 * wait some time... 1391 */ 1392 DELAY(1000); 1393 1394 ifp->if_timer = 5; 1395 1396 return; 1397} 1398 1399static void 1400dc_setfilt(sc) 1401 struct dc_softc *sc; 1402{ 1403 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1404 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1405 dc_setfilt_21143(sc); 1406 1407 if (DC_IS_ASIX(sc)) 1408 dc_setfilt_asix(sc); 1409 1410 if (DC_IS_ADMTEK(sc)) 1411 dc_setfilt_admtek(sc); 1412 1413 if (DC_IS_XIRCOM(sc)) 1414 dc_setfilt_xircom(sc); 1415 1416 return; 1417} 1418 1419/* 1420 * In order to fiddle with the 1421 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1422 * first have to put the transmit and/or receive logic in the idle state. 1423 */ 1424static void 1425dc_setcfg(sc, media) 1426 struct dc_softc *sc; 1427 int media; 1428{ 1429 int i, restart = 0; 1430 u_int32_t isr; 1431 1432 if (IFM_SUBTYPE(media) == IFM_NONE) 1433 return; 1434 1435 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1436 restart = 1; 1437 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1438 1439 for (i = 0; i < DC_TIMEOUT; i++) { 1440 isr = CSR_READ_4(sc, DC_ISR); 1441 if (isr & DC_ISR_TX_IDLE && 1442 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1443 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1444 break; 1445 DELAY(10); 1446 } 1447 1448 if (i == DC_TIMEOUT) 1449 printf("dc%d: failed to force tx and " 1450 "rx to idle state\n", sc->dc_unit); 1451 } 1452 1453 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1454 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1455 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1456 if (sc->dc_pmode == DC_PMODE_MII) { 1457 int watchdogreg; 1458 1459 if (DC_IS_INTEL(sc)) { 1460 /* there's a write enable bit here that reads as 1 */ 1461 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1462 watchdogreg &= ~DC_WDOG_CTLWREN; 1463 watchdogreg |= DC_WDOG_JABBERDIS; 1464 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1465 } else { 1466 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1467 } 1468 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1469 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1470 if (sc->dc_type == DC_TYPE_98713) 1471 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1472 DC_NETCFG_SCRAMBLER)); 1473 if (!DC_IS_DAVICOM(sc)) 1474 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1475 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1476 if (DC_IS_INTEL(sc)) 1477 dc_apply_fixup(sc, IFM_AUTO); 1478 } else { 1479 if (DC_IS_PNIC(sc)) { 1480 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1481 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1482 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1483 } 1484 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1485 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1486 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1487 if (DC_IS_INTEL(sc)) 1488 dc_apply_fixup(sc, 1489 (media & IFM_GMASK) == IFM_FDX ? 1490 IFM_100_TX|IFM_FDX : IFM_100_TX); 1491 } 1492 } 1493 1494 if (IFM_SUBTYPE(media) == IFM_10_T) { 1495 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1496 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1497 if (sc->dc_pmode == DC_PMODE_MII) { 1498 int watchdogreg; 1499 1500 /* there's a write enable bit here that reads as 1 */ 1501 if (DC_IS_INTEL(sc)) { 1502 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1503 watchdogreg &= ~DC_WDOG_CTLWREN; 1504 watchdogreg |= DC_WDOG_JABBERDIS; 1505 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1506 } else { 1507 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1508 } 1509 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1510 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1511 if (sc->dc_type == DC_TYPE_98713) 1512 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1513 if (!DC_IS_DAVICOM(sc)) 1514 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1515 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1516 if (DC_IS_INTEL(sc)) 1517 dc_apply_fixup(sc, IFM_AUTO); 1518 } else { 1519 if (DC_IS_PNIC(sc)) { 1520 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1521 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1522 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1523 } 1524 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1525 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1526 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1527 if (DC_IS_INTEL(sc)) { 1528 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1529 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1530 if ((media & IFM_GMASK) == IFM_FDX) 1531 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1532 else 1533 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1534 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1535 DC_CLRBIT(sc, DC_10BTCTRL, 1536 DC_TCTL_AUTONEGENBL); 1537 dc_apply_fixup(sc, 1538 (media & IFM_GMASK) == IFM_FDX ? 1539 IFM_10_T|IFM_FDX : IFM_10_T); 1540 DELAY(20000); 1541 } 1542 } 1543 } 1544 1545 /* 1546 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1547 * PHY and we want HomePNA mode, set the portsel bit to turn 1548 * on the external MII port. 1549 */ 1550 if (DC_IS_DAVICOM(sc)) { 1551 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1552 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1553 sc->dc_link = 1; 1554 } else { 1555 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1556 } 1557 } 1558 1559 if ((media & IFM_GMASK) == IFM_FDX) { 1560 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1561 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1562 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1563 } else { 1564 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1565 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1566 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1567 } 1568 1569 if (restart) 1570 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1571 1572 return; 1573} 1574 1575static void 1576dc_reset(sc) 1577 struct dc_softc *sc; 1578{ 1579 register int i; 1580 1581 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1582 1583 for (i = 0; i < DC_TIMEOUT; i++) { 1584 DELAY(10); 1585 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1586 break; 1587 } 1588 1589 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1590 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1591 DELAY(10000); 1592 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1593 i = 0; 1594 } 1595 1596 if (i == DC_TIMEOUT) 1597 printf("dc%d: reset never completed!\n", sc->dc_unit); 1598 1599 /* Wait a little while for the chip to get its brains in order. */ 1600 DELAY(1000); 1601 1602 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1603 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1604 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1605 1606 /* 1607 * Bring the SIA out of reset. In some cases, it looks 1608 * like failing to unreset the SIA soon enough gets it 1609 * into a state where it will never come out of reset 1610 * until we reset the whole chip again. 1611 */ 1612 if (DC_IS_INTEL(sc)) { 1613 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1614 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1615 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1616 } 1617 1618 return; 1619} 1620 1621static struct dc_type * 1622dc_devtype(dev) 1623 device_t dev; 1624{ 1625 struct dc_type *t; 1626 u_int32_t rev; 1627 1628 t = dc_devs; 1629 1630 while(t->dc_name != NULL) { 1631 if ((pci_get_vendor(dev) == t->dc_vid) && 1632 (pci_get_device(dev) == t->dc_did)) { 1633 /* Check the PCI revision */ 1634 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1635 if (t->dc_did == DC_DEVICEID_98713 && 1636 rev >= DC_REVISION_98713A) 1637 t++; 1638 if (t->dc_did == DC_DEVICEID_98713_CP && 1639 rev >= DC_REVISION_98713A) 1640 t++; 1641 if (t->dc_did == DC_DEVICEID_987x5 && 1642 rev >= DC_REVISION_98715AEC_C) 1643 t++; 1644 if (t->dc_did == DC_DEVICEID_987x5 && 1645 rev >= DC_REVISION_98725) 1646 t++; 1647 if (t->dc_did == DC_DEVICEID_AX88140A && 1648 rev >= DC_REVISION_88141) 1649 t++; 1650 if (t->dc_did == DC_DEVICEID_82C168 && 1651 rev >= DC_REVISION_82C169) 1652 t++; 1653 if (t->dc_did == DC_DEVICEID_DM9102 && 1654 rev >= DC_REVISION_DM9102A) 1655 t++; 1656 return(t); 1657 } 1658 t++; 1659 } 1660 1661 return(NULL); 1662} 1663 1664/* 1665 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1666 * IDs against our list and return a device name if we find a match. 1667 * We do a little bit of extra work to identify the exact type of 1668 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1669 * but different revision IDs. The same is true for 98715/98715A 1670 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1671 * cases, the exact chip revision affects driver behavior. 1672 */ 1673static int 1674dc_probe(dev) 1675 device_t dev; 1676{ 1677 struct dc_type *t; 1678 1679 t = dc_devtype(dev); 1680 1681 if (t != NULL) { 1682 device_set_desc(dev, t->dc_name); 1683 return(0); 1684 } 1685 1686 return(ENXIO); 1687} 1688 1689static void 1690dc_acpi(dev) 1691 device_t dev; 1692{ 1693 int unit; 1694 1695 unit = device_get_unit(dev); 1696 1697 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1698 u_int32_t iobase, membase, irq; 1699 1700 /* Save important PCI config data. */ 1701 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1702 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1703 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1704 1705 /* Reset the power state. */ 1706 printf("dc%d: chip is in D%d power mode " 1707 "-- setting to D0\n", unit, 1708 pci_get_powerstate(dev)); 1709 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1710 1711 /* Restore PCI config data. */ 1712 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1713 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1714 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1715 } 1716 1717 return; 1718} 1719 1720static void 1721dc_apply_fixup(sc, media) 1722 struct dc_softc *sc; 1723 int media; 1724{ 1725 struct dc_mediainfo *m; 1726 u_int8_t *p; 1727 int i; 1728 u_int32_t reg; 1729 1730 m = sc->dc_mi; 1731 1732 while (m != NULL) { 1733 if (m->dc_media == media) 1734 break; 1735 m = m->dc_next; 1736 } 1737 1738 if (m == NULL) 1739 return; 1740 1741 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1742 reg = (p[0] | (p[1] << 8)) << 16; 1743 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1744 } 1745 1746 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1747 reg = (p[0] | (p[1] << 8)) << 16; 1748 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1749 } 1750 1751 return; 1752} 1753 1754static void 1755dc_decode_leaf_sia(sc, l) 1756 struct dc_softc *sc; 1757 struct dc_eblock_sia *l; 1758{ 1759 struct dc_mediainfo *m; 1760 1761 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1762 bzero(m, sizeof(struct dc_mediainfo)); 1763 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1764 m->dc_media = IFM_10_T; 1765 1766 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1767 m->dc_media = IFM_10_T|IFM_FDX; 1768 1769 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1770 m->dc_media = IFM_10_2; 1771 1772 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1773 m->dc_media = IFM_10_5; 1774 1775 m->dc_gp_len = 2; 1776 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1777 1778 m->dc_next = sc->dc_mi; 1779 sc->dc_mi = m; 1780 1781 sc->dc_pmode = DC_PMODE_SIA; 1782 1783 return; 1784} 1785 1786static void 1787dc_decode_leaf_sym(sc, l) 1788 struct dc_softc *sc; 1789 struct dc_eblock_sym *l; 1790{ 1791 struct dc_mediainfo *m; 1792 1793 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1794 bzero(m, sizeof(struct dc_mediainfo)); 1795 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1796 m->dc_media = IFM_100_TX; 1797 1798 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1799 m->dc_media = IFM_100_TX|IFM_FDX; 1800 1801 m->dc_gp_len = 2; 1802 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1803 1804 m->dc_next = sc->dc_mi; 1805 sc->dc_mi = m; 1806 1807 sc->dc_pmode = DC_PMODE_SYM; 1808 1809 return; 1810} 1811 1812static void 1813dc_decode_leaf_mii(sc, l) 1814 struct dc_softc *sc; 1815 struct dc_eblock_mii *l; 1816{ 1817 u_int8_t *p; 1818 struct dc_mediainfo *m; 1819 1820 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1821 bzero(m, sizeof(struct dc_mediainfo)); 1822 /* We abuse IFM_AUTO to represent MII. */ 1823 m->dc_media = IFM_AUTO; 1824 m->dc_gp_len = l->dc_gpr_len; 1825 1826 p = (u_int8_t *)l; 1827 p += sizeof(struct dc_eblock_mii); 1828 m->dc_gp_ptr = p; 1829 p += 2 * l->dc_gpr_len; 1830 m->dc_reset_len = *p; 1831 p++; 1832 m->dc_reset_ptr = p; 1833 1834 m->dc_next = sc->dc_mi; 1835 sc->dc_mi = m; 1836 1837 return; 1838} 1839 1840static void 1841dc_read_srom(sc, bits) 1842 struct dc_softc *sc; 1843 int bits; 1844{ 1845 int size; 1846 1847 size = 2 << bits; 1848 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1849 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1850} 1851 1852static void 1853dc_parse_21143_srom(sc) 1854 struct dc_softc *sc; 1855{ 1856 struct dc_leaf_hdr *lhdr; 1857 struct dc_eblock_hdr *hdr; 1858 int i, loff; 1859 char *ptr; 1860 1861 loff = sc->dc_srom[27]; 1862 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1863 1864 ptr = (char *)lhdr; 1865 ptr += sizeof(struct dc_leaf_hdr) - 1; 1866 for (i = 0; i < lhdr->dc_mcnt; i++) { 1867 hdr = (struct dc_eblock_hdr *)ptr; 1868 switch(hdr->dc_type) { 1869 case DC_EBLOCK_MII: 1870 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1871 break; 1872 case DC_EBLOCK_SIA: 1873 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1874 break; 1875 case DC_EBLOCK_SYM: 1876 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1877 break; 1878 default: 1879 /* Don't care. Yet. */ 1880 break; 1881 } 1882 ptr += (hdr->dc_len & 0x7F); 1883 ptr++; 1884 } 1885 1886 return; 1887} 1888 1889/* 1890 * Attach the interface. Allocate softc structures, do ifmedia 1891 * setup and ethernet/BPF attach. 1892 */ 1893static int 1894dc_attach(dev) 1895 device_t dev; 1896{ 1897 int tmp = 0; 1898 u_char eaddr[ETHER_ADDR_LEN]; 1899 u_int32_t command; 1900 struct dc_softc *sc; 1901 struct ifnet *ifp; 1902 u_int32_t revision; 1903 int unit, error = 0, rid, mac_offset; 1904 u_int8_t *mac; 1905 1906 sc = device_get_softc(dev); 1907 unit = device_get_unit(dev); 1908 1909 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1910 MTX_DEF | MTX_RECURSE); 1911 1912 /* 1913 * Handle power management nonsense. 1914 */ 1915 dc_acpi(dev); 1916 1917 /* 1918 * Map control/status registers. 1919 */ 1920 pci_enable_busmaster(dev); 1921 pci_enable_io(dev, SYS_RES_IOPORT); 1922 pci_enable_io(dev, SYS_RES_MEMORY); 1923 command = pci_read_config(dev, PCIR_COMMAND, 4); 1924 1925#ifdef DC_USEIOSPACE 1926 if (!(command & PCIM_CMD_PORTEN)) { 1927 printf("dc%d: failed to enable I/O ports!\n", unit); 1928 error = ENXIO; 1929 goto fail; 1930 } 1931#else 1932 if (!(command & PCIM_CMD_MEMEN)) { 1933 printf("dc%d: failed to enable memory mapping!\n", unit); 1934 error = ENXIO; 1935 goto fail; 1936 } 1937#endif 1938 1939 rid = DC_RID; 1940 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1941 0, ~0, 1, RF_ACTIVE); 1942 1943 if (sc->dc_res == NULL) { 1944 printf("dc%d: couldn't map ports/memory\n", unit); 1945 error = ENXIO; 1946 goto fail; 1947 } 1948 1949 sc->dc_btag = rman_get_bustag(sc->dc_res); 1950 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1951 1952 /* Allocate interrupt */ 1953 rid = 0; 1954 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1955 RF_SHAREABLE | RF_ACTIVE); 1956 1957 if (sc->dc_irq == NULL) { 1958 printf("dc%d: couldn't map interrupt\n", unit); 1959 error = ENXIO; 1960 goto fail; 1961 } 1962 1963 /* Need this info to decide on a chip type. */ 1964 sc->dc_info = dc_devtype(dev); 1965 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1966 1967 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1968 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1969 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1970 dc_eeprom_width(sc); 1971 1972 switch(sc->dc_info->dc_did) { 1973 case DC_DEVICEID_21143: 1974 sc->dc_type = DC_TYPE_21143; 1975 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1976 sc->dc_flags |= DC_REDUCED_MII_POLL; 1977 /* Save EEPROM contents so we can parse them later. */ 1978 dc_read_srom(sc, sc->dc_romwidth); 1979 break; 1980 case DC_DEVICEID_DM9009: 1981 case DC_DEVICEID_DM9100: 1982 case DC_DEVICEID_DM9102: 1983 sc->dc_type = DC_TYPE_DM9102; 1984 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1985 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1986 sc->dc_pmode = DC_PMODE_MII; 1987 /* Increase the latency timer value. */ 1988 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1989 command &= 0xFFFF00FF; 1990 command |= 0x00008000; 1991 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1992 break; 1993 case DC_DEVICEID_AL981: 1994 sc->dc_type = DC_TYPE_AL981; 1995 sc->dc_flags |= DC_TX_USE_TX_INTR; 1996 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1997 sc->dc_pmode = DC_PMODE_MII; 1998 dc_read_srom(sc, sc->dc_romwidth); 1999 break; 2000 case DC_DEVICEID_AN985: 2001 case DC_DEVICEID_FE2500: 2002 case DC_DEVICEID_EN2242: 2003 case DC_DEVICEID_HAWKING_PN672TX: 2004 sc->dc_type = DC_TYPE_AN985; 2005 sc->dc_flags |= DC_TX_USE_TX_INTR; 2006 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2007 sc->dc_pmode = DC_PMODE_MII; 2008 dc_read_srom(sc, sc->dc_romwidth); 2009 break; 2010 case DC_DEVICEID_98713: 2011 case DC_DEVICEID_98713_CP: 2012 if (revision < DC_REVISION_98713A) { 2013 sc->dc_type = DC_TYPE_98713; 2014 } 2015 if (revision >= DC_REVISION_98713A) { 2016 sc->dc_type = DC_TYPE_98713A; 2017 sc->dc_flags |= DC_21143_NWAY; 2018 } 2019 sc->dc_flags |= DC_REDUCED_MII_POLL; 2020 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2021 break; 2022 case DC_DEVICEID_987x5: 2023 case DC_DEVICEID_EN1217: 2024 /* 2025 * Macronix MX98715AEC-C/D/E parts have only a 2026 * 128-bit hash table. We need to deal with these 2027 * in the same manner as the PNIC II so that we 2028 * get the right number of bits out of the 2029 * CRC routine. 2030 */ 2031 if (revision >= DC_REVISION_98715AEC_C && 2032 revision < DC_REVISION_98725) 2033 sc->dc_flags |= DC_128BIT_HASH; 2034 sc->dc_type = DC_TYPE_987x5; 2035 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2036 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2037 break; 2038 case DC_DEVICEID_98727: 2039 sc->dc_type = DC_TYPE_987x5; 2040 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2041 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2042 break; 2043 case DC_DEVICEID_82C115: 2044 sc->dc_type = DC_TYPE_PNICII; 2045 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 2046 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2047 break; 2048 case DC_DEVICEID_82C168: 2049 sc->dc_type = DC_TYPE_PNIC; 2050 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 2051 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2052 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2053 if (revision < DC_REVISION_82C169) 2054 sc->dc_pmode = DC_PMODE_SYM; 2055 break; 2056 case DC_DEVICEID_AX88140A: 2057 sc->dc_type = DC_TYPE_ASIX; 2058 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 2059 sc->dc_flags |= DC_REDUCED_MII_POLL; 2060 sc->dc_pmode = DC_PMODE_MII; 2061 break; 2062 case DC_DEVICEID_X3201: 2063 sc->dc_type = DC_TYPE_XIRCOM; 2064 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2065 DC_TX_ALIGN; 2066 /* 2067 * We don't actually need to coalesce, but we're doing 2068 * it to obtain a double word aligned buffer. 2069 * The DC_TX_COALESCE flag is required. 2070 */ 2071 sc->dc_pmode = DC_PMODE_MII; 2072 break; 2073 case DC_DEVICEID_RS7112: 2074 sc->dc_type = DC_TYPE_CONEXANT; 2075 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2076 sc->dc_flags |= DC_REDUCED_MII_POLL; 2077 sc->dc_pmode = DC_PMODE_MII; 2078 dc_read_srom(sc, sc->dc_romwidth); 2079 break; 2080 default: 2081 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2082 sc->dc_info->dc_did); 2083 break; 2084 } 2085 2086 /* Save the cache line size. */ 2087 if (DC_IS_DAVICOM(sc)) 2088 sc->dc_cachesize = 0; 2089 else 2090 sc->dc_cachesize = pci_read_config(dev, 2091 DC_PCI_CFLT, 4) & 0xFF; 2092 2093 /* Reset the adapter. */ 2094 dc_reset(sc); 2095 2096 /* Take 21143 out of snooze mode */ 2097 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2098 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2099 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2100 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2101 } 2102 2103 /* 2104 * Try to learn something about the supported media. 2105 * We know that ASIX and ADMtek and Davicom devices 2106 * will *always* be using MII media, so that's a no-brainer. 2107 * The tricky ones are the Macronix/PNIC II and the 2108 * Intel 21143. 2109 */ 2110 if (DC_IS_INTEL(sc)) 2111 dc_parse_21143_srom(sc); 2112 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2113 if (sc->dc_type == DC_TYPE_98713) 2114 sc->dc_pmode = DC_PMODE_MII; 2115 else 2116 sc->dc_pmode = DC_PMODE_SYM; 2117 } else if (!sc->dc_pmode) 2118 sc->dc_pmode = DC_PMODE_MII; 2119 2120 /* 2121 * Get station address from the EEPROM. 2122 */ 2123 switch(sc->dc_type) { 2124 case DC_TYPE_98713: 2125 case DC_TYPE_98713A: 2126 case DC_TYPE_987x5: 2127 case DC_TYPE_PNICII: 2128 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2129 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2130 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2131 break; 2132 case DC_TYPE_PNIC: 2133 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2134 break; 2135 case DC_TYPE_DM9102: 2136 case DC_TYPE_21143: 2137 case DC_TYPE_ASIX: 2138 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2139 break; 2140 case DC_TYPE_AL981: 2141 case DC_TYPE_AN985: 2142 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 2143 ETHER_ADDR_LEN); 2144 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2145 break; 2146 case DC_TYPE_CONEXANT: 2147 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2148 break; 2149 case DC_TYPE_XIRCOM: 2150 /* The MAC comes from the CIS */ 2151 mac = pci_get_ether(dev); 2152 if (!mac) { 2153 device_printf(dev, "No station address in CIS!\n"); 2154 error = ENXIO; 2155 goto fail; 2156 } 2157 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2158 break; 2159 default: 2160 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2161 break; 2162 } 2163 2164 /* 2165 * A 21143 or clone chip was detected. Inform the world. 2166 */ 2167 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2168 2169 sc->dc_unit = unit; 2170 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2171 2172 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2173 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2174 2175 if (sc->dc_ldata == NULL) { 2176 printf("dc%d: no memory for list buffers!\n", unit); 2177 error = ENXIO; 2178 goto fail; 2179 } 2180 2181 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2182 2183 ifp = &sc->arpcom.ac_if; 2184 ifp->if_softc = sc; 2185 ifp->if_unit = unit; 2186 ifp->if_name = "dc"; 2187 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2188 ifp->if_mtu = ETHERMTU; 2189 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2190 ifp->if_ioctl = dc_ioctl; 2191 ifp->if_output = ether_output; 2192 ifp->if_start = dc_start; 2193 ifp->if_watchdog = dc_watchdog; 2194 ifp->if_init = dc_init; 2195 ifp->if_baudrate = 10000000; 2196 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2197 2198 /* 2199 * Do MII setup. If this is a 21143, check for a PHY on the 2200 * MII bus after applying any necessary fixups to twiddle the 2201 * GPIO bits. If we don't end up finding a PHY, restore the 2202 * old selection (SIA only or SIA/SYM) and attach the dcphy 2203 * driver instead. 2204 */ 2205 if (DC_IS_INTEL(sc)) { 2206 dc_apply_fixup(sc, IFM_AUTO); 2207 tmp = sc->dc_pmode; 2208 sc->dc_pmode = DC_PMODE_MII; 2209 } 2210 2211 error = mii_phy_probe(dev, &sc->dc_miibus, 2212 dc_ifmedia_upd, dc_ifmedia_sts); 2213 2214 if (error && DC_IS_INTEL(sc)) { 2215 sc->dc_pmode = tmp; 2216 if (sc->dc_pmode != DC_PMODE_SIA) 2217 sc->dc_pmode = DC_PMODE_SYM; 2218 sc->dc_flags |= DC_21143_NWAY; 2219 mii_phy_probe(dev, &sc->dc_miibus, 2220 dc_ifmedia_upd, dc_ifmedia_sts); 2221 /* 2222 * For non-MII cards, we need to have the 21143 2223 * drive the LEDs. Except there are some systems 2224 * like the NEC VersaPro NoteBook PC which have no 2225 * LEDs, and twiddling these bits has adverse effects 2226 * on them. (I.e. you suddenly can't get a link.) 2227 */ 2228 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2229 sc->dc_flags |= DC_TULIP_LEDS; 2230 error = 0; 2231 } 2232 2233 if (error) { 2234 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2235 goto fail; 2236 } 2237 2238 if (DC_IS_XIRCOM(sc)) { 2239 /* 2240 * setup General Purpose Port mode and data so the tulip 2241 * can talk to the MII. 2242 */ 2243 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2244 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2245 DELAY(10); 2246 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2247 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2248 DELAY(10); 2249 } 2250 2251 if (DC_IS_ADMTEK(sc)) { 2252 /* 2253 * Set automatic TX underrun recovery for the ADMtek chips 2254 */ 2255 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2256 } 2257 2258 /* 2259 * Tell the upper layer(s) we support long frames. 2260 */ 2261 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2262 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2263 2264 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2265 2266#ifdef SRM_MEDIA 2267 sc->dc_srm_media = 0; 2268 2269 /* Remember the SRM console media setting */ 2270 if (DC_IS_INTEL(sc)) { 2271 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2272 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2273 switch ((command >> 8) & 0xff) { 2274 case 3: 2275 sc->dc_srm_media = IFM_10_T; 2276 break; 2277 case 4: 2278 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2279 break; 2280 case 5: 2281 sc->dc_srm_media = IFM_100_TX; 2282 break; 2283 case 6: 2284 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2285 break; 2286 } 2287 if (sc->dc_srm_media) 2288 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2289 } 2290#endif 2291 2292 /* 2293 * Call MI attach routine. 2294 */ 2295 ether_ifattach(ifp, eaddr); 2296 2297 /* Hook interrupt last to avoid having to lock softc */ 2298 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 2299 (IS_MPSAFE ? INTR_MPSAFE : 0), 2300 dc_intr, sc, &sc->dc_intrhand); 2301 2302 if (error) { 2303 printf("dc%d: couldn't set up irq\n", unit); 2304 goto fail; 2305 } 2306 2307fail: 2308 if (error) 2309 dc_detach(dev); 2310 return (error); 2311} 2312 2313static int 2314dc_detach(dev) 2315 device_t dev; 2316{ 2317 struct dc_softc *sc; 2318 struct ifnet *ifp; 2319 struct dc_mediainfo *m; 2320 2321 sc = device_get_softc(dev); 2322 KASSERT(mtx_initialized(&sc->dc_mtx), "dc mutex not initialized"); 2323 DC_LOCK(sc); 2324 2325 ifp = &sc->arpcom.ac_if; 2326 2327 if (device_is_alive(dev)) { 2328 if (bus_child_present(dev)) 2329 dc_stop(sc); 2330 ether_ifdetach(ifp); 2331 device_delete_child(dev, sc->dc_miibus); 2332 bus_generic_detach(dev); 2333 } 2334 2335 if (sc->dc_intrhand) 2336 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2337 if (sc->dc_irq) 2338 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2339 if (sc->dc_res) 2340 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2341 2342 if (sc->dc_ldata) 2343 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2344 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2345 2346 while(sc->dc_mi != NULL) { 2347 m = sc->dc_mi->dc_next; 2348 free(sc->dc_mi, M_DEVBUF); 2349 sc->dc_mi = m; 2350 } 2351 free(sc->dc_srom, M_DEVBUF); 2352 2353 DC_UNLOCK(sc); 2354 mtx_destroy(&sc->dc_mtx); 2355 2356 return(0); 2357} 2358 2359/* 2360 * Initialize the transmit descriptors. 2361 */ 2362static int 2363dc_list_tx_init(sc) 2364 struct dc_softc *sc; 2365{ 2366 struct dc_chain_data *cd; 2367 struct dc_list_data *ld; 2368 int i, nexti; 2369 2370 cd = &sc->dc_cdata; 2371 ld = sc->dc_ldata; 2372 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2373 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2374 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2375 cd->dc_tx_chain[i] = NULL; 2376 ld->dc_tx_list[i].dc_data = 0; 2377 ld->dc_tx_list[i].dc_ctl = 0; 2378 } 2379 2380 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2381 2382 return(0); 2383} 2384 2385 2386/* 2387 * Initialize the RX descriptors and allocate mbufs for them. Note that 2388 * we arrange the descriptors in a closed ring, so that the last descriptor 2389 * points back to the first. 2390 */ 2391static int 2392dc_list_rx_init(sc) 2393 struct dc_softc *sc; 2394{ 2395 struct dc_chain_data *cd; 2396 struct dc_list_data *ld; 2397 int i, nexti; 2398 2399 cd = &sc->dc_cdata; 2400 ld = sc->dc_ldata; 2401 2402 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2403 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2404 return(ENOBUFS); 2405 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2406 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2407 } 2408 2409 cd->dc_rx_prod = 0; 2410 2411 return(0); 2412} 2413 2414/* 2415 * Initialize an RX descriptor and attach an MBUF cluster. 2416 */ 2417static int 2418dc_newbuf(sc, i, m) 2419 struct dc_softc *sc; 2420 int i; 2421 struct mbuf *m; 2422{ 2423 struct mbuf *m_new = NULL; 2424 struct dc_desc *c; 2425 2426 c = &sc->dc_ldata->dc_rx_list[i]; 2427 2428 if (m == NULL) { 2429 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2430 if (m_new == NULL) 2431 return(ENOBUFS); 2432 2433 MCLGET(m_new, M_DONTWAIT); 2434 if (!(m_new->m_flags & M_EXT)) { 2435 m_freem(m_new); 2436 return(ENOBUFS); 2437 } 2438 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2439 } else { 2440 m_new = m; 2441 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2442 m_new->m_data = m_new->m_ext.ext_buf; 2443 } 2444 2445 m_adj(m_new, sizeof(u_int64_t)); 2446 2447 /* 2448 * If this is a PNIC chip, zero the buffer. This is part 2449 * of the workaround for the receive bug in the 82c168 and 2450 * 82c169 chips. 2451 */ 2452 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2453 bzero((char *)mtod(m_new, char *), m_new->m_len); 2454 2455 sc->dc_cdata.dc_rx_chain[i] = m_new; 2456 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2457 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2458 c->dc_status = DC_RXSTAT_OWN; 2459 2460 return(0); 2461} 2462 2463/* 2464 * Grrrrr. 2465 * The PNIC chip has a terrible bug in it that manifests itself during 2466 * periods of heavy activity. The exact mode of failure if difficult to 2467 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2468 * will happen on slow machines. The bug is that sometimes instead of 2469 * uploading one complete frame during reception, it uploads what looks 2470 * like the entire contents of its FIFO memory. The frame we want is at 2471 * the end of the whole mess, but we never know exactly how much data has 2472 * been uploaded, so salvaging the frame is hard. 2473 * 2474 * There is only one way to do it reliably, and it's disgusting. 2475 * Here's what we know: 2476 * 2477 * - We know there will always be somewhere between one and three extra 2478 * descriptors uploaded. 2479 * 2480 * - We know the desired received frame will always be at the end of the 2481 * total data upload. 2482 * 2483 * - We know the size of the desired received frame because it will be 2484 * provided in the length field of the status word in the last descriptor. 2485 * 2486 * Here's what we do: 2487 * 2488 * - When we allocate buffers for the receive ring, we bzero() them. 2489 * This means that we know that the buffer contents should be all 2490 * zeros, except for data uploaded by the chip. 2491 * 2492 * - We also force the PNIC chip to upload frames that include the 2493 * ethernet CRC at the end. 2494 * 2495 * - We gather all of the bogus frame data into a single buffer. 2496 * 2497 * - We then position a pointer at the end of this buffer and scan 2498 * backwards until we encounter the first non-zero byte of data. 2499 * This is the end of the received frame. We know we will encounter 2500 * some data at the end of the frame because the CRC will always be 2501 * there, so even if the sender transmits a packet of all zeros, 2502 * we won't be fooled. 2503 * 2504 * - We know the size of the actual received frame, so we subtract 2505 * that value from the current pointer location. This brings us 2506 * to the start of the actual received packet. 2507 * 2508 * - We copy this into an mbuf and pass it on, along with the actual 2509 * frame length. 2510 * 2511 * The performance hit is tremendous, but it beats dropping frames all 2512 * the time. 2513 */ 2514 2515#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2516static void 2517dc_pnic_rx_bug_war(sc, idx) 2518 struct dc_softc *sc; 2519 int idx; 2520{ 2521 struct dc_desc *cur_rx; 2522 struct dc_desc *c = NULL; 2523 struct mbuf *m = NULL; 2524 unsigned char *ptr; 2525 int i, total_len; 2526 u_int32_t rxstat = 0; 2527 2528 i = sc->dc_pnic_rx_bug_save; 2529 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2530 ptr = sc->dc_pnic_rx_buf; 2531 bzero(ptr, sizeof(DC_RXLEN * 5)); 2532 2533 /* Copy all the bytes from the bogus buffers. */ 2534 while (1) { 2535 c = &sc->dc_ldata->dc_rx_list[i]; 2536 rxstat = c->dc_status; 2537 m = sc->dc_cdata.dc_rx_chain[i]; 2538 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2539 ptr += DC_RXLEN; 2540 /* If this is the last buffer, break out. */ 2541 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2542 break; 2543 dc_newbuf(sc, i, m); 2544 DC_INC(i, DC_RX_LIST_CNT); 2545 } 2546 2547 /* Find the length of the actual receive frame. */ 2548 total_len = DC_RXBYTES(rxstat); 2549 2550 /* Scan backwards until we hit a non-zero byte. */ 2551 while(*ptr == 0x00) 2552 ptr--; 2553 2554 /* Round off. */ 2555 if ((uintptr_t)(ptr) & 0x3) 2556 ptr -= 1; 2557 2558 /* Now find the start of the frame. */ 2559 ptr -= total_len; 2560 if (ptr < sc->dc_pnic_rx_buf) 2561 ptr = sc->dc_pnic_rx_buf; 2562 2563 /* 2564 * Now copy the salvaged frame to the last mbuf and fake up 2565 * the status word to make it look like a successful 2566 * frame reception. 2567 */ 2568 dc_newbuf(sc, i, m); 2569 bcopy(ptr, mtod(m, char *), total_len); 2570 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2571 2572 return; 2573} 2574 2575/* 2576 * This routine searches the RX ring for dirty descriptors in the 2577 * event that the rxeof routine falls out of sync with the chip's 2578 * current descriptor pointer. This may happen sometimes as a result 2579 * of a "no RX buffer available" condition that happens when the chip 2580 * consumes all of the RX buffers before the driver has a chance to 2581 * process the RX ring. This routine may need to be called more than 2582 * once to bring the driver back in sync with the chip, however we 2583 * should still be getting RX DONE interrupts to drive the search 2584 * for new packets in the RX ring, so we should catch up eventually. 2585 */ 2586static int 2587dc_rx_resync(sc) 2588 struct dc_softc *sc; 2589{ 2590 int i, pos; 2591 struct dc_desc *cur_rx; 2592 2593 pos = sc->dc_cdata.dc_rx_prod; 2594 2595 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2596 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2597 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2598 break; 2599 DC_INC(pos, DC_RX_LIST_CNT); 2600 } 2601 2602 /* If the ring really is empty, then just return. */ 2603 if (i == DC_RX_LIST_CNT) 2604 return(0); 2605 2606 /* We've fallen behing the chip: catch it. */ 2607 sc->dc_cdata.dc_rx_prod = pos; 2608 2609 return(EAGAIN); 2610} 2611 2612/* 2613 * A frame has been uploaded: pass the resulting mbuf chain up to 2614 * the higher level protocols. 2615 */ 2616static void 2617dc_rxeof(sc) 2618 struct dc_softc *sc; 2619{ 2620 struct mbuf *m; 2621 struct ifnet *ifp; 2622 struct dc_desc *cur_rx; 2623 int i, total_len = 0; 2624 u_int32_t rxstat; 2625 2626 ifp = &sc->arpcom.ac_if; 2627 i = sc->dc_cdata.dc_rx_prod; 2628 2629 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2630 2631#ifdef DEVICE_POLLING 2632 if (ifp->if_flags & IFF_POLLING) { 2633 if (sc->rxcycles <= 0) 2634 break; 2635 sc->rxcycles--; 2636 } 2637#endif /* DEVICE_POLLING */ 2638 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2639 rxstat = cur_rx->dc_status; 2640 m = sc->dc_cdata.dc_rx_chain[i]; 2641 total_len = DC_RXBYTES(rxstat); 2642 2643 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2644 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2645 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2646 sc->dc_pnic_rx_bug_save = i; 2647 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2648 DC_INC(i, DC_RX_LIST_CNT); 2649 continue; 2650 } 2651 dc_pnic_rx_bug_war(sc, i); 2652 rxstat = cur_rx->dc_status; 2653 total_len = DC_RXBYTES(rxstat); 2654 } 2655 } 2656 2657 sc->dc_cdata.dc_rx_chain[i] = NULL; 2658 2659 /* 2660 * If an error occurs, update stats, clear the 2661 * status word and leave the mbuf cluster in place: 2662 * it should simply get re-used next time this descriptor 2663 * comes up in the ring. However, don't report long 2664 * frames as errors since they could be vlans 2665 */ 2666 if ((rxstat & DC_RXSTAT_RXERR)){ 2667 if (!(rxstat & DC_RXSTAT_GIANT) || 2668 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2669 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2670 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2671 ifp->if_ierrors++; 2672 if (rxstat & DC_RXSTAT_COLLSEEN) 2673 ifp->if_collisions++; 2674 dc_newbuf(sc, i, m); 2675 if (rxstat & DC_RXSTAT_CRCERR) { 2676 DC_INC(i, DC_RX_LIST_CNT); 2677 continue; 2678 } else { 2679 dc_init(sc); 2680 return; 2681 } 2682 } 2683 } 2684 2685 /* No errors; receive the packet. */ 2686 total_len -= ETHER_CRC_LEN; 2687#ifdef __i386__ 2688 /* 2689 * On the x86 we do not have alignment problems, so try to 2690 * allocate a new buffer for the receive ring, and pass up 2691 * the one where the packet is already, saving the expensive 2692 * copy done in m_devget(). 2693 * If we are on an architecture with alignment problems, or 2694 * if the allocation fails, then use m_devget and leave the 2695 * existing buffer in the receive ring. 2696 */ 2697 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2698 m->m_pkthdr.rcvif = ifp; 2699 m->m_pkthdr.len = m->m_len = total_len; 2700 DC_INC(i, DC_RX_LIST_CNT); 2701 } else 2702#endif 2703 { 2704 struct mbuf *m0; 2705 2706 m0 = m_devget(mtod(m, char *), total_len, 2707 ETHER_ALIGN, ifp, NULL); 2708 dc_newbuf(sc, i, m); 2709 DC_INC(i, DC_RX_LIST_CNT); 2710 if (m0 == NULL) { 2711 ifp->if_ierrors++; 2712 continue; 2713 } 2714 m = m0; 2715 } 2716 2717 ifp->if_ipackets++; 2718 (*ifp->if_input)(ifp, m); 2719 } 2720 2721 sc->dc_cdata.dc_rx_prod = i; 2722} 2723 2724/* 2725 * A frame was downloaded to the chip. It's safe for us to clean up 2726 * the list buffers. 2727 */ 2728 2729static void 2730dc_txeof(sc) 2731 struct dc_softc *sc; 2732{ 2733 struct dc_desc *cur_tx = NULL; 2734 struct ifnet *ifp; 2735 int idx; 2736 2737 ifp = &sc->arpcom.ac_if; 2738 2739 /* 2740 * Go through our tx list and free mbufs for those 2741 * frames that have been transmitted. 2742 */ 2743 idx = sc->dc_cdata.dc_tx_cons; 2744 while(idx != sc->dc_cdata.dc_tx_prod) { 2745 u_int32_t txstat; 2746 2747 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2748 txstat = cur_tx->dc_status; 2749 2750 if (txstat & DC_TXSTAT_OWN) 2751 break; 2752 2753 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2754 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2755 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2756 /* 2757 * Yes, the PNIC is so brain damaged 2758 * that it will sometimes generate a TX 2759 * underrun error while DMAing the RX 2760 * filter setup frame. If we detect this, 2761 * we have to send the setup frame again, 2762 * or else the filter won't be programmed 2763 * correctly. 2764 */ 2765 if (DC_IS_PNIC(sc)) { 2766 if (txstat & DC_TXSTAT_ERRSUM) 2767 dc_setfilt(sc); 2768 } 2769 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2770 } 2771 sc->dc_cdata.dc_tx_cnt--; 2772 DC_INC(idx, DC_TX_LIST_CNT); 2773 continue; 2774 } 2775 2776 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2777 /* 2778 * XXX: Why does my Xircom taunt me so? 2779 * For some reason it likes setting the CARRLOST flag 2780 * even when the carrier is there. wtf?!? 2781 * Who knows, but Conexant chips have the 2782 * same problem. Maybe they took lessons 2783 * from Xircom. 2784 */ 2785 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2786 sc->dc_pmode == DC_PMODE_MII && 2787 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2788 DC_TXSTAT_NOCARRIER))) 2789 txstat &= ~DC_TXSTAT_ERRSUM; 2790 } else { 2791 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2792 sc->dc_pmode == DC_PMODE_MII && 2793 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2794 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2795 txstat &= ~DC_TXSTAT_ERRSUM; 2796 } 2797 2798 if (txstat & DC_TXSTAT_ERRSUM) { 2799 ifp->if_oerrors++; 2800 if (txstat & DC_TXSTAT_EXCESSCOLL) 2801 ifp->if_collisions++; 2802 if (txstat & DC_TXSTAT_LATECOLL) 2803 ifp->if_collisions++; 2804 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2805 dc_init(sc); 2806 return; 2807 } 2808 } 2809 2810 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2811 2812 ifp->if_opackets++; 2813 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2814 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2815 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2816 } 2817 2818 sc->dc_cdata.dc_tx_cnt--; 2819 DC_INC(idx, DC_TX_LIST_CNT); 2820 } 2821 2822 if (idx != sc->dc_cdata.dc_tx_cons) { 2823 /* some buffers have been freed */ 2824 sc->dc_cdata.dc_tx_cons = idx; 2825 ifp->if_flags &= ~IFF_OACTIVE; 2826 } 2827 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2828 2829 return; 2830} 2831 2832static void 2833dc_tick(xsc) 2834 void *xsc; 2835{ 2836 struct dc_softc *sc; 2837 struct mii_data *mii; 2838 struct ifnet *ifp; 2839 u_int32_t r; 2840 2841 sc = xsc; 2842 DC_LOCK(sc); 2843 ifp = &sc->arpcom.ac_if; 2844 mii = device_get_softc(sc->dc_miibus); 2845 2846 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2847 if (sc->dc_flags & DC_21143_NWAY) { 2848 r = CSR_READ_4(sc, DC_10BTSTAT); 2849 if (IFM_SUBTYPE(mii->mii_media_active) == 2850 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2851 sc->dc_link = 0; 2852 mii_mediachg(mii); 2853 } 2854 if (IFM_SUBTYPE(mii->mii_media_active) == 2855 IFM_10_T && (r & DC_TSTAT_LS10)) { 2856 sc->dc_link = 0; 2857 mii_mediachg(mii); 2858 } 2859 if (sc->dc_link == 0) 2860 mii_tick(mii); 2861 } else { 2862 r = CSR_READ_4(sc, DC_ISR); 2863 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2864 sc->dc_cdata.dc_tx_cnt == 0) { 2865 mii_tick(mii); 2866 if (!(mii->mii_media_status & IFM_ACTIVE)) 2867 sc->dc_link = 0; 2868 } 2869 } 2870 } else 2871 mii_tick(mii); 2872 2873 /* 2874 * When the init routine completes, we expect to be able to send 2875 * packets right away, and in fact the network code will send a 2876 * gratuitous ARP the moment the init routine marks the interface 2877 * as running. However, even though the MAC may have been initialized, 2878 * there may be a delay of a few seconds before the PHY completes 2879 * autonegotiation and the link is brought up. Any transmissions 2880 * made during that delay will be lost. Dealing with this is tricky: 2881 * we can't just pause in the init routine while waiting for the 2882 * PHY to come ready since that would bring the whole system to 2883 * a screeching halt for several seconds. 2884 * 2885 * What we do here is prevent the TX start routine from sending 2886 * any packets until a link has been established. After the 2887 * interface has been initialized, the tick routine will poll 2888 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2889 * that time, packets will stay in the send queue, and once the 2890 * link comes up, they will be flushed out to the wire. 2891 */ 2892 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2893 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2894 sc->dc_link++; 2895 if (ifp->if_snd.ifq_head != NULL) 2896 dc_start(ifp); 2897 } 2898 2899 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2900 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2901 else 2902 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2903 2904 DC_UNLOCK(sc); 2905 2906 return; 2907} 2908 2909/* 2910 * A transmit underrun has occurred. Back off the transmit threshold, 2911 * or switch to store and forward mode if we have to. 2912 */ 2913static void 2914dc_tx_underrun(sc) 2915 struct dc_softc *sc; 2916{ 2917 u_int32_t isr; 2918 int i; 2919 2920 if (DC_IS_DAVICOM(sc)) 2921 dc_init(sc); 2922 2923 if (DC_IS_INTEL(sc)) { 2924 /* 2925 * The real 21143 requires that the transmitter be idle 2926 * in order to change the transmit threshold or store 2927 * and forward state. 2928 */ 2929 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2930 2931 for (i = 0; i < DC_TIMEOUT; i++) { 2932 isr = CSR_READ_4(sc, DC_ISR); 2933 if (isr & DC_ISR_TX_IDLE) 2934 break; 2935 DELAY(10); 2936 } 2937 if (i == DC_TIMEOUT) { 2938 printf("dc%d: failed to force tx to idle state\n", 2939 sc->dc_unit); 2940 dc_init(sc); 2941 } 2942 } 2943 2944 printf("dc%d: TX underrun -- ", sc->dc_unit); 2945 sc->dc_txthresh += DC_TXTHRESH_INC; 2946 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2947 printf("using store and forward mode\n"); 2948 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2949 } else { 2950 printf("increasing TX threshold\n"); 2951 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2952 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2953 } 2954 2955 if (DC_IS_INTEL(sc)) 2956 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2957 2958 return; 2959} 2960 2961#ifdef DEVICE_POLLING 2962static poll_handler_t dc_poll; 2963 2964static void 2965dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2966{ 2967 struct dc_softc *sc = ifp->if_softc; 2968 2969 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2970 /* Re-enable interrupts. */ 2971 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2972 return; 2973 } 2974 sc->rxcycles = count; 2975 dc_rxeof(sc); 2976 dc_txeof(sc); 2977 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2978 dc_start(ifp); 2979 2980 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2981 u_int32_t status; 2982 2983 status = CSR_READ_4(sc, DC_ISR); 2984 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2985 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2986 DC_ISR_BUS_ERR); 2987 if (!status) 2988 return; 2989 /* ack what we have */ 2990 CSR_WRITE_4(sc, DC_ISR, status); 2991 2992 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 2993 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2994 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2995 2996 if (dc_rx_resync(sc)) 2997 dc_rxeof(sc); 2998 } 2999 /* restart transmit unit if necessary */ 3000 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 3001 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3002 3003 if (status & DC_ISR_TX_UNDERRUN) 3004 dc_tx_underrun(sc); 3005 3006 if (status & DC_ISR_BUS_ERR) { 3007 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3008 dc_reset(sc); 3009 dc_init(sc); 3010 } 3011 } 3012} 3013#endif /* DEVICE_POLLING */ 3014 3015static void 3016dc_intr(arg) 3017 void *arg; 3018{ 3019 struct dc_softc *sc; 3020 struct ifnet *ifp; 3021 u_int32_t status; 3022 3023 sc = arg; 3024 3025 if (sc->suspended) { 3026 return; 3027 } 3028 3029 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3030 return; 3031 3032 DC_LOCK(sc); 3033 ifp = &sc->arpcom.ac_if; 3034#ifdef DEVICE_POLLING 3035 if (ifp->if_flags & IFF_POLLING) 3036 goto done; 3037 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3038 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3039 goto done; 3040 } 3041#endif /* DEVICE_POLLING */ 3042 3043 /* Suppress unwanted interrupts */ 3044 if (!(ifp->if_flags & IFF_UP)) { 3045 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3046 dc_stop(sc); 3047 DC_UNLOCK(sc); 3048 return; 3049 } 3050 3051 /* Disable interrupts. */ 3052 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3053 3054 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3055 && status != 0xFFFFFFFF) { 3056 3057 CSR_WRITE_4(sc, DC_ISR, status); 3058 3059 if (status & DC_ISR_RX_OK) { 3060 int curpkts; 3061 curpkts = ifp->if_ipackets; 3062 dc_rxeof(sc); 3063 if (curpkts == ifp->if_ipackets) { 3064 while(dc_rx_resync(sc)) 3065 dc_rxeof(sc); 3066 } 3067 } 3068 3069 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 3070 dc_txeof(sc); 3071 3072 if (status & DC_ISR_TX_IDLE) { 3073 dc_txeof(sc); 3074 if (sc->dc_cdata.dc_tx_cnt) { 3075 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3076 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3077 } 3078 } 3079 3080 if (status & DC_ISR_TX_UNDERRUN) 3081 dc_tx_underrun(sc); 3082 3083 if ((status & DC_ISR_RX_WATDOGTIMEO) 3084 || (status & DC_ISR_RX_NOBUF)) { 3085 int curpkts; 3086 curpkts = ifp->if_ipackets; 3087 dc_rxeof(sc); 3088 if (curpkts == ifp->if_ipackets) { 3089 while(dc_rx_resync(sc)) 3090 dc_rxeof(sc); 3091 } 3092 } 3093 3094 if (status & DC_ISR_BUS_ERR) { 3095 dc_reset(sc); 3096 dc_init(sc); 3097 } 3098 } 3099 3100 /* Re-enable interrupts. */ 3101 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3102 3103 if (ifp->if_snd.ifq_head != NULL) 3104 dc_start(ifp); 3105 3106#ifdef DEVICE_POLLING 3107done: 3108#endif /* DEVICE_POLLING */ 3109 3110 DC_UNLOCK(sc); 3111 3112 return; 3113} 3114 3115/* 3116 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3117 * pointers to the fragment pointers. 3118 */ 3119static int 3120dc_encap(sc, m_head, txidx) 3121 struct dc_softc *sc; 3122 struct mbuf *m_head; 3123 u_int32_t *txidx; 3124{ 3125 struct dc_desc *f = NULL; 3126 struct mbuf *m; 3127 int frag, cur, cnt = 0, chainlen = 0; 3128 3129 /* 3130 * If there's no way we can send any packets, return now. 3131 */ 3132 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt < 6) 3133 return (ENOBUFS); 3134 3135 /* 3136 * Count the number of frags in this chain to see if 3137 * we need to m_defrag. Since the descriptor list is shared 3138 * by all packets, we'll m_defrag long chains so that they 3139 * do not use up the entire list, even if they would fit. 3140 */ 3141 3142 for (m = m_head; m != NULL; m = m->m_next) 3143 chainlen++; 3144 3145 if ((chainlen > DC_TX_LIST_CNT / 4) || 3146 ((DC_TX_LIST_CNT - (chainlen + sc->dc_cdata.dc_tx_cnt)) < 6)) { 3147 m = m_defrag(m_head, M_DONTWAIT); 3148 if (m == NULL) 3149 return (ENOBUFS); 3150 m_head = m; 3151 } 3152 3153 /* 3154 * Start packing the mbufs in this chain into 3155 * the fragment pointers. Stop when we run out 3156 * of fragments or hit the end of the mbuf chain. 3157 */ 3158 m = m_head; 3159 cur = frag = *txidx; 3160 3161 for (m = m_head; m != NULL; m = m->m_next) { 3162 if (m->m_len != 0) { 3163 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3164 if (*txidx != sc->dc_cdata.dc_tx_prod && 3165 frag == (DC_TX_LIST_CNT - 1)) 3166 return(ENOBUFS); 3167 } 3168 if ((DC_TX_LIST_CNT - 3169 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3170 return(ENOBUFS); 3171 3172 f = &sc->dc_ldata->dc_tx_list[frag]; 3173 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3174 if (cnt == 0) { 3175 f->dc_status = 0; 3176 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3177 } else 3178 f->dc_status = DC_TXSTAT_OWN; 3179 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3180 cur = frag; 3181 DC_INC(frag, DC_TX_LIST_CNT); 3182 cnt++; 3183 } 3184 } 3185 3186 if (m != NULL) 3187 return(ENOBUFS); 3188 3189 sc->dc_cdata.dc_tx_cnt += cnt; 3190 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3191 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3192 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3193 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3194 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3195 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3196 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3197 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3198 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3199 *txidx = frag; 3200 3201 return(0); 3202} 3203 3204/* 3205 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3206 * to the mbuf data regions directly in the transmit lists. We also save a 3207 * copy of the pointers since the transmit list fragment pointers are 3208 * physical addresses. 3209 */ 3210 3211static void 3212dc_start(ifp) 3213 struct ifnet *ifp; 3214{ 3215 struct dc_softc *sc; 3216 struct mbuf *m_head = NULL, *m; 3217 int idx; 3218 3219 sc = ifp->if_softc; 3220 3221 DC_LOCK(sc); 3222 3223 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3224 DC_UNLOCK(sc); 3225 return; 3226 } 3227 3228 if (ifp->if_flags & IFF_OACTIVE) { 3229 DC_UNLOCK(sc); 3230 return; 3231 } 3232 3233 idx = sc->dc_cdata.dc_tx_prod; 3234 3235 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3236 IF_DEQUEUE(&ifp->if_snd, m_head); 3237 if (m_head == NULL) 3238 break; 3239 3240 if (sc->dc_flags & DC_TX_COALESCE && 3241 (m_head->m_next != NULL || 3242 sc->dc_flags & DC_TX_ALIGN)) { 3243 m = m_defrag(m_head, M_DONTWAIT); 3244 if (m == NULL) { 3245 IF_PREPEND(&ifp->if_snd, m_head); 3246 ifp->if_flags |= IFF_OACTIVE; 3247 break; 3248 } else { 3249 m_head = m; 3250 } 3251 } 3252 3253 if (dc_encap(sc, m_head, &idx)) { 3254 IF_PREPEND(&ifp->if_snd, m_head); 3255 ifp->if_flags |= IFF_OACTIVE; 3256 break; 3257 } 3258 3259 /* 3260 * If there's a BPF listener, bounce a copy of this frame 3261 * to him. 3262 */ 3263 BPF_MTAP(ifp, m_head); 3264 3265 if (sc->dc_flags & DC_TX_ONE) { 3266 ifp->if_flags |= IFF_OACTIVE; 3267 break; 3268 } 3269 } 3270 3271 /* Transmit */ 3272 sc->dc_cdata.dc_tx_prod = idx; 3273 if (!(sc->dc_flags & DC_TX_POLL)) 3274 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3275 3276 /* 3277 * Set a timeout in case the chip goes out to lunch. 3278 */ 3279 ifp->if_timer = 5; 3280 3281 DC_UNLOCK(sc); 3282 3283 return; 3284} 3285 3286static void 3287dc_init(xsc) 3288 void *xsc; 3289{ 3290 struct dc_softc *sc = xsc; 3291 struct ifnet *ifp = &sc->arpcom.ac_if; 3292 struct mii_data *mii; 3293 3294 DC_LOCK(sc); 3295 3296 mii = device_get_softc(sc->dc_miibus); 3297 3298 /* 3299 * Cancel pending I/O and free all RX/TX buffers. 3300 */ 3301 dc_stop(sc); 3302 dc_reset(sc); 3303 3304 /* 3305 * Set cache alignment and burst length. 3306 */ 3307 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3308 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3309 else 3310 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3311 /* 3312 * Evenly share the bus between receive and transmit process. 3313 */ 3314 if (DC_IS_INTEL(sc)) 3315 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3316 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3317 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3318 } else { 3319 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3320 } 3321 if (sc->dc_flags & DC_TX_POLL) 3322 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3323 switch(sc->dc_cachesize) { 3324 case 32: 3325 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3326 break; 3327 case 16: 3328 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3329 break; 3330 case 8: 3331 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3332 break; 3333 case 0: 3334 default: 3335 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3336 break; 3337 } 3338 3339 if (sc->dc_flags & DC_TX_STORENFWD) 3340 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3341 else { 3342 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3343 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3344 } else { 3345 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3346 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3347 } 3348 } 3349 3350 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3351 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3352 3353 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3354 /* 3355 * The app notes for the 98713 and 98715A say that 3356 * in order to have the chips operate properly, a magic 3357 * number must be written to CSR16. Macronix does not 3358 * document the meaning of these bits so there's no way 3359 * to know exactly what they do. The 98713 has a magic 3360 * number all its own; the rest all use a different one. 3361 */ 3362 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3363 if (sc->dc_type == DC_TYPE_98713) 3364 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3365 else 3366 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3367 } 3368 3369 if (DC_IS_XIRCOM(sc)) { 3370 /* 3371 * setup General Purpose Port mode and data so the tulip 3372 * can talk to the MII. 3373 */ 3374 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3375 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3376 DELAY(10); 3377 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3378 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3379 DELAY(10); 3380 } 3381 3382 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3383 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3384 3385 /* Init circular RX list. */ 3386 if (dc_list_rx_init(sc) == ENOBUFS) { 3387 printf("dc%d: initialization failed: no " 3388 "memory for rx buffers\n", sc->dc_unit); 3389 dc_stop(sc); 3390 DC_UNLOCK(sc); 3391 return; 3392 } 3393 3394 /* 3395 * Init tx descriptors. 3396 */ 3397 dc_list_tx_init(sc); 3398 3399 /* 3400 * Load the address of the RX list. 3401 */ 3402 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3403 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3404 3405 /* 3406 * Enable interrupts. 3407 */ 3408#ifdef DEVICE_POLLING 3409 /* 3410 * ... but only if we are not polling, and make sure they are off in 3411 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3412 * after a reset. 3413 */ 3414 if (ifp->if_flags & IFF_POLLING) 3415 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3416 else 3417#endif 3418 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3419 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3420 3421 /* Enable transmitter. */ 3422 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3423 3424 /* 3425 * If this is an Intel 21143 and we're not using the 3426 * MII port, program the LED control pins so we get 3427 * link and activity indications. 3428 */ 3429 if (sc->dc_flags & DC_TULIP_LEDS) { 3430 CSR_WRITE_4(sc, DC_WATCHDOG, 3431 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3432 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3433 } 3434 3435 /* 3436 * Load the RX/multicast filter. We do this sort of late 3437 * because the filter programming scheme on the 21143 and 3438 * some clones requires DMAing a setup frame via the TX 3439 * engine, and we need the transmitter enabled for that. 3440 */ 3441 dc_setfilt(sc); 3442 3443 /* Enable receiver. */ 3444 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3445 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3446 3447 mii_mediachg(mii); 3448 dc_setcfg(sc, sc->dc_if_media); 3449 3450 ifp->if_flags |= IFF_RUNNING; 3451 ifp->if_flags &= ~IFF_OACTIVE; 3452 3453 /* Don't start the ticker if this is a homePNA link. */ 3454 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3455 sc->dc_link = 1; 3456 else { 3457 if (sc->dc_flags & DC_21143_NWAY) 3458 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3459 else 3460 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3461 } 3462 3463#ifdef SRM_MEDIA 3464 if(sc->dc_srm_media) { 3465 struct ifreq ifr; 3466 3467 ifr.ifr_media = sc->dc_srm_media; 3468 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3469 sc->dc_srm_media = 0; 3470 } 3471#endif 3472 DC_UNLOCK(sc); 3473 return; 3474} 3475 3476/* 3477 * Set media options. 3478 */ 3479static int 3480dc_ifmedia_upd(ifp) 3481 struct ifnet *ifp; 3482{ 3483 struct dc_softc *sc; 3484 struct mii_data *mii; 3485 struct ifmedia *ifm; 3486 3487 sc = ifp->if_softc; 3488 mii = device_get_softc(sc->dc_miibus); 3489 mii_mediachg(mii); 3490 ifm = &mii->mii_media; 3491 3492 if (DC_IS_DAVICOM(sc) && 3493 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3494 dc_setcfg(sc, ifm->ifm_media); 3495 else 3496 sc->dc_link = 0; 3497 3498 return(0); 3499} 3500 3501/* 3502 * Report current media status. 3503 */ 3504static void 3505dc_ifmedia_sts(ifp, ifmr) 3506 struct ifnet *ifp; 3507 struct ifmediareq *ifmr; 3508{ 3509 struct dc_softc *sc; 3510 struct mii_data *mii; 3511 struct ifmedia *ifm; 3512 3513 sc = ifp->if_softc; 3514 mii = device_get_softc(sc->dc_miibus); 3515 mii_pollstat(mii); 3516 ifm = &mii->mii_media; 3517 if (DC_IS_DAVICOM(sc)) { 3518 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3519 ifmr->ifm_active = ifm->ifm_media; 3520 ifmr->ifm_status = 0; 3521 return; 3522 } 3523 } 3524 ifmr->ifm_active = mii->mii_media_active; 3525 ifmr->ifm_status = mii->mii_media_status; 3526 3527 return; 3528} 3529 3530static int 3531dc_ioctl(ifp, command, data) 3532 struct ifnet *ifp; 3533 u_long command; 3534 caddr_t data; 3535{ 3536 struct dc_softc *sc = ifp->if_softc; 3537 struct ifreq *ifr = (struct ifreq *) data; 3538 struct mii_data *mii; 3539 int error = 0; 3540 3541 DC_LOCK(sc); 3542 3543 switch(command) { 3544 case SIOCSIFFLAGS: 3545 if (ifp->if_flags & IFF_UP) { 3546 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3547 (IFF_PROMISC | IFF_ALLMULTI); 3548 3549 if (ifp->if_flags & IFF_RUNNING) { 3550 if (need_setfilt) 3551 dc_setfilt(sc); 3552 } else { 3553 sc->dc_txthresh = 0; 3554 dc_init(sc); 3555 } 3556 } else { 3557 if (ifp->if_flags & IFF_RUNNING) 3558 dc_stop(sc); 3559 } 3560 sc->dc_if_flags = ifp->if_flags; 3561 error = 0; 3562 break; 3563 case SIOCADDMULTI: 3564 case SIOCDELMULTI: 3565 dc_setfilt(sc); 3566 error = 0; 3567 break; 3568 case SIOCGIFMEDIA: 3569 case SIOCSIFMEDIA: 3570 mii = device_get_softc(sc->dc_miibus); 3571 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3572#ifdef SRM_MEDIA 3573 if (sc->dc_srm_media) 3574 sc->dc_srm_media = 0; 3575#endif 3576 break; 3577 default: 3578 error = ether_ioctl(ifp, command, data); 3579 break; 3580 } 3581 3582 DC_UNLOCK(sc); 3583 3584 return(error); 3585} 3586 3587static void 3588dc_watchdog(ifp) 3589 struct ifnet *ifp; 3590{ 3591 struct dc_softc *sc; 3592 3593 sc = ifp->if_softc; 3594 3595 DC_LOCK(sc); 3596 3597 ifp->if_oerrors++; 3598 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3599 3600 dc_stop(sc); 3601 dc_reset(sc); 3602 dc_init(sc); 3603 3604 if (ifp->if_snd.ifq_head != NULL) 3605 dc_start(ifp); 3606 3607 DC_UNLOCK(sc); 3608 3609 return; 3610} 3611 3612/* 3613 * Stop the adapter and free any mbufs allocated to the 3614 * RX and TX lists. 3615 */ 3616static void 3617dc_stop(sc) 3618 struct dc_softc *sc; 3619{ 3620 register int i; 3621 struct ifnet *ifp; 3622 3623 DC_LOCK(sc); 3624 3625 ifp = &sc->arpcom.ac_if; 3626 ifp->if_timer = 0; 3627 3628 callout_stop(&sc->dc_stat_ch); 3629 3630 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3631#ifdef DEVICE_POLLING 3632 ether_poll_deregister(ifp); 3633#endif 3634 3635 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3636 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3637 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3638 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3639 sc->dc_link = 0; 3640 3641 /* 3642 * Free data in the RX lists. 3643 */ 3644 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3645 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3646 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3647 sc->dc_cdata.dc_rx_chain[i] = NULL; 3648 } 3649 } 3650 bzero((char *)&sc->dc_ldata->dc_rx_list, 3651 sizeof(sc->dc_ldata->dc_rx_list)); 3652 3653 /* 3654 * Free the TX list buffers. 3655 */ 3656 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3657 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3658 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3659 DC_TXCTL_SETUP) { 3660 sc->dc_cdata.dc_tx_chain[i] = NULL; 3661 continue; 3662 } 3663 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3664 sc->dc_cdata.dc_tx_chain[i] = NULL; 3665 } 3666 } 3667 3668 bzero((char *)&sc->dc_ldata->dc_tx_list, 3669 sizeof(sc->dc_ldata->dc_tx_list)); 3670 3671 DC_UNLOCK(sc); 3672 3673 return; 3674} 3675 3676/* 3677 * Device suspend routine. Stop the interface and save some PCI 3678 * settings in case the BIOS doesn't restore them properly on 3679 * resume. 3680 */ 3681static int 3682dc_suspend(dev) 3683 device_t dev; 3684{ 3685 register int i; 3686 int s; 3687 struct dc_softc *sc; 3688 3689 s = splimp(); 3690 3691 sc = device_get_softc(dev); 3692 3693 dc_stop(sc); 3694 3695 for (i = 0; i < 5; i++) 3696 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3697 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3698 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3699 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3700 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3701 3702 sc->suspended = 1; 3703 3704 splx(s); 3705 return (0); 3706} 3707 3708/* 3709 * Device resume routine. Restore some PCI settings in case the BIOS 3710 * doesn't, re-enable busmastering, and restart the interface if 3711 * appropriate. 3712 */ 3713static int 3714dc_resume(dev) 3715 device_t dev; 3716{ 3717 register int i; 3718 int s; 3719 struct dc_softc *sc; 3720 struct ifnet *ifp; 3721 3722 s = splimp(); 3723 3724 sc = device_get_softc(dev); 3725 ifp = &sc->arpcom.ac_if; 3726 3727 dc_acpi(dev); 3728 3729 /* better way to do this? */ 3730 for (i = 0; i < 5; i++) 3731 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3732 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3733 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3734 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3735 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3736 3737 /* reenable busmastering */ 3738 pci_enable_busmaster(dev); 3739 pci_enable_io(dev, DC_RES); 3740 3741 /* reinitialize interface if necessary */ 3742 if (ifp->if_flags & IFF_UP) 3743 dc_init(sc); 3744 3745 sc->suspended = 0; 3746 3747 splx(s); 3748 return (0); 3749} 3750 3751/* 3752 * Stop all chip I/O so that the kernel's probe routines don't 3753 * get confused by errant DMAs when rebooting. 3754 */ 3755static void 3756dc_shutdown(dev) 3757 device_t dev; 3758{ 3759 struct dc_softc *sc; 3760 3761 sc = device_get_softc(dev); 3762 3763 dc_stop(sc); 3764 3765 return; 3766} 3767