if_dc.c revision 104600
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/dc/if_dc.c 104600 2002-10-07 05:29:13Z imp $ 33 */ 34 35/* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 47 * Accton EN1217 (www.accton.com) 48 * Xircom X3201 (www.xircom.com) 49 * Abocom FE2500 50 * Conexant LANfinity (www.conexant.com) 51 * 52 * Datasheets for the 21143 are available at developer.intel.com. 53 * Datasheets for the clone parts can be found at their respective sites. 54 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 55 * The PNIC II is essentially a Macronix 98715A chip; the only difference 56 * worth noting is that its multicast hash table is only 128 bits wide 57 * instead of 512. 58 * 59 * Written by Bill Paul <wpaul@ee.columbia.edu> 60 * Electrical Engineering Department 61 * Columbia University, New York City 62 */ 63 64/* 65 * The Intel 21143 is the successor to the DEC 21140. It is basically 66 * the same as the 21140 but with a few new features. The 21143 supports 67 * three kinds of media attachments: 68 * 69 * o MII port, for 10Mbps and 100Mbps support and NWAY 70 * autonegotiation provided by an external PHY. 71 * o SYM port, for symbol mode 100Mbps support. 72 * o 10baseT port. 73 * o AUI/BNC port. 74 * 75 * The 100Mbps SYM port and 10baseT port can be used together in 76 * combination with the internal NWAY support to create a 10/100 77 * autosensing configuration. 78 * 79 * Note that not all tulip workalikes are handled in this driver: we only 80 * deal with those which are relatively well behaved. The Winbond is 81 * handled separately due to its different register offsets and the 82 * special handling needed for its various bugs. The PNIC is handled 83 * here, but I'm not thrilled about it. 84 * 85 * All of the workalike chips use some form of MII transceiver support 86 * with the exception of the Macronix chips, which also have a SYM port. 87 * The ASIX AX88140A is also documented to have a SYM port, but all 88 * the cards I've seen use an MII transceiver, probably because the 89 * AX88140A doesn't support internal NWAY. 90 */ 91 92#include <sys/param.h> 93#include <sys/systm.h> 94#include <sys/sockio.h> 95#include <sys/mbuf.h> 96#include <sys/malloc.h> 97#include <sys/kernel.h> 98#include <sys/socket.h> 99#include <sys/sysctl.h> 100 101#include <net/if.h> 102#include <net/if_arp.h> 103#include <net/ethernet.h> 104#include <net/if_dl.h> 105#include <net/if_media.h> 106#include <net/if_types.h> 107#include <net/if_vlan_var.h> 108 109#include <net/bpf.h> 110 111#include <vm/vm.h> /* for vtophys */ 112#include <vm/pmap.h> /* for vtophys */ 113#include <machine/bus_pio.h> 114#include <machine/bus_memio.h> 115#include <machine/bus.h> 116#include <machine/resource.h> 117#include <sys/bus.h> 118#include <sys/rman.h> 119 120#include <dev/mii/mii.h> 121#include <dev/mii/miivar.h> 122 123#include <pci/pcireg.h> 124#include <pci/pcivar.h> 125 126#define DC_USEIOSPACE 127#ifdef __alpha__ 128#define SRM_MEDIA 129#endif 130 131#include <pci/if_dcreg.h> 132 133MODULE_DEPEND(dc, miibus, 1, 1, 1); 134 135/* "controller miibus0" required. See GENERIC if you get errors here. */ 136#include "miibus_if.h" 137 138#ifndef lint 139static const char rcsid[] = 140 "$FreeBSD: head/sys/dev/dc/if_dc.c 104600 2002-10-07 05:29:13Z imp $"; 141#endif 142 143/* 144 * Various supported device vendors/types and their names. 145 */ 146static struct dc_type dc_devs[] = { 147 { DC_VENDORID_DEC, DC_DEVICEID_21143, 148 "Intel 21143 10/100BaseTX" }, 149 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 150 "Davicom DM9100 10/100BaseTX" }, 151 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 152 "Davicom DM9102 10/100BaseTX" }, 153 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 154 "Davicom DM9102A 10/100BaseTX" }, 155 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 156 "ADMtek AL981 10/100BaseTX" }, 157 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 158 "ADMtek AN985 10/100BaseTX" }, 159 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 160 "ASIX AX88140A 10/100BaseTX" }, 161 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 162 "ASIX AX88141 10/100BaseTX" }, 163 { DC_VENDORID_MX, DC_DEVICEID_98713, 164 "Macronix 98713 10/100BaseTX" }, 165 { DC_VENDORID_MX, DC_DEVICEID_98713, 166 "Macronix 98713A 10/100BaseTX" }, 167 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 168 "Compex RL100-TX 10/100BaseTX" }, 169 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 170 "Compex RL100-TX 10/100BaseTX" }, 171 { DC_VENDORID_MX, DC_DEVICEID_987x5, 172 "Macronix 98715/98715A 10/100BaseTX" }, 173 { DC_VENDORID_MX, DC_DEVICEID_987x5, 174 "Macronix 98715AEC-C 10/100BaseTX" }, 175 { DC_VENDORID_MX, DC_DEVICEID_987x5, 176 "Macronix 98725 10/100BaseTX" }, 177 { DC_VENDORID_MX, DC_DEVICEID_98727, 178 "Macronix 98727/98732 10/100BaseTX" }, 179 { DC_VENDORID_LO, DC_DEVICEID_82C115, 180 "LC82C115 PNIC II 10/100BaseTX" }, 181 { DC_VENDORID_LO, DC_DEVICEID_82C168, 182 "82c168 PNIC 10/100BaseTX" }, 183 { DC_VENDORID_LO, DC_DEVICEID_82C168, 184 "82c169 PNIC 10/100BaseTX" }, 185 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 186 "Accton EN1217 10/100BaseTX" }, 187 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 188 "Accton EN2242 MiniPCI 10/100BaseTX" }, 189 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 190 "Xircom X3201 10/100BaseTX" }, 191 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 192 "Abocom FE2500 10/100BaseTX" }, 193 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 194 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 195 { 0, 0, NULL } 196}; 197 198static int dc_probe (device_t); 199static int dc_attach (device_t); 200static int dc_detach (device_t); 201static int dc_suspend (device_t); 202static int dc_resume (device_t); 203static void dc_acpi (device_t); 204static struct dc_type *dc_devtype (device_t); 205static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 206static int dc_encap (struct dc_softc *, struct mbuf *, u_int32_t *); 207static int dc_coal (struct dc_softc *, struct mbuf **); 208static void dc_pnic_rx_bug_war (struct dc_softc *, int); 209static int dc_rx_resync (struct dc_softc *); 210static void dc_rxeof (struct dc_softc *); 211static void dc_txeof (struct dc_softc *); 212static void dc_tick (void *); 213static void dc_tx_underrun (struct dc_softc *); 214static void dc_intr (void *); 215static void dc_start (struct ifnet *); 216static int dc_ioctl (struct ifnet *, u_long, caddr_t); 217static void dc_init (void *); 218static void dc_stop (struct dc_softc *); 219static void dc_watchdog (struct ifnet *); 220static void dc_shutdown (device_t); 221static int dc_ifmedia_upd (struct ifnet *); 222static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 223 224static void dc_delay (struct dc_softc *); 225static void dc_eeprom_idle (struct dc_softc *); 226static void dc_eeprom_putbyte (struct dc_softc *, int); 227static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 228static void dc_eeprom_getword_pnic 229 (struct dc_softc *, int, u_int16_t *); 230static void dc_eeprom_getword_xircom 231 (struct dc_softc *, int, u_int16_t *); 232static void dc_eeprom_width (struct dc_softc *); 233static void dc_read_eeprom (struct dc_softc *, caddr_t, int, int, int); 234 235static void dc_mii_writebit (struct dc_softc *, int); 236static int dc_mii_readbit (struct dc_softc *); 237static void dc_mii_sync (struct dc_softc *); 238static void dc_mii_send (struct dc_softc *, u_int32_t, int); 239static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 240static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 241static int dc_miibus_readreg (device_t, int, int); 242static int dc_miibus_writereg (device_t, int, int, int); 243static void dc_miibus_statchg (device_t); 244static void dc_miibus_mediainit (device_t); 245 246static void dc_setcfg (struct dc_softc *, int); 247static u_int32_t dc_crc_le (struct dc_softc *, caddr_t); 248static u_int32_t dc_crc_be (caddr_t); 249static void dc_setfilt_21143 (struct dc_softc *); 250static void dc_setfilt_asix (struct dc_softc *); 251static void dc_setfilt_admtek (struct dc_softc *); 252static void dc_setfilt_xircom (struct dc_softc *); 253 254static void dc_setfilt (struct dc_softc *); 255 256static void dc_reset (struct dc_softc *); 257static int dc_list_rx_init (struct dc_softc *); 258static int dc_list_tx_init (struct dc_softc *); 259 260static void dc_read_srom (struct dc_softc *, int); 261static void dc_parse_21143_srom (struct dc_softc *); 262static void dc_decode_leaf_sia (struct dc_softc *, struct dc_eblock_sia *); 263static void dc_decode_leaf_mii (struct dc_softc *, struct dc_eblock_mii *); 264static void dc_decode_leaf_sym (struct dc_softc *, struct dc_eblock_sym *); 265static void dc_apply_fixup (struct dc_softc *, int); 266 267#ifdef DC_USEIOSPACE 268#define DC_RES SYS_RES_IOPORT 269#define DC_RID DC_PCI_CFBIO 270#else 271#define DC_RES SYS_RES_MEMORY 272#define DC_RID DC_PCI_CFBMA 273#endif 274 275static device_method_t dc_methods[] = { 276 /* Device interface */ 277 DEVMETHOD(device_probe, dc_probe), 278 DEVMETHOD(device_attach, dc_attach), 279 DEVMETHOD(device_detach, dc_detach), 280 DEVMETHOD(device_suspend, dc_suspend), 281 DEVMETHOD(device_resume, dc_resume), 282 DEVMETHOD(device_shutdown, dc_shutdown), 283 284 /* bus interface */ 285 DEVMETHOD(bus_print_child, bus_generic_print_child), 286 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 287 288 /* MII interface */ 289 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 290 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 291 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 292 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 293 294 { 0, 0 } 295}; 296 297static driver_t dc_driver = { 298 "dc", 299 dc_methods, 300 sizeof(struct dc_softc) 301}; 302 303static devclass_t dc_devclass; 304#ifdef __i386__ 305static int dc_quick=1; 306SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 307 &dc_quick,0,"do not mdevget in dc driver"); 308#endif 309 310DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, 0, 0); 311DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0); 312DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0); 313 314#define DC_SETBIT(sc, reg, x) \ 315 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 316 317#define DC_CLRBIT(sc, reg, x) \ 318 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 319 320#define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 321#define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 322 323#define IS_MPSAFE 0 324 325static void 326dc_delay(sc) 327 struct dc_softc *sc; 328{ 329 int idx; 330 331 for (idx = (300 / 33) + 1; idx > 0; idx--) 332 CSR_READ_4(sc, DC_BUSCTL); 333} 334 335void dc_eeprom_width(sc) 336 struct dc_softc *sc; 337{ 338 int i; 339 340 /* Force EEPROM to idle state. */ 341 dc_eeprom_idle(sc); 342 343 /* Enter EEPROM access mode. */ 344 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 345 dc_delay(sc); 346 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 347 dc_delay(sc); 348 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 349 dc_delay(sc); 350 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 351 dc_delay(sc); 352 353 for (i = 3; i--;) { 354 if (6 & (1 << i)) 355 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 356 else 357 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 358 dc_delay(sc); 359 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 360 dc_delay(sc); 361 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 362 dc_delay(sc); 363 } 364 365 for (i = 1; i <= 12; i++) { 366 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 367 dc_delay(sc); 368 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 370 dc_delay(sc); 371 break; 372 } 373 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 374 dc_delay(sc); 375 } 376 377 /* Turn off EEPROM access mode. */ 378 dc_eeprom_idle(sc); 379 380 if (i < 4 || i > 12) 381 sc->dc_romwidth = 6; 382 else 383 sc->dc_romwidth = i; 384 385 /* Enter EEPROM access mode. */ 386 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 387 dc_delay(sc); 388 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 389 dc_delay(sc); 390 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 391 dc_delay(sc); 392 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 393 dc_delay(sc); 394 395 /* Turn off EEPROM access mode. */ 396 dc_eeprom_idle(sc); 397} 398 399static void 400dc_eeprom_idle(sc) 401 struct dc_softc *sc; 402{ 403 register int i; 404 405 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 406 dc_delay(sc); 407 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 408 dc_delay(sc); 409 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 410 dc_delay(sc); 411 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 412 dc_delay(sc); 413 414 for (i = 0; i < 25; i++) { 415 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 416 dc_delay(sc); 417 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 418 dc_delay(sc); 419 } 420 421 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 422 dc_delay(sc); 423 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 424 dc_delay(sc); 425 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 426 427 return; 428} 429 430/* 431 * Send a read command and address to the EEPROM, check for ACK. 432 */ 433static void 434dc_eeprom_putbyte(sc, addr) 435 struct dc_softc *sc; 436 int addr; 437{ 438 register int d, i; 439 440 d = DC_EECMD_READ >> 6; 441 for (i = 3; i--; ) { 442 if (d & (1 << i)) 443 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 444 else 445 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 446 dc_delay(sc); 447 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 448 dc_delay(sc); 449 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 450 dc_delay(sc); 451 } 452 453 /* 454 * Feed in each bit and strobe the clock. 455 */ 456 for (i = sc->dc_romwidth; i--;) { 457 if (addr & (1 << i)) { 458 SIO_SET(DC_SIO_EE_DATAIN); 459 } else { 460 SIO_CLR(DC_SIO_EE_DATAIN); 461 } 462 dc_delay(sc); 463 SIO_SET(DC_SIO_EE_CLK); 464 dc_delay(sc); 465 SIO_CLR(DC_SIO_EE_CLK); 466 dc_delay(sc); 467 } 468 469 return; 470} 471 472/* 473 * Read a word of data stored in the EEPROM at address 'addr.' 474 * The PNIC 82c168/82c169 has its own non-standard way to read 475 * the EEPROM. 476 */ 477static void 478dc_eeprom_getword_pnic(sc, addr, dest) 479 struct dc_softc *sc; 480 int addr; 481 u_int16_t *dest; 482{ 483 register int i; 484 u_int32_t r; 485 486 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 487 488 for (i = 0; i < DC_TIMEOUT; i++) { 489 DELAY(1); 490 r = CSR_READ_4(sc, DC_SIO); 491 if (!(r & DC_PN_SIOCTL_BUSY)) { 492 *dest = (u_int16_t)(r & 0xFFFF); 493 return; 494 } 495 } 496 497 return; 498} 499 500/* 501 * Read a word of data stored in the EEPROM at address 'addr.' 502 * The Xircom X3201 has its own non-standard way to read 503 * the EEPROM, too. 504 */ 505static void 506dc_eeprom_getword_xircom(sc, addr, dest) 507 struct dc_softc *sc; 508 int addr; 509 u_int16_t *dest; 510{ 511 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 512 513 addr *= 2; 514 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 515 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 516 addr += 1; 517 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 518 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 519 520 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 521 return; 522} 523 524/* 525 * Read a word of data stored in the EEPROM at address 'addr.' 526 */ 527static void 528dc_eeprom_getword(sc, addr, dest) 529 struct dc_softc *sc; 530 int addr; 531 u_int16_t *dest; 532{ 533 register int i; 534 u_int16_t word = 0; 535 536 /* Force EEPROM to idle state. */ 537 dc_eeprom_idle(sc); 538 539 /* Enter EEPROM access mode. */ 540 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 541 dc_delay(sc); 542 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 543 dc_delay(sc); 544 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 545 dc_delay(sc); 546 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 547 dc_delay(sc); 548 549 /* 550 * Send address of word we want to read. 551 */ 552 dc_eeprom_putbyte(sc, addr); 553 554 /* 555 * Start reading bits from EEPROM. 556 */ 557 for (i = 0x8000; i; i >>= 1) { 558 SIO_SET(DC_SIO_EE_CLK); 559 dc_delay(sc); 560 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 561 word |= i; 562 dc_delay(sc); 563 SIO_CLR(DC_SIO_EE_CLK); 564 dc_delay(sc); 565 } 566 567 /* Turn off EEPROM access mode. */ 568 dc_eeprom_idle(sc); 569 570 *dest = word; 571 572 return; 573} 574 575/* 576 * Read a sequence of words from the EEPROM. 577 */ 578static void 579dc_read_eeprom(sc, dest, off, cnt, swap) 580 struct dc_softc *sc; 581 caddr_t dest; 582 int off; 583 int cnt; 584 int swap; 585{ 586 int i; 587 u_int16_t word = 0, *ptr; 588 589 for (i = 0; i < cnt; i++) { 590 if (DC_IS_PNIC(sc)) 591 dc_eeprom_getword_pnic(sc, off + i, &word); 592 else if (DC_IS_XIRCOM(sc)) 593 dc_eeprom_getword_xircom(sc, off + i, &word); 594 else 595 dc_eeprom_getword(sc, off + i, &word); 596 ptr = (u_int16_t *)(dest + (i * 2)); 597 if (swap) 598 *ptr = ntohs(word); 599 else 600 *ptr = word; 601 } 602 603 return; 604} 605 606/* 607 * The following two routines are taken from the Macronix 98713 608 * Application Notes pp.19-21. 609 */ 610/* 611 * Write a bit to the MII bus. 612 */ 613static void 614dc_mii_writebit(sc, bit) 615 struct dc_softc *sc; 616 int bit; 617{ 618 if (bit) 619 CSR_WRITE_4(sc, DC_SIO, 620 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 621 else 622 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 623 624 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 625 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 626 627 return; 628} 629 630/* 631 * Read a bit from the MII bus. 632 */ 633static int 634dc_mii_readbit(sc) 635 struct dc_softc *sc; 636{ 637 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 638 CSR_READ_4(sc, DC_SIO); 639 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 640 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 641 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 642 return(1); 643 644 return(0); 645} 646 647/* 648 * Sync the PHYs by setting data bit and strobing the clock 32 times. 649 */ 650static void 651dc_mii_sync(sc) 652 struct dc_softc *sc; 653{ 654 register int i; 655 656 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 657 658 for (i = 0; i < 32; i++) 659 dc_mii_writebit(sc, 1); 660 661 return; 662} 663 664/* 665 * Clock a series of bits through the MII. 666 */ 667static void 668dc_mii_send(sc, bits, cnt) 669 struct dc_softc *sc; 670 u_int32_t bits; 671 int cnt; 672{ 673 int i; 674 675 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 676 dc_mii_writebit(sc, bits & i); 677} 678 679/* 680 * Read an PHY register through the MII. 681 */ 682static int 683dc_mii_readreg(sc, frame) 684 struct dc_softc *sc; 685 struct dc_mii_frame *frame; 686 687{ 688 int i, ack; 689 690 DC_LOCK(sc); 691 692 /* 693 * Set up frame for RX. 694 */ 695 frame->mii_stdelim = DC_MII_STARTDELIM; 696 frame->mii_opcode = DC_MII_READOP; 697 frame->mii_turnaround = 0; 698 frame->mii_data = 0; 699 700 /* 701 * Sync the PHYs. 702 */ 703 dc_mii_sync(sc); 704 705 /* 706 * Send command/address info. 707 */ 708 dc_mii_send(sc, frame->mii_stdelim, 2); 709 dc_mii_send(sc, frame->mii_opcode, 2); 710 dc_mii_send(sc, frame->mii_phyaddr, 5); 711 dc_mii_send(sc, frame->mii_regaddr, 5); 712 713#ifdef notdef 714 /* Idle bit */ 715 dc_mii_writebit(sc, 1); 716 dc_mii_writebit(sc, 0); 717#endif 718 719 /* Check for ack */ 720 ack = dc_mii_readbit(sc); 721 722 /* 723 * Now try reading data bits. If the ack failed, we still 724 * need to clock through 16 cycles to keep the PHY(s) in sync. 725 */ 726 if (ack) { 727 for(i = 0; i < 16; i++) { 728 dc_mii_readbit(sc); 729 } 730 goto fail; 731 } 732 733 for (i = 0x8000; i; i >>= 1) { 734 if (!ack) { 735 if (dc_mii_readbit(sc)) 736 frame->mii_data |= i; 737 } 738 } 739 740fail: 741 742 dc_mii_writebit(sc, 0); 743 dc_mii_writebit(sc, 0); 744 745 DC_UNLOCK(sc); 746 747 if (ack) 748 return(1); 749 return(0); 750} 751 752/* 753 * Write to a PHY register through the MII. 754 */ 755static int 756dc_mii_writereg(sc, frame) 757 struct dc_softc *sc; 758 struct dc_mii_frame *frame; 759 760{ 761 DC_LOCK(sc); 762 /* 763 * Set up frame for TX. 764 */ 765 766 frame->mii_stdelim = DC_MII_STARTDELIM; 767 frame->mii_opcode = DC_MII_WRITEOP; 768 frame->mii_turnaround = DC_MII_TURNAROUND; 769 770 /* 771 * Sync the PHYs. 772 */ 773 dc_mii_sync(sc); 774 775 dc_mii_send(sc, frame->mii_stdelim, 2); 776 dc_mii_send(sc, frame->mii_opcode, 2); 777 dc_mii_send(sc, frame->mii_phyaddr, 5); 778 dc_mii_send(sc, frame->mii_regaddr, 5); 779 dc_mii_send(sc, frame->mii_turnaround, 2); 780 dc_mii_send(sc, frame->mii_data, 16); 781 782 /* Idle bit. */ 783 dc_mii_writebit(sc, 0); 784 dc_mii_writebit(sc, 0); 785 786 DC_UNLOCK(sc); 787 788 return(0); 789} 790 791static int 792dc_miibus_readreg(dev, phy, reg) 793 device_t dev; 794 int phy, reg; 795{ 796 struct dc_mii_frame frame; 797 struct dc_softc *sc; 798 int i, rval, phy_reg = 0; 799 800 sc = device_get_softc(dev); 801 bzero((char *)&frame, sizeof(frame)); 802 803 /* 804 * Note: both the AL981 and AN985 have internal PHYs, 805 * however the AL981 provides direct access to the PHY 806 * registers while the AN985 uses a serial MII interface. 807 * The AN985's MII interface is also buggy in that you 808 * can read from any MII address (0 to 31), but only address 1 809 * behaves normally. To deal with both cases, we pretend 810 * that the PHY is at MII address 1. 811 */ 812 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 813 return(0); 814 815 /* 816 * Note: the ukphy probes of the RS7112 report a PHY at 817 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 818 * so we only respond to correct one. 819 */ 820 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 821 return(0); 822 823 if (sc->dc_pmode != DC_PMODE_MII) { 824 if (phy == (MII_NPHY - 1)) { 825 switch(reg) { 826 case MII_BMSR: 827 /* 828 * Fake something to make the probe 829 * code think there's a PHY here. 830 */ 831 return(BMSR_MEDIAMASK); 832 break; 833 case MII_PHYIDR1: 834 if (DC_IS_PNIC(sc)) 835 return(DC_VENDORID_LO); 836 return(DC_VENDORID_DEC); 837 break; 838 case MII_PHYIDR2: 839 if (DC_IS_PNIC(sc)) 840 return(DC_DEVICEID_82C168); 841 return(DC_DEVICEID_21143); 842 break; 843 default: 844 return(0); 845 break; 846 } 847 } else 848 return(0); 849 } 850 851 if (DC_IS_PNIC(sc)) { 852 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 853 (phy << 23) | (reg << 18)); 854 for (i = 0; i < DC_TIMEOUT; i++) { 855 DELAY(1); 856 rval = CSR_READ_4(sc, DC_PN_MII); 857 if (!(rval & DC_PN_MII_BUSY)) { 858 rval &= 0xFFFF; 859 return(rval == 0xFFFF ? 0 : rval); 860 } 861 } 862 return(0); 863 } 864 865 if (DC_IS_COMET(sc)) { 866 switch(reg) { 867 case MII_BMCR: 868 phy_reg = DC_AL_BMCR; 869 break; 870 case MII_BMSR: 871 phy_reg = DC_AL_BMSR; 872 break; 873 case MII_PHYIDR1: 874 phy_reg = DC_AL_VENID; 875 break; 876 case MII_PHYIDR2: 877 phy_reg = DC_AL_DEVID; 878 break; 879 case MII_ANAR: 880 phy_reg = DC_AL_ANAR; 881 break; 882 case MII_ANLPAR: 883 phy_reg = DC_AL_LPAR; 884 break; 885 case MII_ANER: 886 phy_reg = DC_AL_ANER; 887 break; 888 default: 889 printf("dc%d: phy_read: bad phy register %x\n", 890 sc->dc_unit, reg); 891 return(0); 892 break; 893 } 894 895 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 896 897 if (rval == 0xFFFF) 898 return(0); 899 return(rval); 900 } 901 902 frame.mii_phyaddr = phy; 903 frame.mii_regaddr = reg; 904 if (sc->dc_type == DC_TYPE_98713) { 905 phy_reg = CSR_READ_4(sc, DC_NETCFG); 906 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 907 } 908 dc_mii_readreg(sc, &frame); 909 if (sc->dc_type == DC_TYPE_98713) 910 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 911 912 return(frame.mii_data); 913} 914 915static int 916dc_miibus_writereg(dev, phy, reg, data) 917 device_t dev; 918 int phy, reg, data; 919{ 920 struct dc_softc *sc; 921 struct dc_mii_frame frame; 922 int i, phy_reg = 0; 923 924 sc = device_get_softc(dev); 925 bzero((char *)&frame, sizeof(frame)); 926 927 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 928 return(0); 929 930 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 931 return(0); 932 933 if (DC_IS_PNIC(sc)) { 934 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 935 (phy << 23) | (reg << 10) | data); 936 for (i = 0; i < DC_TIMEOUT; i++) { 937 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 938 break; 939 } 940 return(0); 941 } 942 943 if (DC_IS_COMET(sc)) { 944 switch(reg) { 945 case MII_BMCR: 946 phy_reg = DC_AL_BMCR; 947 break; 948 case MII_BMSR: 949 phy_reg = DC_AL_BMSR; 950 break; 951 case MII_PHYIDR1: 952 phy_reg = DC_AL_VENID; 953 break; 954 case MII_PHYIDR2: 955 phy_reg = DC_AL_DEVID; 956 break; 957 case MII_ANAR: 958 phy_reg = DC_AL_ANAR; 959 break; 960 case MII_ANLPAR: 961 phy_reg = DC_AL_LPAR; 962 break; 963 case MII_ANER: 964 phy_reg = DC_AL_ANER; 965 break; 966 default: 967 printf("dc%d: phy_write: bad phy register %x\n", 968 sc->dc_unit, reg); 969 return(0); 970 break; 971 } 972 973 CSR_WRITE_4(sc, phy_reg, data); 974 return(0); 975 } 976 977 frame.mii_phyaddr = phy; 978 frame.mii_regaddr = reg; 979 frame.mii_data = data; 980 981 if (sc->dc_type == DC_TYPE_98713) { 982 phy_reg = CSR_READ_4(sc, DC_NETCFG); 983 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 984 } 985 dc_mii_writereg(sc, &frame); 986 if (sc->dc_type == DC_TYPE_98713) 987 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 988 989 return(0); 990} 991 992static void 993dc_miibus_statchg(dev) 994 device_t dev; 995{ 996 struct dc_softc *sc; 997 struct mii_data *mii; 998 struct ifmedia *ifm; 999 1000 sc = device_get_softc(dev); 1001 if (DC_IS_ADMTEK(sc)) 1002 return; 1003 1004 mii = device_get_softc(sc->dc_miibus); 1005 ifm = &mii->mii_media; 1006 if (DC_IS_DAVICOM(sc) && 1007 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 1008 dc_setcfg(sc, ifm->ifm_media); 1009 sc->dc_if_media = ifm->ifm_media; 1010 } else { 1011 dc_setcfg(sc, mii->mii_media_active); 1012 sc->dc_if_media = mii->mii_media_active; 1013 } 1014 1015 return; 1016} 1017 1018/* 1019 * Special support for DM9102A cards with HomePNA PHYs. Note: 1020 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 1021 * to be impossible to talk to the management interface of the DM9801 1022 * PHY (its MDIO pin is not connected to anything). Consequently, 1023 * the driver has to just 'know' about the additional mode and deal 1024 * with it itself. *sigh* 1025 */ 1026static void 1027dc_miibus_mediainit(dev) 1028 device_t dev; 1029{ 1030 struct dc_softc *sc; 1031 struct mii_data *mii; 1032 struct ifmedia *ifm; 1033 int rev; 1034 1035 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1036 1037 sc = device_get_softc(dev); 1038 mii = device_get_softc(sc->dc_miibus); 1039 ifm = &mii->mii_media; 1040 1041 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1042 ifmedia_add(ifm, IFM_ETHER|IFM_HPNA_1, 0, NULL); 1043 1044 return; 1045} 1046 1047#define DC_POLY 0xEDB88320 1048#define DC_BITS_512 9 1049#define DC_BITS_128 7 1050#define DC_BITS_64 6 1051 1052static u_int32_t 1053dc_crc_le(sc, addr) 1054 struct dc_softc *sc; 1055 caddr_t addr; 1056{ 1057 u_int32_t idx, bit, data, crc; 1058 1059 /* Compute CRC for the address value. */ 1060 crc = 0xFFFFFFFF; /* initial value */ 1061 1062 for (idx = 0; idx < 6; idx++) { 1063 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1064 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 1065 } 1066 1067 /* 1068 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1069 * chips is only 128 bits wide. 1070 */ 1071 if (sc->dc_flags & DC_128BIT_HASH) 1072 return (crc & ((1 << DC_BITS_128) - 1)); 1073 1074 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1075 if (sc->dc_flags & DC_64BIT_HASH) 1076 return (crc & ((1 << DC_BITS_64) - 1)); 1077 1078 /* Xircom's hash filtering table is different (read: weird) */ 1079 /* Xircom uses the LEAST significant bits */ 1080 if (DC_IS_XIRCOM(sc)) { 1081 if ((crc & 0x180) == 0x180) 1082 return (crc & 0x0F) + (crc & 0x70)*3 + (14 << 4); 1083 else 1084 return (crc & 0x1F) + ((crc>>1) & 0xF0)*3 + (12 << 4); 1085 } 1086 1087 return (crc & ((1 << DC_BITS_512) - 1)); 1088} 1089 1090/* 1091 * Calculate CRC of a multicast group address, return the lower 6 bits. 1092 */ 1093static u_int32_t 1094dc_crc_be(addr) 1095 caddr_t addr; 1096{ 1097 u_int32_t crc, carry; 1098 int i, j; 1099 u_int8_t c; 1100 1101 /* Compute CRC for the address value. */ 1102 crc = 0xFFFFFFFF; /* initial value */ 1103 1104 for (i = 0; i < 6; i++) { 1105 c = *(addr + i); 1106 for (j = 0; j < 8; j++) { 1107 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 1108 crc <<= 1; 1109 c >>= 1; 1110 if (carry) 1111 crc = (crc ^ 0x04c11db6) | carry; 1112 } 1113 } 1114 1115 /* return the filter bit position */ 1116 return((crc >> 26) & 0x0000003F); 1117} 1118 1119/* 1120 * 21143-style RX filter setup routine. Filter programming is done by 1121 * downloading a special setup frame into the TX engine. 21143, Macronix, 1122 * PNIC, PNIC II and Davicom chips are programmed this way. 1123 * 1124 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1125 * address (our node address) and a 512-bit hash filter for multicast 1126 * frames. We also sneak the broadcast address into the hash filter since 1127 * we need that too. 1128 */ 1129void 1130dc_setfilt_21143(sc) 1131 struct dc_softc *sc; 1132{ 1133 struct dc_desc *sframe; 1134 u_int32_t h, *sp; 1135 struct ifmultiaddr *ifma; 1136 struct ifnet *ifp; 1137 int i; 1138 1139 ifp = &sc->arpcom.ac_if; 1140 1141 i = sc->dc_cdata.dc_tx_prod; 1142 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1143 sc->dc_cdata.dc_tx_cnt++; 1144 sframe = &sc->dc_ldata->dc_tx_list[i]; 1145 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1146 bzero((char *)sp, DC_SFRAME_LEN); 1147 1148 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1149 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1150 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1151 1152 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1153 1154 /* If we want promiscuous mode, set the allframes bit. */ 1155 if (ifp->if_flags & IFF_PROMISC) 1156 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1157 else 1158 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1159 1160 if (ifp->if_flags & IFF_ALLMULTI) 1161 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1162 else 1163 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1164 1165 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1166 if (ifma->ifma_addr->sa_family != AF_LINK) 1167 continue; 1168 h = dc_crc_le(sc, 1169 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1170 sp[h >> 4] |= 1 << (h & 0xF); 1171 } 1172 1173 if (ifp->if_flags & IFF_BROADCAST) { 1174 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1175 sp[h >> 4] |= 1 << (h & 0xF); 1176 } 1177 1178 /* Set our MAC address */ 1179 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1180 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1181 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1182 1183 sframe->dc_status = DC_TXSTAT_OWN; 1184 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1185 1186 /* 1187 * The PNIC takes an exceedingly long time to process its 1188 * setup frame; wait 10ms after posting the setup frame 1189 * before proceeding, just so it has time to swallow its 1190 * medicine. 1191 */ 1192 DELAY(10000); 1193 1194 ifp->if_timer = 5; 1195 1196 return; 1197} 1198 1199void 1200dc_setfilt_admtek(sc) 1201 struct dc_softc *sc; 1202{ 1203 struct ifnet *ifp; 1204 int h = 0; 1205 u_int32_t hashes[2] = { 0, 0 }; 1206 struct ifmultiaddr *ifma; 1207 1208 ifp = &sc->arpcom.ac_if; 1209 1210 /* Init our MAC address */ 1211 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1212 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1213 1214 /* If we want promiscuous mode, set the allframes bit. */ 1215 if (ifp->if_flags & IFF_PROMISC) 1216 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1217 else 1218 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1219 1220 if (ifp->if_flags & IFF_ALLMULTI) 1221 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1222 else 1223 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1224 1225 /* first, zot all the existing hash bits */ 1226 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1227 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1228 1229 /* 1230 * If we're already in promisc or allmulti mode, we 1231 * don't have to bother programming the multicast filter. 1232 */ 1233 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1234 return; 1235 1236 /* now program new ones */ 1237 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1238 if (ifma->ifma_addr->sa_family != AF_LINK) 1239 continue; 1240 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1241 if (h < 32) 1242 hashes[0] |= (1 << h); 1243 else 1244 hashes[1] |= (1 << (h - 32)); 1245 } 1246 1247 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1248 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1249 1250 return; 1251} 1252 1253void 1254dc_setfilt_asix(sc) 1255 struct dc_softc *sc; 1256{ 1257 struct ifnet *ifp; 1258 int h = 0; 1259 u_int32_t hashes[2] = { 0, 0 }; 1260 struct ifmultiaddr *ifma; 1261 1262 ifp = &sc->arpcom.ac_if; 1263 1264 /* Init our MAC address */ 1265 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1266 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1267 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1268 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1269 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1270 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1271 1272 /* If we want promiscuous mode, set the allframes bit. */ 1273 if (ifp->if_flags & IFF_PROMISC) 1274 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1275 else 1276 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1277 1278 if (ifp->if_flags & IFF_ALLMULTI) 1279 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1280 else 1281 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1282 1283 /* 1284 * The ASIX chip has a special bit to enable reception 1285 * of broadcast frames. 1286 */ 1287 if (ifp->if_flags & IFF_BROADCAST) 1288 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1289 else 1290 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1291 1292 /* first, zot all the existing hash bits */ 1293 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1294 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1295 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1296 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1297 1298 /* 1299 * If we're already in promisc or allmulti mode, we 1300 * don't have to bother programming the multicast filter. 1301 */ 1302 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1303 return; 1304 1305 /* now program new ones */ 1306 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1307 if (ifma->ifma_addr->sa_family != AF_LINK) 1308 continue; 1309 h = dc_crc_be(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1310 if (h < 32) 1311 hashes[0] |= (1 << h); 1312 else 1313 hashes[1] |= (1 << (h - 32)); 1314 } 1315 1316 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1317 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1318 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1319 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1320 1321 return; 1322} 1323 1324void 1325dc_setfilt_xircom(sc) 1326 struct dc_softc *sc; 1327{ 1328 struct dc_desc *sframe; 1329 u_int32_t h, *sp; 1330 struct ifmultiaddr *ifma; 1331 struct ifnet *ifp; 1332 int i; 1333 1334 ifp = &sc->arpcom.ac_if; 1335 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1336 1337 i = sc->dc_cdata.dc_tx_prod; 1338 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1339 sc->dc_cdata.dc_tx_cnt++; 1340 sframe = &sc->dc_ldata->dc_tx_list[i]; 1341 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1342 bzero((char *)sp, DC_SFRAME_LEN); 1343 1344 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1345 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1346 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1347 1348 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1349 1350 /* If we want promiscuous mode, set the allframes bit. */ 1351 if (ifp->if_flags & IFF_PROMISC) 1352 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1353 else 1354 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1355 1356 if (ifp->if_flags & IFF_ALLMULTI) 1357 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1358 else 1359 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1360 1361 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1362 if (ifma->ifma_addr->sa_family != AF_LINK) 1363 continue; 1364 h = dc_crc_le(sc, 1365 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1366 sp[h >> 4] |= 1 << (h & 0xF); 1367 } 1368 1369 if (ifp->if_flags & IFF_BROADCAST) { 1370 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr); 1371 sp[h >> 4] |= 1 << (h & 0xF); 1372 } 1373 1374 /* Set our MAC address */ 1375 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1376 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1377 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1378 1379 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1381 ifp->if_flags |= IFF_RUNNING; 1382 sframe->dc_status = DC_TXSTAT_OWN; 1383 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1384 1385 /* 1386 * wait some time... 1387 */ 1388 DELAY(1000); 1389 1390 ifp->if_timer = 5; 1391 1392 return; 1393} 1394 1395static void 1396dc_setfilt(sc) 1397 struct dc_softc *sc; 1398{ 1399 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1400 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1401 dc_setfilt_21143(sc); 1402 1403 if (DC_IS_ASIX(sc)) 1404 dc_setfilt_asix(sc); 1405 1406 if (DC_IS_ADMTEK(sc)) 1407 dc_setfilt_admtek(sc); 1408 1409 if (DC_IS_XIRCOM(sc)) 1410 dc_setfilt_xircom(sc); 1411 1412 return; 1413} 1414 1415/* 1416 * In order to fiddle with the 1417 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1418 * first have to put the transmit and/or receive logic in the idle state. 1419 */ 1420static void 1421dc_setcfg(sc, media) 1422 struct dc_softc *sc; 1423 int media; 1424{ 1425 int i, restart = 0; 1426 u_int32_t isr; 1427 1428 if (IFM_SUBTYPE(media) == IFM_NONE) 1429 return; 1430 1431 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1432 restart = 1; 1433 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1434 1435 for (i = 0; i < DC_TIMEOUT; i++) { 1436 isr = CSR_READ_4(sc, DC_ISR); 1437 if (isr & DC_ISR_TX_IDLE && 1438 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1439 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1440 break; 1441 DELAY(10); 1442 } 1443 1444 if (i == DC_TIMEOUT) 1445 printf("dc%d: failed to force tx and " 1446 "rx to idle state\n", sc->dc_unit); 1447 } 1448 1449 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1450 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1451 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1452 if (sc->dc_pmode == DC_PMODE_MII) { 1453 int watchdogreg; 1454 1455 if (DC_IS_INTEL(sc)) { 1456 /* there's a write enable bit here that reads as 1 */ 1457 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1458 watchdogreg &= ~DC_WDOG_CTLWREN; 1459 watchdogreg |= DC_WDOG_JABBERDIS; 1460 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1461 } else { 1462 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1463 } 1464 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1465 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1466 if (sc->dc_type == DC_TYPE_98713) 1467 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1468 DC_NETCFG_SCRAMBLER)); 1469 if (!DC_IS_DAVICOM(sc)) 1470 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1471 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1472 if (DC_IS_INTEL(sc)) 1473 dc_apply_fixup(sc, IFM_AUTO); 1474 } else { 1475 if (DC_IS_PNIC(sc)) { 1476 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1477 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1478 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1479 } 1480 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1481 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1482 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1483 if (DC_IS_INTEL(sc)) 1484 dc_apply_fixup(sc, 1485 (media & IFM_GMASK) == IFM_FDX ? 1486 IFM_100_TX|IFM_FDX : IFM_100_TX); 1487 } 1488 } 1489 1490 if (IFM_SUBTYPE(media) == IFM_10_T) { 1491 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1492 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1493 if (sc->dc_pmode == DC_PMODE_MII) { 1494 int watchdogreg; 1495 1496 /* there's a write enable bit here that reads as 1 */ 1497 if (DC_IS_INTEL(sc)) { 1498 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1499 watchdogreg &= ~DC_WDOG_CTLWREN; 1500 watchdogreg |= DC_WDOG_JABBERDIS; 1501 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1502 } else { 1503 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1504 } 1505 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1506 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1507 if (sc->dc_type == DC_TYPE_98713) 1508 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1509 if (!DC_IS_DAVICOM(sc)) 1510 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1511 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1512 if (DC_IS_INTEL(sc)) 1513 dc_apply_fixup(sc, IFM_AUTO); 1514 } else { 1515 if (DC_IS_PNIC(sc)) { 1516 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1517 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1518 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1519 } 1520 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1521 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1522 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1523 if (DC_IS_INTEL(sc)) { 1524 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1525 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1526 if ((media & IFM_GMASK) == IFM_FDX) 1527 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1528 else 1529 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1530 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1531 DC_CLRBIT(sc, DC_10BTCTRL, 1532 DC_TCTL_AUTONEGENBL); 1533 dc_apply_fixup(sc, 1534 (media & IFM_GMASK) == IFM_FDX ? 1535 IFM_10_T|IFM_FDX : IFM_10_T); 1536 DELAY(20000); 1537 } 1538 } 1539 } 1540 1541 /* 1542 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1543 * PHY and we want HomePNA mode, set the portsel bit to turn 1544 * on the external MII port. 1545 */ 1546 if (DC_IS_DAVICOM(sc)) { 1547 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1548 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1549 sc->dc_link = 1; 1550 } else { 1551 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1552 } 1553 } 1554 1555 if (DC_IS_ADMTEK(sc)) 1556 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 1557 1558 if ((media & IFM_GMASK) == IFM_FDX) { 1559 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1560 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1561 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1562 } else { 1563 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1564 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1565 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1566 } 1567 1568 if (restart) 1569 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1570 1571 return; 1572} 1573 1574static void 1575dc_reset(sc) 1576 struct dc_softc *sc; 1577{ 1578 register int i; 1579 1580 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1581 1582 for (i = 0; i < DC_TIMEOUT; i++) { 1583 DELAY(10); 1584 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1585 break; 1586 } 1587 1588 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc) || 1589 DC_IS_XIRCOM(sc) || DC_IS_INTEL(sc)) { 1590 DELAY(10000); 1591 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1592 i = 0; 1593 } 1594 1595 if (i == DC_TIMEOUT) 1596 printf("dc%d: reset never completed!\n", sc->dc_unit); 1597 1598 /* Wait a little while for the chip to get its brains in order. */ 1599 DELAY(1000); 1600 1601 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1602 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1603 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1604 1605 /* 1606 * Bring the SIA out of reset. In some cases, it looks 1607 * like failing to unreset the SIA soon enough gets it 1608 * into a state where it will never come out of reset 1609 * until we reset the whole chip again. 1610 */ 1611 if (DC_IS_INTEL(sc)) { 1612 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1613 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1614 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1615 } 1616 1617 return; 1618} 1619 1620static struct dc_type * 1621dc_devtype(dev) 1622 device_t dev; 1623{ 1624 struct dc_type *t; 1625 u_int32_t rev; 1626 1627 t = dc_devs; 1628 1629 while(t->dc_name != NULL) { 1630 if ((pci_get_vendor(dev) == t->dc_vid) && 1631 (pci_get_device(dev) == t->dc_did)) { 1632 /* Check the PCI revision */ 1633 rev = pci_read_config(dev, DC_PCI_CFRV, 4) & 0xFF; 1634 if (t->dc_did == DC_DEVICEID_98713 && 1635 rev >= DC_REVISION_98713A) 1636 t++; 1637 if (t->dc_did == DC_DEVICEID_98713_CP && 1638 rev >= DC_REVISION_98713A) 1639 t++; 1640 if (t->dc_did == DC_DEVICEID_987x5 && 1641 rev >= DC_REVISION_98715AEC_C) 1642 t++; 1643 if (t->dc_did == DC_DEVICEID_987x5 && 1644 rev >= DC_REVISION_98725) 1645 t++; 1646 if (t->dc_did == DC_DEVICEID_AX88140A && 1647 rev >= DC_REVISION_88141) 1648 t++; 1649 if (t->dc_did == DC_DEVICEID_82C168 && 1650 rev >= DC_REVISION_82C169) 1651 t++; 1652 if (t->dc_did == DC_DEVICEID_DM9102 && 1653 rev >= DC_REVISION_DM9102A) 1654 t++; 1655 return(t); 1656 } 1657 t++; 1658 } 1659 1660 return(NULL); 1661} 1662 1663/* 1664 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1665 * IDs against our list and return a device name if we find a match. 1666 * We do a little bit of extra work to identify the exact type of 1667 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1668 * but different revision IDs. The same is true for 98715/98715A 1669 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1670 * cases, the exact chip revision affects driver behavior. 1671 */ 1672static int 1673dc_probe(dev) 1674 device_t dev; 1675{ 1676 struct dc_type *t; 1677 1678 t = dc_devtype(dev); 1679 1680 if (t != NULL) { 1681 device_set_desc(dev, t->dc_name); 1682 return(0); 1683 } 1684 1685 return(ENXIO); 1686} 1687 1688static void 1689dc_acpi(dev) 1690 device_t dev; 1691{ 1692 int unit; 1693 1694 unit = device_get_unit(dev); 1695 1696 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1697 u_int32_t iobase, membase, irq; 1698 1699 /* Save important PCI config data. */ 1700 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1701 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1702 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1703 1704 /* Reset the power state. */ 1705 printf("dc%d: chip is in D%d power mode " 1706 "-- setting to D0\n", unit, 1707 pci_get_powerstate(dev)); 1708 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1709 1710 /* Restore PCI config data. */ 1711 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1712 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1713 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1714 } 1715 1716 return; 1717} 1718 1719static void 1720dc_apply_fixup(sc, media) 1721 struct dc_softc *sc; 1722 int media; 1723{ 1724 struct dc_mediainfo *m; 1725 u_int8_t *p; 1726 int i; 1727 u_int32_t reg; 1728 1729 m = sc->dc_mi; 1730 1731 while (m != NULL) { 1732 if (m->dc_media == media) 1733 break; 1734 m = m->dc_next; 1735 } 1736 1737 if (m == NULL) 1738 return; 1739 1740 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1741 reg = (p[0] | (p[1] << 8)) << 16; 1742 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1743 } 1744 1745 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1746 reg = (p[0] | (p[1] << 8)) << 16; 1747 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1748 } 1749 1750 return; 1751} 1752 1753static void 1754dc_decode_leaf_sia(sc, l) 1755 struct dc_softc *sc; 1756 struct dc_eblock_sia *l; 1757{ 1758 struct dc_mediainfo *m; 1759 1760 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1761 bzero(m, sizeof(struct dc_mediainfo)); 1762 if (l->dc_sia_code == DC_SIA_CODE_10BT) 1763 m->dc_media = IFM_10_T; 1764 1765 if (l->dc_sia_code == DC_SIA_CODE_10BT_FDX) 1766 m->dc_media = IFM_10_T|IFM_FDX; 1767 1768 if (l->dc_sia_code == DC_SIA_CODE_10B2) 1769 m->dc_media = IFM_10_2; 1770 1771 if (l->dc_sia_code == DC_SIA_CODE_10B5) 1772 m->dc_media = IFM_10_5; 1773 1774 m->dc_gp_len = 2; 1775 m->dc_gp_ptr = (u_int8_t *)&l->dc_sia_gpio_ctl; 1776 1777 m->dc_next = sc->dc_mi; 1778 sc->dc_mi = m; 1779 1780 sc->dc_pmode = DC_PMODE_SIA; 1781 1782 return; 1783} 1784 1785static void 1786dc_decode_leaf_sym(sc, l) 1787 struct dc_softc *sc; 1788 struct dc_eblock_sym *l; 1789{ 1790 struct dc_mediainfo *m; 1791 1792 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1793 bzero(m, sizeof(struct dc_mediainfo)); 1794 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1795 m->dc_media = IFM_100_TX; 1796 1797 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1798 m->dc_media = IFM_100_TX|IFM_FDX; 1799 1800 m->dc_gp_len = 2; 1801 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1802 1803 m->dc_next = sc->dc_mi; 1804 sc->dc_mi = m; 1805 1806 sc->dc_pmode = DC_PMODE_SYM; 1807 1808 return; 1809} 1810 1811static void 1812dc_decode_leaf_mii(sc, l) 1813 struct dc_softc *sc; 1814 struct dc_eblock_mii *l; 1815{ 1816 u_int8_t *p; 1817 struct dc_mediainfo *m; 1818 1819 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_NOWAIT); 1820 bzero(m, sizeof(struct dc_mediainfo)); 1821 /* We abuse IFM_AUTO to represent MII. */ 1822 m->dc_media = IFM_AUTO; 1823 m->dc_gp_len = l->dc_gpr_len; 1824 1825 p = (u_int8_t *)l; 1826 p += sizeof(struct dc_eblock_mii); 1827 m->dc_gp_ptr = p; 1828 p += 2 * l->dc_gpr_len; 1829 m->dc_reset_len = *p; 1830 p++; 1831 m->dc_reset_ptr = p; 1832 1833 m->dc_next = sc->dc_mi; 1834 sc->dc_mi = m; 1835 1836 return; 1837} 1838 1839void dc_read_srom(sc, bits) 1840 struct dc_softc *sc; 1841 int bits; 1842{ 1843 int size; 1844 1845 size = 2 << bits; 1846 sc->dc_srom = malloc(size, M_DEVBUF, M_NOWAIT); 1847 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1848} 1849 1850static void 1851dc_parse_21143_srom(sc) 1852 struct dc_softc *sc; 1853{ 1854 struct dc_leaf_hdr *lhdr; 1855 struct dc_eblock_hdr *hdr; 1856 int i, loff; 1857 char *ptr; 1858 1859 loff = sc->dc_srom[27]; 1860 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1861 1862 ptr = (char *)lhdr; 1863 ptr += sizeof(struct dc_leaf_hdr) - 1; 1864 for (i = 0; i < lhdr->dc_mcnt; i++) { 1865 hdr = (struct dc_eblock_hdr *)ptr; 1866 switch(hdr->dc_type) { 1867 case DC_EBLOCK_MII: 1868 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1869 break; 1870 case DC_EBLOCK_SIA: 1871 dc_decode_leaf_sia(sc, (struct dc_eblock_sia *)hdr); 1872 break; 1873 case DC_EBLOCK_SYM: 1874 dc_decode_leaf_sym(sc, (struct dc_eblock_sym *)hdr); 1875 break; 1876 default: 1877 /* Don't care. Yet. */ 1878 break; 1879 } 1880 ptr += (hdr->dc_len & 0x7F); 1881 ptr++; 1882 } 1883 1884 return; 1885} 1886 1887/* 1888 * Attach the interface. Allocate softc structures, do ifmedia 1889 * setup and ethernet/BPF attach. 1890 */ 1891static int 1892dc_attach(dev) 1893 device_t dev; 1894{ 1895 int tmp = 0; 1896 u_char eaddr[ETHER_ADDR_LEN]; 1897 u_int32_t command; 1898 struct dc_softc *sc; 1899 struct ifnet *ifp; 1900 u_int32_t revision; 1901 int unit, error = 0, rid, mac_offset; 1902 1903 sc = device_get_softc(dev); 1904 unit = device_get_unit(dev); 1905 bzero(sc, sizeof(struct dc_softc)); 1906 1907 mtx_init(&sc->dc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1908 MTX_DEF | MTX_RECURSE); 1909 1910 /* 1911 * Handle power management nonsense. 1912 */ 1913 dc_acpi(dev); 1914 1915 /* 1916 * Map control/status registers. 1917 */ 1918 pci_enable_busmaster(dev); 1919 pci_enable_io(dev, SYS_RES_IOPORT); 1920 pci_enable_io(dev, SYS_RES_MEMORY); 1921 command = pci_read_config(dev, PCIR_COMMAND, 4); 1922 1923#ifdef DC_USEIOSPACE 1924 if (!(command & PCIM_CMD_PORTEN)) { 1925 printf("dc%d: failed to enable I/O ports!\n", unit); 1926 error = ENXIO; 1927 goto fail_nolock; 1928 } 1929#else 1930 if (!(command & PCIM_CMD_MEMEN)) { 1931 printf("dc%d: failed to enable memory mapping!\n", unit); 1932 error = ENXIO; 1933 goto fail_nolock; 1934 } 1935#endif 1936 1937 rid = DC_RID; 1938 sc->dc_res = bus_alloc_resource(dev, DC_RES, &rid, 1939 0, ~0, 1, RF_ACTIVE); 1940 1941 if (sc->dc_res == NULL) { 1942 printf("dc%d: couldn't map ports/memory\n", unit); 1943 error = ENXIO; 1944 goto fail_nolock; 1945 } 1946 1947 sc->dc_btag = rman_get_bustag(sc->dc_res); 1948 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1949 1950 /* Allocate interrupt */ 1951 rid = 0; 1952 sc->dc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1953 RF_SHAREABLE | RF_ACTIVE); 1954 1955 if (sc->dc_irq == NULL) { 1956 printf("dc%d: couldn't map interrupt\n", unit); 1957 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1958 error = ENXIO; 1959 goto fail_nolock; 1960 } 1961 1962 error = bus_setup_intr(dev, sc->dc_irq, INTR_TYPE_NET | 1963 (IS_MPSAFE ? INTR_MPSAFE : 0), 1964 dc_intr, sc, &sc->dc_intrhand); 1965 1966 if (error) { 1967 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 1968 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 1969 printf("dc%d: couldn't set up irq\n", unit); 1970 goto fail_nolock; 1971 } 1972 DC_LOCK(sc); 1973 1974 /* Need this info to decide on a chip type. */ 1975 sc->dc_info = dc_devtype(dev); 1976 revision = pci_read_config(dev, DC_PCI_CFRV, 4) & 0x000000FF; 1977 1978 switch(sc->dc_info->dc_did) { 1979 case DC_DEVICEID_21143: 1980 sc->dc_type = DC_TYPE_21143; 1981 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1982 sc->dc_flags |= DC_REDUCED_MII_POLL; 1983 /* Save EEPROM contents so we can parse them later. */ 1984 dc_eeprom_width(sc); 1985 dc_read_srom(sc, sc->dc_romwidth); 1986 break; 1987 case DC_DEVICEID_DM9100: 1988 case DC_DEVICEID_DM9102: 1989 sc->dc_type = DC_TYPE_DM9102; 1990 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1991 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1992 sc->dc_pmode = DC_PMODE_MII; 1993 /* Increase the latency timer value. */ 1994 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1995 command &= 0xFFFF00FF; 1996 command |= 0x00008000; 1997 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1998 break; 1999 case DC_DEVICEID_AL981: 2000 sc->dc_type = DC_TYPE_AL981; 2001 sc->dc_flags |= DC_TX_USE_TX_INTR; 2002 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2003 sc->dc_pmode = DC_PMODE_MII; 2004 dc_eeprom_width(sc); 2005 dc_read_srom(sc, sc->dc_romwidth); 2006 break; 2007 case DC_DEVICEID_AN985: 2008 case DC_DEVICEID_FE2500: 2009 case DC_DEVICEID_EN2242: 2010 sc->dc_type = DC_TYPE_AN985; 2011 sc->dc_flags |= DC_TX_USE_TX_INTR; 2012 sc->dc_flags |= DC_TX_ADMTEK_WAR; 2013 sc->dc_pmode = DC_PMODE_MII; 2014 dc_eeprom_width(sc); 2015 dc_read_srom(sc, sc->dc_romwidth); 2016 break; 2017 case DC_DEVICEID_98713: 2018 case DC_DEVICEID_98713_CP: 2019 if (revision < DC_REVISION_98713A) { 2020 sc->dc_type = DC_TYPE_98713; 2021 } 2022 if (revision >= DC_REVISION_98713A) { 2023 sc->dc_type = DC_TYPE_98713A; 2024 sc->dc_flags |= DC_21143_NWAY; 2025 } 2026 sc->dc_flags |= DC_REDUCED_MII_POLL; 2027 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2028 break; 2029 case DC_DEVICEID_987x5: 2030 case DC_DEVICEID_EN1217: 2031 /* 2032 * Macronix MX98715AEC-C/D/E parts have only a 2033 * 128-bit hash table. We need to deal with these 2034 * in the same manner as the PNIC II so that we 2035 * get the right number of bits out of the 2036 * CRC routine. 2037 */ 2038 if (revision >= DC_REVISION_98715AEC_C && 2039 revision < DC_REVISION_98725) 2040 sc->dc_flags |= DC_128BIT_HASH; 2041 sc->dc_type = DC_TYPE_987x5; 2042 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2043 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2044 break; 2045 case DC_DEVICEID_98727: 2046 sc->dc_type = DC_TYPE_987x5; 2047 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 2048 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2049 break; 2050 case DC_DEVICEID_82C115: 2051 sc->dc_type = DC_TYPE_PNICII; 2052 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 2053 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 2054 break; 2055 case DC_DEVICEID_82C168: 2056 sc->dc_type = DC_TYPE_PNIC; 2057 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 2058 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 2059 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_NOWAIT); 2060 if (revision < DC_REVISION_82C169) 2061 sc->dc_pmode = DC_PMODE_SYM; 2062 break; 2063 case DC_DEVICEID_AX88140A: 2064 sc->dc_type = DC_TYPE_ASIX; 2065 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 2066 sc->dc_flags |= DC_REDUCED_MII_POLL; 2067 sc->dc_pmode = DC_PMODE_MII; 2068 break; 2069 case DC_DEVICEID_X3201: 2070 sc->dc_type = DC_TYPE_XIRCOM; 2071 sc->dc_flags |= DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 2072 DC_TX_ALIGN; 2073 /* 2074 * We don't actually need to coalesce, but we're doing 2075 * it to obtain a double word aligned buffer. 2076 * The DC_TX_COALESCE flag is required. 2077 */ 2078 sc->dc_pmode = DC_PMODE_MII; 2079 /* XXX Call the cardbus function to get nic from the CIS */ 2080 break; 2081 case DC_DEVICEID_RS7112: 2082 sc->dc_type = DC_TYPE_CONEXANT; 2083 sc->dc_flags |= DC_TX_INTR_ALWAYS; 2084 sc->dc_flags |= DC_REDUCED_MII_POLL; 2085 sc->dc_pmode = DC_PMODE_MII; 2086 dc_eeprom_width(sc); 2087 dc_read_srom(sc, sc->dc_romwidth); 2088 break; 2089 default: 2090 printf("dc%d: unknown device: %x\n", sc->dc_unit, 2091 sc->dc_info->dc_did); 2092 break; 2093 } 2094 2095 /* Save the cache line size. */ 2096 if (DC_IS_DAVICOM(sc)) 2097 sc->dc_cachesize = 0; 2098 else 2099 sc->dc_cachesize = pci_read_config(dev, 2100 DC_PCI_CFLT, 4) & 0xFF; 2101 2102 /* Reset the adapter. */ 2103 dc_reset(sc); 2104 2105 /* Take 21143 out of snooze mode */ 2106 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2107 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2108 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2109 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2110 } 2111 2112 /* 2113 * Try to learn something about the supported media. 2114 * We know that ASIX and ADMtek and Davicom devices 2115 * will *always* be using MII media, so that's a no-brainer. 2116 * The tricky ones are the Macronix/PNIC II and the 2117 * Intel 21143. 2118 */ 2119 if (DC_IS_INTEL(sc)) 2120 dc_parse_21143_srom(sc); 2121 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2122 if (sc->dc_type == DC_TYPE_98713) 2123 sc->dc_pmode = DC_PMODE_MII; 2124 else 2125 sc->dc_pmode = DC_PMODE_SYM; 2126 } else if (!sc->dc_pmode) 2127 sc->dc_pmode = DC_PMODE_MII; 2128 2129 /* 2130 * Get station address from the EEPROM. 2131 */ 2132 switch(sc->dc_type) { 2133 case DC_TYPE_98713: 2134 case DC_TYPE_98713A: 2135 case DC_TYPE_987x5: 2136 case DC_TYPE_PNICII: 2137 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2138 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2139 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2140 break; 2141 case DC_TYPE_PNIC: 2142 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2143 break; 2144 case DC_TYPE_DM9102: 2145 case DC_TYPE_21143: 2146 case DC_TYPE_ASIX: 2147 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2148 break; 2149 case DC_TYPE_AL981: 2150 case DC_TYPE_AN985: 2151 bcopy(&sc->dc_srom[DC_AL_EE_NODEADDR], (caddr_t)&eaddr, 2152 ETHER_ADDR_LEN); 2153 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_AL_EE_NODEADDR, 3, 0); 2154 break; 2155 case DC_TYPE_CONEXANT: 2156 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2157 break; 2158 case DC_TYPE_XIRCOM: 2159 2160 break; 2161 default: 2162 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2163 break; 2164 } 2165 2166 /* 2167 * A 21143 or clone chip was detected. Inform the world. 2168 */ 2169 printf("dc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 2170 2171 sc->dc_unit = unit; 2172 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 2173 2174 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2175 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 2176 2177 if (sc->dc_ldata == NULL) { 2178 printf("dc%d: no memory for list buffers!\n", unit); 2179 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2180 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2181 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2182 error = ENXIO; 2183 goto fail; 2184 } 2185 2186 bzero(sc->dc_ldata, sizeof(struct dc_list_data)); 2187 2188 ifp = &sc->arpcom.ac_if; 2189 ifp->if_softc = sc; 2190 ifp->if_unit = unit; 2191 ifp->if_name = "dc"; 2192 /* XXX: bleah, MTU gets overwritten in ether_ifattach() */ 2193 ifp->if_mtu = ETHERMTU; 2194 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2195 ifp->if_ioctl = dc_ioctl; 2196 ifp->if_output = ether_output; 2197 ifp->if_start = dc_start; 2198 ifp->if_watchdog = dc_watchdog; 2199 ifp->if_init = dc_init; 2200 ifp->if_baudrate = 10000000; 2201 ifp->if_snd.ifq_maxlen = DC_TX_LIST_CNT - 1; 2202 2203 /* 2204 * Do MII setup. If this is a 21143, check for a PHY on the 2205 * MII bus after applying any necessary fixups to twiddle the 2206 * GPIO bits. If we don't end up finding a PHY, restore the 2207 * old selection (SIA only or SIA/SYM) and attach the dcphy 2208 * driver instead. 2209 */ 2210 if (DC_IS_INTEL(sc)) { 2211 dc_apply_fixup(sc, IFM_AUTO); 2212 tmp = sc->dc_pmode; 2213 sc->dc_pmode = DC_PMODE_MII; 2214 } 2215 2216 error = mii_phy_probe(dev, &sc->dc_miibus, 2217 dc_ifmedia_upd, dc_ifmedia_sts); 2218 2219 if (error && DC_IS_INTEL(sc)) { 2220 sc->dc_pmode = tmp; 2221 if (sc->dc_pmode != DC_PMODE_SIA) 2222 sc->dc_pmode = DC_PMODE_SYM; 2223 sc->dc_flags |= DC_21143_NWAY; 2224 mii_phy_probe(dev, &sc->dc_miibus, 2225 dc_ifmedia_upd, dc_ifmedia_sts); 2226 /* 2227 * For non-MII cards, we need to have the 21143 2228 * drive the LEDs. Except there are some systems 2229 * like the NEC VersaPro NoteBook PC which have no 2230 * LEDs, and twiddling these bits has adverse effects 2231 * on them. (I.e. you suddenly can't get a link.) 2232 */ 2233 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2234 sc->dc_flags |= DC_TULIP_LEDS; 2235 error = 0; 2236 } 2237 2238 if (error) { 2239 printf("dc%d: MII without any PHY!\n", sc->dc_unit); 2240 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2241 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2242 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2243 error = ENXIO; 2244 goto fail; 2245 } 2246 2247 if (DC_IS_XIRCOM(sc)) { 2248 /* 2249 * setup General Purpose Port mode and data so the tulip 2250 * can talk to the MII. 2251 */ 2252 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2253 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2254 DELAY(10); 2255 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2256 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2257 DELAY(10); 2258 } 2259 2260 /* 2261 * Call MI attach routine. 2262 */ 2263 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 2264 2265 /* 2266 * Tell the upper layer(s) we support long frames. 2267 */ 2268 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2269 2270 callout_init(&sc->dc_stat_ch, IS_MPSAFE); 2271 2272#ifdef SRM_MEDIA 2273 sc->dc_srm_media = 0; 2274 2275 /* Remember the SRM console media setting */ 2276 if (DC_IS_INTEL(sc)) { 2277 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2278 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2279 switch ((command >> 8) & 0xff) { 2280 case 3: 2281 sc->dc_srm_media = IFM_10_T; 2282 break; 2283 case 4: 2284 sc->dc_srm_media = IFM_10_T | IFM_FDX; 2285 break; 2286 case 5: 2287 sc->dc_srm_media = IFM_100_TX; 2288 break; 2289 case 6: 2290 sc->dc_srm_media = IFM_100_TX | IFM_FDX; 2291 break; 2292 } 2293 if (sc->dc_srm_media) 2294 sc->dc_srm_media |= IFM_ACTIVE | IFM_ETHER; 2295 } 2296#endif 2297 2298 DC_UNLOCK(sc); 2299 return(0); 2300 2301fail: 2302 DC_UNLOCK(sc); 2303fail_nolock: 2304 mtx_destroy(&sc->dc_mtx); 2305 return(error); 2306} 2307 2308static int 2309dc_detach(dev) 2310 device_t dev; 2311{ 2312 struct dc_softc *sc; 2313 struct ifnet *ifp; 2314 struct dc_mediainfo *m; 2315 2316 sc = device_get_softc(dev); 2317 2318 DC_LOCK(sc); 2319 2320 ifp = &sc->arpcom.ac_if; 2321 2322 dc_stop(sc); 2323 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 2324 2325 bus_generic_detach(dev); 2326 device_delete_child(dev, sc->dc_miibus); 2327 2328 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2329 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2330 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2331 2332 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2333 if (sc->dc_pnic_rx_buf != NULL) 2334 free(sc->dc_pnic_rx_buf, M_DEVBUF); 2335 2336 while(sc->dc_mi != NULL) { 2337 m = sc->dc_mi->dc_next; 2338 free(sc->dc_mi, M_DEVBUF); 2339 sc->dc_mi = m; 2340 } 2341 free(sc->dc_srom, M_DEVBUF); 2342 2343 DC_UNLOCK(sc); 2344 mtx_destroy(&sc->dc_mtx); 2345 2346 return(0); 2347} 2348 2349/* 2350 * Initialize the transmit descriptors. 2351 */ 2352static int 2353dc_list_tx_init(sc) 2354 struct dc_softc *sc; 2355{ 2356 struct dc_chain_data *cd; 2357 struct dc_list_data *ld; 2358 int i, nexti; 2359 2360 cd = &sc->dc_cdata; 2361 ld = sc->dc_ldata; 2362 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2363 nexti = (i == (DC_TX_LIST_CNT - 1)) ? 0 : i+1; 2364 ld->dc_tx_list[i].dc_next = vtophys(&ld->dc_tx_list[nexti]); 2365 cd->dc_tx_chain[i] = NULL; 2366 ld->dc_tx_list[i].dc_data = 0; 2367 ld->dc_tx_list[i].dc_ctl = 0; 2368 } 2369 2370 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2371 2372 return(0); 2373} 2374 2375 2376/* 2377 * Initialize the RX descriptors and allocate mbufs for them. Note that 2378 * we arrange the descriptors in a closed ring, so that the last descriptor 2379 * points back to the first. 2380 */ 2381static int 2382dc_list_rx_init(sc) 2383 struct dc_softc *sc; 2384{ 2385 struct dc_chain_data *cd; 2386 struct dc_list_data *ld; 2387 int i, nexti; 2388 2389 cd = &sc->dc_cdata; 2390 ld = sc->dc_ldata; 2391 2392 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2393 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2394 return(ENOBUFS); 2395 nexti = (i == (DC_RX_LIST_CNT - 1)) ? 0 : i+1; 2396 ld->dc_rx_list[i].dc_next = vtophys(&ld->dc_rx_list[nexti]); 2397 } 2398 2399 cd->dc_rx_prod = 0; 2400 2401 return(0); 2402} 2403 2404/* 2405 * Initialize an RX descriptor and attach an MBUF cluster. 2406 */ 2407static int 2408dc_newbuf(sc, i, m) 2409 struct dc_softc *sc; 2410 int i; 2411 struct mbuf *m; 2412{ 2413 struct mbuf *m_new = NULL; 2414 struct dc_desc *c; 2415 2416 c = &sc->dc_ldata->dc_rx_list[i]; 2417 2418 if (m == NULL) { 2419 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2420 if (m_new == NULL) 2421 return(ENOBUFS); 2422 2423 MCLGET(m_new, M_DONTWAIT); 2424 if (!(m_new->m_flags & M_EXT)) { 2425 m_freem(m_new); 2426 return(ENOBUFS); 2427 } 2428 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2429 } else { 2430 m_new = m; 2431 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2432 m_new->m_data = m_new->m_ext.ext_buf; 2433 } 2434 2435 m_adj(m_new, sizeof(u_int64_t)); 2436 2437 /* 2438 * If this is a PNIC chip, zero the buffer. This is part 2439 * of the workaround for the receive bug in the 82c168 and 2440 * 82c169 chips. 2441 */ 2442 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2443 bzero((char *)mtod(m_new, char *), m_new->m_len); 2444 2445 sc->dc_cdata.dc_rx_chain[i] = m_new; 2446 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2447 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2448 c->dc_status = DC_RXSTAT_OWN; 2449 2450 return(0); 2451} 2452 2453/* 2454 * Grrrrr. 2455 * The PNIC chip has a terrible bug in it that manifests itself during 2456 * periods of heavy activity. The exact mode of failure if difficult to 2457 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2458 * will happen on slow machines. The bug is that sometimes instead of 2459 * uploading one complete frame during reception, it uploads what looks 2460 * like the entire contents of its FIFO memory. The frame we want is at 2461 * the end of the whole mess, but we never know exactly how much data has 2462 * been uploaded, so salvaging the frame is hard. 2463 * 2464 * There is only one way to do it reliably, and it's disgusting. 2465 * Here's what we know: 2466 * 2467 * - We know there will always be somewhere between one and three extra 2468 * descriptors uploaded. 2469 * 2470 * - We know the desired received frame will always be at the end of the 2471 * total data upload. 2472 * 2473 * - We know the size of the desired received frame because it will be 2474 * provided in the length field of the status word in the last descriptor. 2475 * 2476 * Here's what we do: 2477 * 2478 * - When we allocate buffers for the receive ring, we bzero() them. 2479 * This means that we know that the buffer contents should be all 2480 * zeros, except for data uploaded by the chip. 2481 * 2482 * - We also force the PNIC chip to upload frames that include the 2483 * ethernet CRC at the end. 2484 * 2485 * - We gather all of the bogus frame data into a single buffer. 2486 * 2487 * - We then position a pointer at the end of this buffer and scan 2488 * backwards until we encounter the first non-zero byte of data. 2489 * This is the end of the received frame. We know we will encounter 2490 * some data at the end of the frame because the CRC will always be 2491 * there, so even if the sender transmits a packet of all zeros, 2492 * we won't be fooled. 2493 * 2494 * - We know the size of the actual received frame, so we subtract 2495 * that value from the current pointer location. This brings us 2496 * to the start of the actual received packet. 2497 * 2498 * - We copy this into an mbuf and pass it on, along with the actual 2499 * frame length. 2500 * 2501 * The performance hit is tremendous, but it beats dropping frames all 2502 * the time. 2503 */ 2504 2505#define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2506static void 2507dc_pnic_rx_bug_war(sc, idx) 2508 struct dc_softc *sc; 2509 int idx; 2510{ 2511 struct dc_desc *cur_rx; 2512 struct dc_desc *c = NULL; 2513 struct mbuf *m = NULL; 2514 unsigned char *ptr; 2515 int i, total_len; 2516 u_int32_t rxstat = 0; 2517 2518 i = sc->dc_pnic_rx_bug_save; 2519 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2520 ptr = sc->dc_pnic_rx_buf; 2521 bzero(ptr, sizeof(DC_RXLEN * 5)); 2522 2523 /* Copy all the bytes from the bogus buffers. */ 2524 while (1) { 2525 c = &sc->dc_ldata->dc_rx_list[i]; 2526 rxstat = c->dc_status; 2527 m = sc->dc_cdata.dc_rx_chain[i]; 2528 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2529 ptr += DC_RXLEN; 2530 /* If this is the last buffer, break out. */ 2531 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2532 break; 2533 dc_newbuf(sc, i, m); 2534 DC_INC(i, DC_RX_LIST_CNT); 2535 } 2536 2537 /* Find the length of the actual receive frame. */ 2538 total_len = DC_RXBYTES(rxstat); 2539 2540 /* Scan backwards until we hit a non-zero byte. */ 2541 while(*ptr == 0x00) 2542 ptr--; 2543 2544 /* Round off. */ 2545 if ((uintptr_t)(ptr) & 0x3) 2546 ptr -= 1; 2547 2548 /* Now find the start of the frame. */ 2549 ptr -= total_len; 2550 if (ptr < sc->dc_pnic_rx_buf) 2551 ptr = sc->dc_pnic_rx_buf; 2552 2553 /* 2554 * Now copy the salvaged frame to the last mbuf and fake up 2555 * the status word to make it look like a successful 2556 * frame reception. 2557 */ 2558 dc_newbuf(sc, i, m); 2559 bcopy(ptr, mtod(m, char *), total_len); 2560 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2561 2562 return; 2563} 2564 2565/* 2566 * This routine searches the RX ring for dirty descriptors in the 2567 * event that the rxeof routine falls out of sync with the chip's 2568 * current descriptor pointer. This may happen sometimes as a result 2569 * of a "no RX buffer available" condition that happens when the chip 2570 * consumes all of the RX buffers before the driver has a chance to 2571 * process the RX ring. This routine may need to be called more than 2572 * once to bring the driver back in sync with the chip, however we 2573 * should still be getting RX DONE interrupts to drive the search 2574 * for new packets in the RX ring, so we should catch up eventually. 2575 */ 2576static int 2577dc_rx_resync(sc) 2578 struct dc_softc *sc; 2579{ 2580 int i, pos; 2581 struct dc_desc *cur_rx; 2582 2583 pos = sc->dc_cdata.dc_rx_prod; 2584 2585 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2586 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2587 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2588 break; 2589 DC_INC(pos, DC_RX_LIST_CNT); 2590 } 2591 2592 /* If the ring really is empty, then just return. */ 2593 if (i == DC_RX_LIST_CNT) 2594 return(0); 2595 2596 /* We've fallen behing the chip: catch it. */ 2597 sc->dc_cdata.dc_rx_prod = pos; 2598 2599 return(EAGAIN); 2600} 2601 2602/* 2603 * A frame has been uploaded: pass the resulting mbuf chain up to 2604 * the higher level protocols. 2605 */ 2606static void 2607dc_rxeof(sc) 2608 struct dc_softc *sc; 2609{ 2610 struct ether_header *eh; 2611 struct mbuf *m; 2612 struct ifnet *ifp; 2613 struct dc_desc *cur_rx; 2614 int i, total_len = 0; 2615 u_int32_t rxstat; 2616 2617 ifp = &sc->arpcom.ac_if; 2618 i = sc->dc_cdata.dc_rx_prod; 2619 2620 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2621 2622#ifdef DEVICE_POLLING 2623 if (ifp->if_flags & IFF_POLLING) { 2624 if (sc->rxcycles <= 0) 2625 break; 2626 sc->rxcycles--; 2627 } 2628#endif /* DEVICE_POLLING */ 2629 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2630 rxstat = cur_rx->dc_status; 2631 m = sc->dc_cdata.dc_rx_chain[i]; 2632 total_len = DC_RXBYTES(rxstat); 2633 2634 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2635 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2636 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2637 sc->dc_pnic_rx_bug_save = i; 2638 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2639 DC_INC(i, DC_RX_LIST_CNT); 2640 continue; 2641 } 2642 dc_pnic_rx_bug_war(sc, i); 2643 rxstat = cur_rx->dc_status; 2644 total_len = DC_RXBYTES(rxstat); 2645 } 2646 } 2647 2648 sc->dc_cdata.dc_rx_chain[i] = NULL; 2649 2650 /* 2651 * If an error occurs, update stats, clear the 2652 * status word and leave the mbuf cluster in place: 2653 * it should simply get re-used next time this descriptor 2654 * comes up in the ring. However, don't report long 2655 * frames as errors since they could be vlans 2656 */ 2657 if ((rxstat & DC_RXSTAT_RXERR)){ 2658 if (!(rxstat & DC_RXSTAT_GIANT) || 2659 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2660 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2661 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2662 ifp->if_ierrors++; 2663 if (rxstat & DC_RXSTAT_COLLSEEN) 2664 ifp->if_collisions++; 2665 dc_newbuf(sc, i, m); 2666 if (rxstat & DC_RXSTAT_CRCERR) { 2667 DC_INC(i, DC_RX_LIST_CNT); 2668 continue; 2669 } else { 2670 dc_init(sc); 2671 return; 2672 } 2673 } 2674 } 2675 2676 /* No errors; receive the packet. */ 2677 total_len -= ETHER_CRC_LEN; 2678#ifdef __i386__ 2679 /* 2680 * On the x86 we do not have alignment problems, so try to 2681 * allocate a new buffer for the receive ring, and pass up 2682 * the one where the packet is already, saving the expensive 2683 * copy done in m_devget(). 2684 * If we are on an architecture with alignment problems, or 2685 * if the allocation fails, then use m_devget and leave the 2686 * existing buffer in the receive ring. 2687 */ 2688 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2689 m->m_pkthdr.rcvif = ifp; 2690 m->m_pkthdr.len = m->m_len = total_len; 2691 DC_INC(i, DC_RX_LIST_CNT); 2692 } else 2693#endif 2694 { 2695 struct mbuf *m0; 2696 2697 m0 = m_devget(mtod(m, char *), total_len, 2698 ETHER_ALIGN, ifp, NULL); 2699 dc_newbuf(sc, i, m); 2700 DC_INC(i, DC_RX_LIST_CNT); 2701 if (m0 == NULL) { 2702 ifp->if_ierrors++; 2703 continue; 2704 } 2705 m = m0; 2706 } 2707 2708 ifp->if_ipackets++; 2709 eh = mtod(m, struct ether_header *); 2710 2711 /* Remove header from mbuf and pass it on. */ 2712 m_adj(m, sizeof(struct ether_header)); 2713 ether_input(ifp, eh, m); 2714 } 2715 2716 sc->dc_cdata.dc_rx_prod = i; 2717} 2718 2719/* 2720 * A frame was downloaded to the chip. It's safe for us to clean up 2721 * the list buffers. 2722 */ 2723 2724static void 2725dc_txeof(sc) 2726 struct dc_softc *sc; 2727{ 2728 struct dc_desc *cur_tx = NULL; 2729 struct ifnet *ifp; 2730 int idx; 2731 2732 ifp = &sc->arpcom.ac_if; 2733 2734 /* 2735 * Go through our tx list and free mbufs for those 2736 * frames that have been transmitted. 2737 */ 2738 idx = sc->dc_cdata.dc_tx_cons; 2739 while(idx != sc->dc_cdata.dc_tx_prod) { 2740 u_int32_t txstat; 2741 2742 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2743 txstat = cur_tx->dc_status; 2744 2745 if (txstat & DC_TXSTAT_OWN) 2746 break; 2747 2748 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2749 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2750 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2751 /* 2752 * Yes, the PNIC is so brain damaged 2753 * that it will sometimes generate a TX 2754 * underrun error while DMAing the RX 2755 * filter setup frame. If we detect this, 2756 * we have to send the setup frame again, 2757 * or else the filter won't be programmed 2758 * correctly. 2759 */ 2760 if (DC_IS_PNIC(sc)) { 2761 if (txstat & DC_TXSTAT_ERRSUM) 2762 dc_setfilt(sc); 2763 } 2764 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2765 } 2766 sc->dc_cdata.dc_tx_cnt--; 2767 DC_INC(idx, DC_TX_LIST_CNT); 2768 continue; 2769 } 2770 2771 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2772 /* 2773 * XXX: Why does my Xircom taunt me so? 2774 * For some reason it likes setting the CARRLOST flag 2775 * even when the carrier is there. wtf?!? 2776 * Who knows, but Conexant chips have the 2777 * same problem. Maybe they took lessons 2778 * from Xircom. 2779 */ 2780 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2781 sc->dc_pmode == DC_PMODE_MII && 2782 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2783 DC_TXSTAT_NOCARRIER))) 2784 txstat &= ~DC_TXSTAT_ERRSUM; 2785 } else { 2786 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2787 sc->dc_pmode == DC_PMODE_MII && 2788 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2789 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2790 txstat &= ~DC_TXSTAT_ERRSUM; 2791 } 2792 2793 if (txstat & DC_TXSTAT_ERRSUM) { 2794 ifp->if_oerrors++; 2795 if (txstat & DC_TXSTAT_EXCESSCOLL) 2796 ifp->if_collisions++; 2797 if (txstat & DC_TXSTAT_LATECOLL) 2798 ifp->if_collisions++; 2799 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2800 dc_init(sc); 2801 return; 2802 } 2803 } 2804 2805 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3; 2806 2807 ifp->if_opackets++; 2808 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2809 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2810 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2811 } 2812 2813 sc->dc_cdata.dc_tx_cnt--; 2814 DC_INC(idx, DC_TX_LIST_CNT); 2815 } 2816 2817 if (idx != sc->dc_cdata.dc_tx_cons) { 2818 /* some buffers have been freed */ 2819 sc->dc_cdata.dc_tx_cons = idx; 2820 ifp->if_flags &= ~IFF_OACTIVE; 2821 } 2822 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2823 2824 return; 2825} 2826 2827static void 2828dc_tick(xsc) 2829 void *xsc; 2830{ 2831 struct dc_softc *sc; 2832 struct mii_data *mii; 2833 struct ifnet *ifp; 2834 u_int32_t r; 2835 2836 sc = xsc; 2837 DC_LOCK(sc); 2838 ifp = &sc->arpcom.ac_if; 2839 mii = device_get_softc(sc->dc_miibus); 2840 2841 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2842 if (sc->dc_flags & DC_21143_NWAY) { 2843 r = CSR_READ_4(sc, DC_10BTSTAT); 2844 if (IFM_SUBTYPE(mii->mii_media_active) == 2845 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2846 sc->dc_link = 0; 2847 mii_mediachg(mii); 2848 } 2849 if (IFM_SUBTYPE(mii->mii_media_active) == 2850 IFM_10_T && (r & DC_TSTAT_LS10)) { 2851 sc->dc_link = 0; 2852 mii_mediachg(mii); 2853 } 2854 if (sc->dc_link == 0) 2855 mii_tick(mii); 2856 } else { 2857 r = CSR_READ_4(sc, DC_ISR); 2858 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2859 sc->dc_cdata.dc_tx_cnt == 0) 2860 mii_tick(mii); 2861 if (!(mii->mii_media_status & IFM_ACTIVE)) 2862 sc->dc_link = 0; 2863 } 2864 } else 2865 mii_tick(mii); 2866 2867 /* 2868 * When the init routine completes, we expect to be able to send 2869 * packets right away, and in fact the network code will send a 2870 * gratuitous ARP the moment the init routine marks the interface 2871 * as running. However, even though the MAC may have been initialized, 2872 * there may be a delay of a few seconds before the PHY completes 2873 * autonegotiation and the link is brought up. Any transmissions 2874 * made during that delay will be lost. Dealing with this is tricky: 2875 * we can't just pause in the init routine while waiting for the 2876 * PHY to come ready since that would bring the whole system to 2877 * a screeching halt for several seconds. 2878 * 2879 * What we do here is prevent the TX start routine from sending 2880 * any packets until a link has been established. After the 2881 * interface has been initialized, the tick routine will poll 2882 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2883 * that time, packets will stay in the send queue, and once the 2884 * link comes up, they will be flushed out to the wire. 2885 */ 2886 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE && 2887 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2888 sc->dc_link++; 2889 if (ifp->if_snd.ifq_head != NULL) 2890 dc_start(ifp); 2891 } 2892 2893 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2894 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 2895 else 2896 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 2897 2898 DC_UNLOCK(sc); 2899 2900 return; 2901} 2902 2903/* 2904 * A transmit underrun has occurred. Back off the transmit threshold, 2905 * or switch to store and forward mode if we have to. 2906 */ 2907static void 2908dc_tx_underrun(sc) 2909 struct dc_softc *sc; 2910{ 2911 u_int32_t isr; 2912 int i; 2913 2914 if (DC_IS_DAVICOM(sc)) 2915 dc_init(sc); 2916 2917 if (DC_IS_INTEL(sc)) { 2918 /* 2919 * The real 21143 requires that the transmitter be idle 2920 * in order to change the transmit threshold or store 2921 * and forward state. 2922 */ 2923 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2924 2925 for (i = 0; i < DC_TIMEOUT; i++) { 2926 isr = CSR_READ_4(sc, DC_ISR); 2927 if (isr & DC_ISR_TX_IDLE) 2928 break; 2929 DELAY(10); 2930 } 2931 if (i == DC_TIMEOUT) { 2932 printf("dc%d: failed to force tx to idle state\n", 2933 sc->dc_unit); 2934 dc_init(sc); 2935 } 2936 } 2937 2938 printf("dc%d: TX underrun -- ", sc->dc_unit); 2939 sc->dc_txthresh += DC_TXTHRESH_INC; 2940 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2941 printf("using store and forward mode\n"); 2942 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2943 } else { 2944 printf("increasing TX threshold\n"); 2945 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2946 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2947 } 2948 2949 if (DC_IS_INTEL(sc)) 2950 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2951 2952 return; 2953} 2954 2955#ifdef DEVICE_POLLING 2956static poll_handler_t dc_poll; 2957 2958static void 2959dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2960{ 2961 struct dc_softc *sc = ifp->if_softc; 2962 2963 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 2964 /* Re-enable interrupts. */ 2965 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2966 return; 2967 } 2968 sc->rxcycles = count; 2969 dc_rxeof(sc); 2970 dc_txeof(sc); 2971 if (ifp->if_snd.ifq_head != NULL && !(ifp->if_flags & IFF_OACTIVE)) 2972 dc_start(ifp); 2973 2974 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2975 u_int32_t status; 2976 2977 status = CSR_READ_4(sc, DC_ISR); 2978 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2979 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2980 DC_ISR_BUS_ERR); 2981 if (!status) 2982 return; 2983 /* ack what we have */ 2984 CSR_WRITE_4(sc, DC_ISR, status); 2985 2986 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF)) { 2987 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2988 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff); 2989 2990 if (dc_rx_resync(sc)) 2991 dc_rxeof(sc); 2992 } 2993 /* restart transmit unit if necessary */ 2994 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2995 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2996 2997 if (status & DC_ISR_TX_UNDERRUN) 2998 dc_tx_underrun(sc); 2999 3000 if (status & DC_ISR_BUS_ERR) { 3001 printf("dc_poll: dc%d bus error\n", sc->dc_unit); 3002 dc_reset(sc); 3003 dc_init(sc); 3004 } 3005 } 3006} 3007#endif /* DEVICE_POLLING */ 3008 3009static void 3010dc_intr(arg) 3011 void *arg; 3012{ 3013 struct dc_softc *sc; 3014 struct ifnet *ifp; 3015 u_int32_t status; 3016 3017 sc = arg; 3018 3019 if (sc->suspended) { 3020 return; 3021 } 3022 3023 if ((CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 3024 return; 3025 3026 DC_LOCK(sc); 3027 ifp = &sc->arpcom.ac_if; 3028#ifdef DEVICE_POLLING 3029 if (ifp->if_flags & IFF_POLLING) 3030 goto done; 3031 if (ether_poll_register(dc_poll, ifp)) { /* ok, disable interrupts */ 3032 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3033 goto done; 3034 } 3035#endif /* DEVICE_POLLING */ 3036 3037 /* Suppress unwanted interrupts */ 3038 if (!(ifp->if_flags & IFF_UP)) { 3039 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 3040 dc_stop(sc); 3041 DC_UNLOCK(sc); 3042 return; 3043 } 3044 3045 /* Disable interrupts. */ 3046 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3047 3048 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) 3049 && status != 0xFFFFFFFF) { 3050 3051 CSR_WRITE_4(sc, DC_ISR, status); 3052 3053 if (status & DC_ISR_RX_OK) { 3054 int curpkts; 3055 curpkts = ifp->if_ipackets; 3056 dc_rxeof(sc); 3057 if (curpkts == ifp->if_ipackets) { 3058 while(dc_rx_resync(sc)) 3059 dc_rxeof(sc); 3060 } 3061 } 3062 3063 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 3064 dc_txeof(sc); 3065 3066 if (status & DC_ISR_TX_IDLE) { 3067 dc_txeof(sc); 3068 if (sc->dc_cdata.dc_tx_cnt) { 3069 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3070 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3071 } 3072 } 3073 3074 if (status & DC_ISR_TX_UNDERRUN) 3075 dc_tx_underrun(sc); 3076 3077 if ((status & DC_ISR_RX_WATDOGTIMEO) 3078 || (status & DC_ISR_RX_NOBUF)) { 3079 int curpkts; 3080 curpkts = ifp->if_ipackets; 3081 dc_rxeof(sc); 3082 if (curpkts == ifp->if_ipackets) { 3083 while(dc_rx_resync(sc)) 3084 dc_rxeof(sc); 3085 } 3086 } 3087 3088 if (status & DC_ISR_BUS_ERR) { 3089 dc_reset(sc); 3090 dc_init(sc); 3091 } 3092 } 3093 3094 /* Re-enable interrupts. */ 3095 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3096 3097 if (ifp->if_snd.ifq_head != NULL) 3098 dc_start(ifp); 3099 3100#ifdef DEVICE_POLLING 3101done: 3102#endif /* DEVICE_POLLING */ 3103 3104 DC_UNLOCK(sc); 3105 3106 return; 3107} 3108 3109/* 3110 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3111 * pointers to the fragment pointers. 3112 */ 3113static int 3114dc_encap(sc, m_head, txidx) 3115 struct dc_softc *sc; 3116 struct mbuf *m_head; 3117 u_int32_t *txidx; 3118{ 3119 struct dc_desc *f = NULL; 3120 struct mbuf *m; 3121 int frag, cur, cnt = 0; 3122 3123 /* 3124 * Start packing the mbufs in this chain into 3125 * the fragment pointers. Stop when we run out 3126 * of fragments or hit the end of the mbuf chain. 3127 */ 3128 m = m_head; 3129 cur = frag = *txidx; 3130 3131 for (m = m_head; m != NULL; m = m->m_next) { 3132 if (m->m_len != 0) { 3133 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3134 if (*txidx != sc->dc_cdata.dc_tx_prod && 3135 frag == (DC_TX_LIST_CNT - 1)) 3136 return(ENOBUFS); 3137 } 3138 if ((DC_TX_LIST_CNT - 3139 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3140 return(ENOBUFS); 3141 3142 f = &sc->dc_ldata->dc_tx_list[frag]; 3143 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3144 if (cnt == 0) { 3145 f->dc_status = 0; 3146 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3147 } else 3148 f->dc_status = DC_TXSTAT_OWN; 3149 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3150 cur = frag; 3151 DC_INC(frag, DC_TX_LIST_CNT); 3152 cnt++; 3153 } 3154 } 3155 3156 if (m != NULL) 3157 return(ENOBUFS); 3158 3159 sc->dc_cdata.dc_tx_cnt += cnt; 3160 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3161 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3162 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3163 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3164 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3165 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3166 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3167 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3168 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3169 *txidx = frag; 3170 3171 return(0); 3172} 3173 3174/* 3175 * Coalesce an mbuf chain into a single mbuf cluster buffer. 3176 * Needed for some really badly behaved chips that just can't 3177 * do scatter/gather correctly. 3178 */ 3179static int 3180dc_coal(sc, m_head) 3181 struct dc_softc *sc; 3182 struct mbuf **m_head; 3183{ 3184 struct mbuf *m_new, *m; 3185 3186 m = *m_head; 3187 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3188 if (m_new == NULL) 3189 return(ENOBUFS); 3190 if (m->m_pkthdr.len > MHLEN) { 3191 MCLGET(m_new, M_DONTWAIT); 3192 if (!(m_new->m_flags & M_EXT)) { 3193 m_freem(m_new); 3194 return(ENOBUFS); 3195 } 3196 } 3197 m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, caddr_t)); 3198 m_new->m_pkthdr.len = m_new->m_len = m->m_pkthdr.len; 3199 m_freem(m); 3200 *m_head = m_new; 3201 3202 return(0); 3203} 3204 3205/* 3206 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3207 * to the mbuf data regions directly in the transmit lists. We also save a 3208 * copy of the pointers since the transmit list fragment pointers are 3209 * physical addresses. 3210 */ 3211 3212static void 3213dc_start(ifp) 3214 struct ifnet *ifp; 3215{ 3216 struct dc_softc *sc; 3217 struct mbuf *m_head = NULL; 3218 int idx; 3219 3220 sc = ifp->if_softc; 3221 3222 DC_LOCK(sc); 3223 3224 if (!sc->dc_link && ifp->if_snd.ifq_len < 10) { 3225 DC_UNLOCK(sc); 3226 return; 3227 } 3228 3229 if (ifp->if_flags & IFF_OACTIVE) { 3230 DC_UNLOCK(sc); 3231 return; 3232 } 3233 3234 idx = sc->dc_cdata.dc_tx_prod; 3235 3236 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3237 IF_DEQUEUE(&ifp->if_snd, m_head); 3238 if (m_head == NULL) 3239 break; 3240 3241 if (sc->dc_flags & DC_TX_COALESCE && 3242 (m_head->m_next != NULL || 3243 sc->dc_flags & DC_TX_ALIGN)) { 3244 if (dc_coal(sc, &m_head)) { 3245 IF_PREPEND(&ifp->if_snd, m_head); 3246 ifp->if_flags |= IFF_OACTIVE; 3247 break; 3248 } 3249 } 3250 3251 if (dc_encap(sc, m_head, &idx)) { 3252 IF_PREPEND(&ifp->if_snd, m_head); 3253 ifp->if_flags |= IFF_OACTIVE; 3254 break; 3255 } 3256 3257 /* 3258 * If there's a BPF listener, bounce a copy of this frame 3259 * to him. 3260 */ 3261 if (ifp->if_bpf) 3262 bpf_mtap(ifp, m_head); 3263 3264 if (sc->dc_flags & DC_TX_ONE) { 3265 ifp->if_flags |= IFF_OACTIVE; 3266 break; 3267 } 3268 } 3269 3270 /* Transmit */ 3271 sc->dc_cdata.dc_tx_prod = idx; 3272 if (!(sc->dc_flags & DC_TX_POLL)) 3273 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3274 3275 /* 3276 * Set a timeout in case the chip goes out to lunch. 3277 */ 3278 ifp->if_timer = 5; 3279 3280 DC_UNLOCK(sc); 3281 3282 return; 3283} 3284 3285static void 3286dc_init(xsc) 3287 void *xsc; 3288{ 3289 struct dc_softc *sc = xsc; 3290 struct ifnet *ifp = &sc->arpcom.ac_if; 3291 struct mii_data *mii; 3292 3293 DC_LOCK(sc); 3294 3295 mii = device_get_softc(sc->dc_miibus); 3296 3297 /* 3298 * Cancel pending I/O and free all RX/TX buffers. 3299 */ 3300 dc_stop(sc); 3301 dc_reset(sc); 3302 3303 /* 3304 * Set cache alignment and burst length. 3305 */ 3306 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3307 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3308 else 3309 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3310 /* 3311 * Evenly share the bus between receive and transmit process. 3312 */ 3313 if (DC_IS_INTEL(sc)) 3314 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3315 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3316 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3317 } else { 3318 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3319 } 3320 if (sc->dc_flags & DC_TX_POLL) 3321 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3322 switch(sc->dc_cachesize) { 3323 case 32: 3324 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3325 break; 3326 case 16: 3327 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3328 break; 3329 case 8: 3330 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3331 break; 3332 case 0: 3333 default: 3334 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3335 break; 3336 } 3337 3338 if (sc->dc_flags & DC_TX_STORENFWD) 3339 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3340 else { 3341 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3342 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3343 } else { 3344 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3345 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3346 } 3347 } 3348 3349 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3350 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3351 3352 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3353 /* 3354 * The app notes for the 98713 and 98715A say that 3355 * in order to have the chips operate properly, a magic 3356 * number must be written to CSR16. Macronix does not 3357 * document the meaning of these bits so there's no way 3358 * to know exactly what they do. The 98713 has a magic 3359 * number all its own; the rest all use a different one. 3360 */ 3361 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3362 if (sc->dc_type == DC_TYPE_98713) 3363 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3364 else 3365 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3366 } 3367 3368 if (DC_IS_XIRCOM(sc)) { 3369 /* 3370 * setup General Purpose Port mode and data so the tulip 3371 * can talk to the MII. 3372 */ 3373 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3374 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3375 DELAY(10); 3376 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3377 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3378 DELAY(10); 3379 } 3380 3381 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3382 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3383 3384 /* Init circular RX list. */ 3385 if (dc_list_rx_init(sc) == ENOBUFS) { 3386 printf("dc%d: initialization failed: no " 3387 "memory for rx buffers\n", sc->dc_unit); 3388 dc_stop(sc); 3389 DC_UNLOCK(sc); 3390 return; 3391 } 3392 3393 /* 3394 * Init tx descriptors. 3395 */ 3396 dc_list_tx_init(sc); 3397 3398 /* 3399 * Load the address of the RX list. 3400 */ 3401 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3402 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3403 3404 /* 3405 * Enable interrupts. 3406 */ 3407#ifdef DEVICE_POLLING 3408 /* 3409 * ... but only if we are not polling, and make sure they are off in 3410 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3411 * after a reset. 3412 */ 3413 if (ifp->if_flags & IFF_POLLING) 3414 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3415 else 3416#endif 3417 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3418 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3419 3420 /* Enable transmitter. */ 3421 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3422 3423 /* 3424 * If this is an Intel 21143 and we're not using the 3425 * MII port, program the LED control pins so we get 3426 * link and activity indications. 3427 */ 3428 if (sc->dc_flags & DC_TULIP_LEDS) { 3429 CSR_WRITE_4(sc, DC_WATCHDOG, 3430 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3431 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3432 } 3433 3434 /* 3435 * Load the RX/multicast filter. We do this sort of late 3436 * because the filter programming scheme on the 21143 and 3437 * some clones requires DMAing a setup frame via the TX 3438 * engine, and we need the transmitter enabled for that. 3439 */ 3440 dc_setfilt(sc); 3441 3442 /* Enable receiver. */ 3443 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3444 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3445 3446 mii_mediachg(mii); 3447 dc_setcfg(sc, sc->dc_if_media); 3448 3449 ifp->if_flags |= IFF_RUNNING; 3450 ifp->if_flags &= ~IFF_OACTIVE; 3451 3452 /* Don't start the ticker if this is a homePNA link. */ 3453 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3454 sc->dc_link = 1; 3455 else { 3456 if (sc->dc_flags & DC_21143_NWAY) 3457 callout_reset(&sc->dc_stat_ch, hz/10, dc_tick, sc); 3458 else 3459 callout_reset(&sc->dc_stat_ch, hz, dc_tick, sc); 3460 } 3461 3462#ifdef SRM_MEDIA 3463 if(sc->dc_srm_media) { 3464 struct ifreq ifr; 3465 3466 ifr.ifr_media = sc->dc_srm_media; 3467 ifmedia_ioctl(ifp, &ifr, &mii->mii_media, SIOCSIFMEDIA); 3468 sc->dc_srm_media = 0; 3469 } 3470#endif 3471 DC_UNLOCK(sc); 3472 return; 3473} 3474 3475/* 3476 * Set media options. 3477 */ 3478static int 3479dc_ifmedia_upd(ifp) 3480 struct ifnet *ifp; 3481{ 3482 struct dc_softc *sc; 3483 struct mii_data *mii; 3484 struct ifmedia *ifm; 3485 3486 sc = ifp->if_softc; 3487 mii = device_get_softc(sc->dc_miibus); 3488 mii_mediachg(mii); 3489 ifm = &mii->mii_media; 3490 3491 if (DC_IS_DAVICOM(sc) && 3492 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3493 dc_setcfg(sc, ifm->ifm_media); 3494 else 3495 sc->dc_link = 0; 3496 3497 return(0); 3498} 3499 3500/* 3501 * Report current media status. 3502 */ 3503static void 3504dc_ifmedia_sts(ifp, ifmr) 3505 struct ifnet *ifp; 3506 struct ifmediareq *ifmr; 3507{ 3508 struct dc_softc *sc; 3509 struct mii_data *mii; 3510 struct ifmedia *ifm; 3511 3512 sc = ifp->if_softc; 3513 mii = device_get_softc(sc->dc_miibus); 3514 mii_pollstat(mii); 3515 ifm = &mii->mii_media; 3516 if (DC_IS_DAVICOM(sc)) { 3517 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3518 ifmr->ifm_active = ifm->ifm_media; 3519 ifmr->ifm_status = 0; 3520 return; 3521 } 3522 } 3523 ifmr->ifm_active = mii->mii_media_active; 3524 ifmr->ifm_status = mii->mii_media_status; 3525 3526 return; 3527} 3528 3529static int 3530dc_ioctl(ifp, command, data) 3531 struct ifnet *ifp; 3532 u_long command; 3533 caddr_t data; 3534{ 3535 struct dc_softc *sc = ifp->if_softc; 3536 struct ifreq *ifr = (struct ifreq *) data; 3537 struct mii_data *mii; 3538 int error = 0; 3539 3540 DC_LOCK(sc); 3541 3542 switch(command) { 3543 case SIOCSIFADDR: 3544 case SIOCGIFADDR: 3545 case SIOCSIFMTU: 3546 error = ether_ioctl(ifp, command, data); 3547 break; 3548 case SIOCSIFFLAGS: 3549 if (ifp->if_flags & IFF_UP) { 3550 if (ifp->if_flags & IFF_RUNNING && 3551 ifp->if_flags & IFF_PROMISC && 3552 !(sc->dc_if_flags & IFF_PROMISC)) { 3553 dc_setfilt(sc); 3554 } else if (ifp->if_flags & IFF_RUNNING && 3555 !(ifp->if_flags & IFF_PROMISC) && 3556 sc->dc_if_flags & IFF_PROMISC) { 3557 dc_setfilt(sc); 3558 } else if (!(ifp->if_flags & IFF_RUNNING)) { 3559 sc->dc_txthresh = 0; 3560 dc_init(sc); 3561 } 3562 } else { 3563 if (ifp->if_flags & IFF_RUNNING) 3564 dc_stop(sc); 3565 } 3566 sc->dc_if_flags = ifp->if_flags; 3567 error = 0; 3568 break; 3569 case SIOCADDMULTI: 3570 case SIOCDELMULTI: 3571 dc_setfilt(sc); 3572 error = 0; 3573 break; 3574 case SIOCGIFMEDIA: 3575 case SIOCSIFMEDIA: 3576 mii = device_get_softc(sc->dc_miibus); 3577 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3578#ifdef SRM_MEDIA 3579 if (sc->dc_srm_media) 3580 sc->dc_srm_media = 0; 3581#endif 3582 break; 3583 default: 3584 error = EINVAL; 3585 break; 3586 } 3587 3588 DC_UNLOCK(sc); 3589 3590 return(error); 3591} 3592 3593static void 3594dc_watchdog(ifp) 3595 struct ifnet *ifp; 3596{ 3597 struct dc_softc *sc; 3598 3599 sc = ifp->if_softc; 3600 3601 DC_LOCK(sc); 3602 3603 ifp->if_oerrors++; 3604 printf("dc%d: watchdog timeout\n", sc->dc_unit); 3605 3606 dc_stop(sc); 3607 dc_reset(sc); 3608 dc_init(sc); 3609 3610 if (ifp->if_snd.ifq_head != NULL) 3611 dc_start(ifp); 3612 3613 DC_UNLOCK(sc); 3614 3615 return; 3616} 3617 3618/* 3619 * Stop the adapter and free any mbufs allocated to the 3620 * RX and TX lists. 3621 */ 3622static void 3623dc_stop(sc) 3624 struct dc_softc *sc; 3625{ 3626 register int i; 3627 struct ifnet *ifp; 3628 3629 DC_LOCK(sc); 3630 3631 ifp = &sc->arpcom.ac_if; 3632 ifp->if_timer = 0; 3633 3634 callout_stop(&sc->dc_stat_ch); 3635 3636 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3637#ifdef DEVICE_POLLING 3638 ether_poll_deregister(ifp); 3639#endif 3640 3641 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3642 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3643 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3644 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3645 sc->dc_link = 0; 3646 3647 /* 3648 * Free data in the RX lists. 3649 */ 3650 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3651 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3652 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3653 sc->dc_cdata.dc_rx_chain[i] = NULL; 3654 } 3655 } 3656 bzero((char *)&sc->dc_ldata->dc_rx_list, 3657 sizeof(sc->dc_ldata->dc_rx_list)); 3658 3659 /* 3660 * Free the TX list buffers. 3661 */ 3662 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3663 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3664 if (sc->dc_ldata->dc_tx_list[i].dc_ctl & 3665 DC_TXCTL_SETUP) { 3666 sc->dc_cdata.dc_tx_chain[i] = NULL; 3667 continue; 3668 } 3669 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3670 sc->dc_cdata.dc_tx_chain[i] = NULL; 3671 } 3672 } 3673 3674 bzero((char *)&sc->dc_ldata->dc_tx_list, 3675 sizeof(sc->dc_ldata->dc_tx_list)); 3676 3677 DC_UNLOCK(sc); 3678 3679 return; 3680} 3681 3682/* 3683 * Device suspend routine. Stop the interface and save some PCI 3684 * settings in case the BIOS doesn't restore them properly on 3685 * resume. 3686 */ 3687static int 3688dc_suspend(dev) 3689 device_t dev; 3690{ 3691 register int i; 3692 int s; 3693 struct dc_softc *sc; 3694 3695 s = splimp(); 3696 3697 sc = device_get_softc(dev); 3698 3699 dc_stop(sc); 3700 3701 for (i = 0; i < 5; i++) 3702 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3703 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3704 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3705 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3706 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3707 3708 sc->suspended = 1; 3709 3710 splx(s); 3711 return (0); 3712} 3713 3714/* 3715 * Device resume routine. Restore some PCI settings in case the BIOS 3716 * doesn't, re-enable busmastering, and restart the interface if 3717 * appropriate. 3718 */ 3719static int 3720dc_resume(dev) 3721 device_t dev; 3722{ 3723 register int i; 3724 int s; 3725 struct dc_softc *sc; 3726 struct ifnet *ifp; 3727 3728 s = splimp(); 3729 3730 sc = device_get_softc(dev); 3731 ifp = &sc->arpcom.ac_if; 3732 3733 dc_acpi(dev); 3734 3735 /* better way to do this? */ 3736 for (i = 0; i < 5; i++) 3737 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3738 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3739 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3740 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3741 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3742 3743 /* reenable busmastering */ 3744 pci_enable_busmaster(dev); 3745 pci_enable_io(dev, DC_RES); 3746 3747 /* reinitialize interface if necessary */ 3748 if (ifp->if_flags & IFF_UP) 3749 dc_init(sc); 3750 3751 sc->suspended = 0; 3752 3753 splx(s); 3754 return (0); 3755} 3756 3757/* 3758 * Stop all chip I/O so that the kernel's probe routines don't 3759 * get confused by errant DMAs when rebooting. 3760 */ 3761static void 3762dc_shutdown(dev) 3763 device_t dev; 3764{ 3765 struct dc_softc *sc; 3766 3767 sc = device_get_softc(dev); 3768 3769 dc_stop(sc); 3770 3771 return; 3772} 3773