t4_vf.c revision 309560
1/*- 2 * Copyright (c) 2016 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/10/sys/dev/cxgbe/t4_vf.c 309560 2016-12-05 20:43:25Z jhb $"); 30 31#include "opt_inet.h" 32#include "opt_inet6.h" 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/conf.h> 38#include <sys/counter.h> 39#include <sys/kernel.h> 40#include <sys/module.h> 41#include <sys/priv.h> 42#include <dev/pci/pcivar.h> 43#if defined(__i386__) || defined(__amd64__) 44#include <vm/vm.h> 45#include <vm/pmap.h> 46#endif 47 48#include "common/common.h" 49#include "common/t4_regs.h" 50#include "t4_ioctl.h" 51#include "t4_mp_ring.h" 52 53/* 54 * Some notes: 55 * 56 * The Virtual Interfaces are connected to an internal switch on the chip 57 * which allows VIs attached to the same port to talk to each other even when 58 * the port link is down. As a result, we might want to always report a 59 * VF's link as being "up". 60 * 61 * XXX: Add a TUNABLE and possible per-device sysctl for this? 62 */ 63 64struct intrs_and_queues { 65 uint16_t intr_type; /* MSI, or MSI-X */ 66 uint16_t nirq; /* Total # of vectors */ 67 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */ 68 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */ 69 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */ 70 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */ 71 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */ 72 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */ 73}; 74 75struct { 76 uint16_t device; 77 char *desc; 78} t4vf_pciids[] = { 79 {0x4800, "Chelsio T440-dbg VF"}, 80 {0x4801, "Chelsio T420-CR VF"}, 81 {0x4802, "Chelsio T422-CR VF"}, 82 {0x4803, "Chelsio T440-CR VF"}, 83 {0x4804, "Chelsio T420-BCH VF"}, 84 {0x4805, "Chelsio T440-BCH VF"}, 85 {0x4806, "Chelsio T440-CH VF"}, 86 {0x4807, "Chelsio T420-SO VF"}, 87 {0x4808, "Chelsio T420-CX VF"}, 88 {0x4809, "Chelsio T420-BT VF"}, 89 {0x480a, "Chelsio T404-BT VF"}, 90 {0x480e, "Chelsio T440-LP-CR VF"}, 91}, t5vf_pciids[] = { 92 {0x5800, "Chelsio T580-dbg VF"}, 93 {0x5801, "Chelsio T520-CR VF"}, /* 2 x 10G */ 94 {0x5802, "Chelsio T522-CR VF"}, /* 2 x 10G, 2 X 1G */ 95 {0x5803, "Chelsio T540-CR VF"}, /* 4 x 10G */ 96 {0x5807, "Chelsio T520-SO VF"}, /* 2 x 10G, nomem */ 97 {0x5809, "Chelsio T520-BT VF"}, /* 2 x 10GBaseT */ 98 {0x580a, "Chelsio T504-BT VF"}, /* 4 x 1G */ 99 {0x580d, "Chelsio T580-CR VF"}, /* 2 x 40G */ 100 {0x580e, "Chelsio T540-LP-CR VF"}, /* 4 x 10G */ 101 {0x5810, "Chelsio T580-LP-CR VF"}, /* 2 x 40G */ 102 {0x5811, "Chelsio T520-LL-CR VF"}, /* 2 x 10G */ 103 {0x5812, "Chelsio T560-CR VF"}, /* 1 x 40G, 2 x 10G */ 104 {0x5814, "Chelsio T580-LP-SO-CR VF"}, /* 2 x 40G, nomem */ 105 {0x5815, "Chelsio T502-BT VF"}, /* 2 x 1G */ 106#ifdef notyet 107 {0x5804, "Chelsio T520-BCH VF"}, 108 {0x5805, "Chelsio T540-BCH VF"}, 109 {0x5806, "Chelsio T540-CH VF"}, 110 {0x5808, "Chelsio T520-CX VF"}, 111 {0x580b, "Chelsio B520-SR VF"}, 112 {0x580c, "Chelsio B504-BT VF"}, 113 {0x580f, "Chelsio Amsterdam VF"}, 114 {0x5813, "Chelsio T580-CHR VF"}, 115#endif 116}, t6vf_pciids[] = { 117 {0x6801, "Chelsio T6225-CR VF"}, /* 2 x 10/25G */ 118 {0x6802, "Chelsio T6225-SO-CR VF"}, /* 2 x 10/25G, nomem */ 119 {0x6807, "Chelsio T62100-LP-CR VF"}, /* 2 x 40/50/100G */ 120 {0x6808, "Chelsio T62100-SO-CR VF"}, /* 2 x 40/50/100G, nomem */ 121 {0x680d, "Chelsio T62100-CR VF"}, /* 2 x 40/50/100G */ 122}; 123 124static d_ioctl_t t4vf_ioctl; 125 126static struct cdevsw t4vf_cdevsw = { 127 .d_version = D_VERSION, 128 .d_ioctl = t4vf_ioctl, 129 .d_name = "t4vf", 130}; 131 132static int 133t4vf_probe(device_t dev) 134{ 135 uint16_t d; 136 size_t i; 137 138 d = pci_get_device(dev); 139 for (i = 0; i < nitems(t4vf_pciids); i++) { 140 if (d == t4vf_pciids[i].device) { 141 device_set_desc(dev, t4vf_pciids[i].desc); 142 return (BUS_PROBE_DEFAULT); 143 } 144 } 145 return (ENXIO); 146} 147 148static int 149t5vf_probe(device_t dev) 150{ 151 uint16_t d; 152 size_t i; 153 154 d = pci_get_device(dev); 155 for (i = 0; i < nitems(t5vf_pciids); i++) { 156 if (d == t5vf_pciids[i].device) { 157 device_set_desc(dev, t5vf_pciids[i].desc); 158 return (BUS_PROBE_DEFAULT); 159 } 160 } 161 return (ENXIO); 162} 163 164static int 165t6vf_probe(device_t dev) 166{ 167 uint16_t d; 168 size_t i; 169 170 d = pci_get_device(dev); 171 for (i = 0; i < nitems(t6vf_pciids); i++) { 172 if (d == t6vf_pciids[i].device) { 173 device_set_desc(dev, t6vf_pciids[i].desc); 174 return (BUS_PROBE_DEFAULT); 175 } 176 } 177 return (ENXIO); 178} 179 180#define FW_PARAM_DEV(param) \ 181 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 182 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 183#define FW_PARAM_PFVF(param) \ 184 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 185 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) 186 187static int 188get_params__pre_init(struct adapter *sc) 189{ 190 int rc; 191 uint32_t param[3], val[3]; 192 193 param[0] = FW_PARAM_DEV(FWREV); 194 param[1] = FW_PARAM_DEV(TPREV); 195 param[2] = FW_PARAM_DEV(CCLK); 196 rc = -t4vf_query_params(sc, nitems(param), param, val); 197 if (rc != 0) { 198 device_printf(sc->dev, 199 "failed to query parameters (pre_init): %d.\n", rc); 200 return (rc); 201 } 202 203 sc->params.fw_vers = val[0]; 204 sc->params.tp_vers = val[1]; 205 sc->params.vpd.cclk = val[2]; 206 207 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u", 208 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers), 209 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers), 210 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers), 211 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers)); 212 213 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u", 214 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers), 215 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers), 216 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers), 217 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers)); 218 219 return (0); 220} 221 222static int 223get_params__post_init(struct adapter *sc) 224{ 225 int rc; 226 227 rc = -t4vf_get_sge_params(sc); 228 if (rc != 0) { 229 device_printf(sc->dev, 230 "unable to retrieve adapter SGE parameters: %d\n", rc); 231 return (rc); 232 } 233 234 rc = -t4vf_get_rss_glb_config(sc); 235 if (rc != 0) { 236 device_printf(sc->dev, 237 "unable to retrieve adapter RSS parameters: %d\n", rc); 238 return (rc); 239 } 240 if (sc->params.rss.mode != FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 241 device_printf(sc->dev, 242 "unable to operate with global RSS mode %d\n", 243 sc->params.rss.mode); 244 return (EINVAL); 245 } 246 247 rc = t4_read_chip_settings(sc); 248 if (rc != 0) 249 return (rc); 250 251 /* 252 * Grab our Virtual Interface resource allocation, extract the 253 * features that we're interested in and do a bit of sanity testing on 254 * what we discover. 255 */ 256 rc = -t4vf_get_vfres(sc); 257 if (rc != 0) { 258 device_printf(sc->dev, 259 "unable to get virtual interface resources: %d\n", rc); 260 return (rc); 261 } 262 263 /* 264 * Check for various parameter sanity issues. 265 */ 266 if (sc->params.vfres.pmask == 0) { 267 device_printf(sc->dev, "no port access configured/usable!\n"); 268 return (EINVAL); 269 } 270 if (sc->params.vfres.nvi == 0) { 271 device_printf(sc->dev, 272 "no virtual interfaces configured/usable!\n"); 273 return (EINVAL); 274 } 275 sc->params.portvec = sc->params.vfres.pmask; 276 277 return (0); 278} 279 280static int 281set_params__post_init(struct adapter *sc) 282{ 283 uint32_t param, val; 284 285 /* ask for encapsulated CPLs */ 286 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 287 val = 1; 288 (void)t4vf_set_params(sc, 1, ¶m, &val); 289 290 return (0); 291} 292 293#undef FW_PARAM_PFVF 294#undef FW_PARAM_DEV 295 296static int 297cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, 298 struct intrs_and_queues *iaq) 299{ 300 struct vf_resources *vfres; 301 int nrxq10g, nrxq1g, nrxq; 302 int ntxq10g, ntxq1g, ntxq; 303 int itype, iq_avail, navail, rc; 304 305 /* 306 * Figure out the layout of queues across our VIs and ensure 307 * we can allocate enough interrupts for our layout. 308 */ 309 vfres = &sc->params.vfres; 310 bzero(iaq, sizeof(*iaq)); 311 312 for (itype = INTR_MSIX; itype != 0; itype >>= 1) { 313 if (itype == INTR_INTX) 314 continue; 315 316 if (itype == INTR_MSIX) 317 navail = pci_msix_count(sc->dev); 318 else 319 navail = pci_msi_count(sc->dev); 320 321 if (navail == 0) 322 continue; 323 324 iaq->intr_type = itype; 325 iaq->intr_flags_10g = 0; 326 iaq->intr_flags_1g = 0; 327 328 /* 329 * XXX: The Linux driver reserves an Ingress Queue for 330 * forwarded interrupts when using MSI (but not MSI-X). 331 * It seems it just always asks for 2 interrupts and 332 * forwards all rxqs to the forwarded interrupt. 333 * 334 * We must reserve one IRQ for the for the firmware 335 * event queue. 336 * 337 * Every rxq requires an ingress queue with a free 338 * list and interrupts and an egress queue. Every txq 339 * requires an ETH egress queue. 340 */ 341 iaq->nirq = T4VF_EXTRA_INTR; 342 343 /* 344 * First, determine how many queues we can allocate. 345 * Start by finding the upper bound on rxqs from the 346 * limit on ingress queues. 347 */ 348 iq_avail = vfres->niqflint - iaq->nirq; 349 if (iq_avail < n10g + n1g) { 350 device_printf(sc->dev, 351 "Not enough ingress queues (%d) for %d ports\n", 352 vfres->niqflint, n10g + n1g); 353 return (ENXIO); 354 } 355 356 /* 357 * Try to honor the cap on interrupts. If there aren't 358 * enough interrupts for at least one interrupt per 359 * port, then don't bother, we will just forward all 360 * interrupts to one interrupt in that case. 361 */ 362 if (iaq->nirq + n10g + n1g <= navail) { 363 if (iq_avail > navail - iaq->nirq) 364 iq_avail = navail - iaq->nirq; 365 } 366 367 nrxq10g = t4_nrxq10g; 368 nrxq1g = t4_nrxq1g; 369 nrxq = n10g * nrxq10g + n1g * nrxq1g; 370 if (nrxq > iq_avail && nrxq1g > 1) { 371 /* Too many ingress queues. Try just 1 for 1G. */ 372 nrxq1g = 1; 373 nrxq = n10g * nrxq10g + n1g * nrxq1g; 374 } 375 if (nrxq > iq_avail) { 376 /* 377 * Still too many ingress queues. Use what we 378 * can for each 10G port. 379 */ 380 nrxq10g = (iq_avail - n1g) / n10g; 381 nrxq = n10g * nrxq10g + n1g * nrxq1g; 382 } 383 KASSERT(nrxq <= iq_avail, ("too many ingress queues")); 384 385 /* 386 * Next, determine the upper bound on txqs from the limit 387 * on ETH queues. 388 */ 389 if (vfres->nethctrl < n10g + n1g) { 390 device_printf(sc->dev, 391 "Not enough ETH queues (%d) for %d ports\n", 392 vfres->nethctrl, n10g + n1g); 393 return (ENXIO); 394 } 395 396 ntxq10g = t4_ntxq10g; 397 ntxq1g = t4_ntxq1g; 398 ntxq = n10g * ntxq10g + n1g * ntxq1g; 399 if (ntxq > vfres->nethctrl) { 400 /* Too many ETH queues. Try just 1 for 1G. */ 401 ntxq1g = 1; 402 ntxq = n10g * ntxq10g + n1g * ntxq1g; 403 } 404 if (ntxq > vfres->nethctrl) { 405 /* 406 * Still too many ETH queues. Use what we 407 * can for each 10G port. 408 */ 409 ntxq10g = (vfres->nethctrl - n1g) / n10g; 410 ntxq = n10g * ntxq10g + n1g * ntxq1g; 411 } 412 KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues")); 413 414 /* 415 * Finally, ensure we have enough egress queues. 416 */ 417 if (vfres->neq < (n10g + n1g) * 2) { 418 device_printf(sc->dev, 419 "Not enough egress queues (%d) for %d ports\n", 420 vfres->neq, n10g + n1g); 421 return (ENXIO); 422 } 423 if (nrxq + ntxq > vfres->neq) { 424 /* Just punt and use 1 for everything. */ 425 nrxq1g = ntxq1g = nrxq10g = ntxq10g = 1; 426 nrxq = n10g * nrxq10g + n1g * nrxq1g; 427 ntxq = n10g * ntxq10g + n1g * ntxq1g; 428 } 429 KASSERT(nrxq <= iq_avail, ("too many ingress queues")); 430 KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues")); 431 KASSERT(nrxq + ntxq <= vfres->neq, ("too many egress queues")); 432 433 /* 434 * Do we have enough interrupts? For MSI the interrupts 435 * have to be a power of 2 as well. 436 */ 437 iaq->nirq += nrxq; 438 iaq->ntxq10g = ntxq10g; 439 iaq->ntxq1g = ntxq1g; 440 iaq->nrxq10g = nrxq10g; 441 iaq->nrxq1g = nrxq1g; 442 if (iaq->nirq <= navail && 443 (itype != INTR_MSI || powerof2(iaq->nirq))) { 444 navail = iaq->nirq; 445 if (itype == INTR_MSIX) 446 rc = pci_alloc_msix(sc->dev, &navail); 447 else 448 rc = pci_alloc_msi(sc->dev, &navail); 449 if (rc != 0) { 450 device_printf(sc->dev, 451 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 452 itype, rc, iaq->nirq, navail); 453 return (rc); 454 } 455 if (navail == iaq->nirq) { 456 iaq->intr_flags_10g = INTR_RXQ; 457 iaq->intr_flags_1g = INTR_RXQ; 458 return (0); 459 } 460 pci_release_msi(sc->dev); 461 } 462 463 /* Fall back to a single interrupt. */ 464 iaq->nirq = 1; 465 navail = iaq->nirq; 466 if (itype == INTR_MSIX) 467 rc = pci_alloc_msix(sc->dev, &navail); 468 else 469 rc = pci_alloc_msi(sc->dev, &navail); 470 if (rc != 0) 471 device_printf(sc->dev, 472 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n", 473 itype, rc, iaq->nirq, navail); 474 iaq->intr_flags_10g = 0; 475 iaq->intr_flags_1g = 0; 476 return (rc); 477 } 478 479 device_printf(sc->dev, 480 "failed to find a usable interrupt type. " 481 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types, 482 pci_msix_count(sc->dev), pci_msi_count(sc->dev)); 483 484 return (ENXIO); 485} 486 487static int 488t4vf_attach(device_t dev) 489{ 490 struct adapter *sc; 491 int rc = 0, i, j, n10g, n1g, rqidx, tqidx; 492 struct make_dev_args mda; 493 struct intrs_and_queues iaq; 494 struct sge *s; 495 496 sc = device_get_softc(dev); 497 sc->dev = dev; 498 pci_enable_busmaster(dev); 499 pci_set_max_read_req(dev, 4096); 500 sc->params.pci.mps = pci_get_max_payload(dev); 501 502 sc->flags |= IS_VF; 503 504 sc->sge_gts_reg = VF_SGE_REG(A_SGE_VF_GTS); 505 sc->sge_kdoorbell_reg = VF_SGE_REG(A_SGE_VF_KDOORBELL); 506 snprintf(sc->lockname, sizeof(sc->lockname), "%s", 507 device_get_nameunit(dev)); 508 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF); 509 t4_add_adapter(sc); 510 511 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF); 512 TAILQ_INIT(&sc->sfl); 513 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0); 514 515 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF); 516 517 rc = t4_map_bars_0_and_4(sc); 518 if (rc != 0) 519 goto done; /* error message displayed already */ 520 521 rc = -t4vf_prep_adapter(sc); 522 if (rc != 0) 523 goto done; 524 525 t4_init_devnames(sc); 526 if (sc->names == NULL) { 527 rc = ENOTSUP; 528 goto done; /* error message displayed already */ 529 } 530 531 /* 532 * Leave the 'pf' and 'mbox' values as zero. This ensures 533 * that various firmware messages do not set the fields which 534 * is the correct thing to do for a VF. 535 */ 536 537 memset(sc->chan_map, 0xff, sizeof(sc->chan_map)); 538 539 make_dev_args_init(&mda); 540 mda.mda_devsw = &t4vf_cdevsw; 541 mda.mda_uid = UID_ROOT; 542 mda.mda_gid = GID_WHEEL; 543 mda.mda_mode = 0600; 544 mda.mda_si_drv1 = sc; 545 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev)); 546 if (rc != 0) 547 device_printf(dev, "failed to create nexus char device: %d.\n", 548 rc); 549 550#if defined(__i386__) 551 if ((cpu_feature & CPUID_CX8) == 0) { 552 device_printf(dev, "64 bit atomics not available.\n"); 553 rc = ENOTSUP; 554 goto done; 555 } 556#endif 557 558 /* 559 * Some environments do not properly handle PCIE FLRs -- e.g. in Linux 560 * 2.6.31 and later we can't call pci_reset_function() in order to 561 * issue an FLR because of a self- deadlock on the device semaphore. 562 * Meanwhile, the OS infrastructure doesn't issue FLRs in all the 563 * cases where they're needed -- for instance, some versions of KVM 564 * fail to reset "Assigned Devices" when the VM reboots. Therefore we 565 * use the firmware based reset in order to reset any per function 566 * state. 567 */ 568 rc = -t4vf_fw_reset(sc); 569 if (rc != 0) { 570 device_printf(dev, "FW reset failed: %d\n", rc); 571 goto done; 572 } 573 sc->flags |= FW_OK; 574 575 /* 576 * Grab basic operational parameters. These will predominantly have 577 * been set up by the Physical Function Driver or will be hard coded 578 * into the adapter. We just have to live with them ... Note that 579 * we _must_ get our VPD parameters before our SGE parameters because 580 * we need to know the adapter's core clock from the VPD in order to 581 * properly decode the SGE Timer Values. 582 */ 583 rc = get_params__pre_init(sc); 584 if (rc != 0) 585 goto done; /* error message displayed already */ 586 rc = get_params__post_init(sc); 587 if (rc != 0) 588 goto done; /* error message displayed already */ 589 590 rc = set_params__post_init(sc); 591 if (rc != 0) 592 goto done; /* error message displayed already */ 593 594 rc = t4_map_bar_2(sc); 595 if (rc != 0) 596 goto done; /* error message displayed already */ 597 598 rc = t4_create_dma_tag(sc); 599 if (rc != 0) 600 goto done; /* error message displayed already */ 601 602 /* 603 * The number of "ports" which we support is equal to the number of 604 * Virtual Interfaces with which we've been provisioned. 605 */ 606 sc->params.nports = imin(sc->params.vfres.nvi, MAX_NPORTS); 607 608 /* 609 * We may have been provisioned with more VIs than the number of 610 * ports we're allowed to access (our Port Access Rights Mask). 611 * Just use a single VI for each port. 612 */ 613 sc->params.nports = imin(sc->params.nports, 614 bitcount32(sc->params.vfres.pmask)); 615 616#ifdef notyet 617 /* 618 * XXX: The Linux VF driver will lower nports if it thinks there 619 * are too few resources in vfres (niqflint, nethctrl, neq). 620 */ 621#endif 622 623 /* 624 * First pass over all the ports - allocate VIs and initialize some 625 * basic parameters like mac address, port type, etc. We also figure 626 * out whether a port is 10G or 1G and use that information when 627 * calculating how many interrupts to attempt to allocate. 628 */ 629 n10g = n1g = 0; 630 for_each_port(sc, i) { 631 struct port_info *pi; 632 633 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK); 634 sc->port[i] = pi; 635 636 /* These must be set before t4_port_init */ 637 pi->adapter = sc; 638 pi->port_id = i; 639 pi->nvi = 1; 640 pi->vi = malloc(sizeof(struct vi_info) * pi->nvi, M_CXGBE, 641 M_ZERO | M_WAITOK); 642 643 /* 644 * Allocate the "main" VI and initialize parameters 645 * like mac addr. 646 */ 647 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i); 648 if (rc != 0) { 649 device_printf(dev, "unable to initialize port %d: %d\n", 650 i, rc); 651 free(pi->vi, M_CXGBE); 652 free(pi, M_CXGBE); 653 sc->port[i] = NULL; 654 goto done; 655 } 656 657 /* No t4_link_start. */ 658 659 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d", 660 device_get_nameunit(dev), i); 661 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF); 662 sc->chan_map[pi->tx_chan] = i; 663 664 pi->tc = malloc(sizeof(struct tx_sched_class) * 665 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK); 666 667 if (port_top_speed(pi) >= 10) { 668 n10g++; 669 } else { 670 n1g++; 671 } 672 673 pi->linkdnrc = -1; 674 675 pi->dev = device_add_child(dev, sc->names->vf_ifnet_name, -1); 676 if (pi->dev == NULL) { 677 device_printf(dev, 678 "failed to add device for port %d.\n", i); 679 rc = ENXIO; 680 goto done; 681 } 682 pi->vi[0].dev = pi->dev; 683 device_set_softc(pi->dev, pi); 684 } 685 686 /* 687 * Interrupt type, # of interrupts, # of rx/tx queues, etc. 688 */ 689 rc = cfg_itype_and_nqueues(sc, n10g, n1g, &iaq); 690 if (rc != 0) 691 goto done; /* error message displayed already */ 692 693 sc->intr_type = iaq.intr_type; 694 sc->intr_count = iaq.nirq; 695 696 s = &sc->sge; 697 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g; 698 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g; 699 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */ 700 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */ 701 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */ 702 703 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE, 704 M_ZERO | M_WAITOK); 705 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE, 706 M_ZERO | M_WAITOK); 707 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE, 708 M_ZERO | M_WAITOK); 709 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE, 710 M_ZERO | M_WAITOK); 711 712 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE, 713 M_ZERO | M_WAITOK); 714 715 /* 716 * Second pass over the ports. This time we know the number of rx and 717 * tx queues that each port should get. 718 */ 719 rqidx = tqidx = 0; 720 for_each_port(sc, i) { 721 struct port_info *pi = sc->port[i]; 722 struct vi_info *vi; 723 724 if (pi == NULL) 725 continue; 726 727 for_each_vi(pi, j, vi) { 728 vi->pi = pi; 729 vi->qsize_rxq = t4_qsize_rxq; 730 vi->qsize_txq = t4_qsize_txq; 731 732 vi->first_rxq = rqidx; 733 vi->first_txq = tqidx; 734 if (port_top_speed(pi) >= 10) { 735 vi->tmr_idx = t4_tmr_idx_10g; 736 vi->pktc_idx = t4_pktc_idx_10g; 737 vi->flags |= iaq.intr_flags_10g & INTR_RXQ; 738 vi->nrxq = j == 0 ? iaq.nrxq10g : 1; 739 vi->ntxq = j == 0 ? iaq.ntxq10g : 1; 740 } else { 741 vi->tmr_idx = t4_tmr_idx_1g; 742 vi->pktc_idx = t4_pktc_idx_1g; 743 vi->flags |= iaq.intr_flags_1g & INTR_RXQ; 744 vi->nrxq = j == 0 ? iaq.nrxq1g : 1; 745 vi->ntxq = j == 0 ? iaq.ntxq1g : 1; 746 } 747 rqidx += vi->nrxq; 748 tqidx += vi->ntxq; 749 750 vi->rsrv_noflowq = 0; 751 } 752 } 753 754 rc = t4_setup_intr_handlers(sc); 755 if (rc != 0) { 756 device_printf(dev, 757 "failed to setup interrupt handlers: %d\n", rc); 758 goto done; 759 } 760 761 rc = bus_generic_attach(dev); 762 if (rc != 0) { 763 device_printf(dev, 764 "failed to attach all child ports: %d\n", rc); 765 goto done; 766 } 767 768 device_printf(dev, 769 "%d ports, %d %s interrupt%s, %d eq, %d iq\n", 770 sc->params.nports, sc->intr_count, sc->intr_type == INTR_MSIX ? 771 "MSI-X" : "MSI", sc->intr_count > 1 ? "s" : "", sc->sge.neq, 772 sc->sge.niq); 773 774done: 775 if (rc != 0) 776 t4_detach_common(dev); 777 else 778 t4_sysctls(sc); 779 780 return (rc); 781} 782 783static void 784get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf) 785{ 786 787 /* 0x3f is used as the revision for VFs. */ 788 regs->version = chip_id(sc) | (0x3f << 10); 789 t4_get_regs(sc, buf, regs->len); 790} 791 792static void 793t4_clr_vi_stats(struct adapter *sc) 794{ 795 int reg; 796 797 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L; 798 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4) 799 t4_write_reg(sc, VF_MPS_REG(reg), 0); 800} 801 802static int 803t4vf_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 804 struct thread *td) 805{ 806 int rc; 807 struct adapter *sc = dev->si_drv1; 808 809 rc = priv_check(td, PRIV_DRIVER); 810 if (rc != 0) 811 return (rc); 812 813 switch (cmd) { 814 case CHELSIO_T4_GETREG: { 815 struct t4_reg *edata = (struct t4_reg *)data; 816 817 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 818 return (EFAULT); 819 820 if (edata->size == 4) 821 edata->val = t4_read_reg(sc, edata->addr); 822 else if (edata->size == 8) 823 edata->val = t4_read_reg64(sc, edata->addr); 824 else 825 return (EINVAL); 826 827 break; 828 } 829 case CHELSIO_T4_SETREG: { 830 struct t4_reg *edata = (struct t4_reg *)data; 831 832 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len) 833 return (EFAULT); 834 835 if (edata->size == 4) { 836 if (edata->val & 0xffffffff00000000) 837 return (EINVAL); 838 t4_write_reg(sc, edata->addr, (uint32_t) edata->val); 839 } else if (edata->size == 8) 840 t4_write_reg64(sc, edata->addr, edata->val); 841 else 842 return (EINVAL); 843 break; 844 } 845 case CHELSIO_T4_REGDUMP: { 846 struct t4_regdump *regs = (struct t4_regdump *)data; 847 int reglen = t4_get_regs_len(sc); 848 uint8_t *buf; 849 850 if (regs->len < reglen) { 851 regs->len = reglen; /* hint to the caller */ 852 return (ENOBUFS); 853 } 854 855 regs->len = reglen; 856 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO); 857 get_regs(sc, regs, buf); 858 rc = copyout(buf, regs->data, reglen); 859 free(buf, M_CXGBE); 860 break; 861 } 862 case CHELSIO_T4_CLEAR_STATS: { 863 int i, v; 864 u_int port_id = *(uint32_t *)data; 865 struct port_info *pi; 866 struct vi_info *vi; 867 868 if (port_id >= sc->params.nports) 869 return (EINVAL); 870 pi = sc->port[port_id]; 871 872 /* MAC stats */ 873 pi->tx_parse_error = 0; 874 t4_clr_vi_stats(sc); 875 876 /* 877 * Since this command accepts a port, clear stats for 878 * all VIs on this port. 879 */ 880 for_each_vi(pi, v, vi) { 881 if (vi->flags & VI_INIT_DONE) { 882 struct sge_rxq *rxq; 883 struct sge_txq *txq; 884 885 for_each_rxq(vi, i, rxq) { 886#if defined(INET) || defined(INET6) 887 rxq->lro.lro_queued = 0; 888 rxq->lro.lro_flushed = 0; 889#endif 890 rxq->rxcsum = 0; 891 rxq->vlan_extraction = 0; 892 } 893 894 for_each_txq(vi, i, txq) { 895 txq->txcsum = 0; 896 txq->tso_wrs = 0; 897 txq->vlan_insertion = 0; 898 txq->imm_wrs = 0; 899 txq->sgl_wrs = 0; 900 txq->txpkt_wrs = 0; 901 txq->txpkts0_wrs = 0; 902 txq->txpkts1_wrs = 0; 903 txq->txpkts0_pkts = 0; 904 txq->txpkts1_pkts = 0; 905 mp_ring_reset_stats(txq->r); 906 } 907 } 908 } 909 break; 910 } 911 case CHELSIO_T4_SCHED_CLASS: 912 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data); 913 break; 914 case CHELSIO_T4_SCHED_QUEUE: 915 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data); 916 break; 917 default: 918 rc = ENOTTY; 919 } 920 921 return (rc); 922} 923 924static device_method_t t4vf_methods[] = { 925 DEVMETHOD(device_probe, t4vf_probe), 926 DEVMETHOD(device_attach, t4vf_attach), 927 DEVMETHOD(device_detach, t4_detach_common), 928 929 DEVMETHOD_END 930}; 931 932static driver_t t4vf_driver = { 933 "t4vf", 934 t4vf_methods, 935 sizeof(struct adapter) 936}; 937 938static device_method_t t5vf_methods[] = { 939 DEVMETHOD(device_probe, t5vf_probe), 940 DEVMETHOD(device_attach, t4vf_attach), 941 DEVMETHOD(device_detach, t4_detach_common), 942 943 DEVMETHOD_END 944}; 945 946static driver_t t5vf_driver = { 947 "t5vf", 948 t5vf_methods, 949 sizeof(struct adapter) 950}; 951 952static device_method_t t6vf_methods[] = { 953 DEVMETHOD(device_probe, t6vf_probe), 954 DEVMETHOD(device_attach, t4vf_attach), 955 DEVMETHOD(device_detach, t4_detach_common), 956 957 DEVMETHOD_END 958}; 959 960static driver_t t6vf_driver = { 961 "t6vf", 962 t6vf_methods, 963 sizeof(struct adapter) 964}; 965 966static driver_t cxgbev_driver = { 967 "cxgbev", 968 cxgbe_methods, 969 sizeof(struct port_info) 970}; 971 972static driver_t cxlv_driver = { 973 "cxlv", 974 cxgbe_methods, 975 sizeof(struct port_info) 976}; 977 978static driver_t ccv_driver = { 979 "ccv", 980 cxgbe_methods, 981 sizeof(struct port_info) 982}; 983 984static devclass_t t4vf_devclass, t5vf_devclass, t6vf_devclass; 985static devclass_t cxgbev_devclass, cxlv_devclass, ccv_devclass; 986 987DRIVER_MODULE(t4vf, pci, t4vf_driver, t4vf_devclass, 0, 0); 988MODULE_VERSION(t4vf, 1); 989MODULE_DEPEND(t4vf, t4nex, 1, 1, 1); 990 991DRIVER_MODULE(t5vf, pci, t5vf_driver, t5vf_devclass, 0, 0); 992MODULE_VERSION(t5vf, 1); 993MODULE_DEPEND(t5vf, t5nex, 1, 1, 1); 994 995DRIVER_MODULE(t6vf, pci, t6vf_driver, t6vf_devclass, 0, 0); 996MODULE_VERSION(t6vf, 1); 997MODULE_DEPEND(t6vf, t6nex, 1, 1, 1); 998 999DRIVER_MODULE(cxgbev, t4vf, cxgbev_driver, cxgbev_devclass, 0, 0); 1000MODULE_VERSION(cxgbev, 1); 1001 1002DRIVER_MODULE(cxlv, t5vf, cxlv_driver, cxlv_devclass, 0, 0); 1003MODULE_VERSION(cxlv, 1); 1004 1005DRIVER_MODULE(ccv, t6vf, ccv_driver, ccv_devclass, 0, 0); 1006MODULE_VERSION(ccv, 1); 1007