t4_netmap.c revision 308304
1/*- 2 * Copyright (c) 2014 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/10/sys/dev/cxgbe/t4_netmap.c 308304 2016-11-04 18:45:06Z jhb $"); 30 31#include "opt_inet.h" 32#include "opt_inet6.h" 33 34#ifdef DEV_NETMAP 35#include <sys/param.h> 36#include <sys/bus.h> 37#include <sys/eventhandler.h> 38#include <sys/lock.h> 39#include <sys/mbuf.h> 40#include <sys/module.h> 41#include <sys/selinfo.h> 42#include <sys/socket.h> 43#include <sys/sockio.h> 44#include <machine/bus.h> 45#include <net/ethernet.h> 46#include <net/if.h> 47#include <net/if_media.h> 48#include <net/if_var.h> 49#include <net/if_clone.h> 50#include <net/if_types.h> 51#include <net/netmap.h> 52#include <dev/netmap/netmap_kern.h> 53 54#include "common/common.h" 55#include "common/t4_regs.h" 56#include "common/t4_regs_values.h" 57 58extern int fl_pad; /* XXXNM */ 59 60SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe netmap parameters"); 61 62/* 63 * 0 = normal netmap rx 64 * 1 = black hole 65 * 2 = supermassive black hole (buffer packing enabled) 66 */ 67int black_hole = 0; 68SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RDTUN, &black_hole, 0, 69 "Sink incoming packets."); 70 71int rx_ndesc = 256; 72SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN, 73 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated."); 74 75int holdoff_tmr_idx = 2; 76SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN, 77 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues."); 78 79/* 80 * Congestion drops. 81 * -1: no congestion feedback (not recommended). 82 * 0: backpressure the channel instead of dropping packets right away. 83 * 1: no backpressure, drop packets for the congested queue immediately. 84 */ 85static int nm_cong_drop = 1; 86TUNABLE_INT("hw.cxgbe.nm_cong_drop", &nm_cong_drop); 87 88static int 89alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong) 90{ 91 int rc, cntxt_id, i; 92 __be32 v; 93 struct adapter *sc = vi->pi->adapter; 94 struct sge_params *sp = &sc->params.sge; 95 struct netmap_adapter *na = NA(vi->ifp); 96 struct fw_iq_cmd c; 97 98 MPASS(na != NULL); 99 MPASS(nm_rxq->iq_desc != NULL); 100 MPASS(nm_rxq->fl_desc != NULL); 101 102 bzero(nm_rxq->iq_desc, vi->qsize_rxq * IQ_ESIZE); 103 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + sp->spg_len); 104 105 bzero(&c, sizeof(c)); 106 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 107 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) | 108 V_FW_IQ_CMD_VFN(0)); 109 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART | 110 FW_LEN16(c)); 111 if (vi->flags & INTR_RXQ) { 112 KASSERT(nm_rxq->intr_idx < sc->intr_count, 113 ("%s: invalid direct intr_idx %d", __func__, 114 nm_rxq->intr_idx)); 115 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx); 116 } else { 117 CXGBE_UNIMPLEMENTED(__func__); /* XXXNM: needs review */ 118 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx) | 119 F_FW_IQ_CMD_IQANDST; 120 } 121 c.type_to_iqandstindex = htobe32(v | 122 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) | 123 V_FW_IQ_CMD_VIID(vi->viid) | 124 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT)); 125 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(vi->pi->tx_chan) | 126 F_FW_IQ_CMD_IQGTSMODE | 127 V_FW_IQ_CMD_IQINTCNTTHRESH(0) | 128 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4)); 129 c.iqsize = htobe16(vi->qsize_rxq); 130 c.iqaddr = htobe64(nm_rxq->iq_ba); 131 if (cong >= 0) { 132 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN | 133 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF | 134 F_FW_IQ_CMD_FL0CONGEN); 135 } 136 c.iqns_to_fl0congen |= 137 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) | 138 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO | 139 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) | 140 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0)); 141 c.fl0dcaen_to_fl0cidxfthresh = 142 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) | 143 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B)); 144 c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE); 145 c.fl0addr = htobe64(nm_rxq->fl_ba); 146 147 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 148 if (rc != 0) { 149 device_printf(sc->dev, 150 "failed to create netmap ingress queue: %d\n", rc); 151 return (rc); 152 } 153 154 nm_rxq->iq_cidx = 0; 155 MPASS(nm_rxq->iq_sidx == vi->qsize_rxq - sp->spg_len / IQ_ESIZE); 156 nm_rxq->iq_gen = F_RSPD_GEN; 157 nm_rxq->iq_cntxt_id = be16toh(c.iqid); 158 nm_rxq->iq_abs_id = be16toh(c.physiqid); 159 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start; 160 if (cntxt_id >= sc->sge.niq) { 161 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)", 162 __func__, cntxt_id, sc->sge.niq - 1); 163 } 164 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq; 165 166 nm_rxq->fl_cntxt_id = be16toh(c.fl0id); 167 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0; 168 MPASS(nm_rxq->fl_sidx == na->num_rx_desc); 169 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start; 170 if (cntxt_id >= sc->sge.neq) { 171 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)", 172 __func__, cntxt_id, sc->sge.neq - 1); 173 } 174 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq; 175 176 nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) | 177 sc->chip_params->sge_fl_db; 178 179 if (is_t5(sc) && cong >= 0) { 180 uint32_t param, val; 181 182 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 183 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 184 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 185 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 186 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | 187 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id); 188 if (cong == 0) 189 val = 1 << 19; 190 else { 191 val = 2 << 19; 192 for (i = 0; i < 4; i++) { 193 if (cong & (1 << i)) 194 val |= 1 << (i << 2); 195 } 196 } 197 198 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); 199 if (rc != 0) { 200 /* report error but carry on */ 201 device_printf(sc->dev, 202 "failed to set congestion manager context for " 203 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc); 204 } 205 } 206 207 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 208 V_INGRESSQID(nm_rxq->iq_cntxt_id) | 209 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 210 211 return (rc); 212} 213 214static int 215free_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq) 216{ 217 struct adapter *sc = vi->pi->adapter; 218 int rc; 219 220 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP, 221 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff); 222 if (rc != 0) 223 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n", 224 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc); 225 return (rc); 226} 227 228static int 229alloc_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 230{ 231 int rc, cntxt_id; 232 size_t len; 233 struct adapter *sc = vi->pi->adapter; 234 struct netmap_adapter *na = NA(vi->ifp); 235 struct fw_eq_eth_cmd c; 236 237 MPASS(na != NULL); 238 MPASS(nm_txq->desc != NULL); 239 240 len = na->num_tx_desc * EQ_ESIZE + sc->params.sge.spg_len; 241 bzero(nm_txq->desc, len); 242 243 bzero(&c, sizeof(c)); 244 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST | 245 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) | 246 V_FW_EQ_ETH_CMD_VFN(0)); 247 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC | 248 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); 249 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE | 250 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid)); 251 c.fetchszm_to_iqid = 252 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) | 253 V_FW_EQ_ETH_CMD_PCIECHN(vi->pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO | 254 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id)); 255 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) | 256 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) | 257 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE)); 258 c.eqaddr = htobe64(nm_txq->ba); 259 260 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c); 261 if (rc != 0) { 262 device_printf(vi->dev, 263 "failed to create netmap egress queue: %d\n", rc); 264 return (rc); 265 } 266 267 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd)); 268 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start; 269 if (cntxt_id >= sc->sge.neq) 270 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__, 271 cntxt_id, sc->sge.neq - 1); 272 sc->sge.eqmap[cntxt_id] = (void *)nm_txq; 273 274 nm_txq->pidx = nm_txq->cidx = 0; 275 MPASS(nm_txq->sidx == na->num_tx_desc); 276 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0; 277 278 nm_txq->doorbells = sc->doorbells; 279 if (isset(&nm_txq->doorbells, DOORBELL_UDB) || 280 isset(&nm_txq->doorbells, DOORBELL_UDBWC) || 281 isset(&nm_txq->doorbells, DOORBELL_WCWR)) { 282 uint32_t s_qpp = sc->params.sge.eq_s_qpp; 283 uint32_t mask = (1 << s_qpp) - 1; 284 volatile uint8_t *udb; 285 286 udb = sc->udbs_base + UDBS_DB_OFFSET; 287 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT; 288 nm_txq->udb_qid = nm_txq->cntxt_id & mask; 289 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE) 290 clrbit(&nm_txq->doorbells, DOORBELL_WCWR); 291 else { 292 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT; 293 nm_txq->udb_qid = 0; 294 } 295 nm_txq->udb = (volatile void *)udb; 296 } 297 298 return (rc); 299} 300 301static int 302free_nm_txq_hwq(struct vi_info *vi, struct sge_nm_txq *nm_txq) 303{ 304 struct adapter *sc = vi->pi->adapter; 305 int rc; 306 307 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id); 308 if (rc != 0) 309 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__, 310 nm_txq->cntxt_id, rc); 311 return (rc); 312} 313 314static int 315cxgbe_netmap_on(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 316 struct netmap_adapter *na) 317{ 318 struct netmap_slot *slot; 319 struct sge_nm_rxq *nm_rxq; 320 struct sge_nm_txq *nm_txq; 321 int rc, i, j, hwidx; 322 struct hw_buf_info *hwb; 323 324 ASSERT_SYNCHRONIZED_OP(sc); 325 326 if ((vi->flags & VI_INIT_DONE) == 0 || 327 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 328 return (EAGAIN); 329 330 hwb = &sc->sge.hw_buf_info[0]; 331 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) { 332 if (hwb->size == NETMAP_BUF_SIZE(na)) 333 break; 334 } 335 if (i >= SGE_FLBUF_SIZES) { 336 if_printf(ifp, "no hwidx for netmap buffer size %d.\n", 337 NETMAP_BUF_SIZE(na)); 338 return (ENXIO); 339 } 340 hwidx = i; 341 342 /* Must set caps before calling netmap_reset */ 343 nm_set_native_flags(na); 344 345 for_each_nm_rxq(vi, i, nm_rxq) { 346 struct irq *irq = &sc->irq[vi->first_intr + i]; 347 348 alloc_nm_rxq_hwq(vi, nm_rxq, tnl_cong(vi->pi, nm_cong_drop)); 349 nm_rxq->fl_hwidx = hwidx; 350 slot = netmap_reset(na, NR_RX, i, 0); 351 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 352 353 /* We deal with 8 bufs at a time */ 354 MPASS((na->num_rx_desc & 7) == 0); 355 MPASS(na->num_rx_desc == nm_rxq->fl_sidx); 356 for (j = 0; j < nm_rxq->fl_sidx; j++) { 357 uint64_t ba; 358 359 PNMB(na, &slot[j], &ba); 360 MPASS(ba != 0); 361 nm_rxq->fl_desc[j] = htobe64(ba | hwidx); 362 } 363 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8; 364 MPASS((j & 7) == 0); 365 j /= 8; /* driver pidx to hardware pidx */ 366 wmb(); 367 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 368 nm_rxq->fl_db_val | V_PIDX(j)); 369 370 atomic_cmpset_int(&irq->nm_state, NM_OFF, NM_ON); 371 } 372 373 for_each_nm_txq(vi, i, nm_txq) { 374 alloc_nm_txq_hwq(vi, nm_txq); 375 slot = netmap_reset(na, NR_TX, i, 0); 376 MPASS(slot != NULL); /* XXXNM: error check, not assert */ 377 } 378 379 if (vi->nm_rss == NULL) { 380 vi->nm_rss = malloc(vi->rss_size * sizeof(uint16_t), M_CXGBE, 381 M_ZERO | M_WAITOK); 382 } 383 for (i = 0; i < vi->rss_size;) { 384 for_each_nm_rxq(vi, j, nm_rxq) { 385 vi->nm_rss[i++] = nm_rxq->iq_abs_id; 386 if (i == vi->rss_size) 387 break; 388 } 389 } 390 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 391 vi->nm_rss, vi->rss_size); 392 if (rc != 0) 393 if_printf(ifp, "netmap rss_config failed: %d\n", rc); 394 395 return (rc); 396} 397 398static int 399cxgbe_netmap_off(struct adapter *sc, struct vi_info *vi, struct ifnet *ifp, 400 struct netmap_adapter *na) 401{ 402 int rc, i; 403 struct sge_nm_txq *nm_txq; 404 struct sge_nm_rxq *nm_rxq; 405 406 ASSERT_SYNCHRONIZED_OP(sc); 407 408 if ((vi->flags & VI_INIT_DONE) == 0) 409 return (0); 410 411 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, 412 vi->rss, vi->rss_size); 413 if (rc != 0) 414 if_printf(ifp, "failed to restore RSS config: %d\n", rc); 415 nm_clear_native_flags(na); 416 417 for_each_nm_txq(vi, i, nm_txq) { 418 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 419 420 /* Wait for hw pidx to catch up ... */ 421 while (be16toh(nm_txq->pidx) != spg->pidx) 422 pause("nmpidx", 1); 423 424 /* ... and then for the cidx. */ 425 while (spg->pidx != spg->cidx) 426 pause("nmcidx", 1); 427 428 free_nm_txq_hwq(vi, nm_txq); 429 } 430 for_each_nm_rxq(vi, i, nm_rxq) { 431 struct irq *irq = &sc->irq[vi->first_intr + i]; 432 433 while (!atomic_cmpset_int(&irq->nm_state, NM_ON, NM_OFF)) 434 pause("nmst", 1); 435 436 free_nm_rxq_hwq(vi, nm_rxq); 437 } 438 439 return (rc); 440} 441 442static int 443cxgbe_netmap_reg(struct netmap_adapter *na, int on) 444{ 445 struct ifnet *ifp = na->ifp; 446 struct vi_info *vi = ifp->if_softc; 447 struct adapter *sc = vi->pi->adapter; 448 int rc; 449 450 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4nmreg"); 451 if (rc != 0) 452 return (rc); 453 if (on) 454 rc = cxgbe_netmap_on(sc, vi, ifp, na); 455 else 456 rc = cxgbe_netmap_off(sc, vi, ifp, na); 457 end_synchronized_op(sc, 0); 458 459 return (rc); 460} 461 462/* How many packets can a single type1 WR carry in n descriptors */ 463static inline int 464ndesc_to_npkt(const int n) 465{ 466 467 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC); 468 469 return (n * 2 - 1); 470} 471#define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC)) 472 473/* Space (in descriptors) needed for a type1 WR that carries n packets */ 474static inline int 475npkt_to_ndesc(const int n) 476{ 477 478 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 479 480 return ((n + 2) / 2); 481} 482 483/* Space (in 16B units) needed for a type1 WR that carries n packets */ 484static inline int 485npkt_to_len16(const int n) 486{ 487 488 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR); 489 490 return (n * 2 + 1); 491} 492 493#define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx) 494 495static void 496ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq) 497{ 498 int n; 499 u_int db = nm_txq->doorbells; 500 501 MPASS(nm_txq->pidx != nm_txq->dbidx); 502 503 n = NMIDXDIFF(nm_txq, dbidx); 504 if (n > 1) 505 clrbit(&db, DOORBELL_WCWR); 506 wmb(); 507 508 switch (ffs(db) - 1) { 509 case DOORBELL_UDB: 510 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 511 break; 512 513 case DOORBELL_WCWR: { 514 volatile uint64_t *dst, *src; 515 516 /* 517 * Queues whose 128B doorbell segment fits in the page do not 518 * use relative qid (udb_qid is always 0). Only queues with 519 * doorbell segments can do WCWR. 520 */ 521 KASSERT(nm_txq->udb_qid == 0 && n == 1, 522 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p", 523 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq)); 524 525 dst = (volatile void *)((uintptr_t)nm_txq->udb + 526 UDBS_WR_OFFSET - UDBS_DB_OFFSET); 527 src = (void *)&nm_txq->desc[nm_txq->dbidx]; 528 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1]) 529 *dst++ = *src++; 530 wmb(); 531 break; 532 } 533 534 case DOORBELL_UDBWC: 535 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n)); 536 wmb(); 537 break; 538 539 case DOORBELL_KDB: 540 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 541 V_QID(nm_txq->cntxt_id) | V_PIDX(n)); 542 break; 543 } 544 nm_txq->dbidx = nm_txq->pidx; 545} 546 547int lazy_tx_credit_flush = 1; 548 549/* 550 * Write work requests to send 'npkt' frames and ring the doorbell to send them 551 * on their way. No need to check for wraparound. 552 */ 553static void 554cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq, 555 struct netmap_kring *kring, int npkt, int npkt_remaining, int txcsum) 556{ 557 struct netmap_ring *ring = kring->ring; 558 struct netmap_slot *slot; 559 const u_int lim = kring->nkr_num_slots - 1; 560 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx]; 561 uint16_t len; 562 uint64_t ba; 563 struct cpl_tx_pkt_core *cpl; 564 struct ulptx_sgl *usgl; 565 int i, n; 566 567 while (npkt) { 568 n = min(npkt, MAX_NPKT_IN_TYPE1_WR); 569 len = 0; 570 571 wr = (void *)&nm_txq->desc[nm_txq->pidx]; 572 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)); 573 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n))); 574 wr->npkt = n; 575 wr->r3 = 0; 576 wr->type = 1; 577 cpl = (void *)(wr + 1); 578 579 for (i = 0; i < n; i++) { 580 slot = &ring->slot[kring->nr_hwcur]; 581 PNMB(kring->na, slot, &ba); 582 MPASS(ba != 0); 583 584 cpl->ctrl0 = nm_txq->cpl_ctrl0; 585 cpl->pack = 0; 586 cpl->len = htobe16(slot->len); 587 /* 588 * netmap(4) says "netmap does not use features such as 589 * checksum offloading, TCP segmentation offloading, 590 * encryption, VLAN encapsulation/decapsulation, etc." 591 * 592 * So the ncxl interfaces have tx hardware checksumming 593 * disabled by default. But you can override netmap by 594 * enabling IFCAP_TXCSUM on the interface manully. 595 */ 596 cpl->ctrl1 = txcsum ? 0 : 597 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS); 598 599 usgl = (void *)(cpl + 1); 600 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 601 V_ULPTX_NSGE(1)); 602 usgl->len0 = htobe32(slot->len); 603 usgl->addr0 = htobe64(ba); 604 605 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED); 606 cpl = (void *)(usgl + 1); 607 MPASS(slot->len + len <= UINT16_MAX); 608 len += slot->len; 609 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim); 610 } 611 wr->plen = htobe16(len); 612 613 npkt -= n; 614 nm_txq->pidx += npkt_to_ndesc(n); 615 MPASS(nm_txq->pidx <= nm_txq->sidx); 616 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) { 617 /* 618 * This routine doesn't know how to write WRs that wrap 619 * around. Make sure it wasn't asked to. 620 */ 621 MPASS(npkt == 0); 622 nm_txq->pidx = 0; 623 } 624 625 if (npkt == 0 && npkt_remaining == 0) { 626 /* All done. */ 627 if (lazy_tx_credit_flush == 0) { 628 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 629 F_FW_WR_EQUIQ); 630 nm_txq->equeqidx = nm_txq->pidx; 631 nm_txq->equiqidx = nm_txq->pidx; 632 } 633 ring_nm_txq_db(sc, nm_txq); 634 return; 635 } 636 637 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) { 638 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | 639 F_FW_WR_EQUIQ); 640 nm_txq->equeqidx = nm_txq->pidx; 641 nm_txq->equiqidx = nm_txq->pidx; 642 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) { 643 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ); 644 nm_txq->equeqidx = nm_txq->pidx; 645 } 646 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC) 647 ring_nm_txq_db(sc, nm_txq); 648 } 649 650 /* Will get called again. */ 651 MPASS(npkt_remaining); 652} 653 654/* How many contiguous free descriptors starting at pidx */ 655static inline int 656contiguous_ndesc_available(struct sge_nm_txq *nm_txq) 657{ 658 659 if (nm_txq->cidx > nm_txq->pidx) 660 return (nm_txq->cidx - nm_txq->pidx - 1); 661 else if (nm_txq->cidx > 0) 662 return (nm_txq->sidx - nm_txq->pidx); 663 else 664 return (nm_txq->sidx - nm_txq->pidx - 1); 665} 666 667static int 668reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq) 669{ 670 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx]; 671 uint16_t hw_cidx = spg->cidx; /* snapshot */ 672 struct fw_eth_tx_pkts_wr *wr; 673 int n = 0; 674 675 hw_cidx = be16toh(hw_cidx); 676 677 while (nm_txq->cidx != hw_cidx) { 678 wr = (void *)&nm_txq->desc[nm_txq->cidx]; 679 680 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR))); 681 MPASS(wr->type == 1); 682 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR); 683 684 n += wr->npkt; 685 nm_txq->cidx += npkt_to_ndesc(wr->npkt); 686 687 /* 688 * We never sent a WR that wrapped around so the credits coming 689 * back, WR by WR, should never cause the cidx to wrap around 690 * either. 691 */ 692 MPASS(nm_txq->cidx <= nm_txq->sidx); 693 if (__predict_false(nm_txq->cidx == nm_txq->sidx)) 694 nm_txq->cidx = 0; 695 } 696 697 return (n); 698} 699 700static int 701cxgbe_netmap_txsync(struct netmap_kring *kring, int flags) 702{ 703 struct netmap_adapter *na = kring->na; 704 struct ifnet *ifp = na->ifp; 705 struct vi_info *vi = ifp->if_softc; 706 struct adapter *sc = vi->pi->adapter; 707 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[vi->first_nm_txq + kring->ring_id]; 708 const u_int head = kring->rhead; 709 u_int reclaimed = 0; 710 int n, d, npkt_remaining, ndesc_remaining, txcsum; 711 712 /* 713 * Tx was at kring->nr_hwcur last time around and now we need to advance 714 * to kring->rhead. Note that the driver's pidx moves independent of 715 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation 716 * between descriptors and frames isn't 1:1). 717 */ 718 719 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 720 kring->nkr_num_slots - kring->nr_hwcur + head; 721 txcsum = ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6); 722 while (npkt_remaining) { 723 reclaimed += reclaim_nm_tx_desc(nm_txq); 724 ndesc_remaining = contiguous_ndesc_available(nm_txq); 725 /* Can't run out of descriptors with packets still remaining */ 726 MPASS(ndesc_remaining > 0); 727 728 /* # of desc needed to tx all remaining packets */ 729 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC; 730 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR) 731 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR); 732 733 if (d <= ndesc_remaining) 734 n = npkt_remaining; 735 else { 736 /* Can't send all, calculate how many can be sent */ 737 n = (ndesc_remaining / SGE_MAX_WR_NDESC) * 738 MAX_NPKT_IN_TYPE1_WR; 739 if (ndesc_remaining % SGE_MAX_WR_NDESC) 740 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC); 741 } 742 743 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */ 744 npkt_remaining -= n; 745 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining, txcsum); 746 } 747 MPASS(npkt_remaining == 0); 748 MPASS(kring->nr_hwcur == head); 749 MPASS(nm_txq->dbidx == nm_txq->pidx); 750 751 /* 752 * Second part: reclaim buffers for completed transmissions. 753 */ 754 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) { 755 reclaimed += reclaim_nm_tx_desc(nm_txq); 756 kring->nr_hwtail += reclaimed; 757 if (kring->nr_hwtail >= kring->nkr_num_slots) 758 kring->nr_hwtail -= kring->nkr_num_slots; 759 } 760 761 nm_txsync_finalize(kring); 762 763 return (0); 764} 765 766static int 767cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags) 768{ 769 struct netmap_adapter *na = kring->na; 770 struct netmap_ring *ring = kring->ring; 771 struct ifnet *ifp = na->ifp; 772 struct vi_info *vi = ifp->if_softc; 773 struct adapter *sc = vi->pi->adapter; 774 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[vi->first_nm_rxq + kring->ring_id]; 775 u_int const head = nm_rxsync_prologue(kring); 776 u_int n; 777 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR; 778 779 if (black_hole) 780 return (0); /* No updates ever. */ 781 782 if (netmap_no_pendintr || force_update) { 783 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx); 784 kring->nr_kflags &= ~NKR_PENDINTR; 785 } 786 787 /* Userspace done with buffers from kring->nr_hwcur to head */ 788 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur : 789 kring->nkr_num_slots - kring->nr_hwcur + head; 790 n &= ~7U; 791 if (n > 0) { 792 u_int fl_pidx = nm_rxq->fl_pidx; 793 struct netmap_slot *slot = &ring->slot[fl_pidx]; 794 uint64_t ba; 795 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx; 796 797 /* 798 * We always deal with 8 buffers at a time. We must have 799 * stopped at an 8B boundary (fl_pidx) last time around and we 800 * must have a multiple of 8B buffers to give to the freelist. 801 */ 802 MPASS((fl_pidx & 7) == 0); 803 MPASS((n & 7) == 0); 804 805 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots); 806 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx); 807 808 while (n > 0) { 809 for (i = 0; i < 8; i++, fl_pidx++, slot++) { 810 PNMB(na, slot, &ba); 811 MPASS(ba != 0); 812 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx); 813 slot->flags &= ~NS_BUF_CHANGED; 814 MPASS(fl_pidx <= nm_rxq->fl_sidx); 815 } 816 n -= 8; 817 if (fl_pidx == nm_rxq->fl_sidx) { 818 fl_pidx = 0; 819 slot = &ring->slot[0]; 820 } 821 if (++dbinc == 8 && n >= 32) { 822 wmb(); 823 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 824 nm_rxq->fl_db_val | V_PIDX(dbinc)); 825 dbinc = 0; 826 } 827 } 828 MPASS(nm_rxq->fl_pidx == fl_pidx); 829 830 if (dbinc > 0) { 831 wmb(); 832 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 833 nm_rxq->fl_db_val | V_PIDX(dbinc)); 834 } 835 } 836 837 nm_rxsync_finalize(kring); 838 839 return (0); 840} 841 842void 843cxgbe_nm_attach(struct vi_info *vi) 844{ 845 struct port_info *pi; 846 struct adapter *sc; 847 struct netmap_adapter na; 848 849 MPASS(vi->nnmrxq > 0); 850 MPASS(vi->ifp != NULL); 851 852 pi = vi->pi; 853 sc = pi->adapter; 854 855 bzero(&na, sizeof(na)); 856 857 na.ifp = vi->ifp; 858 na.na_flags = NAF_BDG_MAYSLEEP; 859 860 /* Netmap doesn't know about the space reserved for the status page. */ 861 na.num_tx_desc = vi->qsize_txq - sc->params.sge.spg_len / EQ_ESIZE; 862 863 /* 864 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So 865 * num_rx_desc is based on the number of buffers that can be held in the 866 * freelist, and not the number of entries in the iq. (These two are 867 * not exactly the same due to the space taken up by the status page). 868 */ 869 na.num_rx_desc = (vi->qsize_rxq / 8) * 8; 870 na.nm_txsync = cxgbe_netmap_txsync; 871 na.nm_rxsync = cxgbe_netmap_rxsync; 872 na.nm_register = cxgbe_netmap_reg; 873 na.num_tx_rings = vi->nnmtxq; 874 na.num_rx_rings = vi->nnmrxq; 875 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */ 876} 877 878void 879cxgbe_nm_detach(struct vi_info *vi) 880{ 881 882 MPASS(vi->nnmrxq > 0); 883 MPASS(vi->ifp != NULL); 884 885 netmap_detach(vi->ifp); 886} 887 888static void 889handle_nm_fw6_msg(struct adapter *sc, struct ifnet *ifp, 890 const struct cpl_fw6_msg *cpl) 891{ 892 const struct cpl_sge_egr_update *egr; 893 uint32_t oq; 894 struct sge_nm_txq *nm_txq; 895 896 if (cpl->type != FW_TYPE_RSSCPL && cpl->type != FW6_TYPE_RSSCPL) 897 panic("%s: FW_TYPE 0x%x on nm_rxq.", __func__, cpl->type); 898 899 /* data[0] is RSS header */ 900 egr = (const void *)&cpl->data[1]; 901 oq = be32toh(egr->opcode_qid); 902 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE); 903 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start]; 904 905 netmap_tx_irq(ifp, nm_txq->nid); 906} 907 908void 909t4_nm_intr(void *arg) 910{ 911 struct sge_nm_rxq *nm_rxq = arg; 912 struct vi_info *vi = nm_rxq->vi; 913 struct adapter *sc = vi->pi->adapter; 914 struct ifnet *ifp = vi->ifp; 915 struct netmap_adapter *na = NA(ifp); 916 struct netmap_kring *kring = &na->rx_rings[nm_rxq->nid]; 917 struct netmap_ring *ring = kring->ring; 918 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx]; 919 uint32_t lq; 920 u_int n = 0, work = 0; 921 uint8_t opcode; 922 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx); 923 u_int fl_credits = fl_cidx & 7; 924 925 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) { 926 927 rmb(); 928 929 lq = be32toh(d->rsp.pldbuflen_qid); 930 opcode = d->rss.opcode; 931 932 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) { 933 case X_RSPD_TYPE_FLBUF: 934 if (black_hole != 2) { 935 /* No buffer packing so new buf every time */ 936 MPASS(lq & F_RSPD_NEWBUF); 937 } 938 939 /* fall through */ 940 941 case X_RSPD_TYPE_CPL: 942 MPASS(opcode < NUM_CPL_CMDS); 943 944 switch (opcode) { 945 case CPL_FW4_MSG: 946 case CPL_FW6_MSG: 947 handle_nm_fw6_msg(sc, ifp, 948 (const void *)&d->cpl[0]); 949 break; 950 case CPL_RX_PKT: 951 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - 952 sc->params.sge.fl_pktshift; 953 ring->slot[fl_cidx].flags = kring->nkr_slot_flags; 954 fl_cidx += (lq & F_RSPD_NEWBUF) ? 1 : 0; 955 fl_credits += (lq & F_RSPD_NEWBUF) ? 1 : 0; 956 if (__predict_false(fl_cidx == nm_rxq->fl_sidx)) 957 fl_cidx = 0; 958 break; 959 default: 960 panic("%s: unexpected opcode 0x%x on nm_rxq %p", 961 __func__, opcode, nm_rxq); 962 } 963 break; 964 965 case X_RSPD_TYPE_INTR: 966 /* Not equipped to handle forwarded interrupts. */ 967 panic("%s: netmap queue received interrupt for iq %u\n", 968 __func__, lq); 969 970 default: 971 panic("%s: illegal response type %d on nm_rxq %p", 972 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq); 973 } 974 975 d++; 976 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) { 977 nm_rxq->iq_cidx = 0; 978 d = &nm_rxq->iq_desc[0]; 979 nm_rxq->iq_gen ^= F_RSPD_GEN; 980 } 981 982 if (__predict_false(++n == rx_ndesc)) { 983 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 984 if (black_hole && fl_credits >= 8) { 985 fl_credits /= 8; 986 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, 987 nm_rxq->fl_sidx); 988 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 989 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 990 fl_credits = fl_cidx & 7; 991 } else if (!black_hole) { 992 netmap_rx_irq(ifp, nm_rxq->nid, &work); 993 MPASS(work != 0); 994 } 995 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), 996 V_CIDXINC(n) | V_INGRESSQID(nm_rxq->iq_cntxt_id) | 997 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX))); 998 n = 0; 999 } 1000 } 1001 1002 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx); 1003 if (black_hole) { 1004 fl_credits /= 8; 1005 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx); 1006 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), 1007 nm_rxq->fl_db_val | V_PIDX(fl_credits)); 1008 } else 1009 netmap_rx_irq(ifp, nm_rxq->nid, &work); 1010 1011 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(n) | 1012 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) | 1013 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx))); 1014} 1015#endif 1016