qp.c revision 308304
1/* 2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: stable/10/sys/dev/cxgbe/iw_cxgbe/qp.c 308304 2016-11-04 18:45:06Z jhb $"); 34 35#include "opt_inet.h" 36 37#ifdef TCP_OFFLOAD 38#include <sys/types.h> 39#include <sys/malloc.h> 40#include <sys/socket.h> 41#include <sys/socketvar.h> 42#include <sys/sockio.h> 43#include <sys/taskqueue.h> 44#include <netinet/in.h> 45#include <net/route.h> 46 47#include <netinet/in_systm.h> 48#include <netinet/in_pcb.h> 49#include <netinet/ip.h> 50#include <netinet/ip_var.h> 51#include <netinet/tcp_var.h> 52#include <netinet/tcp.h> 53#include <netinet/tcpip.h> 54 55#include <netinet/toecore.h> 56 57struct sge_iq; 58struct rss_header; 59#include <linux/types.h> 60#include "offload.h" 61#include "tom/t4_tom.h" 62 63#include "iw_cxgbe.h" 64#include "user.h" 65 66extern int db_delay_usecs; 67extern int db_fc_threshold; 68static void creds(struct toepcb *toep, size_t wrsize); 69 70 71static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state) 72{ 73 unsigned long flag; 74 spin_lock_irqsave(&qhp->lock, flag); 75 qhp->attr.state = state; 76 spin_unlock_irqrestore(&qhp->lock, flag); 77} 78 79static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 80{ 81 82 contigfree(sq->queue, sq->memsize, M_DEVBUF); 83} 84 85static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 86{ 87 88 dealloc_host_sq(rdev, sq); 89} 90 91static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq) 92{ 93 sq->queue = contigmalloc(sq->memsize, M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 94 4096, 0); 95 96 if (sq->queue) 97 sq->dma_addr = vtophys(sq->queue); 98 else 99 return -ENOMEM; 100 sq->phys_addr = vtophys(sq->queue); 101 pci_unmap_addr_set(sq, mapping, sq->dma_addr); 102 CTR4(KTR_IW_CXGBE, "%s sq %p dma_addr %p phys_addr %p", __func__, 103 sq->queue, sq->dma_addr, sq->phys_addr); 104 return 0; 105} 106 107static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 108 struct c4iw_dev_ucontext *uctx) 109{ 110 /* 111 * uP clears EQ contexts when the connection exits rdma mode, 112 * so no need to post a RESET WR for these EQs. 113 */ 114 contigfree(wq->rq.queue, wq->rq.memsize, M_DEVBUF); 115 dealloc_sq(rdev, &wq->sq); 116 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 117 kfree(wq->rq.sw_rq); 118 kfree(wq->sq.sw_sq); 119 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 120 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 121 return 0; 122} 123 124static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, 125 struct t4_cq *rcq, struct t4_cq *scq, 126 struct c4iw_dev_ucontext *uctx) 127{ 128 struct adapter *sc = rdev->adap; 129 int user = (uctx != &rdev->uctx); 130 struct fw_ri_res_wr *res_wr; 131 struct fw_ri_res *res; 132 int wr_len; 133 struct c4iw_wr_wait wr_wait; 134 int ret; 135 int eqsize; 136 struct wrqe *wr; 137 138 wq->sq.qid = c4iw_get_qpid(rdev, uctx); 139 if (!wq->sq.qid) 140 return -ENOMEM; 141 142 wq->rq.qid = c4iw_get_qpid(rdev, uctx); 143 if (!wq->rq.qid) 144 goto err1; 145 146 if (!user) { 147 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq, 148 GFP_KERNEL); 149 if (!wq->sq.sw_sq) 150 goto err2; 151 152 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq, 153 GFP_KERNEL); 154 if (!wq->rq.sw_rq) 155 goto err3; 156 } 157 158 /* RQT must be a power of 2. */ 159 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size); 160 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size); 161 if (!wq->rq.rqt_hwaddr) 162 goto err4; 163 164 if (alloc_host_sq(rdev, &wq->sq)) 165 goto err5; 166 167 memset(wq->sq.queue, 0, wq->sq.memsize); 168 pci_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr); 169 170 wq->rq.queue = contigmalloc(wq->rq.memsize, 171 M_DEVBUF, M_NOWAIT, 0ul, ~0ul, 4096, 0); 172 if (wq->rq.queue) 173 wq->rq.dma_addr = vtophys(wq->rq.queue); 174 else 175 goto err6; 176 CTR5(KTR_IW_CXGBE, 177 "%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx", __func__, 178 wq->sq.queue, (unsigned long long)vtophys(wq->sq.queue), 179 wq->rq.queue, (unsigned long long)vtophys(wq->rq.queue)); 180 memset(wq->rq.queue, 0, wq->rq.memsize); 181 pci_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr); 182 183 wq->db = (void *)((unsigned long)rman_get_virtual(sc->regs_res) + 184 MYPF_REG(SGE_PF_KDOORBELL)); 185 wq->gts = (void *)((unsigned long)rman_get_virtual(rdev->adap->regs_res) 186 + MYPF_REG(SGE_PF_GTS)); 187 if (user) { 188 wq->sq.udb = (u64)((char*)rman_get_virtual(rdev->adap->udbs_res) + 189 (wq->sq.qid << rdev->qpshift)); 190 wq->sq.udb &= PAGE_MASK; 191 wq->rq.udb = (u64)((char*)rman_get_virtual(rdev->adap->udbs_res) + 192 (wq->rq.qid << rdev->qpshift)); 193 wq->rq.udb &= PAGE_MASK; 194 } 195 wq->rdev = rdev; 196 wq->rq.msn = 1; 197 198 /* build fw_ri_res_wr */ 199 wr_len = sizeof *res_wr + 2 * sizeof *res; 200 201 wr = alloc_wrqe(wr_len, &sc->sge.mgmtq); 202 if (wr == NULL) 203 return (0); 204 res_wr = wrtod(wr); 205 206 memset(res_wr, 0, wr_len); 207 res_wr->op_nres = cpu_to_be32( 208 V_FW_WR_OP(FW_RI_RES_WR) | 209 V_FW_RI_RES_WR_NRES(2) | 210 F_FW_WR_COMPL); 211 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); 212 res_wr->cookie = (unsigned long) &wr_wait; 213 res = res_wr->res; 214 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ; 215 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 216 217 /* eqsize is the number of 64B entries plus the status page size. */ 218 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + 219 (sc->params.sge.spg_len / EQ_ESIZE); 220 221 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 222 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 223 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 224 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 225 V_FW_RI_RES_WR_IQID(scq->cqid)); 226 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 227 V_FW_RI_RES_WR_DCAEN(0) | 228 V_FW_RI_RES_WR_DCACPU(0) | 229 V_FW_RI_RES_WR_FBMIN(2) | 230 V_FW_RI_RES_WR_FBMAX(2) | 231 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 232 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 233 V_FW_RI_RES_WR_EQSIZE(eqsize)); 234 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid); 235 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr); 236 res++; 237 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ; 238 res->u.sqrq.op = FW_RI_RES_OP_WRITE; 239 240 /* eqsize is the number of 64B entries plus the status page size. */ 241 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + 242 (sc->params.sge.spg_len / EQ_ESIZE); 243 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( 244 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ 245 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ 246 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */ 247 V_FW_RI_RES_WR_IQID(rcq->cqid)); 248 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32( 249 V_FW_RI_RES_WR_DCAEN(0) | 250 V_FW_RI_RES_WR_DCACPU(0) | 251 V_FW_RI_RES_WR_FBMIN(2) | 252 V_FW_RI_RES_WR_FBMAX(2) | 253 V_FW_RI_RES_WR_CIDXFTHRESHO(0) | 254 V_FW_RI_RES_WR_CIDXFTHRESH(0) | 255 V_FW_RI_RES_WR_EQSIZE(eqsize)); 256 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid); 257 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr); 258 259 c4iw_init_wr_wait(&wr_wait); 260 261 t4_wrq_tx(sc, wr); 262 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__); 263 if (ret) 264 goto err7; 265 266 CTR6(KTR_IW_CXGBE, 267 "%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx", 268 __func__, wq->sq.qid, wq->rq.qid, wq->db, 269 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb); 270 271 return 0; 272err7: 273 contigfree(wq->rq.queue, wq->rq.memsize, M_DEVBUF); 274err6: 275 dealloc_sq(rdev, &wq->sq); 276err5: 277 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size); 278err4: 279 kfree(wq->rq.sw_rq); 280err3: 281 kfree(wq->sq.sw_sq); 282err2: 283 c4iw_put_qpid(rdev, wq->rq.qid, uctx); 284err1: 285 c4iw_put_qpid(rdev, wq->sq.qid, uctx); 286 return -ENOMEM; 287} 288 289static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp, 290 struct ib_send_wr *wr, int max, u32 *plenp) 291{ 292 u8 *dstp, *srcp; 293 u32 plen = 0; 294 int i; 295 int rem, len; 296 297 dstp = (u8 *)immdp->data; 298 for (i = 0; i < wr->num_sge; i++) { 299 if ((plen + wr->sg_list[i].length) > max) 300 return -EMSGSIZE; 301 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr; 302 plen += wr->sg_list[i].length; 303 rem = wr->sg_list[i].length; 304 while (rem) { 305 if (dstp == (u8 *)&sq->queue[sq->size]) 306 dstp = (u8 *)sq->queue; 307 if (rem <= (u8 *)&sq->queue[sq->size] - dstp) 308 len = rem; 309 else 310 len = (u8 *)&sq->queue[sq->size] - dstp; 311 memcpy(dstp, srcp, len); 312 dstp += len; 313 srcp += len; 314 rem -= len; 315 } 316 } 317 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp); 318 if (len) 319 memset(dstp, 0, len); 320 immdp->op = FW_RI_DATA_IMMD; 321 immdp->r1 = 0; 322 immdp->r2 = 0; 323 immdp->immdlen = cpu_to_be32(plen); 324 *plenp = plen; 325 return 0; 326} 327 328static int build_isgl(__be64 *queue_start, __be64 *queue_end, 329 struct fw_ri_isgl *isglp, struct ib_sge *sg_list, 330 int num_sge, u32 *plenp) 331 332{ 333 int i; 334 u32 plen = 0; 335 __be64 *flitp = (__be64 *)isglp->sge; 336 337 for (i = 0; i < num_sge; i++) { 338 if ((plen + sg_list[i].length) < plen) 339 return -EMSGSIZE; 340 plen += sg_list[i].length; 341 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) | 342 sg_list[i].length); 343 if (++flitp == queue_end) 344 flitp = queue_start; 345 *flitp = cpu_to_be64(sg_list[i].addr); 346 if (++flitp == queue_end) 347 flitp = queue_start; 348 } 349 *flitp = (__force __be64)0; 350 isglp->op = FW_RI_DATA_ISGL; 351 isglp->r1 = 0; 352 isglp->nsge = cpu_to_be16(num_sge); 353 isglp->r2 = 0; 354 if (plenp) 355 *plenp = plen; 356 return 0; 357} 358 359static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe, 360 struct ib_send_wr *wr, u8 *len16) 361{ 362 u32 plen; 363 int size; 364 int ret; 365 366 if (wr->num_sge > T4_MAX_SEND_SGE) 367 return -EINVAL; 368 switch (wr->opcode) { 369 case IB_WR_SEND: 370 if (wr->send_flags & IB_SEND_SOLICITED) 371 wqe->send.sendop_pkd = cpu_to_be32( 372 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE)); 373 else 374 wqe->send.sendop_pkd = cpu_to_be32( 375 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND)); 376 wqe->send.stag_inv = 0; 377 break; 378 case IB_WR_SEND_WITH_INV: 379 if (wr->send_flags & IB_SEND_SOLICITED) 380 wqe->send.sendop_pkd = cpu_to_be32( 381 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV)); 382 else 383 wqe->send.sendop_pkd = cpu_to_be32( 384 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV)); 385 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 386 break; 387 388 default: 389 return -EINVAL; 390 } 391 392 plen = 0; 393 if (wr->num_sge) { 394 if (wr->send_flags & IB_SEND_INLINE) { 395 ret = build_immd(sq, wqe->send.u.immd_src, wr, 396 T4_MAX_SEND_INLINE, &plen); 397 if (ret) 398 return ret; 399 size = sizeof wqe->send + sizeof(struct fw_ri_immd) + 400 plen; 401 } else { 402 ret = build_isgl((__be64 *)sq->queue, 403 (__be64 *)&sq->queue[sq->size], 404 wqe->send.u.isgl_src, 405 wr->sg_list, wr->num_sge, &plen); 406 if (ret) 407 return ret; 408 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) + 409 wr->num_sge * sizeof(struct fw_ri_sge); 410 } 411 } else { 412 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD; 413 wqe->send.u.immd_src[0].r1 = 0; 414 wqe->send.u.immd_src[0].r2 = 0; 415 wqe->send.u.immd_src[0].immdlen = 0; 416 size = sizeof wqe->send + sizeof(struct fw_ri_immd); 417 plen = 0; 418 } 419 *len16 = DIV_ROUND_UP(size, 16); 420 wqe->send.plen = cpu_to_be32(plen); 421 return 0; 422} 423 424static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe, 425 struct ib_send_wr *wr, u8 *len16) 426{ 427 u32 plen; 428 int size; 429 int ret; 430 431 if (wr->num_sge > T4_MAX_SEND_SGE) 432 return -EINVAL; 433 wqe->write.r2 = 0; 434 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey); 435 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr); 436 if (wr->num_sge) { 437 if (wr->send_flags & IB_SEND_INLINE) { 438 ret = build_immd(sq, wqe->write.u.immd_src, wr, 439 T4_MAX_WRITE_INLINE, &plen); 440 if (ret) 441 return ret; 442 size = sizeof wqe->write + sizeof(struct fw_ri_immd) + 443 plen; 444 } else { 445 ret = build_isgl((__be64 *)sq->queue, 446 (__be64 *)&sq->queue[sq->size], 447 wqe->write.u.isgl_src, 448 wr->sg_list, wr->num_sge, &plen); 449 if (ret) 450 return ret; 451 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) + 452 wr->num_sge * sizeof(struct fw_ri_sge); 453 } 454 } else { 455 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD; 456 wqe->write.u.immd_src[0].r1 = 0; 457 wqe->write.u.immd_src[0].r2 = 0; 458 wqe->write.u.immd_src[0].immdlen = 0; 459 size = sizeof wqe->write + sizeof(struct fw_ri_immd); 460 plen = 0; 461 } 462 *len16 = DIV_ROUND_UP(size, 16); 463 wqe->write.plen = cpu_to_be32(plen); 464 return 0; 465} 466 467static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16) 468{ 469 if (wr->num_sge > 1) 470 return -EINVAL; 471 if (wr->num_sge) { 472 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey); 473 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr 474 >> 32)); 475 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr); 476 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey); 477 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length); 478 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr 479 >> 32)); 480 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr)); 481 } else { 482 wqe->read.stag_src = cpu_to_be32(2); 483 wqe->read.to_src_hi = 0; 484 wqe->read.to_src_lo = 0; 485 wqe->read.stag_sink = cpu_to_be32(2); 486 wqe->read.plen = 0; 487 wqe->read.to_sink_hi = 0; 488 wqe->read.to_sink_lo = 0; 489 } 490 wqe->read.r2 = 0; 491 wqe->read.r5 = 0; 492 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 493 return 0; 494} 495 496static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe, 497 struct ib_recv_wr *wr, u8 *len16) 498{ 499 int ret; 500 501 ret = build_isgl((__be64 *)qhp->wq.rq.queue, 502 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size], 503 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL); 504 if (ret) 505 return ret; 506 *len16 = DIV_ROUND_UP(sizeof wqe->recv + 507 wr->num_sge * sizeof(struct fw_ri_sge), 16); 508 return 0; 509} 510 511static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe, 512 struct ib_send_wr *wr, u8 *len16) 513{ 514 515 struct fw_ri_immd *imdp; 516 __be64 *p; 517 int i; 518 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32); 519 int rem; 520 521 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH) 522 return -EINVAL; 523 524 wqe->fr.qpbinde_to_dcacpu = 0; 525 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12; 526 wqe->fr.addr_type = FW_RI_VA_BASED_TO; 527 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags); 528 wqe->fr.len_hi = 0; 529 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length); 530 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey); 531 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32); 532 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start & 533 0xffffffff); 534 WARN_ON(pbllen > T4_MAX_FR_IMMD); 535 imdp = (struct fw_ri_immd *)(&wqe->fr + 1); 536 imdp->op = FW_RI_DATA_IMMD; 537 imdp->r1 = 0; 538 imdp->r2 = 0; 539 imdp->immdlen = cpu_to_be32(pbllen); 540 p = (__be64 *)(imdp + 1); 541 rem = pbllen; 542 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) { 543 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]); 544 rem -= sizeof *p; 545 if (++p == (__be64 *)&sq->queue[sq->size]) 546 p = (__be64 *)sq->queue; 547 } 548 BUG_ON(rem < 0); 549 while (rem) { 550 *p = 0; 551 rem -= sizeof *p; 552 if (++p == (__be64 *)&sq->queue[sq->size]) 553 p = (__be64 *)sq->queue; 554 } 555 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16); 556 return 0; 557} 558 559static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, 560 u8 *len16) 561{ 562 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); 563 wqe->inv.r2 = 0; 564 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); 565 return 0; 566} 567 568void c4iw_qp_add_ref(struct ib_qp *qp) 569{ 570 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 571 atomic_inc(&(to_c4iw_qp(qp)->refcnt)); 572} 573 574void c4iw_qp_rem_ref(struct ib_qp *qp) 575{ 576 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, qp); 577 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt))) 578 wake_up(&(to_c4iw_qp(qp)->wait)); 579} 580 581int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 582 struct ib_send_wr **bad_wr) 583{ 584 int err = 0; 585 u8 len16 = 0; 586 enum fw_wr_opcodes fw_opcode = 0; 587 enum fw_ri_wr_flags fw_flags; 588 struct c4iw_qp *qhp; 589 union t4_wr *wqe; 590 u32 num_wrs; 591 struct t4_swsqe *swsqe; 592 unsigned long flag; 593 u16 idx = 0; 594 595 qhp = to_c4iw_qp(ibqp); 596 spin_lock_irqsave(&qhp->lock, flag); 597 if (t4_wq_in_error(&qhp->wq)) { 598 spin_unlock_irqrestore(&qhp->lock, flag); 599 return -EINVAL; 600 } 601 num_wrs = t4_sq_avail(&qhp->wq); 602 if (num_wrs == 0) { 603 spin_unlock_irqrestore(&qhp->lock, flag); 604 return -ENOMEM; 605 } 606 while (wr) { 607 if (num_wrs == 0) { 608 err = -ENOMEM; 609 *bad_wr = wr; 610 break; 611 } 612 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue + 613 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE); 614 615 fw_flags = 0; 616 if (wr->send_flags & IB_SEND_SOLICITED) 617 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG; 618 if (wr->send_flags & IB_SEND_SIGNALED) 619 fw_flags |= FW_RI_COMPLETION_FLAG; 620 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx]; 621 switch (wr->opcode) { 622 case IB_WR_SEND_WITH_INV: 623 case IB_WR_SEND: 624 if (wr->send_flags & IB_SEND_FENCE) 625 fw_flags |= FW_RI_READ_FENCE_FLAG; 626 fw_opcode = FW_RI_SEND_WR; 627 if (wr->opcode == IB_WR_SEND) 628 swsqe->opcode = FW_RI_SEND; 629 else 630 swsqe->opcode = FW_RI_SEND_WITH_INV; 631 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16); 632 break; 633 case IB_WR_RDMA_WRITE: 634 fw_opcode = FW_RI_RDMA_WRITE_WR; 635 swsqe->opcode = FW_RI_RDMA_WRITE; 636 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16); 637 break; 638 case IB_WR_RDMA_READ: 639 case IB_WR_RDMA_READ_WITH_INV: 640 fw_opcode = FW_RI_RDMA_READ_WR; 641 swsqe->opcode = FW_RI_READ_REQ; 642 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) 643 fw_flags = FW_RI_RDMA_READ_INVALIDATE; 644 else 645 fw_flags = 0; 646 err = build_rdma_read(wqe, wr, &len16); 647 if (err) 648 break; 649 swsqe->read_len = wr->sg_list[0].length; 650 if (!qhp->wq.sq.oldest_read) 651 qhp->wq.sq.oldest_read = swsqe; 652 break; 653 case IB_WR_FAST_REG_MR: 654 fw_opcode = FW_RI_FR_NSMR_WR; 655 swsqe->opcode = FW_RI_FAST_REGISTER; 656 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16); 657 break; 658 case IB_WR_LOCAL_INV: 659 if (wr->send_flags & IB_SEND_FENCE) 660 fw_flags |= FW_RI_LOCAL_FENCE_FLAG; 661 fw_opcode = FW_RI_INV_LSTAG_WR; 662 swsqe->opcode = FW_RI_LOCAL_INV; 663 err = build_inv_stag(wqe, wr, &len16); 664 break; 665 default: 666 CTR2(KTR_IW_CXGBE, "%s post of type =%d TBD!", __func__, 667 wr->opcode); 668 err = -EINVAL; 669 } 670 if (err) { 671 *bad_wr = wr; 672 break; 673 } 674 swsqe->idx = qhp->wq.sq.pidx; 675 swsqe->complete = 0; 676 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED); 677 swsqe->wr_id = wr->wr_id; 678 679 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16); 680 681 CTR5(KTR_IW_CXGBE, 682 "%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u", 683 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx, 684 swsqe->opcode, swsqe->read_len); 685 wr = wr->next; 686 num_wrs--; 687 t4_sq_produce(&qhp->wq, len16); 688 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 689 } 690 if (t4_wq_db_enabled(&qhp->wq)) 691 t4_ring_sq_db(&qhp->wq, idx); 692 spin_unlock_irqrestore(&qhp->lock, flag); 693 return err; 694} 695 696int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, 697 struct ib_recv_wr **bad_wr) 698{ 699 int err = 0; 700 struct c4iw_qp *qhp; 701 union t4_recv_wr *wqe; 702 u32 num_wrs; 703 u8 len16 = 0; 704 unsigned long flag; 705 u16 idx = 0; 706 707 qhp = to_c4iw_qp(ibqp); 708 spin_lock_irqsave(&qhp->lock, flag); 709 if (t4_wq_in_error(&qhp->wq)) { 710 spin_unlock_irqrestore(&qhp->lock, flag); 711 return -EINVAL; 712 } 713 num_wrs = t4_rq_avail(&qhp->wq); 714 if (num_wrs == 0) { 715 spin_unlock_irqrestore(&qhp->lock, flag); 716 return -ENOMEM; 717 } 718 while (wr) { 719 if (wr->num_sge > T4_MAX_RECV_SGE) { 720 err = -EINVAL; 721 *bad_wr = wr; 722 break; 723 } 724 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue + 725 qhp->wq.rq.wq_pidx * 726 T4_EQ_ENTRY_SIZE); 727 if (num_wrs) 728 err = build_rdma_recv(qhp, wqe, wr, &len16); 729 else 730 err = -ENOMEM; 731 if (err) { 732 *bad_wr = wr; 733 break; 734 } 735 736 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id; 737 738 wqe->recv.opcode = FW_RI_RECV_WR; 739 wqe->recv.r1 = 0; 740 wqe->recv.wrid = qhp->wq.rq.pidx; 741 wqe->recv.r2[0] = 0; 742 wqe->recv.r2[1] = 0; 743 wqe->recv.r2[2] = 0; 744 wqe->recv.len16 = len16; 745 CTR3(KTR_IW_CXGBE, "%s cookie 0x%llx pidx %u", __func__, 746 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx); 747 t4_rq_produce(&qhp->wq, len16); 748 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); 749 wr = wr->next; 750 num_wrs--; 751 } 752 if (t4_wq_db_enabled(&qhp->wq)) 753 t4_ring_rq_db(&qhp->wq, idx); 754 spin_unlock_irqrestore(&qhp->lock, flag); 755 return err; 756} 757 758int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind) 759{ 760 return -ENOSYS; 761} 762 763static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type, 764 u8 *ecode) 765{ 766 int status; 767 int tagged; 768 int opcode; 769 int rqtype; 770 int send_inv; 771 772 if (!err_cqe) { 773 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 774 *ecode = 0; 775 return; 776 } 777 778 status = CQE_STATUS(err_cqe); 779 opcode = CQE_OPCODE(err_cqe); 780 rqtype = RQ_TYPE(err_cqe); 781 send_inv = (opcode == FW_RI_SEND_WITH_INV) || 782 (opcode == FW_RI_SEND_WITH_SE_INV); 783 tagged = (opcode == FW_RI_RDMA_WRITE) || 784 (rqtype && (opcode == FW_RI_READ_RESP)); 785 786 switch (status) { 787 case T4_ERR_STAG: 788 if (send_inv) { 789 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 790 *ecode = RDMAP_CANT_INV_STAG; 791 } else { 792 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 793 *ecode = RDMAP_INV_STAG; 794 } 795 break; 796 case T4_ERR_PDID: 797 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 798 if ((opcode == FW_RI_SEND_WITH_INV) || 799 (opcode == FW_RI_SEND_WITH_SE_INV)) 800 *ecode = RDMAP_CANT_INV_STAG; 801 else 802 *ecode = RDMAP_STAG_NOT_ASSOC; 803 break; 804 case T4_ERR_QPID: 805 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 806 *ecode = RDMAP_STAG_NOT_ASSOC; 807 break; 808 case T4_ERR_ACCESS: 809 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 810 *ecode = RDMAP_ACC_VIOL; 811 break; 812 case T4_ERR_WRAP: 813 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 814 *ecode = RDMAP_TO_WRAP; 815 break; 816 case T4_ERR_BOUND: 817 if (tagged) { 818 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 819 *ecode = DDPT_BASE_BOUNDS; 820 } else { 821 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT; 822 *ecode = RDMAP_BASE_BOUNDS; 823 } 824 break; 825 case T4_ERR_INVALIDATE_SHARED_MR: 826 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND: 827 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 828 *ecode = RDMAP_CANT_INV_STAG; 829 break; 830 case T4_ERR_ECC: 831 case T4_ERR_ECC_PSTAG: 832 case T4_ERR_INTERNAL_ERR: 833 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA; 834 *ecode = 0; 835 break; 836 case T4_ERR_OUT_OF_RQE: 837 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 838 *ecode = DDPU_INV_MSN_NOBUF; 839 break; 840 case T4_ERR_PBL_ADDR_BOUND: 841 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 842 *ecode = DDPT_BASE_BOUNDS; 843 break; 844 case T4_ERR_CRC: 845 *layer_type = LAYER_MPA|DDP_LLP; 846 *ecode = MPA_CRC_ERR; 847 break; 848 case T4_ERR_MARKER: 849 *layer_type = LAYER_MPA|DDP_LLP; 850 *ecode = MPA_MARKER_ERR; 851 break; 852 case T4_ERR_PDU_LEN_ERR: 853 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 854 *ecode = DDPU_MSG_TOOBIG; 855 break; 856 case T4_ERR_DDP_VERSION: 857 if (tagged) { 858 *layer_type = LAYER_DDP|DDP_TAGGED_ERR; 859 *ecode = DDPT_INV_VERS; 860 } else { 861 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 862 *ecode = DDPU_INV_VERS; 863 } 864 break; 865 case T4_ERR_RDMA_VERSION: 866 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 867 *ecode = RDMAP_INV_VERS; 868 break; 869 case T4_ERR_OPCODE: 870 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP; 871 *ecode = RDMAP_INV_OPCODE; 872 break; 873 case T4_ERR_DDP_QUEUE_NUM: 874 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 875 *ecode = DDPU_INV_QN; 876 break; 877 case T4_ERR_MSN: 878 case T4_ERR_MSN_GAP: 879 case T4_ERR_MSN_RANGE: 880 case T4_ERR_IRD_OVERFLOW: 881 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 882 *ecode = DDPU_INV_MSN_RANGE; 883 break; 884 case T4_ERR_TBIT: 885 *layer_type = LAYER_DDP|DDP_LOCAL_CATA; 886 *ecode = 0; 887 break; 888 case T4_ERR_MO: 889 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR; 890 *ecode = DDPU_INV_MO; 891 break; 892 default: 893 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA; 894 *ecode = 0; 895 break; 896 } 897} 898 899static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 900 gfp_t gfp) 901{ 902 struct fw_ri_wr *wqe; 903 struct terminate_message *term; 904 struct wrqe *wr; 905 struct socket *so = qhp->ep->com.so; 906 struct inpcb *inp = sotoinpcb(so); 907 struct tcpcb *tp = intotcpcb(inp); 908 struct toepcb *toep = tp->t_toe; 909 910 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 911 qhp->wq.sq.qid, qhp->ep->hwtid); 912 913 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 914 if (wr == NULL) 915 return; 916 wqe = wrtod(wr); 917 918 memset(wqe, 0, sizeof *wqe); 919 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR)); 920 wqe->flowid_len16 = cpu_to_be32( 921 V_FW_WR_FLOWID(qhp->ep->hwtid) | 922 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 923 924 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; 925 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); 926 term = (struct terminate_message *)wqe->u.terminate.termmsg; 927 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) { 928 term->layer_etype = qhp->attr.layer_etype; 929 term->ecode = qhp->attr.ecode; 930 } else 931 build_term_codes(err_cqe, &term->layer_etype, &term->ecode); 932 creds(toep, sizeof(*wqe)); 933 t4_wrq_tx(qhp->rhp->rdev.adap, wr); 934} 935 936/* Assumes qhp lock is held. */ 937static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp, 938 struct c4iw_cq *schp) 939{ 940 int count; 941 int flushed; 942 unsigned long flag; 943 944 CTR4(KTR_IW_CXGBE, "%s qhp %p rchp %p schp %p", __func__, qhp, rchp, 945 schp); 946 947 /* locking hierarchy: cq lock first, then qp lock. */ 948 spin_lock_irqsave(&rchp->lock, flag); 949 spin_lock(&qhp->lock); 950 c4iw_flush_hw_cq(&rchp->cq); 951 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count); 952 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count); 953 spin_unlock(&qhp->lock); 954 spin_unlock_irqrestore(&rchp->lock, flag); 955 if (flushed) { 956 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 957 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 958 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 959 } 960 961 /* locking hierarchy: cq lock first, then qp lock. */ 962 spin_lock_irqsave(&schp->lock, flag); 963 spin_lock(&qhp->lock); 964 c4iw_flush_hw_cq(&schp->cq); 965 c4iw_count_scqes(&schp->cq, &qhp->wq, &count); 966 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count); 967 spin_unlock(&qhp->lock); 968 spin_unlock_irqrestore(&schp->lock, flag); 969 if (flushed) { 970 spin_lock_irqsave(&schp->comp_handler_lock, flag); 971 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context); 972 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 973 } 974} 975 976static void flush_qp(struct c4iw_qp *qhp) 977{ 978 struct c4iw_cq *rchp, *schp; 979 unsigned long flag; 980 981 rchp = get_chp(qhp->rhp, qhp->attr.rcq); 982 schp = get_chp(qhp->rhp, qhp->attr.scq); 983 984 if (qhp->ibqp.uobject) { 985 t4_set_wq_in_error(&qhp->wq); 986 t4_set_cq_in_error(&rchp->cq); 987 spin_lock_irqsave(&rchp->comp_handler_lock, flag); 988 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context); 989 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag); 990 if (schp != rchp) { 991 t4_set_cq_in_error(&schp->cq); 992 spin_lock_irqsave(&schp->comp_handler_lock, flag); 993 (*schp->ibcq.comp_handler)(&schp->ibcq, 994 schp->ibcq.cq_context); 995 spin_unlock_irqrestore(&schp->comp_handler_lock, flag); 996 } 997 return; 998 } 999 __flush_qp(qhp, rchp, schp); 1000} 1001 1002static int 1003rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, struct c4iw_ep *ep) 1004{ 1005 struct c4iw_rdev *rdev = &rhp->rdev; 1006 struct adapter *sc = rdev->adap; 1007 struct fw_ri_wr *wqe; 1008 int ret; 1009 struct wrqe *wr; 1010 struct socket *so = ep->com.so; 1011 struct inpcb *inp = sotoinpcb(so); 1012 struct tcpcb *tp = intotcpcb(inp); 1013 struct toepcb *toep = tp->t_toe; 1014 1015 KASSERT(rhp == qhp->rhp && ep == qhp->ep, ("%s: EDOOFUS", __func__)); 1016 1017 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 1018 qhp->wq.sq.qid, ep->hwtid); 1019 1020 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 1021 if (wr == NULL) 1022 return (0); 1023 wqe = wrtod(wr); 1024 1025 memset(wqe, 0, sizeof *wqe); 1026 1027 wqe->op_compl = cpu_to_be32(V_FW_WR_OP(FW_RI_WR) | F_FW_WR_COMPL); 1028 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1029 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1030 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1031 wqe->u.fini.type = FW_RI_TYPE_FINI; 1032 1033 c4iw_init_wr_wait(&ep->com.wr_wait); 1034 1035 creds(toep, sizeof(*wqe)); 1036 t4_wrq_tx(sc, wr); 1037 1038 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1039 qhp->wq.sq.qid, __func__); 1040 return ret; 1041} 1042 1043static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init) 1044{ 1045 CTR2(KTR_IW_CXGBE, "%s p2p_type = %d", __func__, p2p_type); 1046 memset(&init->u, 0, sizeof init->u); 1047 switch (p2p_type) { 1048 case FW_RI_INIT_P2PTYPE_RDMA_WRITE: 1049 init->u.write.opcode = FW_RI_RDMA_WRITE_WR; 1050 init->u.write.stag_sink = cpu_to_be32(1); 1051 init->u.write.to_sink = cpu_to_be64(1); 1052 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD; 1053 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write + 1054 sizeof(struct fw_ri_immd), 1055 16); 1056 break; 1057 case FW_RI_INIT_P2PTYPE_READ_REQ: 1058 init->u.write.opcode = FW_RI_RDMA_READ_WR; 1059 init->u.read.stag_src = cpu_to_be32(1); 1060 init->u.read.to_src_lo = cpu_to_be32(1); 1061 init->u.read.stag_sink = cpu_to_be32(1); 1062 init->u.read.to_sink_lo = cpu_to_be32(1); 1063 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16); 1064 break; 1065 } 1066} 1067 1068static void 1069creds(struct toepcb *toep, size_t wrsize) 1070{ 1071 struct ofld_tx_sdesc *txsd; 1072 1073 CTR3(KTR_IW_CXGBE, "%s:creB %p %u", __func__, toep , wrsize); 1074 INP_WLOCK(toep->inp); 1075 txsd = &toep->txsd[toep->txsd_pidx]; 1076 txsd->tx_credits = howmany(wrsize, 16); 1077 txsd->plen = 0; 1078 KASSERT(toep->tx_credits >= txsd->tx_credits && toep->txsd_avail > 0, 1079 ("%s: not enough credits (%d)", __func__, toep->tx_credits)); 1080 toep->tx_credits -= txsd->tx_credits; 1081 if (__predict_false(++toep->txsd_pidx == toep->txsd_total)) 1082 toep->txsd_pidx = 0; 1083 toep->txsd_avail--; 1084 INP_WUNLOCK(toep->inp); 1085 CTR5(KTR_IW_CXGBE, "%s:creE %p %u %u %u", __func__, toep , 1086 txsd->tx_credits, toep->tx_credits, toep->txsd_pidx); 1087} 1088 1089static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) 1090{ 1091 struct fw_ri_wr *wqe; 1092 int ret; 1093 struct wrqe *wr; 1094 struct c4iw_ep *ep = qhp->ep; 1095 struct c4iw_rdev *rdev = &qhp->rhp->rdev; 1096 struct adapter *sc = rdev->adap; 1097 struct socket *so = ep->com.so; 1098 struct inpcb *inp = sotoinpcb(so); 1099 struct tcpcb *tp = intotcpcb(inp); 1100 struct toepcb *toep = tp->t_toe; 1101 1102 CTR4(KTR_IW_CXGBE, "%s qhp %p qid 0x%x tid %u", __func__, qhp, 1103 qhp->wq.sq.qid, ep->hwtid); 1104 1105 wr = alloc_wrqe(sizeof(*wqe), toep->ofld_txq); 1106 if (wr == NULL) 1107 return (0); 1108 wqe = wrtod(wr); 1109 1110 memset(wqe, 0, sizeof *wqe); 1111 1112 wqe->op_compl = cpu_to_be32( 1113 V_FW_WR_OP(FW_RI_WR) | 1114 F_FW_WR_COMPL); 1115 wqe->flowid_len16 = cpu_to_be32(V_FW_WR_FLOWID(ep->hwtid) | 1116 V_FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); 1117 1118 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1119 1120 wqe->u.init.type = FW_RI_TYPE_INIT; 1121 wqe->u.init.mpareqbit_p2ptype = 1122 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) | 1123 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type); 1124 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE; 1125 if (qhp->attr.mpa_attr.recv_marker_enabled) 1126 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE; 1127 if (qhp->attr.mpa_attr.xmit_marker_enabled) 1128 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE; 1129 if (qhp->attr.mpa_attr.crc_enabled) 1130 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE; 1131 1132 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE | 1133 FW_RI_QP_RDMA_WRITE_ENABLE | 1134 FW_RI_QP_BIND_ENABLE; 1135 if (!qhp->ibqp.uobject) 1136 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE | 1137 FW_RI_QP_STAG0_ENABLE; 1138 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq)); 1139 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd); 1140 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid); 1141 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid); 1142 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid); 1143 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq); 1144 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq); 1145 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord); 1146 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird); 1147 wqe->u.init.iss = cpu_to_be32(ep->snd_seq); 1148 wqe->u.init.irs = cpu_to_be32(ep->rcv_seq); 1149 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size); 1150 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr - 1151 sc->vres.rq.start); 1152 if (qhp->attr.mpa_attr.initiator) 1153 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1154 1155 c4iw_init_wr_wait(&ep->com.wr_wait); 1156 1157 creds(toep, sizeof(*wqe)); 1158 t4_wrq_tx(sc, wr); 1159 1160 ret = c4iw_wait_for_reply(rdev, &ep->com.wr_wait, ep->hwtid, 1161 qhp->wq.sq.qid, __func__); 1162 1163 toep->ulp_mode = ULP_MODE_RDMA; 1164 1165 return ret; 1166} 1167 1168int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp, 1169 enum c4iw_qp_attr_mask mask, 1170 struct c4iw_qp_attributes *attrs, 1171 int internal) 1172{ 1173 int ret = 0; 1174 struct c4iw_qp_attributes newattr = qhp->attr; 1175 int disconnect = 0; 1176 int terminate = 0; 1177 int abort = 0; 1178 int free = 0; 1179 struct c4iw_ep *ep = NULL; 1180 1181 CTR5(KTR_IW_CXGBE, "%s qhp %p sqid 0x%x rqid 0x%x ep %p", __func__, qhp, 1182 qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep); 1183 CTR3(KTR_IW_CXGBE, "%s state %d -> %d", __func__, qhp->attr.state, 1184 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1); 1185 1186 mutex_lock(&qhp->mutex); 1187 1188 /* Process attr changes if in IDLE */ 1189 if (mask & C4IW_QP_ATTR_VALID_MODIFY) { 1190 if (qhp->attr.state != C4IW_QP_STATE_IDLE) { 1191 ret = -EIO; 1192 goto out; 1193 } 1194 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ) 1195 newattr.enable_rdma_read = attrs->enable_rdma_read; 1196 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE) 1197 newattr.enable_rdma_write = attrs->enable_rdma_write; 1198 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND) 1199 newattr.enable_bind = attrs->enable_bind; 1200 if (mask & C4IW_QP_ATTR_MAX_ORD) { 1201 if (attrs->max_ord > c4iw_max_read_depth) { 1202 ret = -EINVAL; 1203 goto out; 1204 } 1205 newattr.max_ord = attrs->max_ord; 1206 } 1207 if (mask & C4IW_QP_ATTR_MAX_IRD) { 1208 if (attrs->max_ird > c4iw_max_read_depth) { 1209 ret = -EINVAL; 1210 goto out; 1211 } 1212 newattr.max_ird = attrs->max_ird; 1213 } 1214 qhp->attr = newattr; 1215 } 1216 1217 if (!(mask & C4IW_QP_ATTR_NEXT_STATE)) 1218 goto out; 1219 if (qhp->attr.state == attrs->next_state) 1220 goto out; 1221 1222 switch (qhp->attr.state) { 1223 case C4IW_QP_STATE_IDLE: 1224 switch (attrs->next_state) { 1225 case C4IW_QP_STATE_RTS: 1226 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) { 1227 ret = -EINVAL; 1228 goto out; 1229 } 1230 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) { 1231 ret = -EINVAL; 1232 goto out; 1233 } 1234 qhp->attr.mpa_attr = attrs->mpa_attr; 1235 qhp->attr.llp_stream_handle = attrs->llp_stream_handle; 1236 qhp->ep = qhp->attr.llp_stream_handle; 1237 set_state(qhp, C4IW_QP_STATE_RTS); 1238 1239 /* 1240 * Ref the endpoint here and deref when we 1241 * disassociate the endpoint from the QP. This 1242 * happens in CLOSING->IDLE transition or *->ERROR 1243 * transition. 1244 */ 1245 c4iw_get_ep(&qhp->ep->com); 1246 ret = rdma_init(rhp, qhp); 1247 if (ret) 1248 goto err; 1249 break; 1250 case C4IW_QP_STATE_ERROR: 1251 set_state(qhp, C4IW_QP_STATE_ERROR); 1252 flush_qp(qhp); 1253 break; 1254 default: 1255 ret = -EINVAL; 1256 goto out; 1257 } 1258 break; 1259 case C4IW_QP_STATE_RTS: 1260 switch (attrs->next_state) { 1261 case C4IW_QP_STATE_CLOSING: 1262 //Fixme: Use atomic_read as same as Linux 1263 BUG_ON(qhp->ep->com.kref.count < 2); 1264 set_state(qhp, C4IW_QP_STATE_CLOSING); 1265 ep = qhp->ep; 1266 if (!internal) { 1267 abort = 0; 1268 disconnect = 1; 1269 c4iw_get_ep(&qhp->ep->com); 1270 } 1271 if (qhp->ibqp.uobject) 1272 t4_set_wq_in_error(&qhp->wq); 1273 ret = rdma_fini(rhp, qhp, ep); 1274 if (ret) 1275 goto err; 1276 break; 1277 case C4IW_QP_STATE_TERMINATE: 1278 set_state(qhp, C4IW_QP_STATE_TERMINATE); 1279 qhp->attr.layer_etype = attrs->layer_etype; 1280 qhp->attr.ecode = attrs->ecode; 1281 if (qhp->ibqp.uobject) 1282 t4_set_wq_in_error(&qhp->wq); 1283 ep = qhp->ep; 1284 if (!internal) 1285 terminate = 1; 1286 disconnect = 1; 1287 c4iw_get_ep(&qhp->ep->com); 1288 break; 1289 case C4IW_QP_STATE_ERROR: 1290 set_state(qhp, C4IW_QP_STATE_ERROR); 1291 if (qhp->ibqp.uobject) 1292 t4_set_wq_in_error(&qhp->wq); 1293 if (!internal) { 1294 abort = 1; 1295 disconnect = 1; 1296 ep = qhp->ep; 1297 c4iw_get_ep(&qhp->ep->com); 1298 } 1299 goto err; 1300 break; 1301 default: 1302 ret = -EINVAL; 1303 goto out; 1304 } 1305 break; 1306 case C4IW_QP_STATE_CLOSING: 1307 if (!internal) { 1308 ret = -EINVAL; 1309 goto out; 1310 } 1311 switch (attrs->next_state) { 1312 case C4IW_QP_STATE_IDLE: 1313 flush_qp(qhp); 1314 set_state(qhp, C4IW_QP_STATE_IDLE); 1315 qhp->attr.llp_stream_handle = NULL; 1316 c4iw_put_ep(&qhp->ep->com); 1317 qhp->ep = NULL; 1318 wake_up(&qhp->wait); 1319 break; 1320 case C4IW_QP_STATE_ERROR: 1321 goto err; 1322 default: 1323 ret = -EINVAL; 1324 goto err; 1325 } 1326 break; 1327 case C4IW_QP_STATE_ERROR: 1328 if (attrs->next_state != C4IW_QP_STATE_IDLE) { 1329 ret = -EINVAL; 1330 goto out; 1331 } 1332 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) { 1333 ret = -EINVAL; 1334 goto out; 1335 } 1336 set_state(qhp, C4IW_QP_STATE_IDLE); 1337 break; 1338 case C4IW_QP_STATE_TERMINATE: 1339 if (!internal) { 1340 ret = -EINVAL; 1341 goto out; 1342 } 1343 goto err; 1344 break; 1345 default: 1346 printf("%s in a bad state %d\n", 1347 __func__, qhp->attr.state); 1348 ret = -EINVAL; 1349 goto err; 1350 break; 1351 } 1352 goto out; 1353err: 1354 CTR3(KTR_IW_CXGBE, "%s disassociating ep %p qpid 0x%x", __func__, 1355 qhp->ep, qhp->wq.sq.qid); 1356 1357 /* disassociate the LLP connection */ 1358 qhp->attr.llp_stream_handle = NULL; 1359 if (!ep) 1360 ep = qhp->ep; 1361 qhp->ep = NULL; 1362 set_state(qhp, C4IW_QP_STATE_ERROR); 1363 free = 1; 1364 BUG_ON(!ep); 1365 flush_qp(qhp); 1366 wake_up(&qhp->wait); 1367out: 1368 mutex_unlock(&qhp->mutex); 1369 1370 if (terminate) 1371 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL); 1372 1373 /* 1374 * If disconnect is 1, then we need to initiate a disconnect 1375 * on the EP. This can be a normal close (RTS->CLOSING) or 1376 * an abnormal close (RTS/CLOSING->ERROR). 1377 */ 1378 if (disconnect) { 1379 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC : 1380 GFP_KERNEL); 1381 c4iw_put_ep(&ep->com); 1382 } 1383 1384 /* 1385 * If free is 1, then we've disassociated the EP from the QP 1386 * and we need to dereference the EP. 1387 */ 1388 if (free) 1389 c4iw_put_ep(&ep->com); 1390 CTR2(KTR_IW_CXGBE, "%s exit state %d", __func__, qhp->attr.state); 1391 return ret; 1392} 1393 1394static int enable_qp_db(int id, void *p, void *data) 1395{ 1396 struct c4iw_qp *qp = p; 1397 1398 t4_enable_wq_db(&qp->wq); 1399 return 0; 1400} 1401 1402int c4iw_destroy_qp(struct ib_qp *ib_qp) 1403{ 1404 struct c4iw_dev *rhp; 1405 struct c4iw_qp *qhp; 1406 struct c4iw_qp_attributes attrs; 1407 struct c4iw_ucontext *ucontext; 1408 1409 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ib_qp); 1410 qhp = to_c4iw_qp(ib_qp); 1411 rhp = qhp->rhp; 1412 1413 attrs.next_state = C4IW_QP_STATE_ERROR; 1414 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE) 1415 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1); 1416 else 1417 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0); 1418 wait_event(qhp->wait, !qhp->ep); 1419 1420 spin_lock_irq(&rhp->lock); 1421 remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1422 rhp->qpcnt--; 1423 BUG_ON(rhp->qpcnt < 0); 1424 if (rhp->qpcnt <= db_fc_threshold && rhp->db_state == FLOW_CONTROL) { 1425 rhp->rdev.stats.db_state_transitions++; 1426 rhp->db_state = NORMAL; 1427 idr_for_each(&rhp->qpidr, enable_qp_db, NULL); 1428 } 1429 spin_unlock_irq(&rhp->lock); 1430 atomic_dec(&qhp->refcnt); 1431 wait_event(qhp->wait, !atomic_read(&qhp->refcnt)); 1432 1433 ucontext = ib_qp->uobject ? 1434 to_c4iw_ucontext(ib_qp->uobject->context) : NULL; 1435 destroy_qp(&rhp->rdev, &qhp->wq, 1436 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1437 1438 CTR3(KTR_IW_CXGBE, "%s ib_qp %p qpid 0x%0x", __func__, ib_qp, 1439 qhp->wq.sq.qid); 1440 kfree(qhp); 1441 return 0; 1442} 1443 1444static int disable_qp_db(int id, void *p, void *data) 1445{ 1446 struct c4iw_qp *qp = p; 1447 1448 t4_disable_wq_db(&qp->wq); 1449 return 0; 1450} 1451 1452struct ib_qp * 1453c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs, 1454 struct ib_udata *udata) 1455{ 1456 struct c4iw_dev *rhp; 1457 struct c4iw_qp *qhp; 1458 struct c4iw_pd *php; 1459 struct c4iw_cq *schp; 1460 struct c4iw_cq *rchp; 1461 struct c4iw_create_qp_resp uresp; 1462 int sqsize, rqsize; 1463 struct c4iw_ucontext *ucontext; 1464 int ret; 1465 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4; 1466 1467 CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); 1468 1469 if (attrs->qp_type != IB_QPT_RC) 1470 return ERR_PTR(-EINVAL); 1471 1472 php = to_c4iw_pd(pd); 1473 rhp = php->rhp; 1474 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid); 1475 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid); 1476 if (!schp || !rchp) 1477 return ERR_PTR(-EINVAL); 1478 1479 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) 1480 return ERR_PTR(-EINVAL); 1481 1482 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16); 1483 if (rqsize > T4_MAX_RQ_SIZE) 1484 return ERR_PTR(-E2BIG); 1485 1486 sqsize = roundup(attrs->cap.max_send_wr + 1, 16); 1487 if (sqsize > T4_MAX_SQ_SIZE) 1488 return ERR_PTR(-E2BIG); 1489 1490 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; 1491 1492 1493 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL); 1494 if (!qhp) 1495 return ERR_PTR(-ENOMEM); 1496 qhp->wq.sq.size = sqsize; 1497 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue; 1498 qhp->wq.rq.size = rqsize; 1499 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue; 1500 1501 if (ucontext) { 1502 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); 1503 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE); 1504 } 1505 1506 CTR5(KTR_IW_CXGBE, "%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu", 1507 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize); 1508 1509 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq, 1510 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1511 if (ret) 1512 goto err1; 1513 1514 attrs->cap.max_recv_wr = rqsize - 1; 1515 attrs->cap.max_send_wr = sqsize - 1; 1516 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE; 1517 1518 qhp->rhp = rhp; 1519 qhp->attr.pd = php->pdid; 1520 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid; 1521 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid; 1522 qhp->attr.sq_num_entries = attrs->cap.max_send_wr; 1523 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr; 1524 qhp->attr.sq_max_sges = attrs->cap.max_send_sge; 1525 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge; 1526 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge; 1527 qhp->attr.state = C4IW_QP_STATE_IDLE; 1528 qhp->attr.next_state = C4IW_QP_STATE_IDLE; 1529 qhp->attr.enable_rdma_read = 1; 1530 qhp->attr.enable_rdma_write = 1; 1531 qhp->attr.enable_bind = 1; 1532 qhp->attr.max_ord = 1; 1533 qhp->attr.max_ird = 1; 1534 spin_lock_init(&qhp->lock); 1535 mutex_init(&qhp->mutex); 1536 init_waitqueue_head(&qhp->wait); 1537 atomic_set(&qhp->refcnt, 1); 1538 1539 spin_lock_irq(&rhp->lock); 1540 if (rhp->db_state != NORMAL) 1541 t4_disable_wq_db(&qhp->wq); 1542 if (++rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) { 1543 rhp->rdev.stats.db_state_transitions++; 1544 rhp->db_state = FLOW_CONTROL; 1545 idr_for_each(&rhp->qpidr, disable_qp_db, NULL); 1546 } 1547 ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid); 1548 spin_unlock_irq(&rhp->lock); 1549 if (ret) 1550 goto err2; 1551 1552 if (udata) { 1553 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL); 1554 if (!mm1) { 1555 ret = -ENOMEM; 1556 goto err3; 1557 } 1558 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL); 1559 if (!mm2) { 1560 ret = -ENOMEM; 1561 goto err4; 1562 } 1563 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL); 1564 if (!mm3) { 1565 ret = -ENOMEM; 1566 goto err5; 1567 } 1568 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL); 1569 if (!mm4) { 1570 ret = -ENOMEM; 1571 goto err6; 1572 } 1573 uresp.flags = 0; 1574 uresp.qid_mask = rhp->rdev.qpmask; 1575 uresp.sqid = qhp->wq.sq.qid; 1576 uresp.sq_size = qhp->wq.sq.size; 1577 uresp.sq_memsize = qhp->wq.sq.memsize; 1578 uresp.rqid = qhp->wq.rq.qid; 1579 uresp.rq_size = qhp->wq.rq.size; 1580 uresp.rq_memsize = qhp->wq.rq.memsize; 1581 spin_lock(&ucontext->mmap_lock); 1582 uresp.sq_key = ucontext->key; 1583 ucontext->key += PAGE_SIZE; 1584 uresp.rq_key = ucontext->key; 1585 ucontext->key += PAGE_SIZE; 1586 uresp.sq_db_gts_key = ucontext->key; 1587 ucontext->key += PAGE_SIZE; 1588 uresp.rq_db_gts_key = ucontext->key; 1589 ucontext->key += PAGE_SIZE; 1590 spin_unlock(&ucontext->mmap_lock); 1591 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp); 1592 if (ret) 1593 goto err7; 1594 mm1->key = uresp.sq_key; 1595 mm1->addr = qhp->wq.sq.phys_addr; 1596 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize); 1597 CTR4(KTR_IW_CXGBE, "%s mm1 %x, %x, %d", __func__, mm1->key, 1598 mm1->addr, mm1->len); 1599 insert_mmap(ucontext, mm1); 1600 mm2->key = uresp.rq_key; 1601 mm2->addr = vtophys(qhp->wq.rq.queue); 1602 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize); 1603 CTR4(KTR_IW_CXGBE, "%s mm2 %x, %x, %d", __func__, mm2->key, 1604 mm2->addr, mm2->len); 1605 insert_mmap(ucontext, mm2); 1606 mm3->key = uresp.sq_db_gts_key; 1607 mm3->addr = qhp->wq.sq.udb; 1608 mm3->len = PAGE_SIZE; 1609 CTR4(KTR_IW_CXGBE, "%s mm3 %x, %x, %d", __func__, mm3->key, 1610 mm3->addr, mm3->len); 1611 insert_mmap(ucontext, mm3); 1612 mm4->key = uresp.rq_db_gts_key; 1613 mm4->addr = qhp->wq.rq.udb; 1614 mm4->len = PAGE_SIZE; 1615 CTR4(KTR_IW_CXGBE, "%s mm4 %x, %x, %d", __func__, mm4->key, 1616 mm4->addr, mm4->len); 1617 insert_mmap(ucontext, mm4); 1618 } 1619 qhp->ibqp.qp_num = qhp->wq.sq.qid; 1620 init_timer(&(qhp->timer)); 1621 CTR5(KTR_IW_CXGBE, 1622 "%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x", 1623 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries, 1624 qhp->wq.sq.qid); 1625 return &qhp->ibqp; 1626err7: 1627 kfree(mm4); 1628err6: 1629 kfree(mm3); 1630err5: 1631 kfree(mm2); 1632err4: 1633 kfree(mm1); 1634err3: 1635 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid); 1636err2: 1637 destroy_qp(&rhp->rdev, &qhp->wq, 1638 ucontext ? &ucontext->uctx : &rhp->rdev.uctx); 1639err1: 1640 kfree(qhp); 1641 return ERR_PTR(ret); 1642} 1643 1644int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1645 int attr_mask, struct ib_udata *udata) 1646{ 1647 struct c4iw_dev *rhp; 1648 struct c4iw_qp *qhp; 1649 enum c4iw_qp_attr_mask mask = 0; 1650 struct c4iw_qp_attributes attrs; 1651 1652 CTR2(KTR_IW_CXGBE, "%s ib_qp %p", __func__, ibqp); 1653 1654 /* iwarp does not support the RTR state */ 1655 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR)) 1656 attr_mask &= ~IB_QP_STATE; 1657 1658 /* Make sure we still have something left to do */ 1659 if (!attr_mask) 1660 return 0; 1661 1662 memset(&attrs, 0, sizeof attrs); 1663 qhp = to_c4iw_qp(ibqp); 1664 rhp = qhp->rhp; 1665 1666 attrs.next_state = c4iw_convert_state(attr->qp_state); 1667 attrs.enable_rdma_read = (attr->qp_access_flags & 1668 IB_ACCESS_REMOTE_READ) ? 1 : 0; 1669 attrs.enable_rdma_write = (attr->qp_access_flags & 1670 IB_ACCESS_REMOTE_WRITE) ? 1 : 0; 1671 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0; 1672 1673 1674 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0; 1675 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ? 1676 (C4IW_QP_ATTR_ENABLE_RDMA_READ | 1677 C4IW_QP_ATTR_ENABLE_RDMA_WRITE | 1678 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0; 1679 1680 /* 1681 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for 1682 * ringing the queue db when we're in DB_FULL mode. 1683 */ 1684 attrs.sq_db_inc = attr->sq_psn; 1685 attrs.rq_db_inc = attr->rq_psn; 1686 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0; 1687 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0; 1688 1689 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0); 1690} 1691 1692struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn) 1693{ 1694 CTR3(KTR_IW_CXGBE, "%s ib_dev %p qpn 0x%x", __func__, dev, qpn); 1695 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn); 1696} 1697 1698int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1699 int attr_mask, struct ib_qp_init_attr *init_attr) 1700{ 1701 struct c4iw_qp *qhp = to_c4iw_qp(ibqp); 1702 1703 memset(attr, 0, sizeof *attr); 1704 memset(init_attr, 0, sizeof *init_attr); 1705 attr->qp_state = to_ib_qp_state(qhp->attr.state); 1706 return 0; 1707} 1708#endif 1709