t6fw_cfg.txt revision 309560
1# Chelsio T6 Factory Default configuration file. 2# 3# Copyright (C) 2014-2016 Chelsio Communications. All rights reserved. 4# 5# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE 6# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE 7# TO ADAPTERS. 8 9 10# This file provides the default, power-on configuration for 2-port T6-based 11# adapters shipped from the factory. These defaults are designed to address 12# the needs of the vast majority of Terminator customers. The basic idea is to 13# have a default configuration which allows a customer to plug a Terminator 14# adapter in and have it work regardless of OS, driver or application except in 15# the most unusual and/or demanding customer applications. 16# 17# Many of the Terminator resources which are described by this configuration 18# are finite. This requires balancing the configuration/operation needs of 19# device drivers across OSes and a large number of customer application. 20# 21# Some of the more important resources to allocate and their constaints are: 22# 1. Virtual Interfaces: 256. 23# 2. Ingress Queues with Free Lists: 1024. 24# 3. Egress Queues: 128K. 25# 4. MSI-X Vectors: 1088. 26# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 27# address matching on Ingress Packets. 28# 29# Some of the important OS/Driver resource needs are: 30# 6. Some OS Drivers will manage all resources through a single Physical 31# Function (currently PF4 but it could be any Physical Function). 32# 7. Some OS Drivers will manage different ports and functions (NIC, 33# storage, etc.) on different Physical Functions. For example, NIC 34# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc. 35# 36# Some of the customer application needs which need to be accommodated: 37# 8. Some customers will want to support large CPU count systems with 38# good scaling. Thus, we'll need to accommodate a number of 39# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 40# to be involved per port and per application function. For example, 41# in the case where all ports and application functions will be 42# managed via a single Unified PF and we want to accommodate scaling up 43# to 8 CPUs, we would want: 44# 45# 2 ports * 46# 3 application functions (NIC, FCoE, iSCSI) per port * 47# 16 Ingress Queue/MSI-X Vectors per application function 48# 49# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 50# (Plus a few for Firmware Event Queues, etc.) 51# 52# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual 53# Machines to directly access T6 functionality via SR-IOV Virtual Functions 54# and "PCI Device Passthrough" -- this is especially true for the NIC 55# application functionality. 56# 57 58 59# Global configuration settings. 60# 61[global] 62 rss_glb_config_mode = basicvirtual 63 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 64 65 # PL_TIMEOUT register 66 pl_timeout_value = 200 # the timeout value in units of us 67 68 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 69 # Page Size and a 64B L1 Cache Line Size. It programs the 70 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 71 # If a Master PF Driver finds itself on a machine with different 72 # parameters, then the Master PF Driver is responsible for initializing 73 # these parameters to appropriate values. 74 # 75 # Notes: 76 # 1. The Free List Buffer Sizes below are raw and the firmware will 77 # round them up to the Ingress Padding Boundary. 78 # 2. The SGE Timer Values below are expressed below in microseconds. 79 # The firmware will convert these values to Core Clock Ticks when 80 # it processes the configuration parameters. 81 # 82 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 83 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 84 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 85 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 86 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 87 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 88 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 89 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 90 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 91 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 92 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 93 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 94 reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS 95 reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL 96 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 97 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread 98 99 # enable TP_OUT_CONFIG.IPIDSPLITMODE 100 reg[0x7d04] = 0x00010000/0x00010000 101 102 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 103 104 #Tick granularities in kbps 105 tsch_ticks = 100000, 10000, 1000, 10 106 107 # TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram 108 # filter control: compact, fcoemask 109 # server sram : srvrsram 110 # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 111 # protocol, tos, vlan, vnic_id, port, fcoe 112 # valid filterModes are described the Terminator 5 Data Book 113 filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe 114 115 # filter tuples enforced in LE active region (equal to or subset of filterMode) 116 filterMask = protocol, fcoe 117 118 # Percentage of dynamic memory (in either the EDRAM or external MEM) 119 # to use for TP RX payload 120 tp_pmrx = 30 121 122 # TP RX payload page size 123 tp_pmrx_pagesize = 64K 124 125 # TP number of RX channels 126 tp_nrxch = 0 # 0 (auto) = 1 127 128 # Percentage of dynamic memory (in either the EDRAM or external MEM) 129 # to use for TP TX payload 130 tp_pmtx = 50 131 132 # TP TX payload page size 133 tp_pmtx_pagesize = 64K 134 135 # TP number of TX channels 136 tp_ntxch = 0 # 0 (auto) = equal number of ports 137 138 # TP OFLD MTUs 139 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 140 141 # enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC 142 reg[0x7d04] = 0x00010008/0x00010008 143 144 # TP_GLOBAL_CONFIG 145 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 146 147 # TP_PC_CONFIG 148 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 149 150 # TP_PARA_REG0 151 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 152 153 # LE_DB_CONFIG 154 reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled 155 # LE IPv4 compression disabled 156 # LE_DB_HASH_CONFIG 157 reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8, 158 159 # ULP_TX_CONFIG 160 reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err 161 # Enable more error msg for ... 162 # TPT error. 163 164 # ULP_RX_MISC_FEATURE_ENABLE 165 #reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit 166 # Enable offset decrement after ... 167 # PI extraction and before DDP 168 # ulp insert pi source info in DIF 169 # iscsi_eff_offset_en 170 171 #Enable iscsi completion moderation feature 172 reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after 173 # PI extraction and before DDP. 174 # ulp insert pi source info in 175 # DIF. 176 # Enable iscsi hdr cmd mode. 177 # iscsi force cmd mode. 178 # Enable iscsi cmp mode. 179 # MC configuration 180 #mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC 181 182# Some "definitions" to make the rest of this a bit more readable. We support 183# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 184# per function per port ... 185# 186# NMSIX = 1088 # available MSI-X Vectors 187# NVI = 256 # available Virtual Interfaces 188# NMPSTCAM = 336 # MPS TCAM entries 189# 190# NPORTS = 2 # ports 191# NCPUS = 16 # CPUs we want to support scalably 192# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 193 194# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 195# PF" which many OS Drivers will use to manage most or all functions. 196# 197# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 198# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 199# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 200# will be specified as the "Ingress Queue Asynchronous Destination Index." 201# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 202# than or equal to the number of Ingress Queues ... 203# 204# NVI_NIC = 4 # NIC access to NPORTS 205# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 206# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 207# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 208# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 209# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 210# 211# NVI_OFLD = 0 # Offload uses NIC function to access ports 212# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 213# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 214# NEQ_OFLD = 16 # Offload Egress Queues (FL) 215# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 216# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 217# 218# NVI_RDMA = 0 # RDMA uses NIC function to access ports 219# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 220# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 221# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 222# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 223# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 224# 225# NEQ_WD = 128 # Wire Direct TX Queues and FLs 226# NETHCTRL_WD = 64 # Wire Direct TX Queues 227# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 228# 229# NVI_ISCSI = 4 # ISCSI access to NPORTS 230# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 231# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 232# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 233# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 234# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 235# 236# NVI_FCOE = 4 # FCOE access to NPORTS 237# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 238# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 239# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 240# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 241# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 242 243# Two extra Ingress Queues per function for Firmware Events and Forwarded 244# Interrupts, and two extra interrupts per function for Firmware Events (or a 245# Forwarded Interrupt Queue) and General Interrupts per function. 246# 247# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 248# # Forwarded Interrupts 249# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 250# # General Interrupts 251 252# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 253# their interrupts forwarded to another set of Forwarded Interrupt Queues. 254# 255# NVI_HYPERV = 16 # VMs we want to support 256# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 257# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 258# NEQ_HYPERV = 32 # VIQs Free Lists 259# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 260# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 261 262# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 263# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 264# 265# NVI_UNIFIED = 28 266# NFLIQ_UNIFIED = 106 267# NETHCTRL_UNIFIED = 32 268# NEQ_UNIFIED = 124 269# NMPSTCAM_UNIFIED = 40 270# 271# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 272# that up to 128 to make sure the Unified PF doesn't run out of resources. 273# 274# NMSIX_UNIFIED = 128 275# 276# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 277# which is 34 but they're probably safe with 32. 278# 279# NMSIX_STORAGE = 32 280 281# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 282# associated with it. Thus, the MSI-X Vector allocations we give to the 283# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 284# provision many more Virtual Functions than we can if the UnifiedPF were 285# one of PF0-3. 286# 287 288# All of the below PCI-E parameters are actually stored in various *_init.txt 289# files. We include them below essentially as comments. 290# 291# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 292# ports 0-3. 293# 294# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 295# 296# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 297# storage applications across all four possible ports. 298# 299# Additionally, since the UnifiedPF isn't one of the per-port Physical 300# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 301# different PCI Device IDs which will allow Unified and Per-Port Drivers 302# to directly select the type of Physical Function to which they wish to be 303# attached. 304# 305# Note that the actual values used for the PCI-E Intelectual Property will be 306# 1 less than those below since that's the way it "counts" things. For 307# readability, we use the number we actually mean ... 308# 309# PF0_INT = 8 # NCPUS 310# PF1_INT = 8 # NCPUS 311# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 312# 313# PF4_INT = 128 # NMSIX_UNIFIED 314# PF5_INT = 32 # NMSIX_STORAGE 315# PF6_INT = 32 # NMSIX_STORAGE 316# PF7_INT = 0 # Nothing Assigned 317# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 318# 319# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 320# 321# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 322# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 323# 324# NVF = 16 325 326 327# For those OSes which manage different ports on different PFs, we need 328# only enough resources to support a single port's NIC application functions 329# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 330# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 331# managed on the "storage PFs" (see below). 332# 333[function "0"] 334 nvf = 16 # NVF on this function 335 wx_caps = all # write/execute permissions for all commands 336 r_caps = all # read permissions for all commands 337 nvi = 1 # 1 port 338 niqflint = 8 # NCPUS "Queue Sets" 339 nethctrl = 8 # NCPUS "Queue Sets" 340 neq = 16 # niqflint + nethctrl Egress Queues 341 nexactf = 8 # number of exact MPSTCAM MAC filters 342 cmask = all # access to all channels 343 pmask = 0x1 # access to only one port 344 345 346[function "1"] 347 nvf = 16 # NVF on this function 348 wx_caps = all # write/execute permissions for all commands 349 r_caps = all # read permissions for all commands 350 nvi = 1 # 1 port 351 niqflint = 8 # NCPUS "Queue Sets" 352 nethctrl = 8 # NCPUS "Queue Sets" 353 neq = 16 # niqflint + nethctrl Egress Queues 354 nexactf = 8 # number of exact MPSTCAM MAC filters 355 cmask = all # access to all channels 356 pmask = 0x2 # access to only one port 357 358[function "2"] 359 nvf = 16 # NVF on this function 360 wx_caps = all # write/execute permissions for all commands 361 r_caps = all # read permissions for all commands 362 nvi = 1 # 1 port 363 niqflint = 8 # NCPUS "Queue Sets" 364 nethctrl = 8 # NCPUS "Queue Sets" 365 neq = 16 # niqflint + nethctrl Egress Queues 366 nexactf = 8 # number of exact MPSTCAM MAC filters 367 cmask = all # access to all channels 368 pmask = 0x4 # access to only one port 369 370[function "3"] 371 nvf = 16 # NVF on this function 372 wx_caps = all # write/execute permissions for all commands 373 r_caps = all # read permissions for all commands 374 nvi = 1 # 1 port 375 niqflint = 8 # NCPUS "Queue Sets" 376 nethctrl = 8 # NCPUS "Queue Sets" 377 neq = 16 # niqflint + nethctrl Egress Queues 378 nexactf = 8 # number of exact MPSTCAM MAC filters 379 cmask = all # access to all channels 380 pmask = 0x8 # access to only one port 381 382 383# Some OS Drivers manage all application functions for all ports via PF4. 384# Thus we need to provide a large number of resources here. For Egress 385# Queues we need to account for both TX Queues as well as Free List Queues 386# (because the host is responsible for producing Free List Buffers for the 387# hardware to consume). 388# 389[function "4"] 390 wx_caps = all # write/execute permissions for all commands 391 r_caps = all # read permissions for all commands 392 nvi = 28 # NVI_UNIFIED 393 niqflint = 202 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32) 394 nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD 395 neq = 256 # NEQ_UNIFIED + NEQ_WD 396 nqpcq = 12288 397 nexactf = 40 # NMPSTCAM_UNIFIED 398 cmask = all # access to all channels 399 pmask = all # access to all four ports ... 400 nethofld = 1024 # number of user mode ethernet flow contexts 401 ncrypto_lookaside = 16 # Number of lookaside flow contexts 402 nclip = 320 # number of clip region entries 403 nfilter = 496 # number of filter region entries 404 nserver = 496 # number of server region entries 405 nhash = 12288 # number of hash region entries 406 nhpfilter = 0 # number of high priority filter region entries 407 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside 408 tp_l2t = 3072 409 tp_ddp = 2 410 tp_ddp_iscsi = 2 411 tp_tls_key = 3 412 tp_stag = 2 413 tp_pbl = 5 414 tp_rq = 7 415 tp_srq = 128 416 417# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 418# need to have Virtual Interfaces on each of the four ports with up to NCPUS 419# "Queue Sets" each. 420# 421[function "5"] 422 wx_caps = all # write/execute permissions for all commands 423 r_caps = all # read permissions for all commands 424 nvi = 4 # NPORTS 425 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 426 nethctrl = 32 # NPORTS*NCPUS 427 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 428 nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16. 429 cmask = all # access to all channels 430 pmask = all # access to all four ports ... 431 nserver = 16 432 nhash = 2048 433 tp_l2t = 1020 434 nclip = 64 435 protocol = iscsi_initiator_fofld 436 tp_ddp_iscsi = 2 437 iscsi_ntask = 2048 438 iscsi_nsess = 2048 439 iscsi_nconn_per_session = 1 440 iscsi_ninitiator_instance = 64 441 442 443[function "6"] 444 wx_caps = all # write/execute permissions for all commands 445 r_caps = all # read permissions for all commands 446 nvi = 4 # NPORTS 447 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 448 nethctrl = 32 # NPORTS*NCPUS 449 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 450 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 451 # which is OK since < MIN(SUM PF0..3, PF4) 452 # and we never load PF0..3 and PF4 concurrently 453 cmask = all # access to all channels 454 pmask = all # access to all four ports ... 455 nhash = 2048 456 tp_l2t = 4 457 protocol = fcoe_initiator 458 tp_ddp = 2 459 fcoe_nfcf = 16 460 fcoe_nvnp = 32 461 fcoe_nssn = 1024 462 463 464# The following function, 1023, is not an actual PCIE function but is used to 465# configure and reserve firmware internal resources that come from the global 466# resource pool. 467# 468[function "1023"] 469 wx_caps = all # write/execute permissions for all commands 470 r_caps = all # read permissions for all commands 471 nvi = 4 # NVI_UNIFIED 472 cmask = all # access to all channels 473 pmask = all # access to all four ports ... 474 nexactf = 8 # NPORTS + DCBX + 475 nfilter = 16 # number of filter region entries 476 477 478# For Virtual functions, we only allow NIC functionality and we only allow 479# access to one port (1 << PF). Note that because of limitations in the 480# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 481# and GTS registers, the number of Ingress and Egress Queues must be a power 482# of 2. 483# 484[function "0/*"] # NVF 485 wx_caps = 0x82 # DMAQ | VF 486 r_caps = 0x86 # DMAQ | VF | PORT 487 nvi = 1 # 1 port 488 niqflint = 4 # 2 "Queue Sets" + NXIQ 489 nethctrl = 2 # 2 "Queue Sets" 490 neq = 4 # 2 "Queue Sets" * 2 491 nexactf = 4 492 cmask = all # access to all channels 493 pmask = 0x1 # access to only one port ... 494 495 496[function "1/*"] # NVF 497 wx_caps = 0x82 # DMAQ | VF 498 r_caps = 0x86 # DMAQ | VF | PORT 499 nvi = 1 # 1 port 500 niqflint = 4 # 2 "Queue Sets" + NXIQ 501 nethctrl = 2 # 2 "Queue Sets" 502 neq = 4 # 2 "Queue Sets" * 2 503 nexactf = 4 504 cmask = all # access to all channels 505 pmask = 0x2 # access to only one port ... 506 507[function "2/*"] # NVF 508 wx_caps = 0x82 # DMAQ | VF 509 r_caps = 0x86 # DMAQ | VF | PORT 510 nvi = 1 # 1 port 511 niqflint = 4 # 2 "Queue Sets" + NXIQ 512 nethctrl = 2 # 2 "Queue Sets" 513 neq = 4 # 2 "Queue Sets" * 2 514 nexactf = 4 515 cmask = all # access to all channels 516 pmask = 0x1 # access to only one port ... 517 518 519[function "3/*"] # NVF 520 wx_caps = 0x82 # DMAQ | VF 521 r_caps = 0x86 # DMAQ | VF | PORT 522 nvi = 1 # 1 port 523 niqflint = 4 # 2 "Queue Sets" + NXIQ 524 nethctrl = 2 # 2 "Queue Sets" 525 neq = 4 # 2 "Queue Sets" * 2 526 nexactf = 4 527 cmask = all # access to all channels 528 pmask = 0x2 # access to only one port ... 529 530# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 531# for packets from the wire as well as the loopback path of the L2 switch. The 532# folling params control how the buffer memory is distributed and the L2 flow 533# control settings: 534# 535# bg_mem: %-age of mem to use for port/buffer group 536# lpbk_mem: %-age of port/bg mem to use for loopback 537# hwm: high watermark; bytes available when starting to send pause 538# frames (in units of 0.1 MTU) 539# lwm: low watermark; bytes remaining when sending 'unpause' frame 540# (in inuits of 0.1 MTU) 541# dwm: minimum delta between high and low watermark (in units of 100 542# Bytes) 543# 544[port "0"] 545 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 546 #bg_mem = 25 547 #lpbk_mem = 25 548 hwm = 60 549 lwm = 15 550 dwm = 30 551 dcb_app_tlv[0] = 0x8906, ethertype, 3 552 dcb_app_tlv[1] = 0x8914, ethertype, 3 553 dcb_app_tlv[2] = 3260, socketnum, 5 554 aec_retry_cnt = 4 555 556 557[port "1"] 558 dcb = ppp, dcbx 559 #bg_mem = 25 560 #lpbk_mem = 25 561 hwm = 60 562 lwm = 15 563 dwm = 30 564 dcb_app_tlv[0] = 0x8906, ethertype, 3 565 dcb_app_tlv[1] = 0x8914, ethertype, 3 566 dcb_app_tlv[2] = 3260, socketnum, 5 567 aec_retry_cnt = 4 568 569 570[fini] 571 version = 0x01000023 572 checksum = 0x683208a2 573 574# Total resources used by above allocations: 575# Virtual Interfaces: 104 576# Ingress Queues/w Free Lists and Interrupts: 526 577# Egress Queues: 702 578# MPS TCAM Entries: 336 579# MSI-X Vectors: 736 580# Virtual Functions: 64 581# 582# $FreeBSD: stable/10/sys/dev/cxgbe/firmware/t6fw_cfg.txt 309560 2016-12-05 20:43:25Z jhb $ 583# 584