1218792Snp/*- 2308304Sjhb * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 3218792Snp * All rights reserved. 4218792Snp * 5218792Snp * Redistribution and use in source and binary forms, with or without 6218792Snp * modification, are permitted provided that the following conditions 7218792Snp * are met: 8218792Snp * 1. Redistributions of source code must retain the above copyright 9218792Snp * notice, this list of conditions and the following disclaimer. 10218792Snp * 2. Redistributions in binary form must reproduce the above copyright 11218792Snp * notice, this list of conditions and the following disclaimer in the 12218792Snp * documentation and/or other materials provided with the distribution. 13218792Snp * 14218792Snp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15218792Snp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16218792Snp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17218792Snp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18218792Snp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19218792Snp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20218792Snp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21218792Snp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22218792Snp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23218792Snp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24218792Snp * SUCH DAMAGE. 25218792Snp * 26218792Snp * $FreeBSD: stable/10/sys/dev/cxgbe/common/t4_regs_values.h 308304 2016-11-04 18:45:06Z jhb $ 27218792Snp * 28218792Snp */ 29218792Snp 30218792Snp#ifndef __T4_REGS_VALUES_H__ 31218792Snp#define __T4_REGS_VALUES_H__ 32218792Snp 33218792Snp/* 34218792Snp * This file contains definitions for various T4 register value hardware 35218792Snp * constants. The types of values encoded here are predominantly those for 36218792Snp * register fields which control "modal" behavior. For the most part, we do 37218792Snp * not include definitions for register fields which are simple numeric 38218792Snp * metrics, etc. 39218792Snp * 40218792Snp * These new "modal values" use a naming convention which matches the 41218792Snp * currently existing macros in t4_reg.h. For register field FOO which would 42218792Snp * have S_FOO, M_FOO, V_FOO() and G_FOO() macros, we introduce X_FOO_{MODE} 43218792Snp * definitions. These can be used as V_FOO(X_FOO_MODE) or as (G_FOO(x) == 44218792Snp * X_FOO_MODE). 45218792Snp * 46218792Snp * Note that this should all be part of t4_regs.h but the toolset used to 47218792Snp * generate that file doesn't [yet] have the capability of collecting these 48218792Snp * constants. 49218792Snp */ 50218792Snp 51218792Snp/* 52218792Snp * SGE definitions. 53218792Snp * ================ 54218792Snp */ 55218792Snp 56218792Snp/* 57218792Snp * SGE register field values. 58218792Snp */ 59218792Snp 60218792Snp/* CONTROL register */ 61218792Snp#define X_FLSPLITMODE_FLSPLITMIN 0 62218792Snp#define X_FLSPLITMODE_ETHHDR 1 63218792Snp#define X_FLSPLITMODE_IPHDR 2 64218792Snp#define X_FLSPLITMODE_TCPHDR 3 65218792Snp 66218792Snp#define X_DCASYSTYPE_FSB 0 67218792Snp#define X_DCASYSTYPE_CSI 1 68218792Snp 69218792Snp#define X_EGSTATPAGESIZE_64B 0 70218792Snp#define X_EGSTATPAGESIZE_128B 1 71218792Snp 72218792Snp#define X_RXPKTCPLMODE_DATA 0 73218792Snp#define X_RXPKTCPLMODE_SPLIT 1 74218792Snp 75218792Snp#define X_INGPCIEBOUNDARY_SHIFT 5 76218792Snp#define X_INGPCIEBOUNDARY_32B 0 77218792Snp#define X_INGPCIEBOUNDARY_64B 1 78218792Snp#define X_INGPCIEBOUNDARY_128B 2 79218792Snp#define X_INGPCIEBOUNDARY_256B 3 80218792Snp#define X_INGPCIEBOUNDARY_512B 4 81218792Snp#define X_INGPCIEBOUNDARY_1024B 5 82218792Snp#define X_INGPCIEBOUNDARY_2048B 6 83218792Snp#define X_INGPCIEBOUNDARY_4096B 7 84218792Snp 85308304Sjhb#define X_T6_INGPADBOUNDARY_SHIFT 3 86308304Sjhb#define X_T6_INGPADBOUNDARY_8B 0 87308304Sjhb#define X_T6_INGPADBOUNDARY_16B 1 88308304Sjhb#define X_T6_INGPADBOUNDARY_32B 2 89308304Sjhb#define X_T6_INGPADBOUNDARY_64B 3 90308304Sjhb#define X_T6_INGPADBOUNDARY_128B 4 91308304Sjhb#define X_T6_INGPADBOUNDARY_256B 5 92308304Sjhb#define X_T6_INGPADBOUNDARY_512B 6 93308304Sjhb#define X_T6_INGPADBOUNDARY_1024B 7 94308304Sjhb 95218792Snp#define X_INGPADBOUNDARY_SHIFT 5 96218792Snp#define X_INGPADBOUNDARY_32B 0 97218792Snp#define X_INGPADBOUNDARY_64B 1 98218792Snp#define X_INGPADBOUNDARY_128B 2 99218792Snp#define X_INGPADBOUNDARY_256B 3 100218792Snp#define X_INGPADBOUNDARY_512B 4 101218792Snp#define X_INGPADBOUNDARY_1024B 5 102218792Snp#define X_INGPADBOUNDARY_2048B 6 103218792Snp#define X_INGPADBOUNDARY_4096B 7 104218792Snp 105218792Snp#define X_EGRPCIEBOUNDARY_SHIFT 5 106218792Snp#define X_EGRPCIEBOUNDARY_32B 0 107218792Snp#define X_EGRPCIEBOUNDARY_64B 1 108218792Snp#define X_EGRPCIEBOUNDARY_128B 2 109218792Snp#define X_EGRPCIEBOUNDARY_256B 3 110218792Snp#define X_EGRPCIEBOUNDARY_512B 4 111218792Snp#define X_EGRPCIEBOUNDARY_1024B 5 112218792Snp#define X_EGRPCIEBOUNDARY_2048B 6 113218792Snp#define X_EGRPCIEBOUNDARY_4096B 7 114218792Snp 115308304Sjhb/* CONTROL2 register */ 116308304Sjhb#define X_INGPACKBOUNDARY_SHIFT 5 // *most* of the values ... 117308304Sjhb#define X_INGPACKBOUNDARY_16B 0 // Note weird value! 118308304Sjhb#define X_INGPACKBOUNDARY_64B 1 119308304Sjhb#define X_INGPACKBOUNDARY_128B 2 120308304Sjhb#define X_INGPACKBOUNDARY_256B 3 121308304Sjhb#define X_INGPACKBOUNDARY_512B 4 122308304Sjhb#define X_INGPACKBOUNDARY_1024B 5 123308304Sjhb#define X_INGPACKBOUNDARY_2048B 6 124308304Sjhb#define X_INGPACKBOUNDARY_4096B 7 125308304Sjhb 126218792Snp/* GTS register */ 127218792Snp#define SGE_TIMERREGS 6 128218792Snp#define X_TIMERREG_COUNTER0 0 129218792Snp#define X_TIMERREG_COUNTER1 1 130218792Snp#define X_TIMERREG_COUNTER2 2 131218792Snp#define X_TIMERREG_COUNTER3 3 132218792Snp#define X_TIMERREG_COUNTER4 4 133218792Snp#define X_TIMERREG_COUNTER5 5 134218792Snp#define X_TIMERREG_RESTART_COUNTER 6 135218792Snp#define X_TIMERREG_UPDATE_CIDX 7 136218792Snp 137218792Snp/* 138218792Snp * Egress Context field values 139218792Snp */ 140218792Snp#define EC_WR_UNITS 16 141218792Snp 142218792Snp#define X_FETCHBURSTMIN_SHIFT 4 143218792Snp#define X_FETCHBURSTMIN_16B 0 144218792Snp#define X_FETCHBURSTMIN_32B 1 145218792Snp#define X_FETCHBURSTMIN_64B 2 146218792Snp#define X_FETCHBURSTMIN_128B 3 147218792Snp 148218792Snp#define X_FETCHBURSTMAX_SHIFT 6 149218792Snp#define X_FETCHBURSTMAX_64B 0 150218792Snp#define X_FETCHBURSTMAX_128B 1 151218792Snp#define X_FETCHBURSTMAX_256B 2 152218792Snp#define X_FETCHBURSTMAX_512B 3 153218792Snp 154218792Snp#define X_HOSTFCMODE_NONE 0 155218792Snp#define X_HOSTFCMODE_INGRESS_QUEUE 1 156218792Snp#define X_HOSTFCMODE_STATUS_PAGE 2 157218792Snp#define X_HOSTFCMODE_BOTH 3 158218792Snp 159218792Snp#define X_HOSTFCOWNER_UP 0 160218792Snp#define X_HOSTFCOWNER_SGE 1 161218792Snp 162218792Snp#define X_CIDXFLUSHTHRESH_1 0 163218792Snp#define X_CIDXFLUSHTHRESH_2 1 164218792Snp#define X_CIDXFLUSHTHRESH_4 2 165218792Snp#define X_CIDXFLUSHTHRESH_8 3 166218792Snp#define X_CIDXFLUSHTHRESH_16 4 167218792Snp#define X_CIDXFLUSHTHRESH_32 5 168218792Snp#define X_CIDXFLUSHTHRESH_64 6 169218792Snp#define X_CIDXFLUSHTHRESH_128 7 170218792Snp 171218792Snp#define X_IDXSIZE_UNIT 64 172218792Snp 173218792Snp#define X_BASEADDRESS_ALIGN 512 174218792Snp 175218792Snp/* 176218792Snp * Ingress Context field values 177218792Snp */ 178218792Snp#define X_UPDATESCHEDULING_TIMER 0 179218792Snp#define X_UPDATESCHEDULING_COUNTER_OPTTIMER 1 180218792Snp 181218792Snp#define X_UPDATEDELIVERY_NONE 0 182218792Snp#define X_UPDATEDELIVERY_INTERRUPT 1 183218792Snp#define X_UPDATEDELIVERY_STATUS_PAGE 2 184218792Snp#define X_UPDATEDELIVERY_BOTH 3 185218792Snp 186218792Snp#define X_INTERRUPTDESTINATION_PCIE 0 187218792Snp#define X_INTERRUPTDESTINATION_IQ 1 188218792Snp 189218792Snp#define X_QUEUEENTRYSIZE_16B 0 190218792Snp#define X_QUEUEENTRYSIZE_32B 1 191218792Snp#define X_QUEUEENTRYSIZE_64B 2 192218792Snp#define X_QUEUEENTRYSIZE_128B 3 193218792Snp 194218792Snp#define IC_SIZE_UNIT 16 195218792Snp#define IC_BASEADDRESS_ALIGN 512 196218792Snp 197218792Snp#define X_RSPD_TYPE_FLBUF 0 198218792Snp#define X_RSPD_TYPE_CPL 1 199218792Snp#define X_RSPD_TYPE_INTR 2 200218792Snp 201218792Snp/* 202308304Sjhb * Context field definitions. This is by no means a complete list of SGE 203308304Sjhb * Context fields. In the vast majority of cases the firmware initializes 204308304Sjhb * things the way they need to be set up. But in a few small cases, we need 205308304Sjhb * to compute new values and ship them off to the firmware to be applied to 206308304Sjhb * the SGE Conexts ... 207308304Sjhb */ 208308304Sjhb 209308304Sjhb/* 210308304Sjhb * Congestion Manager Definitions. 211308304Sjhb */ 212308304Sjhb#define S_CONMCTXT_CNGTPMODE 19 213308304Sjhb#define M_CONMCTXT_CNGTPMODE 0x3 214308304Sjhb#define V_CONMCTXT_CNGTPMODE(x) ((x) << S_CONMCTXT_CNGTPMODE) 215308304Sjhb#define G_CONMCTXT_CNGTPMODE(x) \ 216308304Sjhb (((x) >> S_CONMCTXT_CNGTPMODE) & M_CONMCTXT_CNGTPMODE) 217308304Sjhb#define S_CONMCTXT_CNGCHMAP 0 218308304Sjhb#define M_CONMCTXT_CNGCHMAP 0xffff 219308304Sjhb#define V_CONMCTXT_CNGCHMAP(x) ((x) << S_CONMCTXT_CNGCHMAP) 220308304Sjhb#define G_CONMCTXT_CNGCHMAP(x) \ 221308304Sjhb (((x) >> S_CONMCTXT_CNGCHMAP) & M_CONMCTXT_CNGCHMAP) 222308304Sjhb 223308304Sjhb#define X_CONMCTXT_CNGTPMODE_DISABLE 0 224308304Sjhb#define X_CONMCTXT_CNGTPMODE_QUEUE 1 225308304Sjhb#define X_CONMCTXT_CNGTPMODE_CHANNEL 2 226308304Sjhb#define X_CONMCTXT_CNGTPMODE_BOTH 3 227308304Sjhb 228308304Sjhb/* 229308304Sjhb * T5 and later support a new BAR2-based doorbell mechanism for Egress Queues. 230308304Sjhb * The User Doorbells are each 128 bytes in length with a Simple Doorbell at 231308304Sjhb * offsets 8x and a Write Combining single 64-byte Egress Queue Unit 232308304Sjhb * (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64. For Ingress Queues, 233308304Sjhb * we have a Going To Sleep register at offsets 8x+4. 234308304Sjhb * 235308304Sjhb * As noted above, we have many instances of the Simple Doorbell and Going To 236308304Sjhb * Sleep registers at offsets 8x and 8x+4, respectively. We want to use a 237308304Sjhb * non-64-byte aligned offset for the Simple Doorbell in order to attempt to 238308304Sjhb * avoid buffering of the writes to the Simple Doorbell and we want to use a 239308304Sjhb * non-contiguous offset for the Going To Sleep writes in order to avoid 240308304Sjhb * possible combining between them. 241308304Sjhb */ 242308304Sjhb#define SGE_UDB_SIZE 128 243308304Sjhb#define SGE_UDB_KDOORBELL 8 244308304Sjhb#define SGE_UDB_GTS 20 245308304Sjhb#define SGE_UDB_WCDOORBELL 64 246308304Sjhb 247308304Sjhb/* 248218792Snp * CIM definitions. 249218792Snp * ================ 250218792Snp */ 251218792Snp 252218792Snp/* 253218792Snp * CIM register field values. 254218792Snp */ 255218792Snp#define X_MBOWNER_NONE 0 256218792Snp#define X_MBOWNER_FW 1 257218792Snp#define X_MBOWNER_PL 2 258308304Sjhb#define X_MBOWNER_FW_DEFERRED 3 259218792Snp 260252705Snp/* 261252705Snp * PCI-E definitions. 262252705Snp * ================== 263252705Snp */ 264252705Snp 265252705Snp#define X_WINDOW_SHIFT 10 266252705Snp#define X_PCIEOFST_SHIFT 10 267252705Snp 268252705Snp/* 269252705Snp * TP definitions. 270252705Snp * =============== 271252705Snp */ 272252705Snp 273252705Snp/* 274252705Snp * TP_VLAN_PRI_MAP controls which subset of fields will be present in the 275252705Snp * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP 276252705Snp * selects for a particular field being present. These fields, when present 277252705Snp * in the Compressed Filter Tuple, have the following widths in bits. 278252705Snp */ 279308304Sjhb#define S_FT_FIRST S_FCOE 280308304Sjhb#define S_FT_LAST S_FRAGMENTATION 281308304Sjhb 282252705Snp#define W_FT_FCOE 1 283252705Snp#define W_FT_PORT 3 284252705Snp#define W_FT_VNIC_ID 17 285252705Snp#define W_FT_VLAN 17 286252705Snp#define W_FT_TOS 8 287252705Snp#define W_FT_PROTOCOL 8 288252705Snp#define W_FT_ETHERTYPE 16 289252705Snp#define W_FT_MACMATCH 9 290252705Snp#define W_FT_MPSHITTYPE 3 291252705Snp#define W_FT_FRAGMENTATION 1 292252705Snp 293252705Snp/* 294252705Snp * Some of the Compressed Filter Tuple fields have internal structure. These 295252705Snp * bit shifts/masks describe those structures. All shifts are relative to the 296252705Snp * base position of the fields within the Compressed Filter Tuple 297252705Snp */ 298252705Snp#define S_FT_VLAN_VLD 16 299252705Snp#define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD) 300252705Snp#define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U) 301252705Snp 302252705Snp#define S_FT_VNID_ID_VF 0 303252705Snp#define M_FT_VNID_ID_VF 0x7fU 304252705Snp#define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF) 305252705Snp#define G_FT_VNID_ID_VF(x) (((x) >> S_FT_VNID_ID_VF) & M_FT_VNID_ID_VF) 306252705Snp 307252705Snp#define S_FT_VNID_ID_PF 7 308252705Snp#define M_FT_VNID_ID_PF 0x7U 309252705Snp#define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF) 310252705Snp#define G_FT_VNID_ID_PF(x) (((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF) 311252705Snp 312252705Snp#define S_FT_VNID_ID_VLD 16 313252705Snp#define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD) 314252705Snp#define F_FT_VNID_ID_VLD(x) V_FT_VNID_ID_VLD(1U) 315252705Snp 316218792Snp#endif /* __T4_REGS_VALUES_H__ */ 317