adapter.h revision 309560
1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/10/sys/dev/cxgbe/adapter.h 309560 2016-12-05 20:43:25Z jhb $ 28 * 29 */ 30 31#ifndef __T4_ADAPTER_H__ 32#define __T4_ADAPTER_H__ 33 34#include <sys/kernel.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/types.h> 38#include <sys/malloc.h> 39#include <dev/pci/pcivar.h> 40#include <dev/pci/pcireg.h> 41#include <machine/bus.h> 42#include <sys/socket.h> 43#include <sys/sysctl.h> 44#include <net/ethernet.h> 45#include <net/if.h> 46#include <net/if_media.h> 47#include <netinet/in.h> 48#include <netinet/tcp_lro.h> 49 50#include "offload.h" 51#include "t4_ioctl.h" 52#include "common/t4_msg.h" 53#include "firmware/t4fw_interface.h" 54 55#define KTR_CXGBE KTR_SPARE3 56MALLOC_DECLARE(M_CXGBE); 57#define CXGBE_UNIMPLEMENTED(s) \ 58 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 59 60#if defined(__i386__) || defined(__amd64__) 61static __inline void 62prefetch(void *x) 63{ 64 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 65} 66#else 67#define prefetch(x) 68#endif 69 70#ifndef SYSCTL_ADD_UQUAD 71#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 72#define sysctl_handle_64 sysctl_handle_quad 73#define CTLTYPE_U64 CTLTYPE_QUAD 74#endif 75 76#if (__FreeBSD_version >= 900030) || \ 77 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 78#define SBUF_DRAIN 1 79#endif 80 81#ifdef __amd64__ 82/* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 83static __inline uint64_t 84t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 85 bus_size_t offset) 86{ 87 KASSERT(tag == X86_BUS_SPACE_MEM, 88 ("%s: can only handle mem space", __func__)); 89 90 return (*(volatile uint64_t *)(handle + offset)); 91} 92 93static __inline void 94t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 95 bus_size_t offset, uint64_t value) 96{ 97 KASSERT(tag == X86_BUS_SPACE_MEM, 98 ("%s: can only handle mem space", __func__)); 99 100 *(volatile uint64_t *)(bsh + offset) = value; 101} 102#else 103static __inline uint64_t 104t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 105 bus_size_t offset) 106{ 107 return (uint64_t)bus_space_read_4(tag, handle, offset) + 108 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 109} 110 111static __inline void 112t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 113 bus_size_t offset, uint64_t value) 114{ 115 bus_space_write_4(tag, bsh, offset, value); 116 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 117} 118#endif 119 120struct adapter; 121typedef struct adapter adapter_t; 122 123enum { 124 /* 125 * All ingress queues use this entry size. Note that the firmware event 126 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 127 * be at least 64. 128 */ 129 IQ_ESIZE = 64, 130 131 /* Default queue sizes for all kinds of ingress queues */ 132 FW_IQ_QSIZE = 256, 133 RX_IQ_QSIZE = 1024, 134 135 /* All egress queues use this entry size */ 136 EQ_ESIZE = 64, 137 138 /* Default queue sizes for all kinds of egress queues */ 139 CTRL_EQ_QSIZE = 128, 140 TX_EQ_QSIZE = 1024, 141 142#if MJUMPAGESIZE != MCLBYTES 143 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 144#else 145 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 146#endif 147 CL_METADATA_SIZE = CACHE_LINE_SIZE, 148 149 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 150 TX_SGL_SEGS = 39, 151 TX_SGL_SEGS_TSO = 38, 152 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 153}; 154 155enum { 156 /* adapter intr_type */ 157 INTR_INTX = (1 << 0), 158 INTR_MSI = (1 << 1), 159 INTR_MSIX = (1 << 2) 160}; 161 162enum { 163 XGMAC_MTU = (1 << 0), 164 XGMAC_PROMISC = (1 << 1), 165 XGMAC_ALLMULTI = (1 << 2), 166 XGMAC_VLANEX = (1 << 3), 167 XGMAC_UCADDR = (1 << 4), 168 XGMAC_MCADDRS = (1 << 5), 169 170 XGMAC_ALL = 0xffff 171}; 172 173enum { 174 /* flags understood by begin_synchronized_op */ 175 HOLD_LOCK = (1 << 0), 176 SLEEP_OK = (1 << 1), 177 INTR_OK = (1 << 2), 178 179 /* flags understood by end_synchronized_op */ 180 LOCK_HELD = HOLD_LOCK, 181}; 182 183enum { 184 /* adapter flags */ 185 FULL_INIT_DONE = (1 << 0), 186 FW_OK = (1 << 1), 187 /* INTR_DIRECT = (1 << 2), No longer used. */ 188 MASTER_PF = (1 << 3), 189 ADAP_SYSCTL_CTX = (1 << 4), 190 /* TOM_INIT_DONE= (1 << 5), No longer used */ 191 BUF_PACKING_OK = (1 << 6), 192 IS_VF = (1 << 7), 193 194 CXGBE_BUSY = (1 << 9), 195 196 /* port flags */ 197 HAS_TRACEQ = (1 << 3), 198 199 /* VI flags */ 200 DOOMED = (1 << 0), 201 VI_INIT_DONE = (1 << 1), 202 VI_SYSCTL_CTX = (1 << 2), 203 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 204 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 205 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ), 206 207 /* adapter debug_flags */ 208 DF_DUMP_MBOX = (1 << 0), 209}; 210 211#define IS_DOOMED(vi) ((vi)->flags & DOOMED) 212#define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 213#define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 214#define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 215#define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 216 217struct vi_info { 218 device_t dev; 219 struct port_info *pi; 220 221 struct ifnet *ifp; 222 struct ifmedia media; 223 224 unsigned long flags; 225 int if_flags; 226 227 uint16_t *rss, *nm_rss; 228 int smt_idx; /* for convenience */ 229 uint16_t viid; 230 int16_t xact_addr_filt;/* index of exact MAC address filter */ 231 uint16_t rss_size; /* size of VI's RSS table slice */ 232 uint16_t rss_base; /* start of VI's RSS table slice */ 233 234 eventhandler_tag vlan_c; 235 236 int nintr; 237 int first_intr; 238 239 /* These need to be int as they are used in sysctl */ 240 int ntxq; /* # of tx queues */ 241 int first_txq; /* index of first tx queue */ 242 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 243 int nrxq; /* # of rx queues */ 244 int first_rxq; /* index of first rx queue */ 245 int nofldtxq; /* # of offload tx queues */ 246 int first_ofld_txq; /* index of first offload tx queue */ 247 int nofldrxq; /* # of offload rx queues */ 248 int first_ofld_rxq; /* index of first offload rx queue */ 249 int nnmtxq; 250 int first_nm_txq; 251 int nnmrxq; 252 int first_nm_rxq; 253 int tmr_idx; 254 int pktc_idx; 255 int qsize_rxq; 256 int qsize_txq; 257 258 struct timeval last_refreshed; 259 struct fw_vi_stats_vf stats; 260 261 struct callout tick; 262 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 263 264 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 265}; 266 267enum { 268 /* tx_sched_class flags */ 269 TX_SC_OK = (1 << 0), /* Set up in hardware, active. */ 270}; 271 272struct tx_sched_class { 273 int refcount; 274 int flags; 275 struct t4_sched_class_params params; 276}; 277 278struct port_info { 279 device_t dev; 280 struct adapter *adapter; 281 282 struct vi_info *vi; 283 int nvi; 284 int up_vis; 285 int uld_vis; 286 287 struct tx_sched_class *tc; /* traffic classes for this channel */ 288 289 struct mtx pi_lock; 290 char lockname[16]; 291 unsigned long flags; 292 293 uint8_t lport; /* associated offload logical port */ 294 int8_t mdio_addr; 295 uint8_t port_type; 296 uint8_t mod_type; 297 uint8_t port_id; 298 uint8_t tx_chan; 299 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 300 301 int linkdnrc; 302 struct link_config link_cfg; 303 304 struct timeval last_refreshed; 305 struct port_stats stats; 306 u_int tx_parse_error; 307 308 struct callout tick; 309}; 310 311#define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 312 313/* Where the cluster came from, how it has been carved up. */ 314struct cluster_layout { 315 int8_t zidx; 316 int8_t hwidx; 317 uint16_t region1; /* mbufs laid out within this region */ 318 /* region2 is the DMA region */ 319 uint16_t region3; /* cluster_metadata within this region */ 320}; 321 322struct cluster_metadata { 323 u_int refcount; 324 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 325}; 326 327struct fl_sdesc { 328 caddr_t cl; 329 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 330 struct cluster_layout cll; 331}; 332 333struct tx_desc { 334 __be64 flit[8]; 335}; 336 337struct tx_sdesc { 338 struct mbuf *m; /* m_nextpkt linked chain of frames */ 339 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 340}; 341 342 343#define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 344struct iq_desc { 345 struct rss_header rss; 346 uint8_t cpl[IQ_PAD]; 347 struct rsp_ctrl rsp; 348}; 349#undef IQ_PAD 350CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 351 352enum { 353 /* iq flags */ 354 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 355 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 356 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 357 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 358 359 /* iq state */ 360 IQS_DISABLED = 0, 361 IQS_BUSY = 1, 362 IQS_IDLE = 2, 363 364 /* netmap related flags */ 365 NM_OFF = 0, 366 NM_ON = 1, 367 NM_BUSY = 2, 368}; 369 370struct sge_iq; 371struct rss_header; 372typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 373 struct mbuf *); 374typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 375typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 376 377/* 378 * Ingress Queue: T4 is producer, driver is consumer. 379 */ 380struct sge_iq { 381 uint32_t flags; 382 volatile int state; 383 struct adapter *adapter; 384 cpl_handler_t set_tcb_rpl; 385 cpl_handler_t l2t_write_rpl; 386 struct iq_desc *desc; /* KVA of descriptor ring */ 387 int8_t intr_pktc_idx; /* packet count threshold index */ 388 uint8_t gen; /* generation bit */ 389 uint8_t intr_params; /* interrupt holdoff parameters */ 390 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 391 uint16_t qsize; /* size (# of entries) of the queue */ 392 uint16_t sidx; /* index of the entry with the status page */ 393 uint16_t cidx; /* consumer index */ 394 uint16_t cntxt_id; /* SGE context id for the iq */ 395 uint16_t abs_id; /* absolute SGE id for the iq */ 396 397 STAILQ_ENTRY(sge_iq) link; 398 399 bus_dma_tag_t desc_tag; 400 bus_dmamap_t desc_map; 401 bus_addr_t ba; /* bus address of descriptor ring */ 402}; 403 404enum { 405 EQ_CTRL = 1, 406 EQ_ETH = 2, 407 EQ_OFLD = 3, 408 409 /* eq flags */ 410 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 411 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 412 EQ_ENABLED = (1 << 3), /* open for business */ 413}; 414 415/* Listed in order of preference. Update t4_sysctls too if you change these */ 416enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 417 418/* 419 * Egress Queue: driver is producer, T4 is consumer. 420 * 421 * Note: A free list is an egress queue (driver produces the buffers and T4 422 * consumes them) but it's special enough to have its own struct (see sge_fl). 423 */ 424struct sge_eq { 425 unsigned int flags; /* MUST be first */ 426 unsigned int cntxt_id; /* SGE context id for the eq */ 427 unsigned int abs_id; /* absolute SGE id for the eq */ 428 struct mtx eq_lock; 429 430 struct tx_desc *desc; /* KVA of descriptor ring */ 431 uint16_t doorbells; 432 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 433 u_int udb_qid; /* relative qid within the doorbell page */ 434 uint16_t sidx; /* index of the entry with the status page */ 435 uint16_t cidx; /* consumer idx (desc idx) */ 436 uint16_t pidx; /* producer idx (desc idx) */ 437 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 438 uint16_t dbidx; /* pidx of the most recent doorbell */ 439 uint16_t iqid; /* iq that gets egr_update for the eq */ 440 uint8_t tx_chan; /* tx channel used by the eq */ 441 volatile u_int equiq; /* EQUIQ outstanding */ 442 443 bus_dma_tag_t desc_tag; 444 bus_dmamap_t desc_map; 445 bus_addr_t ba; /* bus address of descriptor ring */ 446 char lockname[16]; 447}; 448 449struct sw_zone_info { 450 uma_zone_t zone; /* zone that this cluster comes from */ 451 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 452 int type; /* EXT_xxx type of the cluster */ 453 int8_t head_hwidx; 454 int8_t tail_hwidx; 455}; 456 457struct hw_buf_info { 458 int8_t zidx; /* backpointer to zone; -ve means unused */ 459 int8_t next; /* next hwidx for this zone; -1 means no more */ 460 int size; 461}; 462 463enum { 464 NUM_MEMWIN = 3, 465 466 MEMWIN0_APERTURE = 2048, 467 MEMWIN0_BASE = 0x1b800, 468 469 MEMWIN1_APERTURE = 32768, 470 MEMWIN1_BASE = 0x28000, 471 472 MEMWIN2_APERTURE_T4 = 65536, 473 MEMWIN2_BASE_T4 = 0x30000, 474 475 MEMWIN2_APERTURE_T5 = 128 * 1024, 476 MEMWIN2_BASE_T5 = 0x60000, 477}; 478 479struct memwin { 480 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 481 uint32_t mw_base; /* constant after setup_memwin */ 482 uint32_t mw_aperture; /* ditto */ 483 uint32_t mw_curpos; /* protected by mw_lock */ 484}; 485 486enum { 487 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 488 FL_DOOMED = (1 << 1), /* about to be destroyed */ 489 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 490 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 491}; 492 493#define FL_RUNNING_LOW(fl) \ 494 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 495#define FL_NOT_RUNNING_LOW(fl) \ 496 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 497 498struct sge_fl { 499 struct mtx fl_lock; 500 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 501 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 502 struct cluster_layout cll_def; /* default refill zone, layout */ 503 uint16_t lowat; /* # of buffers <= this means fl needs help */ 504 int flags; 505 uint16_t buf_boundary; 506 507 /* The 16b idx all deal with hw descriptors */ 508 uint16_t dbidx; /* hw pidx after last doorbell */ 509 uint16_t sidx; /* index of status page */ 510 volatile uint16_t hw_cidx; 511 512 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 513 uint32_t cidx; /* consumer index */ 514 uint32_t pidx; /* producer index */ 515 516 uint32_t dbval; 517 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 518 volatile uint32_t *udb; 519 520 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 521 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 522 uint64_t cl_allocated; /* # of clusters allocated */ 523 uint64_t cl_recycled; /* # of clusters recycled */ 524 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 525 526 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 527 struct mbuf *m0; 528 struct mbuf **pnext; 529 u_int remaining; 530 531 uint16_t qsize; /* # of hw descriptors (status page included) */ 532 uint16_t cntxt_id; /* SGE context id for the freelist */ 533 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 534 bus_dma_tag_t desc_tag; 535 bus_dmamap_t desc_map; 536 char lockname[16]; 537 bus_addr_t ba; /* bus address of descriptor ring */ 538 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 539}; 540 541struct mp_ring; 542 543/* txq: SGE egress queue + what's needed for Ethernet NIC */ 544struct sge_txq { 545 struct sge_eq eq; /* MUST be first */ 546 547 struct ifnet *ifp; /* the interface this txq belongs to */ 548 struct mp_ring *r; /* tx software ring */ 549 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 550 struct sglist *gl; 551 __be32 cpl_ctrl0; /* for convenience */ 552 int tc_idx; /* traffic class */ 553 554 struct task tx_reclaim_task; 555 /* stats for common events first */ 556 557 uint64_t txcsum; /* # of times hardware assisted with checksum */ 558 uint64_t tso_wrs; /* # of TSO work requests */ 559 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 560 uint64_t imm_wrs; /* # of work requests with immediate data */ 561 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 562 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 563 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 564 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 565 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 566 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 567 568 /* stats for not-that-common events */ 569} __aligned(CACHE_LINE_SIZE); 570 571/* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 572struct sge_rxq { 573 struct sge_iq iq; /* MUST be first */ 574 struct sge_fl fl; /* MUST follow iq */ 575 576 struct ifnet *ifp; /* the interface this rxq belongs to */ 577#if defined(INET) || defined(INET6) 578 struct lro_ctrl lro; /* LRO state */ 579#endif 580 581 /* stats for common events first */ 582 583 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 584 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 585 586 /* stats for not-that-common events */ 587 588} __aligned(CACHE_LINE_SIZE); 589 590static inline struct sge_rxq * 591iq_to_rxq(struct sge_iq *iq) 592{ 593 594 return (__containerof(iq, struct sge_rxq, iq)); 595} 596 597 598/* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 599struct sge_ofld_rxq { 600 struct sge_iq iq; /* MUST be first */ 601 struct sge_fl fl; /* MUST follow iq */ 602} __aligned(CACHE_LINE_SIZE); 603 604static inline struct sge_ofld_rxq * 605iq_to_ofld_rxq(struct sge_iq *iq) 606{ 607 608 return (__containerof(iq, struct sge_ofld_rxq, iq)); 609} 610 611struct wrqe { 612 STAILQ_ENTRY(wrqe) link; 613 struct sge_wrq *wrq; 614 int wr_len; 615 char wr[] __aligned(16); 616}; 617 618struct wrq_cookie { 619 TAILQ_ENTRY(wrq_cookie) link; 620 int ndesc; 621 int pidx; 622}; 623 624/* 625 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 626 * and offload tx queues are of this type. 627 */ 628struct sge_wrq { 629 struct sge_eq eq; /* MUST be first */ 630 631 struct adapter *adapter; 632 struct task wrq_tx_task; 633 634 /* Tx desc reserved but WR not "committed" yet. */ 635 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 636 637 /* List of WRs ready to go out as soon as descriptors are available. */ 638 STAILQ_HEAD(, wrqe) wr_list; 639 u_int nwr_pending; 640 u_int ndesc_needed; 641 642 /* stats for common events first */ 643 644 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 645 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 646 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 647 648 /* stats for not-that-common events */ 649 650 /* 651 * Scratch space for work requests that wrap around after reaching the 652 * status page, and some infomation about the last WR that used it. 653 */ 654 uint16_t ss_pidx; 655 uint16_t ss_len; 656 uint8_t ss[SGE_MAX_WR_LEN]; 657 658} __aligned(CACHE_LINE_SIZE); 659 660 661struct sge_nm_rxq { 662 struct vi_info *vi; 663 664 struct iq_desc *iq_desc; 665 uint16_t iq_abs_id; 666 uint16_t iq_cntxt_id; 667 uint16_t iq_cidx; 668 uint16_t iq_sidx; 669 uint8_t iq_gen; 670 671 __be64 *fl_desc; 672 uint16_t fl_cntxt_id; 673 uint32_t fl_cidx; 674 uint32_t fl_pidx; 675 uint32_t fl_sidx; 676 uint32_t fl_db_val; 677 u_int fl_hwidx:4; 678 679 u_int nid; /* netmap ring # for this queue */ 680 681 /* infrequently used items after this */ 682 683 bus_dma_tag_t iq_desc_tag; 684 bus_dmamap_t iq_desc_map; 685 bus_addr_t iq_ba; 686 int intr_idx; 687 688 bus_dma_tag_t fl_desc_tag; 689 bus_dmamap_t fl_desc_map; 690 bus_addr_t fl_ba; 691} __aligned(CACHE_LINE_SIZE); 692 693struct sge_nm_txq { 694 struct tx_desc *desc; 695 uint16_t cidx; 696 uint16_t pidx; 697 uint16_t sidx; 698 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 699 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 700 uint16_t dbidx; /* pidx of the most recent doorbell */ 701 uint16_t doorbells; 702 volatile uint32_t *udb; 703 u_int udb_qid; 704 u_int cntxt_id; 705 __be32 cpl_ctrl0; /* for convenience */ 706 u_int nid; /* netmap ring # for this queue */ 707 708 /* infrequently used items after this */ 709 710 bus_dma_tag_t desc_tag; 711 bus_dmamap_t desc_map; 712 bus_addr_t ba; 713 int iqidx; 714} __aligned(CACHE_LINE_SIZE); 715 716struct sge { 717 int nrxq; /* total # of Ethernet rx queues */ 718 int ntxq; /* total # of Ethernet tx tx queues */ 719 int nofldrxq; /* total # of TOE rx queues */ 720 int nofldtxq; /* total # of TOE tx queues */ 721 int nnmrxq; /* total # of netmap rx queues */ 722 int nnmtxq; /* total # of netmap tx queues */ 723 int niq; /* total # of ingress queues */ 724 int neq; /* total # of egress queues */ 725 726 struct sge_iq fwq; /* Firmware event queue */ 727 struct sge_wrq mgmtq; /* Management queue (control queue) */ 728 struct sge_wrq *ctrlq; /* Control queues */ 729 struct sge_txq *txq; /* NIC tx queues */ 730 struct sge_rxq *rxq; /* NIC rx queues */ 731 struct sge_wrq *ofld_txq; /* TOE tx queues */ 732 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 733 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 734 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 735 736 uint16_t iq_start; /* first cntxt_id */ 737 uint16_t iq_base; /* first abs_id */ 738 int eq_start; /* first cntxt_id */ 739 int eq_base; /* first abs_id */ 740 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 741 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 742 743 int8_t safe_hwidx1; /* may not have room for metadata */ 744 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 745 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 746 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 747}; 748 749struct devnames { 750 const char *nexus_name; 751 const char *ifnet_name; 752 const char *vi_ifnet_name; 753 const char *pf03_drv_name; 754 const char *vf_nexus_name; 755 const char *vf_ifnet_name; 756}; 757 758struct adapter { 759 SLIST_ENTRY(adapter) link; 760 device_t dev; 761 struct cdev *cdev; 762 const struct devnames *names; 763 764 /* PCIe register resources */ 765 int regs_rid; 766 struct resource *regs_res; 767 int msix_rid; 768 struct resource *msix_res; 769 bus_space_handle_t bh; 770 bus_space_tag_t bt; 771 bus_size_t mmio_len; 772 int udbs_rid; 773 struct resource *udbs_res; 774 volatile uint8_t *udbs_base; 775 776 unsigned int pf; 777 unsigned int mbox; 778 unsigned int vpd_busy; 779 unsigned int vpd_flag; 780 781 /* Interrupt information */ 782 int intr_type; 783 int intr_count; 784 struct irq { 785 struct resource *res; 786 int rid; 787 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 788 void *tag; 789 struct sge_rxq *rxq; 790 struct sge_nm_rxq *nm_rxq; 791 } __aligned(CACHE_LINE_SIZE) *irq; 792 int sge_gts_reg; 793 int sge_kdoorbell_reg; 794 795 bus_dma_tag_t dmat; /* Parent DMA tag */ 796 797 struct sge sge; 798 int lro_timeout; 799 int sc_do_rxcopy; 800 801 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 802 struct port_info *port[MAX_NPORTS]; 803 uint8_t chan_map[MAX_NCHAN]; 804 805 void *tom_softc; /* (struct tom_data *) */ 806 struct tom_tunables tt; 807 void *iwarp_softc; /* (struct c4iw_dev *) */ 808 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 809 struct l2t_data *l2t; /* L2 table */ 810 struct tid_info tids; 811 812 uint16_t doorbells; 813 int offload_map; /* ports with IFCAP_TOE enabled */ 814 int active_ulds; /* ULDs activated on this adapter */ 815 int flags; 816 int debug_flags; 817 818 char ifp_lockname[16]; 819 struct mtx ifp_lock; 820 struct ifnet *ifp; /* tracer ifp */ 821 struct ifmedia media; 822 int traceq; /* iq used by all tracers, -1 if none */ 823 int tracer_valid; /* bitmap of valid tracers */ 824 int tracer_enabled; /* bitmap of enabled tracers */ 825 826 char fw_version[16]; 827 char tp_version[16]; 828 char er_version[16]; 829 char bs_version[16]; 830 char cfg_file[32]; 831 u_int cfcsum; 832 struct adapter_params params; 833 const struct chip_params *chip_params; 834 struct t4_virt_res vres; 835 836 uint16_t nbmcaps; 837 uint16_t linkcaps; 838 uint16_t switchcaps; 839 uint16_t niccaps; 840 uint16_t toecaps; 841 uint16_t rdmacaps; 842 uint16_t cryptocaps; 843 uint16_t iscsicaps; 844 uint16_t fcoecaps; 845 846 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 847 848 struct mtx sc_lock; 849 char lockname[16]; 850 851 /* Starving free lists */ 852 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 853 TAILQ_HEAD(, sge_fl) sfl; 854 struct callout sfl_callout; 855 856 struct mtx reg_lock; /* for indirect register access */ 857 858 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 859 860 const char *last_op; 861 const void *last_op_thr; 862 int last_op_flags; 863}; 864 865#define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 866#define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 867#define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 868#define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 869 870#define ASSERT_SYNCHRONIZED_OP(sc) \ 871 KASSERT(IS_BUSY(sc) && \ 872 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 873 ("%s: operation not synchronized.", __func__)) 874 875#define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 876#define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 877#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 878#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 879 880#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 881#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 882#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 883#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 884#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 885 886#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 887#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 888#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 889#define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 890 891#define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 892#define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 893#define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 894#define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 895#define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 896 897#define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 898#define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 899#define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 900#define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 901#define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 902 903#define CH_DUMP_MBOX(sc, mbox, data_reg) \ 904 do { \ 905 if (sc->debug_flags & DF_DUMP_MBOX) { \ 906 log(LOG_NOTICE, \ 907 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 908 "%016llx %016llx %016llx %016llx\n", \ 909 device_get_nameunit(sc->dev), mbox, \ 910 (unsigned long long)t4_read_reg64(sc, data_reg), \ 911 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 912 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 913 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 914 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 915 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 916 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 917 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 918 } \ 919 } while (0) 920 921#define for_each_txq(vi, iter, q) \ 922 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 923 iter < vi->ntxq; ++iter, ++q) 924#define for_each_rxq(vi, iter, q) \ 925 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 926 iter < vi->nrxq; ++iter, ++q) 927#define for_each_ofld_txq(vi, iter, q) \ 928 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 929 iter < vi->nofldtxq; ++iter, ++q) 930#define for_each_ofld_rxq(vi, iter, q) \ 931 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 932 iter < vi->nofldrxq; ++iter, ++q) 933#define for_each_nm_txq(vi, iter, q) \ 934 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 935 iter < vi->nnmtxq; ++iter, ++q) 936#define for_each_nm_rxq(vi, iter, q) \ 937 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 938 iter < vi->nnmrxq; ++iter, ++q) 939#define for_each_vi(_pi, _iter, _vi) \ 940 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 941 ++(_iter), ++(_vi)) 942 943#define IDXINCR(idx, incr, wrap) do { \ 944 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 945} while (0) 946#define IDXDIFF(head, tail, wrap) \ 947 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 948 949/* One for errors, one for firmware events */ 950#define T4_EXTRA_INTR 2 951 952/* One for firmware events */ 953#define T4VF_EXTRA_INTR 1 954 955static inline uint32_t 956t4_read_reg(struct adapter *sc, uint32_t reg) 957{ 958 959 return bus_space_read_4(sc->bt, sc->bh, reg); 960} 961 962static inline void 963t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 964{ 965 966 bus_space_write_4(sc->bt, sc->bh, reg, val); 967} 968 969static inline uint64_t 970t4_read_reg64(struct adapter *sc, uint32_t reg) 971{ 972 973 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 974} 975 976static inline void 977t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 978{ 979 980 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 981} 982 983static inline void 984t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 985{ 986 987 *val = pci_read_config(sc->dev, reg, 1); 988} 989 990static inline void 991t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 992{ 993 994 pci_write_config(sc->dev, reg, val, 1); 995} 996 997static inline void 998t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 999{ 1000 1001 *val = pci_read_config(sc->dev, reg, 2); 1002} 1003 1004static inline void 1005t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1006{ 1007 1008 pci_write_config(sc->dev, reg, val, 2); 1009} 1010 1011static inline void 1012t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1013{ 1014 1015 *val = pci_read_config(sc->dev, reg, 4); 1016} 1017 1018static inline void 1019t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1020{ 1021 1022 pci_write_config(sc->dev, reg, val, 4); 1023} 1024 1025static inline struct port_info * 1026adap2pinfo(struct adapter *sc, int idx) 1027{ 1028 1029 return (sc->port[idx]); 1030} 1031 1032static inline void 1033t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 1034{ 1035 1036 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN); 1037} 1038 1039static inline bool 1040is_10G_port(const struct port_info *pi) 1041{ 1042 1043 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1044} 1045 1046static inline bool 1047is_25G_port(const struct port_info *pi) 1048{ 1049 1050 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0); 1051} 1052 1053static inline bool 1054is_40G_port(const struct port_info *pi) 1055{ 1056 1057 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1058} 1059 1060static inline bool 1061is_100G_port(const struct port_info *pi) 1062{ 1063 1064 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0); 1065} 1066 1067static inline int 1068port_top_speed(const struct port_info *pi) 1069{ 1070 1071 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1072 return (100); 1073 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1074 return (40); 1075 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) 1076 return (25); 1077 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1078 return (10); 1079 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1080 return (1); 1081 1082 return (0); 1083} 1084 1085static inline int 1086tx_resume_threshold(struct sge_eq *eq) 1087{ 1088 1089 /* not quite the same as qsize / 4, but this will do. */ 1090 return (eq->sidx / 4); 1091} 1092 1093static inline int 1094t4_use_ldst(struct adapter *sc) 1095{ 1096 1097#ifdef notyet 1098 return (sc->flags & FW_OK || !sc->use_bd); 1099#else 1100 return (0); 1101#endif 1102} 1103 1104/* t4_main.c */ 1105extern int t4_ntxq10g; 1106extern int t4_nrxq10g; 1107extern int t4_ntxq1g; 1108extern int t4_nrxq1g; 1109extern int t4_intr_types; 1110extern int t4_tmr_idx_10g; 1111extern int t4_pktc_idx_10g; 1112extern int t4_tmr_idx_1g; 1113extern int t4_pktc_idx_1g; 1114extern unsigned int t4_qsize_rxq; 1115extern unsigned int t4_qsize_txq; 1116extern device_method_t cxgbe_methods[]; 1117 1118int t4_os_find_pci_capability(struct adapter *, int); 1119int t4_os_pci_save_state(struct adapter *); 1120int t4_os_pci_restore_state(struct adapter *); 1121void t4_os_portmod_changed(const struct adapter *, int); 1122void t4_os_link_changed(struct adapter *, int, int, int); 1123void t4_iterate(void (*)(struct adapter *, void *), void *); 1124void t4_init_devnames(struct adapter *); 1125void t4_add_adapter(struct adapter *); 1126int t4_detach_common(device_t); 1127int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1128int t4_map_bars_0_and_4(struct adapter *); 1129int t4_map_bar_2(struct adapter *); 1130int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1131int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1132int t4_setup_intr_handlers(struct adapter *); 1133void t4_sysctls(struct adapter *); 1134int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1135void doom_vi(struct adapter *, struct vi_info *); 1136void end_synchronized_op(struct adapter *, int); 1137int update_mac_settings(struct ifnet *, int); 1138int adapter_full_init(struct adapter *); 1139int adapter_full_uninit(struct adapter *); 1140uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1141int vi_full_init(struct vi_info *); 1142int vi_full_uninit(struct vi_info *); 1143void vi_sysctls(struct vi_info *); 1144void vi_tick(void *); 1145 1146#ifdef DEV_NETMAP 1147/* t4_netmap.c */ 1148void cxgbe_nm_attach(struct vi_info *); 1149void cxgbe_nm_detach(struct vi_info *); 1150void t4_nm_intr(void *); 1151#endif 1152 1153/* t4_sge.c */ 1154void t4_sge_modload(void); 1155void t4_sge_modunload(void); 1156uint64_t t4_sge_extfree_refs(void); 1157void t4_tweak_chip_settings(struct adapter *); 1158int t4_read_chip_settings(struct adapter *); 1159int t4_create_dma_tag(struct adapter *); 1160void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1161 struct sysctl_oid_list *); 1162int t4_destroy_dma_tag(struct adapter *); 1163int t4_setup_adapter_queues(struct adapter *); 1164int t4_teardown_adapter_queues(struct adapter *); 1165int t4_setup_vi_queues(struct vi_info *); 1166int t4_teardown_vi_queues(struct vi_info *); 1167void t4_intr_all(void *); 1168void t4_intr(void *); 1169void t4_vi_intr(void *); 1170void t4_intr_err(void *); 1171void t4_intr_evt(void *); 1172void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1173void t4_update_fl_bufsize(struct ifnet *); 1174int parse_pkt(struct adapter *, struct mbuf **); 1175void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1176void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1177int tnl_cong(struct port_info *, int); 1178int t4_register_an_handler(an_handler_t); 1179int t4_register_fw_msg_handler(int, fw_msg_handler_t); 1180int t4_register_cpl_handler(int, cpl_handler_t); 1181 1182/* t4_tracer.c */ 1183struct t4_tracer; 1184void t4_tracer_modload(void); 1185void t4_tracer_modunload(void); 1186void t4_tracer_port_detach(struct adapter *); 1187int t4_get_tracer(struct adapter *, struct t4_tracer *); 1188int t4_set_tracer(struct adapter *, struct t4_tracer *); 1189int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1190int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1191 1192static inline struct wrqe * 1193alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1194{ 1195 int len = offsetof(struct wrqe, wr) + wr_len; 1196 struct wrqe *wr; 1197 1198 wr = malloc(len, M_CXGBE, M_NOWAIT); 1199 if (__predict_false(wr == NULL)) 1200 return (NULL); 1201 wr->wr_len = wr_len; 1202 wr->wrq = wrq; 1203 return (wr); 1204} 1205 1206static inline void * 1207wrtod(struct wrqe *wr) 1208{ 1209 return (&wr->wr[0]); 1210} 1211 1212static inline void 1213free_wrqe(struct wrqe *wr) 1214{ 1215 free(wr, M_CXGBE); 1216} 1217 1218static inline void 1219t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1220{ 1221 struct sge_wrq *wrq = wr->wrq; 1222 1223 TXQ_LOCK(wrq); 1224 t4_wrq_tx_locked(sc, wrq, wr); 1225 TXQ_UNLOCK(wrq); 1226} 1227 1228#endif 1229